Vision-Based Teleoperation of Dexterous Robotic Systems

Abstract

To improve teleoperation interfaces.SOLUTION: A human pilot controls a robotic arm and gripper by simulating a set of desired motions with a human hand. In at least one embodiment, one or more images of the pilot's hand are captured and analyzed to determine a set of hand poses. In at least one embodiment, the set of hand poses is translated to a corresponding set of robotic-gripper poses. In at least one embodiment, a set of motions is determined that perform the set of robotic-gripper poses, and the robot is directed to perform the set of motions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 903,671, entitled "DEPTH BASED TELEOPERATION OF DEXTEROUS ROBOTIC HAND ARM SYSTEM," filed September 20, 2019, which is incorporated herein by reference in its entirety. This application also incorporates by reference the entire disclosures of co-pending U.S. Provisional Patent Application No. 16 / 863,111, entitled "IN-HAND OBJECT POSE TRACKING," filed April 30, 2020, and co-pending U.S. Provisional Patent Application No. 62 / 925,669, entitled "IN-HAND OBJECT POSE TRACKING VIA CONTACT FEEDBACK AND GPU-ACCELERATED ROBOTIC SIMULATION," filed October 24, 2019, all of which are hereby incorporated by reference for all purposes.

[0002] At least one embodiment relates to the use of a robot to perform and facilitate tasks under the control of a human operator. For example, at least one embodiment relates to controlling a robotic arm by mimicking the movements of a human hand through various novel techniques described herein. [Background technology]

[0003] Controlling a robot to perform a task can be a difficult and challenging problem. One way to control a robot is through direct human control. For example, some robotic systems provide the human operator with a joystick or programmatic interface that allows the operator to move the robot. However, these interfaces are generally unintuitive, difficult to use, and require significant training and practice. This is especially true when the operator is attempting to perform complex tasks, such as interacting with other objects. Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, improving teleoperation interfaces is an important area of ​​research in the field of robotic control. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 illustrates an example of teleoperation across various tasks, according to at least one embodiment. [Figure 2] FIG. 1 illustrates an example of a robotic arm and hand, according to at least one embodiment. [Figure 3] FIG. 1 illustrates an example system for tracking human hand movements and translating those movements into corresponding movements of a robotic arm, according to at least one embodiment. [Figure 4] FIG. 1 illustrates an example of a glove that can be used to assist in hand pose estimation, according to at least one embodiment. [Figure 5] FIG. 1 illustrates an example architecture of a system for determining hand posture, according to at least one embodiment. [Figure 6] FIG. 1 illustrates an example of estimating hand pose from point clouds, according to at least one embodiment. [Figure 7] 1A-1C illustrate examples of human hand poses and corresponding poses of a robotic gripper, according to at least one embodiment. [Figure 8] 1A-1C illustrate examples of human hand poses and corresponding robotic gripper poses, according to at least one embodiment. [Figure 9] FIG. 1 illustrates an example task in which a robot is controlled to remove paper from a folded wallet, according to at least one embodiment. [Figure 10] FIG. 1 illustrates an example task in which a robot is controlled to retrieve an object from a drawer, according to at least one embodiment. [Figure 11] FIG. 1 illustrates an example task in which a robot is controlled to open a bottle, according to at least one embodiment. [Figure 12] FIG. 10 illustrates an example of completion time for a teleoperation task, according to one embodiment. [Figure 13] FIG. 10 illustrates an example of a success rate of a teleoperation task, according to one embodiment. [Figure 14] FIG. 1 illustrates an example of a process performed by a computer system to guide a robotic arm to perform a task by mimicking the actions of a human hand. [Figure 15A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 15B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 16] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 17] FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 18A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 18B] 18B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 18A, according to at least one embodiment. [Figure 18C] FIG. 18B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 18A, according to at least one embodiment. [Figure 18D] FIG. 18B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 18A, according to at least one embodiment. [Figure 19] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 20] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 21] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 22] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 23A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 23B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 23C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 23D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 23E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 23F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 24] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 25A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 25B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 26A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 26B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 27] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 28A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 28B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 28C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 28D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 29] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 30] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 31] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 32] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 33] FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor, according to at least one embodiment. [Figure 34] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 35] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 36] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 37] FIG. 37 is a block diagram of a graphics processing engine 3710 of a graphics processor according to at least one embodiment. [Figure 38] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 39A] FIG. 39 illustrates thread execution logic 3900 including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 39B] FIG. 39 illustrates thread execution logic 3900 including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 40] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 41] FIG. 1 illustrates a general purpose processing cluster (“GPC”), according to at least one embodiment. [Figure 42] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 43] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] This specification describes a system and method for teleoperated robot control. In at least one embodiment, the system estimates the pose of a human hand and then guides the robot to the corresponding pose. In one example, as a human operator performs an action with their hand, the action is captured by a depth camera, and the system generates a point cloud using data from the depth camera. The point cloud is processed to determine the hand pose. The hand pose identifies the location of the fingertips and the approximate joint angles and bones of the hand. The system then translates the hand pose to the corresponding pose of the robotic hand. In some examples, the system compensates for differences in robotic hand size and the number of fingers between human hands and robotic hands. In some examples, the human hand pose may be translated to a robotic hand with more or fewer fingers. In some examples, the human hand pose may be translated to the pose of an excavator, industrial robot, or vehicle. For example, a human may mimic the shape of a claw or bucket on an earthmoving machine, and the system may translate the hand pose to the corresponding pose of the claw or bucket, thereby achieving intuitive control of the machine. A human operator can view the robot directly or remotely via a video display and guide it to perform tasks by reproducing the required actions in real time.

[0007] In at least one embodiment, teleoperation offers the potential to empower robotic systems with advanced reasoning, intuition, and creativity to perform tasks. At least one example described herein provides a low-cost, vision-based teleoperation system capable of fully controlling a robotic system across 23 DoA by observing a human's bare hands. Some examples enable operators to perform a variety of complex manipulation tasks beyond simple pick-and-place operations. At least one example enables the collection of high-dimensional, multi-modality state-behavior data, which can be used in the future to learn sensorimotor policies for performing challenging manipulation tasks. System performance in at least one example is measured by metrics of speed and accuracy between two performers for a variety of tasks. In various embodiments, the system may be implemented by one or more of the systems described / illustrated in Figures 15-43.

[0008] Various embodiments may be applied in the fields of search and rescue, space, medicine, prosthetics, and applied machine learning. In at least one embodiment, teleoperation enables robotic systems to perform complex tasks by leveraging human cognition, creativity, and reaction capabilities through a human-machine interface (“HMI”). At least one embodiment relies on the incorporation of haptic feedback and improved tracking of the human skeleton and fingers. At least one embodiment provides a low-cost, markerless, gloveless teleoperation solution that utilizes innovations in machine vision, optimization, motion generation, and GPU computing. At least one embodiment is capable of capturing and relaying fine dexterous manipulations to drive highly agile robotic systems capable of solving diverse grasping and manipulation tasks. In one example, four Intel RealSense depth cameras and two NVIDIA GPUs were combined with deep learning and nonlinear optimization to create a minimal-footprint dexterous teleoperation system. Despite the lack of haptic feedback, this system example is highly capable and effective through human cognition. In at least one embodiment, this result supports human gaze studies showing that humans learn to use vision to plan, control, and predict hand movements and then precisely control their hands. In some instances, the depth camera can be a RADAR- or LIDAR-based imaging system, or a medical imaging system such as a magnetic resonance imaging machine or an x-ray imaging machine.

[0009] In various examples, teleoperation systems leverage the human ability to plan, move, and predict the outcomes of their physical actions from vision alone, a sufficient condition for solving a variety of tasks. Various embodiments have one or more of the following advantages: a markerless, gloveless, fully vision-based teleoperation system that dexterously articulates a highly actuated robotic hand-arm system through direct imitation; a novel cost function and projection scheme for kinematically retargeting human hand joints to robotic hand joints that maintains hand dexterity and the feasibility of precision grasps even in the presence of hand joint tracking errors; demonstrations of the teleoperation system for a variety of tasks, particularly those requiring fine manipulation and dexterity; and system evaluations between two trained demonstrators (also called pilots) that revealed high task success rates despite the absence of haptic feedback.

[0010] In various embodiments, the developed system enables such dexterous robotic manipulation using multiple camera depth observations of bare human hands. In some instances, the system can be a gloveless, fully vision-based teleoperation system that dexterously articulates a highly actuated robotic hand-arm system through direct imitation. The system may also demonstrate a variety of tasks requiring particularly fine manipulation and dexterity (e.g., removing a bill from a wallet and simultaneously lifting two cubes with four fingers, as shown in FIG. 1).

[0011] 1 illustrates examples of teleoperation across various tasks, according to at least one embodiment. In one example, robotic gripper 104 grasps a cylinder using a grasping posture based on human hand 102. In another example, robotic gripper 108 grasps a cube using a grasping posture based on human hand 106. In another example, robotic gripper 112 grasps a cup using a grasping posture based on human hand 110. In another example, robotic gripper 116 grasps a wallet using a grasping posture based on human hand 114.

[0012] As shown in FIG. 2, a teleoperation configuration may include a robotic system and an adjacent human operator's field of operation. FIG. 2 illustrates an example of a robot with tactile sensors, according to at least one embodiment. In at least one embodiment, robot 202 has a robotic gripper 204 used to grasp an object. In at least one embodiment, a set of cameras 206, 208, 210, and 212 is used to observe the workspace of robot 202. In at least one embodiment, gripper 204 includes a set of tactile sensors 216, 218, 220, and 222 that provide sensory information for controlling a computer system. In at least one embodiment, the tactile sensors may be covered with a frictional material to enhance and / or improve the robot's ability to grasp an object.

[0013] In some embodiments, as shown in Figure 2, the robotic system may be a KUKA LBR iiwa7 R800 series arm with a Wonik Robotics Allegro Hand, four SynTouch BioTac tactile sensors retrofitted to the fingertips, and 3M TB641 gripping tape attached to the phalanges and medial surfaces of the palm, where the rubbery surfaces of both the BioTac sensors and the 3M tape improve hand friction, and the BioTac itself may generate 23 signals that can later be used to learn sensorimotor control from demonstrations. The human activity area may be a table covered with a black cloth and surrounded by four calibrated, time-synchronized cameras, such as Intel RealSense RGB-D cameras, spatially arranged to cover an 80 cm x 55 cm x 38 cm workspace. In some instances, because teleoperation is based entirely on human vision and spatial reasoning, the cameras may be directly adjacent to the robot to improve line of sight and visual proximity. FIG. 2 is intended to be an illustrative example, and in various embodiments, the system may include any robotic system utilizing any robotic components (e.g., various types of robotic arms, hands, tactile sensors, graspers, other sensors, cameras, and / or variations thereof) in any suitable environment.

[0014] To create a natural-feeling teleoperation system, an imitation-type paradigm may be employed. The movements of a human hand, i.e., posture and finger configuration, may be constantly observed and measured by a visual perception module. The human hand movements may then be relayed to the robotic system in a manner that reveals the copied movements. This approach allows the human operator to bend, align, and grasp their fingers, orient and move their palm, and the robotic system to follow suit in a similar manner. In at least one embodiment, the system relies heavily on Dense Articulated Real-Time Tracking ("DART"), which may be the backbone for tracking the posture and joint angles of the human hand. This system architecture and component connections are shown in Figure 3 in one embodiment.

[0015] FIG. 3 illustrates an example system for tracking a human hand in real time and controlling a robot to perform corresponding movements, according to at least one embodiment. In at least one embodiment, the system operates using three threads, which are independent processes running on one or more processors of a computer system. In at least one embodiment, the training thread uses a fused input point cloud from four studio cameras to provide prior knowledge of the hand pose and joint angles. In at least one embodiment, the tracking thread operates DART for hand tracking using prior knowledge and the kinematic retargeting required to map the human hand configuration to the Allegro Hand. In at least one embodiment, the control thread operates Riemannian motion policies to provide target joint commands to the KUKA and Allegro Hand given the hand pose and joint angles.

[0016] In at least one embodiment, one or more images of a hand are acquired from an RGB-depth (“RGB-G”) camera 302. The images are processed by PointNet: Stage 1 (304), PointNet: Stage 2 (306), and JointNet (308) to generate hand poses for the hands in the images. In at least one embodiment, the articulated hand model 310 and hand poses are processed using DART 312 and kinematic retargeting 314 to generate corresponding hand poses for the robot gripper. In at least one embodiment, a control thread applies a Riemannian motion policy 318 to the gripper hand poses, and the resulting information is used to control the robot 320.

[0017] Figure 3 shows an example implementation that includes the following components: 1) DART for hand tracking, 2) a deep neural network for human hand state estimation and DART robustness, 3) refining the human hand state using DART and converting it to an Allegro Hand state via nonlinear optimization, and 4) motion generation and control using a Riemannian Motion Policy (RMP) and a torque-level impedance controller. An example implementation of the above components daisy-chained together is shown in Figure 3. In at least one example implementation, the entire system produces a latency of approximately 1 second.

[0018] In at least one embodiment, DART is used to continuously track the pose and joint angles of a human hand. In at least one embodiment, DART uses an articulated model of the hand that is registered to an input point cloud. The human hand model may be acquired and reduced to a single mesh model. Using computer-aided design ("CAD") software, the fingers of the mesh model may be separated into their respective proximal, middle, and distal links and re-exported as separate meshes along with associated extensible markup language ("XML") files describing their kinematic configurations. The human hand model may have four rotational joints per finger, plus one abduction joint and three flexion joints, for a total of 20 rotational joints.

[0019] In at least one embodiment, DART is a model-based tracker that relies on nonlinear optimization and initialization (e.g., from a previous frame or from an initial guess). In some instances, if this initialization is not within the convergence region, the tracker may fail to converge to the correct solution. In various embodiments, when tracking a human hand model using point cloud data, the hand model often stutters and enters spurious local minima, which can lead to tracking failures every few minutes. Therefore, to reliably track human hands over long periods of time useful for teleoperation, it may be desirable to have reliable prior knowledge of hand poses, clean hand segmentation, and a multi-view camera studio to prevent the hand model from stuttering and entering unexpected local minima. In various embodiments, one method for generating prior knowledge of hand poses is to train a neural network on a large dataset of human hand poses given camera images.

[0020] FIG. 4 shows an example of a color glove used to obtain hand pose and segmentation. In at least one embodiment, glove 402 includes five fingers 404, 406, 408, 410, and 412, each colored with a different color of fabric. In at least one embodiment, the unique colors are printed to minimize annotation generation using OpenCV color thresholding. In at least one embodiment, the color of the back of the hand 414 uniquely determines the hand pose.

[0021] In at least one embodiment, fabric gloves (such as those shown in FIG. 4) with colored blobs are initially used as an effective solution for acquiring prior knowledge of hand pose using deep neural networks. In at least one embodiment, data collection proceeds in two stages. In at least one embodiment, in the first stage, a user wears the gloves to acquire prior knowledge of hand pose for DART to robustly track the human hand. In at least one embodiment, this process generates annotations of hand pose and joint angles for the raw depth map from the RGB-D camera for the second stage. In at least one embodiment, the second stage uses these annotations and operates on the raw point cloud from the corresponding depth map, freeing the user from having to wear gloves.

[0022] In at least one embodiment, a colored glove is used for hand tracking. In at least one embodiment, the glove has colored blobs on the fingertips and three on the back of the hand. In at least one embodiment, hand tracking includes both hand pose and finger joint angles. In at least one embodiment, a user moves their hand above a table in a multi-camera studio with four Intel RealSense D415 RGB-D cameras pointing downward toward the table. In at least one embodiment, the problem of hand pose estimation using the glove is formulated via keypoint localization. In at least one embodiment, regression to the 2D locations of the centers of the colored blobs on the glove is performed from the RGB image using ResNet-50 and spatial softmax, referred to as GloveNet. In at least one embodiment, colored blobs on the fingertips are also regressed, but are found to be less useful in the final whole-hand tracking, and predictions of the blobs on the back of the hand are used for hand pose estimation.

[0023] In at least one embodiment, hand pose can be estimated by three unique keypoints indicated by three different colored blobs on the back of the glove. In at least one embodiment, a segmentation is generated using HSV thresholding in OpenCV, and the centers of mass of these segmented colored blobs are calculated to obtain annotations for the centers of the blobs. In at least one embodiment, to aid in the segmentation and obtain high-quality annotations, a user wears a black glove with colored blobs and moves their hand over a table also covered with a black cloth. In at least one embodiment, hand pose can be obtained via the predicted 2D locations of the blobs from all four cameras, and the 2D keypoints are converted to their corresponding 3D locations using depth values, resulting in each blob having a total of four 3D predictions from the four cameras. In at least one embodiment, these 3D locations are filtered and temporarily smoothed to obtain the hand pose. In at least one embodiment, hand segmentation is also obtained by removing 3D points that fall outside the bounding volume of the hand. In at least one embodiment, the dimensions of this volume were derived heuristically from the hand pose obtained from neural network predictions. Crucially, in at least one embodiment, DART now optimizes only the segmented hand points to prevent the hand model from shifting to points on the arm, which is common when the full point cloud is used. In at least one embodiment, DART does not use RGB images; the glove only provides pose priors and aids in hand segmentation. Thus, using DART in a first stage, along with hand pose priors and segmentation, results in annotations on the raw camera-captured point cloud for a second stage that can operate on a bare human hand.

[0024] In at least one embodiment, the second stage desirably relieves the user from having to wear gloves in the future for any remote manipulation. In at least one embodiment, the first stage operates on RGB images, while the second stage operates directly on a fused point cloud of a bare human hand obtained by back-projecting four depth maps from an externally calibrated camera into a global reference frame. In at least one embodiment, annotations for this stage are derived from the data generated in the first stage. In at least one embodiment, the cameras also provide synchronized depth images, so that the tracking results of the first stage can provide point cloud annotations.

[0025] In at least one embodiment, the fused point cloud includes both points on the table and points on the human body and arms, making it essential to first localize the hand. In at least one embodiment, the points on the table are removed by fitting a plane, and the remaining points, including the arms and human body, are fed into an architecture that localizes the hand and provides hand pose. In at least one embodiment, the network estimates hand pose by voting-based regression to the 3D locations of specific keypoints on the hand. In at least one embodiment, the network is trained to predict the 3D coordinates of 23 keypoints identified on the hand: four joint keypoints on each of the five fingers and three keypoints on the back of the hand to provide hand pose estimation. In at least one embodiment, the loss function is a combination of a standard Euclidean loss and a voting loss between the predicted keypoints and ground truth keypoints. In at least one embodiment, an auxiliary segmentation loss is also added to obtain hand segmentation. In at least one embodiment, for efficiency, any input point cloud of size Nx3 is uniformly subsampled to a fixed size of 8192x3 before being fed into the network.

[0026] While at least one embodiment achieves reasonable hand pose estimation and segmentation, obtaining high-quality predictions for the 20 finger joint keypoints remains challenging for this network. In at least one embodiment, the uniform subsampling used at the input means that the finger points are not densely sampled, necessitating a second stage of refinement that resamples hand points from the original raw point cloud given the pose and segmentation from the first stage. In at least one embodiment, the overall network architecture is shown in Figure 5. In at least one embodiment, the second stage is trained solely on a loss function for keypoints; no segmentation is required. In at least one embodiment, the second stage instead uses sampled points for the hand and accurately predicts 23 keypoints. In at least one embodiment, additional randomization is added to the hand pose for the second stage to enable robustness against any errors in the hand pose from the first stage. In at least one embodiment, Figure 7 illustrates how the second stage refinement improves the system. In at least one embodiment, both stages of the network are trained on 100K point clouds collected over a total of 7-8 hours in 30-45 minute batches each by running DART with prior knowledge from the globe. In at least one embodiment, they together provide annotations for keypoints, joint angles, and segmentation. Training takes a total of 15 hours on a single NVIDIA TitanXp GPU.

[0027] In at least one embodiment, keypoints are a natural representation of the Euclidean space used in the PointNet++ architecture, while most articulated models use joints as a natural parameterization. In at least one embodiment, it is desirable to have an output in joint space that can serve as joint prior knowledge for DART. In at least one embodiment, a third neural network is trained that maps the 23 keypoint locations predicted by the PointNet++-derived architecture to corresponding joint angles. In at least one embodiment, this neural network, called JointNet, is a two-layer fully connected network that takes inputs of size 23 x 3 and predicts a 20-dimensional vector of joint angles for the fingers.

[0028] In at least one embodiment, the neural network is trained on data collected within the confines of a studio's working volume for multiple human hands, ensuring accurate poses for this application and enabling practical prior knowledge for DART. In at least one embodiment, the hand tracker performs qualitatively well for hands that are close in shape to DART's human hand model. In at least one embodiment, the average keypoint error on a validation set of 7,000 images of different hand poses and finger configurations was 9.7 mm, and the joint error was 1.33 degrees per joint.

[0029] In Figure 5, the resulting architecture from PointNet++ operates in two stages. The first stage segments the hand (shown in pink) and provides a rough hand pose. The second stage refines the hand pose given the hand segmentation and pose from the first stage. The loss functions include a segmentation loss, a Euclidean loss between predicted and ground truth keypoints, and a voting loss as used in

[11] . Because the second stage refines keypoints, no segmentation loss is required. The set abstraction layer takes an input of size N × (d + C) and outputs an N' × (d + C4), while the feature propagation layer takes an input of size N' × (d + C') and outputs a tensor of size N × (d + C3). These two together form the backbone of the network. Using MLP, the embeddings in PointNet++'s backbone are mapped to the corresponding desired outputs. Details of the network are provided in the appendix.

[0030] In Figure 6, in one embodiment, the input point cloud includes both points from the table and points from the human body and arm. In at least one embodiment, a plane is fitted to remove points on the table, and the remaining points are input to a first stage of a network that recovers the hand pose. In at least one embodiment, a second stage refines the pose and provides more accurate results. In at least one embodiment, the image of the hand on the right shows the results from Stage 1 and Stage 2 of Figure 5.

[0031] In at least one embodiment, data collection begins with DART without prior knowledge of hand poses, and an initial network begins training to generate prior knowledge of the hand. DART and the latest trained neural network may then generate larger amounts of data. In at least one embodiment, the network may be continually updated with the latest datasets to generate increasingly better prior knowledge for DART, ultimately expanding the range of objects over which DART can operate without failure. In some instances, the hand pose neural network may be a PointNet-based architecture that operates directly on fused point cloud data obtained by backprojecting depth images from an externally calibrated depth camera into a single global reference frame using annotations provided by DART. In various embodiments, because the fused point cloud includes points on both the table and points on the human body and arm, it may be necessary to first localize the hand. Points may be removed from the table by fitting a plane, and the remaining points, including the arm and human body, may be fed into PointNet, which may localize the hand and provide the hand pose. PointNet may be based on estimating hand pose via a voting-based regression scheme to the 3D locations of specific keypoints on the hand, a technique sometimes associated with spatial softmax, which is commonly used for 2D keypoint localization. In at least one embodiment, PointNet may be trained to predict the 3D coordinates of 23 keypoints identified on the hand for hand pose estimation: four joint keypoints on each of the five fingers and three keypoints on the back of the hand. The loss function may be the Euclidean distance between the predicted keypoints and ground truth keypoints. Additionally, an auxiliary segmentation loss may be included to obtain hand segmentation. For efficiency, any input point cloud may be uniformly subsampled to a fixed size of 8192x3 before being fed into PointNet.While at least one embodiment achieves reasonable hand pose estimation and segmentation, high-quality prediction of the 20 finger joint keypoints is still not possible. In at least one embodiment, the uniform subsampling used in the input means that the points on the fingers are not densely sampled, necessitating a second stage of refinement in which the hand points are resampled from the original raw point cloud given the first-stage pose and segmentation. In at least one embodiment, the second stage may be trained on the same loss function, but instead may accurately predict the 23 keypoints using only the sampled points for the hand. In at least one embodiment, random perturbations may be added to the hand pose for the second stage to enable robustness against any errors in the hand pose obtained from the first stage. Figure 4 illustrates second-stage refinement in a system, according to at least one embodiment. In at least one embodiment, both stages of PointNet may be trained by running DART on 100K point clouds collected over a total of 7-8 hours in 30-45 minute batches to provide keypoint, joint angle, and segmentation annotations. In at least one embodiment, to provide prior knowledge of joint angles for fingers, a third neural network may be trained to map keypoint locations predicted by PointNet to corresponding joint angles. This neural network, sometimes referred to as JointNet, may be a two-layer fully connected network that takes inputs of size 23x3 and predicts a 20-dimensional vector of joint angles for the fingers.

[0032] In at least one embodiment, the neural network is trained on data collected for multiple human hands to ensure accurate poses are captured by the system, enabling practical prior knowledge for DART. In some embodiments, the hand tracker performs well for hands whose shape closely matches DART's human hand model.

[0033] In at least one embodiment, teleoperation of a robotic hand that is kinematically dissimilar from a human hand may require a module that can map observed human hand joints to the robotic hand joints, which in some embodiments may be referred to as Allegro Hand joints. FIG. 7 illustrates an example of a human hand pose 702 and a correspondingly posed robotic gripper 704, in accordance with at least one embodiment. Many different approaches to kinematic retargeting may exist. For example, in at least one embodiment, modules may be used to align the palm-to-fingert position with the medial joint position and to align the orientation of the proximal phalanges and distal phalanges of the thumb. In at least one embodiment, the optimized mapping may be used to label depth images of the human, allowing a deep network to ingest the depth images and output joint angles. In at least one embodiment, motion retargeting is also utilized. For example, a deep recurrent neural network may be trained unsupervised to retarget motion between skeletons. In at least one embodiment, the system utilizes spatial metrics for fingertip tasks because distal regions may be prioritized for grasping and manipulation tasks, as measured by contact spread, degree of innervation, and high controllability for fine-tuning skills. In at least one embodiment, joint axes and locations may differ between two hands, and therefore metrics that directly compare joint angles between the two hands cannot be used. In at least one embodiment, both the distance and orientation between fingertips are considered to capture and optimize fingertip positioning. Specifically, in at least one embodiment, a cost function for kinematic retargeting may be selected as follows:

number

[0034] where q h ,q a can be the angles of the human hand model and the Allegro Hand, respectively, and r i ∈R3 can be a vector pointing from the origin of one coordinate system to the origin of another coordinate system, expressed in the origin coordinate system (see FIG. 7). Furthermore, in at least one embodiment, di=||r i (q h )||, and

number

number

[0035] Here, S1 can be a vector originating from a primary finger (index, middle, ring finger) towards the thumb, and S2 can be a vector between two primary fingers when they both have an associated vector ∈S1 (e.g., when both primary fingers are projecting with the thumb). In at least one embodiment, a distance function f(d i )∈R is defined as follows:

number

[0036] Here, β=1.6 can be used as a magnification, and η1=1×10 -4 m can be the distance between the major finger and the thumb, η2 = 3 × 10 -2 m may be the minimum separation distance between the two major fingers when both fingers are extended along with the thumb. [Table 1] In at least one embodiment, such protrusion ensures close contact between the primary finger and thumb in a precision grasp without causing collision of the primary finger. In at least one embodiment, this can be particularly useful in the presence of visual finger tracking errors. In some instances, the vector r i may not only capture the distance and direction from one task space to another; expressing that vector in local coordinates may further include information about the coordinate system and therefore how the fingertips are oriented relative to one another. Thus, in at least one embodiment, the coordinate system of the human hand model may have an equivalent coordinate system for the Allegro model, which has a similar orientation and placement. The vectors shown in FIG. 7 may form a minimal set that produces the desired retargeting behavior. In some embodiments, γ = 2.5 × 10 -3 may be a weight for regularizing the Allegro angles to zero (equivalent to a fully open hand). In at least one embodiment, this condition helps reduce redundancy in the solution and ensures that the hand never enters a strange minimum that can be difficult to recover from (e.g., fingers tucking into the palm). In at least one embodiment, various mappings from human hands 602-617 to Allegro robotic hands 618-633 produced by kinematic retargeting are shown in FIG. 8. FIG. 8 shows a collection of human hand poses 802-817 and the corresponding poses 818-833 of the robotic gripper.

[0037] In at least one embodiment, the above cost function is minimized in real time using a Sequential Least Squares Quadratic Programming ("SLSQP") algorithm. In at least one embodiment, the routine begins with the Allegro joint angles set to zero, and all subsequent solutions may begin with the previous solution. In at least one embodiment, forward kinematic calculations are found between the various coordinate systems of both the human hand model and the Allegro Hand. In at least one embodiment, a first-order low-pass filter is applied to the raw retargeted joint angles to remove high-frequency noise present in tracking a human hand and to smooth out discrete events, such as projection algorithms that cause step-response changes in the retargeted angles.

[0038] In at least one embodiment, the Riemannian Motion Policy (“RMP”) is a real-time motion generation method that calculates acceleration fields from potential function gradients and corresponding Riemannian metrics. In at least one embodiment, the RMP combines multi-priority Cartesian trajectory generation and collision avoidance behavior in a cohesive framework. In at least one embodiment, the RMP is used to control the Cartesian pose of the Allegro palm given the observed pose of the human hand and to use a collision plane to avoid arm and palm collisions with the table or operator. In at least one embodiment, given these objectives, the RMP generated targeted arm joint trajectories that were sent to the arm's torque-level impedance controller at 200 Hz. In at least one embodiment, the kinematically retargeted Allegro angles were sent to the torque-level joint controller at 30 Hz. In at least one embodiment, one final calibration detail requires registering the human hand's pose movements with the robotic system. In at least one embodiment, this is accomplished by finding a transformation from the robot's coordinate system to the camera's coordinate system. In at least one embodiment, this transformation is calculated using an initial representation of the human hand and an initial pose of the robot hand. In at least one embodiment, to facilitate the operator's spatial reasoning, the desired initial hand pose for the operator is a fully open hand with the palm parallel to the table and the fingers pointing forward. In at least one embodiment, the initial pose of the robot mimics this pose. In at least one embodiment, the robot thus moves in the same direction as the operator's hand, enabling intuitive spatial reasoning.

[0039] Overall, the system can be reliably used to solve a variety of tasks of varying difficulty. In some instances, the ability to solve these tasks reveals that the system can exhibit dexterity in precision and strength grasps, multi-finger grasping and non-grasping manipulations, finger gait, and complex manual manipulations (e.g., grasping with two fingers while simultaneously manipulating with the remaining fingers).

[0040] 9 shows an example task in which a robot is controlled to remove paper from a folded wallet, according to at least one embodiment. In at least one embodiment, the operator must first open the wallet, move it to a specific vantage location, and remove the paper note. In at least one embodiment, the hand can hold the paper by pinching it between the fingers.

[0041] 10 shows an example task in which a robot is controlled to retrieve an object from a drawer, according to at least one embodiment. In at least one embodiment, this is a somewhat long horizontal task that requires dexterity in opening the drawer and grabbing the tea bag.

[0042] 11 illustrates an example task in which a robot is controlled to open a bottle, which, in at least one embodiment, requires rotating the cap open multiple times while maintaining contact.

[0043] The table below shows 15 illustrative tasks of varying complexity, ranging from traditional pick-and-place to long, multi-step horizontal tasks. In at least one embodiment, each of these tasks is operated over five consecutive trials to avoid preferential selection, with success rates reported accordingly. In at least one embodiment, a trial is considered a failure if the object falls outside the workspace volume. The final column represents the skill required for teleoperation, as the hand changes state over time. [Table 2]

[0044] In one experiment, operators underwent a warm-up training phase in which they attempted to solve the tasks in three to five non-consecutive attempts. Five consecutive trials per task were then performed by each operator, avoiding preferential selection of outcomes, and operators were graded based on their performance. Performance metrics for these tasks included mean completion time ("CT") and success rate, which capture the speed and reliability of the teleoperation system. The system was tested with two operators, and performance measurements are reported in Figures 12 and 13.

[0045] In at least one embodiment, the system can be reliably used to solve a variety of tasks of varying difficulty. In at least one embodiment, the difference in mean CT between tasks indicates the influence of task complexity and horizontal scale. In at least one embodiment, the difference in mean CT between operators per task indicates a clear dependency on operator behavior. In at least one embodiment, influences include fatigue, training, creativity, and motivation. In at least one embodiment, the ability to solve these tasks reveals the dexterity of the teleoperated system, exhibiting precision and strength grasps, multi-fingered grasping and non-grasping manipulations, manual finger gait, and complex manual manipulations (e.g., grasping with two fingers while simultaneously manipulating with the remaining fingers). It should be noted that in at least one embodiment, certain tasks, such as containers and wallets, take particularly long to teleoperate, primarily due to the fact that these tasks are multi-stage tasks. On the other hand, tasks requiring lifting small cubes can be particularly challenging because the release behavior of these objects using the projection scheme used in kinematic retargeting can be unpredictable. Nevertheless, this rich display of dexterous skill conveyed solely by observing a human hand provides empirical evidence that the techniques and architectures herein perform well in various embodiments. In at least one embodiment, it is important to emphasize that while the overall teleoperation process may not have been perfect for a particular task (e.g., the operator lost sight of the object at hand but was able to retrieve it again and accomplish the task), the collected data is still valuable in helping the robot learn to recover from failure. In at least one embodiment, the data can be considered play data useful for learning long-term planning. In at least one embodiment, discrete events, such as intermittent finger-object contact, can be observed in the tactile signals. In at least one embodiment, the waveforms of these state-behavior signals reveal the rich and complex behaviors evoked within the system by this embodied configuration.In at least one embodiment, force estimates can also be obtained. In at least one embodiment, this data can now be generated as needed for a particular task, with the goal that functional sensorimotor patterns can be collected and applied to the system in an autonomous setting.

[0046] In at least one embodiment, this system may enable a highly agile hand-arm system to find motor solutions for various manipulation tasks by translating observed human hand and finger motions into robotic arm and finger motions. In at least one embodiment, some tasks, such as extracting banknotes from a wallet and opening cardboard boxes in plastic containers, are so complex that hand-designing robotic solutions or directly applying learning methods may be intractable. Solving these and other tasks with an embodied robot may enable these solutions to be generated on demand for many demonstrations. Furthermore, generating these solutions within the system itself may enable reading, accessing, and storing various tactile signals from the robot's fingertips, various joint position and velocity signals commanded and measured throughout the hand and arm, various torque commands throughout the system, and any camera feeds associated with the system. In at least one embodiment, this rich data source, along with task demonstrations, may be used to solve complex, multi-stage, long horizontal tasks.

[0047] The techniques described herein, in at least one embodiment, provide a viable, low-cost solution for teleoperating high DoA robotic systems. In at least one embodiment, the operator's observable working volume can be expanded, enabling tasks covering longer distances with better RGB-D cameras. In at least one embodiment, the projection scheme in kinematic retargeting allows for successful manipulation of small objects, but can hinder finger gait tasks and timely release of grasp on small objects. In at least one embodiment, this problem is fully resolved using hand tracking that can accurately resolve human fingertip contact situations. In at least one embodiment, human hand tracking is further improved by improving robustness across operator hand sizes and shapes. The lack of haptic feedback can make completing precision tasks difficult. To compensate, in at least one embodiment, autonomous control features are incorporated to alleviate some of the control burden on the operator. In at least one embodiment, system latency is reduced, and the responsiveness of the RMP motion generator is adjusted for faster response. In at least one embodiment, high precision tasks such as slip-fit, peg-in-hole insertion present challenges. In at least one embodiment, improved hand tracking, automated precision grasp control over assembly objects, and improved visibility of small parts and insertion locations significantly reduce the difficulty of completing the tasks.

[0048] In at least one embodiment, the input to the system is a point cloud of a human performer's hand. In at least one embodiment, a neural network, such as one based on the PointNet++ neural network, maps the point cloud to estimates of the hand's pose relative to the camera and the hand's joint angles. In at least one embodiment, these estimates, along with the articulated hand model and the original point cloud, are then fed to DART, which performs tracking by refining the neural network's estimates. Finally, in one embodiment, an optimization problem is solved to find the joint angles of the Allegro Hand to perform kinematic retargeting, resulting in fingertip poses that approximate those of a human hand.

[0049] In at least one embodiment, gloved hand tracking is performed via neural network keypoint detection. In at least one embodiment, a user wears black gloves with colored blobs and moves their hands across a table covered with a black cloth. That is, the situation is arranged in a way that supports hand tracking. In at least one embodiment, because the colors are clear and the background is mostly black, annotations are generated for these colored blobs using OpenCV HSV color thresholding. In at least one embodiment, the HSV threshold varies over time, thus collecting data over many days to build a large dataset of 50K images. At least one embodiment fits this data using a neural network, making the entire process robust to lighting changes and improper annotations and avoiding the burden on the user to find appropriate thresholds during testing. In at least one embodiment, a network called GloveNet performs regression to the 2D location of the fingertips using a four-layer ResNet-50 with a final spatial softmax. At least one embodiment uses an anti-aliased ResNet-50 to make accurate and consistent predictions. The various stages of the pipeline are described below.

[0050] At least one embodiment uses imgaug and applies various data augmentations during training. At least one embodiment focuses on a hand moving on a table. For each training image, at least one embodiment sets the color value of all pixels with a depth above a threshold to zero. During training, at least one embodiment either sets these zeroed values ​​to a random color of the glove or leaves the image unchanged based on a random number generator. At least one embodiment also replaces these zeroed values ​​with random noise based on some probability. In at least one embodiment, the network learns to ignore background colors that look the same as the color of the glove.

[0051] At least one embodiment obtains the confidence for each predicted fingertip location using test-time augmentation ("TTA"). At least one embodiment generates new images by shifting the original images by a random shift and passing them through the network in a batch. At least one embodiment then subtracts the applied random shift from the predicted positions for each image, puts them in the reference frame of the original image, and averages them to obtain the mean and standard deviation. At least one embodiment uses the standard deviation as a measure of confidence, and at least one embodiment uses it to filter out noisy ground truth data.

[0052] During testing, at least one embodiment generates four randomly shifted images per camera image, totaling 16 images from four cameras. At least one embodiment calculates predicted fingertip locations and their confidence measures, discarding those with low confidence. Of the reliable ones, at least one embodiment calculates the Euclidean distance d between them and the previous fingertip location and assigns them a probability p using softmax. i to

number

[0053] At least one embodiment provides a probability p i The predicted locations with a mean value >0.2 are put into a rolling buffer and the shape median is calculated to obtain the final predicted location of the fingertip in 3D. The hyperparameter α=500. [Table 3]

[0054] In at least one embodiment, predictions of the back-of-hand blob were stable, but predictions of the fingertip blob tended to be highly inconsistent across time. In at least one embodiment, annotations were generated by calculating the center of mass ("CoM") of the segmented blobs using HSV color thresholding in OpenCV, so the fingertip CoMs were somewhat inconsistent across frames due to occlusion. Therefore, at least one embodiment relied solely on the hand pose estimate provided by the back-of-hand blob. [Table 4]

[0055] In at least one embodiment, the architecture consists of four set abstraction layers SAi and four feature propagation layers FPj. In at least one embodiment, the set abstraction layers subsample the points while the feature propagation layers interpolate the features at a higher resolution.

[0056] In at least one embodiment, the set abstraction level takes as input N x (d + C) points with d-dimensional coordinates and C-dimensional point features. At least one embodiment outputs an N' x (d + C') tensor, where N' subsampled points with d-dimensional coordinates and new C'-dimensional feature vectors summarize the local context.

[0057] In at least one embodiment, at the feature propagation level, the features of a point are i ×(d+C) to N iー1is propagated to the point N i-1 and Ni (where N i ≦N i-1 ) is the set size of the input and output points at set abstraction level i. In at least one embodiment, this is N i The feature values ​​of the points are i-1 In at least one embodiment, this is achieved by interpolating the coordinates of the points N i-1 The interpolated features at a point are then concatenated with the features at the skip-linked point from the set abstraction level.

[0058] In at least one embodiment, the backbone of hand pose estimation is an architecture that returns an embedding f of size N × C. Using different MLPs, this embedding is mapped to the corresponding desired output. z=mlp_layer 1(f) δ xyz =vote(z) Code = Input xyz +δ xyz joint mask xyz = sigmoid(seg(z)) Hand Segment xyz =cls(z) Hand Segment Probability xyz = Sigmoid (hand segment xyz ) Weight = Hand Segment Probability xyz joint mask kxy

number

[0059] In at least one embodiment, the voting layer determines the relative positions δ of the 23 keypoints with respect to each other. xyzThe segmentation layer obtains a mask for each keypoint, i.e., a neighborhood of points that contribute to the keypoint's location. In at least one embodiment, the hand segmentation layer segments the hand from the background. At least one embodiment uses Euclidean loss for both voting and keypoints, and sigmoid cross entropy for hand segmentation.

[0060] In at least one implementation, the 23x3 keypoint locations are expanded into a 69-dimensional vector before being fed into JointNet, which returns a 20-dimensional vector of joint angles. Of all the hand-designed and tried architectures, this particular architecture proved to be a useful trade-off between accuracy and efficiency, at least in one implementation. [Table 6]

[0061] In one embodiment, the completion time for five consecutive trials for each task is shown. In at least one embodiment, a failed trial is indicated with an F. In at least one embodiment, for most trials, the pilot warmed up using only three or four training trials. In at least one embodiment, these five consecutive trials both test the pilot's ability to perform a particular task without fatigue and demonstrate that tracking works without failure. In at least one embodiment, performance may vary depending on the pilot and their perception on a given day, but experiments have shown that this performance is generally very similar. [Table 7-1] [Table 7-2]

[0062] In at least one embodiment, retargeting using neural networks does not produce satisfactory results, i.e., it does not provide the same accuracy as online optimization using recursive least squares. In at least one embodiment, the projection threshold used in retargeting may require some adjustment when grasping small objects, thus making training neural networks for novel, arbitrary tasks cumbersome.

[0063] In at least one embodiment, a hand tracking system relies on a combination of model-based and model-free tracking. In at least one embodiment, a model-based tracking system is more accurate because it optimizes input observations online given a model. However, in at least one embodiment, the optimization tends to be highly nonlinear, so the model-based tracking system also requires good initialization to find a practical solution. In at least one embodiment, a model-free system is used, which can provide good initialization. In at least one embodiment, the model-free system is a neural network trained based on data generated by the model-based system.

[0064] In at least one embodiment, a model-based tracker such as DART

[27] is used, and data is collected in regions where the tracker works reliably, repeatedly to cover a wide range of poses. In at least one embodiment, DART performance can be stochastic. DART may work reliably for the same motion, but may fail catastrophically due to spurious local minima in optimization given the input point cloud. However, in at least one embodiment, if data is collected for situations where DART works reasonably well, a neural network can be used to adapt this data, ensuring that it provides good initialization for DART and prevents it from hitting spurious local minima in the future. In at least one embodiment, this is due to the neural network's ability to generalize slightly outside the range of the training set. In at least one embodiment, this procedure of data collection and neural network adaptation is performed iteratively to improve DART performance so that tracking works without any failures over long durations. In at least one embodiment, a two-stage PointNet++-based architecture is trained based on annotations generated by DART, providing good initialization, enabling at least one embodiment of robust and accurate tracking.

[0065] Figure 14 illustrates an example process that, when performed by a computer system, directs a robotic arm to perform a task by mimicking the actions of a human hand. In at least one embodiment, the computer system is the computer system illustrated in Figures 21-23. In at least one embodiment, the computer system includes a processor and memory, the memory storing executable instructions that, when executed by the processor, cause the system to perform the operations illustrated in Figure 14 and described below. In at least one embodiment, the processor is a plurality of processors or a dedicated processor such as a GPU, as illustrated in Figures 15-43 and described below.

[0066] In at least one embodiment, in block 1402, a computer system acquires an image of a human hand from a depth camera. In various embodiments, the depth camera can be an RGB depth camera, a binocular camera, a radar or laser-based imaging device, or an MRI, x-ray, computed tomography, or computed axial tomography scanner. In at least one embodiment, in block 1404, the computer system generates a point cloud of the human hand from the image. The point cloud provides three-dimensional data describing the hand, from which pose can be determined. In at least one embodiment, in block 1406, the computer system analyzes the point cloud to determine the joint structure and joint angles of the hand. In various embodiments, this, combined with the location of the hand in space, constitutes the pose of the hand.

[0067] In at least one embodiment, in block 1408, the computer system translates the pose of the human hand into a corresponding pose of the robotic gripper. In at least one embodiment, the robotic gripper can be an articulated robotic hand similar to the joints of a human hand. The articulated robotic hand may have fewer or more fingers than a human hand, and each finger of the articulated robotic hand may have one or more articulated segments. In at least one embodiment, the pose of the human hand includes a set of articulated segments and joint angles as well as the overall position of the human hand, and the pose of the robotic gripper is determined by replicating the joint angles of the pose of the human hand using the robotic hand. In at least one embodiment, the robotic hand has fewer fingers than a human hand, and the pose associated with a subset of the human fingers is used to determine the corresponding pose of the robotic gripper. In at least one embodiment, the robotic gripper may be larger or smaller than a human hand, and a scaling factor is applied to the pose of the human hand when determining the corresponding pose of the robotic gripper. In at least one embodiment, the pose of the human hand includes a location of the hand, and the corresponding location of the robotic hand is determined by translating the coordinate system from the coordinate system relative to the human operator to the coordinate system of the robot. In some instances, a scaling factor may be applied to the location aspect of the pose. For example, a 15 cm (6 inch) movement of the human hand may correspond to a 180 cm (6 foot) movement of the robotic gripper.

[0068] In at least one embodiment, in block 1410, the computer system determines a set of movements to reposition the robot gripper from its current position to the corresponding pose determined in block 1408. In at least one embodiment, the system determines a motion path for the robot hand that will transform the robot hand from its current pose to the pose determined in block 1408. In at least one embodiment, these movements are determined according to a Riemann motion policy. In at least one embodiment, in block 1412, the computer system causes the robot to execute the set of movements determined in block 1410. In at least one embodiment, the result is that the robot gripper moves to a pose that corresponds to the pose of a human hand. In various embodiments, using these techniques, a human operator can intuitively guide the robot's movements with the movements of their hands. In at least one embodiment, no gloves or wearable devices are required.

[0069] Logic of inference and training Figure 15A illustrates inference and / or training logic 1515 used to perform inference and / or training operations for one or more embodiments. More details regarding inference and / or training logic 1515 are provided below in conjunction with Figures 15A and / or 15B.

[0070] In at least one embodiment, the inference and / or training logic 1515 may include, without limitation, code and / or data storage 1501 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that are trained and / or used to infer in one or more embodiments. In at least one embodiment, the training logic 1515 may include or be coupled to code and / or data storage 1501 for storing graph code or other software for controlling the timing and / or sequence of logic loaded with weights and / or other parameter information, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 1501 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1501 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache, or system memory.

[0071] In at least one embodiment, any portion of code and / or data storage 1501 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1501 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1501 is internal or external to a processor, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0072] In at least one embodiment, the inference and / or training logic 1515 may include, without limitation, code and / or data storage 1505 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with one or more aspects of the embodiments. In at least one embodiment, the code and / or data storage 1505 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while backpropagating input / output data and / or weight parameters during training and / or inference using one or more aspects of the embodiments. In at least one embodiment, training logic 1515 may include or be coupled to code and / or data storage 1505 for storing graph code or other software for timing and / or sequencing control, where weights and / or other parameter information are loaded into the code and / or data storage 1505 to configure logic including integer and / or floating point units (collectively arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which the code corresponds. In one embodiment, any portion of code and / or data storage 1505 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1505 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1505 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage.In at least one embodiment, the choice of whether code and / or data storage 1505 is internal or external to the processor, for example, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0073] In at least one embodiment, code and / or data storage 1501 and code and / or data storage 1505 may be separate storage structures. In at least one embodiment, code and / or data storage 1501 and code and / or data storage 1505 may be the same storage structure. In at least one embodiment, code and / or data storage 1501 and code and / or data storage 1505 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 1501 and code and / or data storage 1505 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0074] In at least one embodiment, inference and / or training logic 1515 may include one or more arithmetic logic units (“ALUs”) 1510, including, without limitation, integer and / or floating point units, for performing logical and / or arithmetic operations based at least in part on or indicated by training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 1520, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1501 and / or code and / or data storage 1505. In at least one embodiment, the activations stored in activation storage 1520 are generated according to linear algebra and / or matrix-based calculations performed by ALU 1510 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 1505 and / or data 1501 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 1505, or code and / or data storage 1501, or in separate storage, on-chip or off-chip.

[0075] In at least one embodiment, ALU 1510 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU 1510 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 1510 may be included within an execution unit of a processor or may otherwise be included within an ALU bank accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, data storage 1501, code and / or data storage 1505, and activation storage 1520 may be in the same processor or other hardware logic devices or circuits, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or some combination of the same processor or other hardware logic devices or circuits and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1520 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0076] In at least one embodiment, activation storage 1520 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 1520 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 1520 is internal or external to a processor, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, for example, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inference and / or training of neural networks, or any combination of these factors. In at least one embodiment, the inference and / or training logic 1515 shown in Figure 15A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the inference and / or training logic 1515 shown in Figure 15A may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0077] FIG. 15B illustrates inference and / or training logic 1515 according to at least one various embodiment. In at least one embodiment, the inference and / or training logic 1515 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 1515 illustrated in FIG. 15B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 1515 illustrated in FIG. 15B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit (“GPU”) hardware, or a field-programmable gate array (FPGA). In at least one embodiment, inference and / or training logic 1515 includes, without limitation, code and / or data storage 1501 and code and / or data storage 1505, which may be used to store code (e.g., graph code), weight and / or bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 15B , each of code and / or data storage 1501 and code and / or data storage 1505 is associated with dedicated computational resources, such as computation hardware 1502 and computation hardware 1506, respectively. In at least one embodiment, computation hardware 1502 and computation hardware 1506 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in code and / or data storage 1501 and code and / or data storage 1505, respectively, with the results stored in activation storage 1520.

[0078] In at least one embodiment, each of code and / or data storage 1501 and 1505 and corresponding computational hardware 1502 and 1506 corresponds to a different layer of a neural network, whereby activations resulting from one "storage / computation pair 1501 / 1502" of code and / or data storage 1501 and computational hardware 1502 are provided as input to the next "storage / computation pair 1505 / 1506" of code and / or data storage 1505 and computational hardware 1506 to reflect the conceptual organization of the neural network. In at least one embodiment, storage / computation pairs 1501 / 1502 and 1505 / 1506 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in inference and / or training logic 1515 after or in parallel with storage / computation pairs 1501 / 1502 and 1505 / 1506.

[0079] Neural network training and deployment FIG. 16 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 91606 is trained using a training data set 1602. In at least one embodiment, the training framework 1604 is the PyTorch framework, while in other embodiments, the training framework 1604 is Tensorflow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 1604 trains the untrained neural network 1606 and enables it to be trained using processing resources described herein to generate a trained neural network 1608. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0080] In at least one embodiment, the untrained neural network 1606 is trained using supervised learning, where the training data set 1602 includes inputs paired with desired outputs for those inputs, or the training data set 1602 includes inputs with known outputs, and the outputs of the neural network 1606 are manually scored. In at least one embodiment, the untrained neural network 1606 is trained in a supervised manner, processing inputs from the training data set 1602 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 1606. In at least one embodiment, the training framework 1604 adjusts the weights that control the untrained neural network 1606. In at least one embodiment, training framework 1604 includes tools to monitor how well untrained neural network 1606 is converging toward a model, such as trained neural network 1608, that is suitable for generating correct answers, such as results 1614, based on known input data, such as new data 1612. In at least one embodiment, training framework 1604 iteratively trains untrained neural network 1606 while adjusting weights to refine the output of untrained neural network 1606 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, training framework 1604 trains untrained neural network 1606 until untrained neural network 1606 reaches a desired accuracy. In at least one embodiment, trained neural network 1608 can then be deployed to implement any number of machine learning operations.

[0081] In at least one embodiment, the untrained neural network 1606 is trained using unsupervised learning, where the untrained neural network 1606 attempts to train itself using unlabeled data. In at least one embodiment, the training data set 1602 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 1606 can learn groupings within the training data set 1602 and determine how individual inputs relate to the untrained data set 1602. In at least one embodiment, unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1608 that can perform operations useful for reducing the dimensionality of the new data 1612. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new data set 1612 that deviate from the normal patterns of the new data set 1612.

[0082] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training data set 1602. In at least one embodiment, the training framework 1604 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 1608 to adapt to new data 1612 without forgetting the knowledge instilled in the network during initial training.

[0083] Data Center 17 illustrates an exemplary data center 1700 in which at least one embodiment may be used. In at least one embodiment, data center 1700 includes a data center infrastructure layer 1710, a framework layer 1720, a software layer 1730, and an application layer 1740.

[0084] 17, data center infrastructure layer 1710 may include a resource orchestrator 1712, grouped computing resources 1714, and node computing resources (“node CRs”) 1716(1) through 1716(N), where “N” represents any positive integer. In at least one embodiment, node CRs 1716(1) through 1716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power supply modules, and cooling modules. In at least one embodiment, one or more of the nodes CR 1716(1)-1716(N) may be a server having one or more of the computing resources described above.

[0085] In at least one embodiment, grouped computing resources 1714 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). Separate groups of node CRs within grouped computing resources 1714 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0086] In at least one embodiment, resource orchestrator 1712 may configure or otherwise control one or more nodes CR 1716(1)-1716(N) and / or grouped computing resources 1714. In at least one embodiment, resource orchestrator 1712 may include a software design infrastructure (“SDI”) management entity for data center 1700. In at least one embodiment, resource orchestrator may include hardware, software, or some combination thereof.

[0087] In at least one embodiment shown in FIG. 17 , framework layer 1720 includes job scheduler 1732, configuration manager 1734, resource manager 1736, and distributed file system 1738. In at least one embodiment, framework layer 1720 may include frameworks to support software 1732 in software layer 1730 and / or one or more applications 1742 in application layer 1740. In at least one embodiment, software 1732 or applications 1742 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1720 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark® (hereinafter “Spark”), which can use distributed file system 1738 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1732 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 1700. In at least one embodiment, configuration manager 1734 may be capable of configuring different tiers, such as software tier 1730 and framework tier 1720, which includes Spark and distributed file system 1738 to support large-scale data processing. In at least one embodiment, resource manager 1736 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 1738 and job scheduler 1732. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1714 in data center infrastructure tier 1710.In at least one embodiment, resource manager 1736 may work in conjunction with resource orchestrator 1712 to manage these mappings or allocated computing resources.

[0088] In at least one embodiment, software 1732 included in software layer 1730 may include software used by nodes CR 1716(1)-1716(N), grouped computing resources 1714, and / or at least a portion of distributed file system 1738 of framework layer 1720. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0089] In at least one embodiment, applications 1742 included in application layer 1740 may include one or more types of applications used by at least a portion of nodes CR 1716(1)-1716(N), grouped computing resources 1714, and / or distributed file system 1738 of framework layer 1720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and machine learning applications including training or inference software, machine learning framework software (e.g., PyTorch, Tensorflow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0090] In at least one embodiment, any of configuration manager 1734, resource manager 1736, and resource orchestrator 1712 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable a data center operator of data center 1700 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0091] In at least one embodiment, data center 1700 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1700. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1700 by using weight parameters calculated by one or more techniques described herein.

[0092] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0093] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in the system of Figure 17 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0094] Autonomous Vehicles 18A illustrates an example of an autonomous vehicle 1800 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1800 (alternatively referred to herein as “vehicle 1800”) may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 1800 may be a semi-tractor trailer truck for transporting cargo. In at least one embodiment, the vehicle 1800 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0095] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In one or more embodiments, vehicle 1800 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1800 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0096] In at least one embodiment, vehicle 1800 may include components such as, without limitation, a chassis, a vehicle body, wheels (2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1800 may include a propulsion system 1850 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1850 may be coupled to a drive train of vehicle 1800, which may include, without limitation, a transmission to enable propulsion of vehicle 1800. In at least one embodiment, propulsion system 1850 may be controlled in response to receiving a signal from throttle / accelerator 1852.

[0097] In at least one embodiment, steering system 1854, which may include without limitation a steering wheel, is used to steer vehicle 1800 (e.g., along a desired path or route) when propulsion system 1850 is operating (e.g., when the vehicle is moving). In at least one embodiment, steering system 1854 may receive signals from steering actuator 1856. The steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1846 may be used to operate vehicle brakes in response to receiving signals from brake actuator 1848 and / or brake sensor.

[0098] In at least one embodiment, controller 1836, which may include, without limitation, one or more systems on a chip (“SoC”) (not shown in FIG. 18A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1800. For example, in at least one embodiment, controller 1836 may send signals to operate vehicle brakes via brake actuators 1848, steering system 1854 via steering actuators 1856, and propulsion system 1850 via throttle / accelerator 1852. Controller 1836 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1800. In at least one embodiment, the controllers 1836 may include a first controller 1836 for autonomous driving functions, a second controller 1836 for functional safety functions, a third controller 1836 for artificial intelligence functions (e.g., computer vision), a fourth controller 1836 for infotainment functions, a fifth controller 1836 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1836 may handle two or more of the above functionalities, two or more controllers 1836 may handle a single functionality, and / or some combination thereof.

[0099] In at least one embodiment, controller 1836 provides signals to control one or more components and / or systems of vehicle 1800 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system (“GNSS”) sensors 1858 (e.g., global positioning system sensors), RADAR sensors 1860, ultrasonic sensors 1862, LIDAR sensors 1864, inertial measurement units (“IMUs”), and the like. The vehicle 1800 vehicle information may be received from sensors 1866 (e.g., accelerometers, gyroscopes, magnetic compasses, magnetometers, etc.), microphones 1896, stereo cameras 1868, wide-angle cameras 1870 (e.g., fisheye cameras), infrared cameras 1872, ambient cameras 1874 (e.g., 360-degree cameras), long-range cameras (not shown in FIG. 18A ), mid-range cameras (not shown in FIG. 18A ), speed sensors 1844 (e.g., for measuring the speed of the vehicle 1800), vibration sensors 1842, steering sensors 1840, brake sensors (e.g., as part of brake sensor system 1846), and / or other types of sensors.

[0100] In at least one embodiment, one or more of controllers 1836 may receive input (e.g., represented by input data) from instrument cluster 1832 of vehicle 1800 and provide output (e.g., represented by output data, display data, etc.) via human-machine interface (“HMI”) display 1834, audible annunciators, loudspeakers, and / or via other components of vehicle 1800. In at least one embodiment, the output may include information such as vehicle speed, speeding, time, map data (e.g., a high definition map (not shown in FIG. 18A )), location data (e.g., the location of the vehicle 1800 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object conditions sensed by the controller 1836, etc. For example, in at least one embodiment, the HMI display 1834 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0101] In at least one embodiment, vehicle 1800 further includes network interface 1824, which may use a wireless antenna 1826 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 1824 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. Additionally, in at least one embodiment, the wireless antenna 1826 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using a local area network such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or a low power wide-area network ("LPWAN") such as LoRaWAN or SigFox.

[0102] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in the system of Figure 18A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0103] 18B illustrates example camera locations and fields of view for autonomous vehicle 1800 of FIG. 18A according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are exemplary examples and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on vehicle 1800.

[0104] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1800. The camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0105] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0106] In at least one embodiment, one or more of the cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from the interior of the vehicle (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate conforms to the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. For side view cameras, in at least one embodiment, the cameras may again be integrated into the four pillars at each corner of the cabin.

[0107] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of vehicle 1800 may be used for a surroundings view to facilitate identification of the forward path and obstacles, and may be used in conjunction with controller 1836 and / or one or more of the control SoCs to assist in generating an occupancy grid and / or providing information essential for determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0108] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1870 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While FIG. 18B shows only one wide-angle camera 1870, in other embodiments, there may be any number (including zero) of wide-angle cameras 1870 on the vehicle 1800. In at least one embodiment, any number of long-range cameras 1898 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 1898 may also be used for object detection and classification, as well as basic object tracking.

[0109] In at least one embodiment, any number of stereo cameras 1868 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 1868 may include an integrated control unit with a scalable processing unit, which may provide a programmable gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1800 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1868 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 1800 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1868 may be used in addition to or instead of those described herein.

[0110] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of vehicle 1800 (e.g., side view cameras) may be used for the surroundings view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 1874 (e.g., four surrounding cameras 1874 as shown in FIG. 18B ) may be disposed on vehicle 1800. Surrounding cameras 1874 may include, without limitation, any number and combination of wide-angle cameras 1870, fisheye cameras, and / or 360-degree cameras. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of vehicle 1800. In at least one embodiment, vehicle 1800 may use three surrounding cameras 1874 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0111] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1800 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras also suitable as front cameras described herein (e.g., long-range camera 1898, and / or mid-range camera 1876, stereo camera 1868, infrared camera 1872, etc.).

[0112] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in the system of Figure 18B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0113] FIG. 18C is a block diagram illustrating an example system architecture for the autonomous vehicle 1800 of FIG. 18A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1800 of FIG. 18C is shown as connected via a bus 1802. In at least one embodiment, the bus 1802 may include, without limitation, a CAN data interface (alternatively referred to herein as a (CAN bus)). In at least one embodiment, the CAN may be a network internal to the vehicle 1800 used to assist in controlling various features and functions of the vehicle 1800, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1802 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1802 may be read to determine steering angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1802 may be an ASIL B compliant CAN bus.

[0114] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or instead of CAN. In at least one embodiment, any number of buses 1802 may be present, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1802 may be used to perform different functions and / or to provide redundancy. For example, a first bus 1802 may be used for collision avoidance functions and a second bus 1802 may be used for actuation control. In at least one embodiment, each bus 1802 may communicate with any of the components of vehicle 1800, or two or more buses 1802 may communicate with the same component. In at least one embodiment, each of any number of systems on a chip (“SoC”) 1804, each of the controllers 1836, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 1800) and may be connected to a common bus, such as a CAN bus.

[0115] In at least one embodiment, vehicle 1800 may include one or more controllers 1836, such as those described herein with respect to FIG. 18A . Controller 1836 may be used for a variety of functions. In at least one embodiment, controller 1836 may be coupled to any of a variety of other components and systems of vehicle 1800 and may be used to control vehicle 1800, artificial intelligence of vehicle 1800, and / or infotainment of vehicle 1800, etc.

[0116] In at least one embodiment, vehicle 1800 may include any number of SoCs 1804. Each of SoCs 1804 may include, without limitation, a central processing unit ("CPU") 1806, a graphics processing unit ("GPU") 1808, a processor 1810, a cache 1812, an accelerator 1814, a data store 1816, and / or other components and features not shown. In at least one embodiment, SoCs 1804 may be used to control vehicle 1800 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1804 may be incorporated into a system (e.g., that of vehicle 1800) having a high definition ("HD") map 1822 that can obtain map refreshes and / or updates via a network interface 1824 from one or more servers (not shown in FIG. 18C ).

[0117] In at least one embodiment, CPU 1806 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 1806 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 1806 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1806 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 MB of L2 cache). In at least one embodiment, CPU 1806 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 1806 to be active at any given time.

[0118] In at least one embodiment, one or more of the CPUs 1806 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to conserve dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPUs 1806 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines the best power state for cores, clusters, and CCPLEXes to enter. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0119] In at least one embodiment, GPU 1808 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1808 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1808 may use an extended tensor instruction set. In one embodiment, GPU 1808 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1808 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1808 may use a compute application programming interface (API). In at least one embodiment, GPU 1808 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA).

[0120] In at least one embodiment, one or more of the GPUs 1808 may be power-optimized for best performance in automotive and embedded use cases. For example, in one embodiment, the GPUs 1808 may be fabricated on fin field-effect transistors ("FinFETs"). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0121] In at least one embodiment, one or more of the GPUs 1808 may include high bandwidth memory (“HBW”) and / or a 16 GB HBM2 memory subsystem, providing, in some examples, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or in place of the HBM memory.

[0122] In at least one embodiment, the GPU 1808 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU 1808 to directly access the CPU 1806 page tables. In at least one embodiment, when the GPU 1808 memory management unit ("MMU") encounters a miss, an address translation request may be sent to the CPU 1806. In at least one embodiment, in response, the CPU 1806 may look up the virtual-to-physical address mapping in its page table and send the translation back to the GPU 1808. In at least one embodiment, the unified memory technology allows for a single, unified virtual address space for both the CPU 1806 and the GPU 1808 memory, thereby simplifying programming the GPU 1808 and porting applications to the GPU 1808.

[0123] In at least one embodiment, GPU 1808 may include any number of access counters that can record the frequency of GPU 1808's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0124] In at least one embodiment, one or more of the SoCs 1804 may include any number of caches 1812, including those described herein. For example, in at least one embodiment, the caches 1812 may include a level 3 (“L3”) cache available to both the CPU 1806 and the GPU 1808 (e.g., connected to both the CPU 1806 and the GPU 1808). In at least one embodiment, the caches 1812 may include a write-back cache that can record line state through the use of a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more, depending on the embodiment, although smaller cache sizes may also be used.

[0125] In at least one embodiment, one or more of the SoCs 1804 may include one or more accelerators 1814 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1804 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1808 and offload some of the GPU 1808's tasks (e.g., freeing up more cycles for the GPU 1808 to perform other tasks). In at least one embodiment, accelerator 1814 may be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0126] In at least one embodiment, the accelerator 1814 (e.g., a hardware-accelerated cluster) may include a deep learning accelerator (“DLA”). The DLA may include, without limitation, one or more tensor processing units (“TPU”), which may be further configured to provide tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized to perform image processing functions (e.g., CNN, RCNN, etc.). The DLA may further be optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the DLA's design allows for improved performance per millimeter over typical general-purpose GPUs, typically far exceeding the performance of a CPU. In at least one embodiment, the TPU may perform several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, a CNN for object identification and detection using data from a camera sensor, a CNN for distance estimation using data from a camera sensor, a CNN for emergency vehicle detection and identification using data from microphone 1896, a CNN for face recognition and vehicle owner identification using data from a camera sensor, and / or a CNN for security and / or safety events.

[0127] In at least one embodiment, the DLA may perform any function of the GPU 1808, and a designer may target either the DLA or the GPU 1808 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 1808 and / or other accelerators 1814.

[0128] In at least one embodiment, the accelerator 1814 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1838, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. The PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0129] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any of the cameras described herein), an image signal processor, and / or the like. In at least one embodiment, each of the RISC cores may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0130] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 1806. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0131] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0132] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0133] In at least one embodiment, the accelerator 1814 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 1814. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM consisting of eight field-configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0134] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0135] In at least one embodiment, one or more of the SoCs 1804 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0136] In at least one embodiment, accelerator 1814 (e.g., a hardware accelerator cluster) has diverse uses for autonomous driving. In at least one embodiment, the PVA may be a programmable vision accelerator that can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA works well for semi-dense or dense regular computations that require low-latency, low-power, and predictable run-times, even with small data sets. In at least one embodiment, in an autonomous vehicle such as vehicle 1800, the PVA is designed to run traditional computer vision algorithms because they are effective for object detection and integer arithmetic.

[0137] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0138] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0139] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence may further enable the system to make decisions regarding which detections should be considered positive detections rather than false detections. For example, in at least one embodiment, the system may set a threshold for confidence and consider only detections that exceed the threshold to be positive detections. In embodiments where automatic emergency braking (“AEB”) is used, a false detection may cause the vehicle to automatically apply the emergency brakes, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as, among others, the bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from an IMU sensor 1866 that correlates with the orientation of the vehicle 1800, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 1864 or a RADAR sensor 1860).

[0140] In at least one embodiment, one or more of the SoCs 1804 may include a data store 1816 (e.g., memory). In at least one embodiment, the data store 1816 may be on-chip memory of the SoC 1804, which may store neural networks running on the GPU 1808 and / or DLA. In at least one embodiment, the capacity of the data store 1816 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1816 may comprise an L2 or L3 cache.

[0141] In at least one embodiment, one or more of the SoCs 1804 may include any number of processors 1810 (e.g., embedded processors). The processors 1810 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1804 and may provide run-time power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 1804, and / or manage the power state of the SoC 1804. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1804 may use the ring oscillator to detect the temperature of the CPU 1806, GPU 1808, and / or accelerator 1814. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 1804 in a low power state, and / or place the vehicle 1800 in a driver-safety shutdown mode (e.g., bring the vehicle 1800 to a safety shutdown).

[0142] In at least one embodiment, processor 1810 may further include a set of embedded processors capable of serving as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that includes a digital signal processor with dedicated RAM.

[0143] In at least one embodiment, processor 1810 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0144] In at least one embodiment, the processor 1810 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor 1810 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to handling real-time camera management. In at least one embodiment, the processor 1810 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0145] In at least one embodiment, processor 1810 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 1870, surrounding camera 1874, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 1804 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0146] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0147] In at least one embodiment, the video image composer may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image composer may also be used to composite a user interface when the operating system desktop is in use, eliminating the need for the GPU 1808 to continually render new surfaces. In at least one embodiment, the video image composer may be used to offload the GPU 1808 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0148] In at least one embodiment, one or more of the SoCs 1804 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1804 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0149] In at least one embodiment, one or more of the SoCs 1804 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. The SoCs 1804 may be used to process data from cameras (e.g., connected via gigabit multimedia serial links and Ethernet), data from sensors (e.g., LIDAR sensors 1864, RADAR sensors 1860, etc., which may be connected via Ethernet), data from bus 1802 (e.g., vehicle 1800 speed, steering wheel position, etc.), data from GNSS sensors 1858 (e.g., connected via Ethernet or CAN bus), etc. In at least one embodiment, one or more of the SoCs 1804 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 1806.

[0150] In at least one embodiment, the SoC 1804 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC 1804 is faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 1814, when combined with the CPU 1806, GPU 1808, and data store 1816, can provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0151] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language, such as the C programming language, to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0152] Embodiments described herein enable multiple neural networks to run simultaneously and / or sequentially, and the results can be combined to enable Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, the CNN running on the DLA or a separate GPU (e.g., GPU1820) may include text and word recognition, enabling the supercomputer to read and understand traffic signs, including signs for which the neural network was not specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0153] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Indicates Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Indicates Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 1808.

[0154] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1800. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves the vehicle. In this way, the SoC 1804 provides security against theft and / or carjacking.

[0155] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1896 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1804 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1858. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in the United States, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program for executing an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 1862 until the emergency vehicle has passed.

[0156] In at least one embodiment, vehicle 1800 may include a CPU 1818 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 1804 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 1818 may include, for example, an X86 processor. CPU 1818 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 1804 and / or monitoring the status and health of controller 1836 and / or infotainment system on a chip (“infotainment SoC”) 1830.

[0157] In at least one embodiment, vehicle 1800 may include a GPU 1820 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 1804 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, GPU 1820 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1800.

[0158] In at least one embodiment, vehicle 1800 may further include a network interface 1824, which may include, without limitation, a wireless antenna 1826 (e.g., one or more wireless antennas 1826 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1824 may be used to enable wireless connectivity over the Internet with the cloud (e.g., servers and / or other network devices), other vehicles, and / or computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1800 and the other vehicles, and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link may provide vehicle 1800 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1800). In at least one embodiment, the above-described functionality may be part of a cooperative adaptive cruise control function of the vehicle 1800.

[0159] In at least one embodiment, network interface 1824 may include an SoC that provides modulation and demodulation functionality and enables controller 1836 to communicate over a wireless network. In at least one embodiment, network interface 1824 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, radio frequency front-end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0160] In at least one embodiment, vehicle 1800 may further include a data store 1828, which may include, without limitation, off-chip (e.g., not on SoC 1804) storage. In at least one embodiment, data store 1828 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0161] In at least one embodiment, vehicle 1800 may further include GNSS sensors 1858 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1858 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0162] In at least one embodiment, vehicle 1800 may further include RADAR sensor 1860. RADAR sensor 1860 may be used by vehicle 1800 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. RADAR sensor 1860 may use CAN and / or bus 1802 for control (e.g., to transmit data generated by RADAR sensor 1860) and to access object tracking data, and in some examples, may have Ethernet access to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 1860 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 1860 are pulse-Doppler RADAR sensors.

[0163] In at least one embodiment, the RADAR sensor 1860 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 meter range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1860 may help distinguish between static and moving objects and may be used by the ADAS system 1838 to provide emergency braking assistance and forward collision warning. The sensors 1860 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1800 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting vehicle 1800's lane.

[0164] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1860 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1838 to provide blind spot detection and / or lane change assistance.

[0165] In at least one embodiment, vehicle 1800 may further include ultrasonic sensors 1862. Ultrasonic sensors 1862 may be located at the front, rear, and / or sides of vehicle 1800 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1862 may be used, and different ultrasonic sensors 1862 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 1862 may operate at functional safety level ASIL B.

[0166] In at least one embodiment, vehicle 1800 may include LIDAR sensor 1864. LIDAR sensor 1864 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor 1864 may be functional safety level ASIL B. In at least one embodiment, vehicle 1800 may include multiple LIDAR sensors 1864 (e.g., two, four, six, etc.), which may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0167] In at least one embodiment, the LIDAR sensor 1864 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1864 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors 1864 may be used. In such an embodiment, the LIDAR sensor 1864 may be implemented as a small device that can be integrated into the front, rear, sides, and / or corners of the vehicle 1800. In at least one embodiment, the LIDAR sensor 1864 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1864 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0168] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1800 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1800 to the object. In at least one embodiment, flash LIDAR allows a highly accurate, distortion-free image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 1800. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0169] In at least one embodiment, the vehicle may further include an IMU sensor 1866. In at least one embodiment, the IMU sensor 1866 may be positioned at the center of the rear axle of the vehicle 1800. In at least one embodiment, the IMU sensor 1866 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, the IMU sensor 1866 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, the IMU sensor 1866 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0170] In at least one embodiment, the IMU sensor 1866 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1866 enables the vehicle 1800 to estimate its orientation by directly observing changes in velocity and correlating them from the GPS to the IMU sensor 1866 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 1866 and the GNSS sensor 1858 may be combined into a single integrated unit.

[0171] In at least one embodiment, vehicle 1800 may include microphones 1896 located in and / or around vehicle 1800. In at least one embodiment, microphones 1896 may be used for, among other things, detection and identification of emergency vehicles.

[0172] In at least one embodiment, vehicle 1800 may further include any number of camera types, including stereo cameras 1868, wide-angle cameras 1870, infrared cameras 1872, perimeter cameras 1874, long-range cameras 1898, mid-range cameras 1876, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 1800. In at least one embodiment, the types of cameras used vary depending on vehicle 1800. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1800. In at least one embodiment, the number of cameras may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1800 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. The cameras may support, by way of example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera is described in further detail herein above with respect to Figures 18A and 18B.

[0173] In at least one embodiment, vehicle 1800 may further include a vibration sensor 1842. Vibration sensor 1842 may measure vibrations of components of vehicle 1800, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 1842 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0174] In at least one embodiment, vehicle 1800 may include an ADAS system 1838. ADAS system 1838 may include, without limitation, an SoC in some examples. In at least one embodiment, ADAS system(s) 1838 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0175] In at least one embodiment, the ACC system may use a RADAR sensor 1860, a LIDAR sensor 1864, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately preceding the vehicle 1800 and automatically adjusts the speed of the vehicle 1800 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 1800 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0176] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by the network interface 1824 and / or wireless antenna 1826 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, the V2V communication concept provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of the vehicle 1800 and in the same lane), while the I2V communication concept provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of the vehicle 1800 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0177] In at least one embodiment, the FCW system is designed to alert the driver to hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 1860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0178] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 1860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0179] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 1800 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. The LKA system provides steering input or brake control to correct the vehicle 1800 if the vehicle 1800 begins to drift out of its lane.

[0180] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 1860 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0181] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1800. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0182] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major issue because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1800 itself determines whether to follow the results from the primary computer (e.g., first controller 1836) or the secondary computer (e.g., second controller 1836). For example, in at least one embodiment, the ADAS system 1838 may be a backup and / or secondary computer for transmitting perceptual information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on various hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 1838 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0183] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0184] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary and secondary computers. In at least one embodiment, the monitoring MCU's neural network may learn when the secondary computer's output may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the monitoring MCU's neural network may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the monitoring MCU's neural network may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC1804.

[0185] In at least one embodiment, the ADAS system 1838 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides the same overall result, the supervisory MCU may have greater confidence that the overall result is correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0186] In at least one embodiment, the output of the ADAS system 1838 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1838 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained, as described herein, thus reducing the risk of false positives.

[0187] In at least one embodiment, vehicle 1800 may further include an infotainment SoC 1830 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 1830 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 1830 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, reverse parking assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 1800. For example, infotainment SoC 1830 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 1834, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1830 may also be used to provide information (e.g., visual and / or auditory) to a vehicle user, such as information from ADAS system 1838, autonomous driving information such as vehicle maneuver plans, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0188] In at least one embodiment, infotainment SoC 1830 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1830 may communicate with other devices, systems, and / or components of vehicle 1800 via bus 1802 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, infotainment SoC 1830 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 1836 (e.g., vehicle 1800's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1830 may place vehicle 1800 in a driver-safety shutdown mode, as described herein.

[0189] In at least one embodiment, vehicle 1800 may further include an instrument cluster 1832 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). The instrument cluster 1832 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, the instrument cluster 1832 may include any number and combination of instruments, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1830 and instrument cluster 1832. In at least one embodiment, the instrument cluster 1832 may be included as part of the infotainment SoC 1830, or vice versa.

[0190] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in the system of Figure 18C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0191] 18D is a diagram of a system 1876 for communicating between a cloud-based server and the autonomous vehicle 1800 of FIG. 18A , according to at least one embodiment. In at least one embodiment, the system 1876 may include any number and type of vehicles, including, without limitation, a server 1878, a network 1890, and a vehicle 1800. The server 1878 may include, without limitation, multiple GPUs 1884(A)-1884(H) (collectively referred to herein as GPUs 1884), PCIe switches 1882(A)-1882(H) (collectively referred to herein as PCIe switches 1882), and / or CPUs 1880(A)-1880(B) (collectively referred to herein as CPUs 1880). The GPUs 1884, CPUs 1880, and PCIe switches 1882 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 1888 developed by NVIDIA, and / or a PCIe connection 1886. In at least one embodiment, the GPUs 1884 are connected to each other via an NVLink and / or NVS switch SoC, and the GPUs 1884 and PCIe switches 1882 are connected via a PCIe interconnect. In at least one embodiment, eight GPUs 1884, two CPUs 1880, and four PCIe switches 1882 are illustrated, but this is not intended to be limiting. In at least one embodiment, each of the servers 1878 may include any number of GPUs 1884, CPUs 1880, and / or PCIe switches 1882 in any combination, without limitation. For example, in at least one embodiment, the servers 1878 may each include 8, 16, 32, and / or more GPUs 1884.

[0192] In at least one embodiment, server 1878 may receive image data from the vehicle over network 1890 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1878 may transmit neural network 1892, updated neural network 1892, and / or map information 1894, including, without limitation, information regarding traffic and road conditions, to the vehicle over network 1890. In at least one embodiment, updates to map information 1894 may include, without limitation, updates to HD map 1822, such as information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 1892, updated neural network 1892, and / or map information 1894 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1878 and / or other servers).

[0193] In at least one embodiment, server 1878 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. The training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 1890) and / or used by server 1878 to remotely monitor the vehicle.

[0194] In at least one embodiment, server 1878 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 1878 may include a deep learning supercomputer and / or dedicated AI computer powered by a GPU 1884, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1878 may also include a deep learning infrastructure using a CPU-powered data center.

[0195] In at least one embodiment, the deep learning infrastructure of server 1878 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1800. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1800, such as a series of images and / or objects that vehicle 1800 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by vehicle 1800; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1800 has failed, server 1878 may send a signal to vehicle 1800 instructing the fail-safe computer of vehicle 1800 to take control, notify the occupants, and complete a safe stopping maneuver.

[0196] In at least one embodiment, server 1878 may include a GPU 1884 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 1515 is used to execute one or more embodiments. Details regarding hardware structure 1515 are provided herein in conjunction with FIG. 15A and / or FIG. 15B.

[0197] Computer Systems 19 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof 1900 formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1900 may include components such as, without limitation, a processor 1902 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1900 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1900 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0198] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0199] In at least one embodiment, computer system 1900 may include, without limitation, a processor 1902, which may include one or more execution units 1908 for performing training and / or inference of machine learning models according to the techniques described herein. In at least one embodiment, system 19 is a single-processor desktop or server system, while in other embodiments, system 19 may be a multiprocessor system. In at least one embodiment, processor 1902 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1902 may be coupled to a processor bus 1910, which may transmit digital signals between processor 1902 and other components within computer system 1900.

[0200] In at least one embodiment, processor 1902 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1904. In at least one embodiment, processor 1902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1902. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1906 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0201] In at least one embodiment, processor 1902 also includes an execution unit 1908, including, without limitation, logic for performing integer and floating-point operations. Processor 1902 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1908 may include logic for a packed instruction set 1909. In at least one embodiment, including the packed instruction set 1909, along with associated circuitry for executing the instructions, in the instruction set of general-purpose processor 1902 allows operations used by many multimedia applications to be performed using packed data in general-purpose processor 1902. In one or more embodiments, many multimedia applications can be accelerated and run more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0202] In at least one embodiment, execution unit 1908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1900 may include, without limitation, memory 1920. In at least one embodiment, memory 1920 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. Memory 1920 may store instructions 1919 and / or data 1921 represented by data signals that may be executed by processor 1902.

[0203] In at least one embodiment, a system logic chip may be coupled to the processor bus 1910 and the memory 1920. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1916, and the processor 1902 may communicate with the MCH 1916 via the processor bus 1910. In at least one embodiment, the MCH 1916 may provide a high-bandwidth memory path 1918 to the memory 1920 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1916 may route data signals between the processor 1902, the memory 1920, and other components of the computer system 1900, and may bridge data signals between the processor bus 1910, the memory 1920, and the system I / O 1922. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1916 may be coupled to memory 1920 via a high-bandwidth memory path 1918, and the graphics / video card 1912 may be coupled to the MCH 1916 via an Accelerated Graphics Port (“AGP”) interconnect 1914.

[0204] In at least one embodiment, computer system 1900 may use system I / O 1922, a proprietary hub interface bus, to couple MCH 1916 to I / O controller hub (“ICH”) 1930. In at least one embodiment, ICH 1930 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1920, a chipset, and processor 1902. Examples may include, without limitation, an audio controller 1929, a firmware hub ("flash BIOS") 1928, a wireless transceiver 1926, data storage 1924, a legacy I / O controller 1923 including a user input and keyboard interface, a serial expansion port 1927 such as a Universal Serial Bus ("USB"), and a network controller 1934. Data storage 1924 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0205] In at least one embodiment, FIG. 19 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, FIG. 19 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in FIG. 19 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1900 may be interconnected using a compute express link (CXL) interconnect.

[0206] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in the system of Figure 19 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0207] 20 is a block diagram illustrating an electronic device 2000 for utilizing a processor 2010, according to at least one embodiment. In at least one embodiment, the electronic device 2000 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0208] In at least one embodiment, system 2000 may include a processor 2010 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, including, without limitation, processor 2010 coupled using a bus or interface, such as an I / C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 20 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, FIG. 20 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in FIG. 20 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 20 may be interconnected using a Compute Express Link (CXL) interconnect.

[0209] In at least one embodiment, FIG. 20 illustrates a display 2024, a touch screen 2025, a touch pad 2030, a Near Field Communications unit ("NFC") 2045, a sensor hub 2040, a thermal sensor 2046, an Express Chipset ("EC") 2035, a Trusted Platform Module ("TPM") 2038, a BIOS / firmware / flash memory ("BIOS,FW flash") 2022, a DSP 2060, a drive ("SSD or HDD") 2020, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") ... touch screen 2030, a touch pad 2030, a touch screen 2030, a touch pad 2030, a touch screen 2030, a touch pad 2030, a touch screen 2030, a touch screen 2030, a touch screen 2030, a touch screen 2030, a touch screen 2030, a touch screen 2030, a touch screen 2030, a touch screen 2030, a touch screen 203 The memory may include a Bluetooth unit 2050, a Bluetooth unit 2052, a Wireless Wide Area Network unit (“WWAN”) 2056, a Global Positioning System (GPS) 2055, a camera such as a USB 3.0 camera (“USB 3.0 camera”) 2054, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 2015, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0210] In at least one embodiment, other components may be communicatively coupled to the processor 2010 via the components described above. In at least one embodiment, an accelerometer 2041, an ambient light sensor (“ALS”) 2042, a compass 2043, and a gyroscope 2044 may be communicatively coupled to the sensor hub 2040. In at least one embodiment, a thermal sensor 2039, a fan 2037, a keyboard 2046, and a touchpad 2030 may be communicatively coupled to the EC 2035. In at least one embodiment, a speaker 2063, headphones 2064, and a microphone (“mic”) 2065 may be communicatively coupled to an audio unit (audio codec and class D amplifier) ​​2062, which may be communicatively coupled to the DSP 2060. In at least one embodiment, the audio unit 2064 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 2057 may be communicatively coupled to the WWAN unit 2056. In at least one embodiment, components such as the WLAN unit 2050 and Bluetooth unit 2052, and the WWAN 2056 may be implemented in a Next Generation Form Factor (“NGFF”).

[0211] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in the system of Figure 20 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0212] 21 illustrates, according to at least one embodiment, a computer system 2100. In at least one embodiment, the computer system 2100 is configured to implement the various processes and methods described throughout this disclosure.

[0213] In at least one embodiment, computer system 2100 includes at least one central processing unit ("CPU") 2102 connected to a communication bus 2110 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 2100 includes main memory 2104 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 2104, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 2122 provides an interface with other computing devices and networks to receive data from other systems and transmit data from computer system 2100 to other systems.

[0214] In at least one embodiment, computer system 2100 includes, without limitation, input device(s) 2108, a parallel processing system 2112, and a display device 2106, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 2108, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the above modules may be located on a single semiconductor platform to form a processing system.

[0215] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, training logic 1515 may be used in the system of Figure 21 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0216] 22 illustrates a computer system 2200 according to at least one embodiment. In at least one embodiment, computer system 2200 may include, without limitation, a computer 2210 and a USB stick 2220. In at least one embodiment, computer system 2210 may include, without limitation, any number and type of processor (not shown) and memory. In at least one embodiment, computer 2210 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0217] In at least one embodiment, USB stick 2220 includes, without limitation, a processing unit 2230, a USB interface 2240, and USB interface logic 2250. In at least one embodiment, processing unit 2230 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 2230 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing core 2230 comprises an application specific integrated circuit ("ASIC") optimized to perform any quantity and type of operations related to machine learning. For example, in at least one embodiment, processing core 2230 is a tensor processing unit ("TPC") optimized to perform machine learning inference operations. In at least one embodiment, processing core 2230 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0218] In at least one embodiment, USB interface 2240 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 2240 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 2240 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 2250 may include any amount and type of logic that enables processing unit 2230 to interface with a device (e.g., computer 2210) via USB connector 2240.

[0219] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in the system of Figure 22 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0220] 23A illustrates an exemplary architecture in which multiple GPUs 2310-2313 are communicatively coupled to multiple multi-core processors 2305-2306 via high-speed links 2340-2343 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 2340-2343 support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. Various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[0221] Additionally, in one embodiment, two or more of the GPUs 2310-2313 are interconnected via high-speed links 2329-2330, which may be implemented using the same or different protocol / links as used for the high-speed links 2340-2343. Similarly, two or more of the multi-core processors 2305-2306 may be connected via high-speed link 2328, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 23A may be achieved using the same protocol / links (e.g., via a common interconnect fabric).

[0222] In one embodiment, each multi-core processor 2305-2306 is communicatively coupled to processor memory 2301-2302 via a memory interconnect 2326-2327, respectively, and each GPU 2310-2313 is communicatively coupled to GPU memory 2320-2323 via a GPU memory interconnect 2350-2353, respectively. The memory interconnects 2326-2327 and 2350-2353 may utilize the same or different memory access technologies. By way of example, and not limitation, the processor memory 2301-2302 and the GPU memory 2320-2323 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-RAM. In one embodiment, some portions of processor memory 2301-2302 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0223] As described herein, the various processors 2305-2306 and GPUs 2310-2313 may each be physically coupled to a particular memory 2301-2302, 2320-2323, but a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among the various physical memories. For example, the processor memories 2301-2302 may each have 64 GB of system memory address space, and the GPU memories 2320-2323 may each have 32 GB of system memory address space (resulting in this example in a total of 256 GB of addressable memory).

[0224] 23B shows further details of the interconnection between multi-core processor 2307 and graphics acceleration module 2346 according to one example embodiment. Graphics acceleration module 2346 may include one or more GPU chips integrated on a line card that is coupled to processor 2307 via high-speed link 2340. Alternatively, graphics acceleration module 2346 may be integrated in the same package or chip as processor 2307.

[0225] In at least one embodiment, the illustrated processor 2307 includes multiple cores 2360A-2360D, each having a translation lookaside buffer 2361A-2361D and one or more caches 2362A-2362D. In at least one embodiment, the cores 2360A-2360D may include various other components (not shown) for executing instructions and processing data. The caches 2362A-2362D may comprise level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 2356 may be included in the caches 2362A-2362D and shared by the set of cores 2360A-2360D. For example, one embodiment of the processor 2307 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. The processor 2307 and graphics acceleration module 2346 are connected to system memory 2314, which may include processor memories 2301-2302 of FIG. 23A.

[0226] Coherence is maintained for data and instructions stored in the various caches 2362A-2362D, 2356, and system memory 2314 through inter-core communication via coherence bus 2364. For example, each cache may have associated cache coherence logic / circuitry for communicating via coherence bus 2364 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 2364 to monitor cache accesses.

[0227] In one embodiment, proxy circuit 2325 communicatively couples graphics acceleration module 2346 to coherence bus 2364 to enable graphics acceleration module 2346 to participate in cache coherence protocols as a peer of cores 2360A-2360D. In particular, interface 2335 provides a connection to proxy circuit 2325 over high-speed link 2340 (e.g., PCIe bus, NVLink, etc.), and interface 2337 connects graphics acceleration module 2346 to link 2340.

[0228] In one implementation, the accelerator integrated circuit 2336 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 2331, 2332, N of the graphics acceleration module 2346. The graphics processing engines 2331, 2332, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 2331, 2332, N may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 2346 may be a GPU having multiple graphics processing engines 2331-2332, N, or the graphics processing engines 2331-2332, N may be individual GPUs integrated into a common package, line card, or chip.

[0229] In one embodiment, the accelerator integrated circuitry 2336 includes a memory management unit (MMU) 2339 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing the system memory 2314. The MMU 2339 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 2338 stores commands and data for efficient access by the graphics processing engines 2331-2332, N. In one embodiment, data stored in the cache 2338 and the graphics memory 2333-2334, M is kept coherent with the core caches 2362A-2362D, 2356, and the system memory 2314. As noted above, this may be achieved via proxy circuitry 2353 on behalf of cache 2338 and memory 2333-2334, M (e.g., sending updates regarding modifications / accesses of cache lines in processor caches 2362A-2362D, 2356 to cache 2338 and receiving updates from cache 2338).

[0230] A set of registers 2345 stores context data for threads executed by the graphics processing engines 2331-2332, N, and a context management circuit 2348 manages thread contexts. For example, the context management circuit 2348 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 2348 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 2348 may restore the register values. In one embodiment, the interrupt management circuit 2347 receives and processes interrupts received from system devices.

[0231] In one implementation, virtual / effective addresses from the graphics processing engine 2331 are translated to real / physical addresses in the system memory 2314 by the MMU 2339. One embodiment of the accelerator integration circuit 2336 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 2346 and / or other accelerator devices. The graphics accelerator modules 2346 may be dedicated to a single application running on the processor 2307 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 2331-2332, N, are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0232] In at least one embodiment, the accelerator integrated circuitry 2336 acts as a bridge to the system for the graphics acceleration module 2346, providing address translation and system memory caching services. Additionally, the accelerator integrated circuitry 2336 may provide a virtualization facility for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 2331-2332.

[0233] The hardware resources of the graphics processing engines 2331-2332, N are explicitly mapped into the real address space seen by the host processor 2307, so that any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuitry 2336 is to physically separate the graphics processing engines 2331-2332, N so that they appear as independent units to the system.

[0234] In at least one embodiment, one or more graphics memories 2333-2334, M are respectively coupled to each of the graphics processing engines 2331-2332, N. The graphics memories 2333-2334, M store instructions and data that are processed by the respective graphics processing engines 2331-2332, N. The graphics memories 2333-2334, M may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0235] In one embodiment, to reduce data traffic over link 2340, a biasing technique is used to ensure that the data stored in graphics memory 2333-2334, M is data that will be most frequently used by graphics processing engines 2331-2332, N, and preferably is data that is not used (or at least not frequently used) by cores 2360A-2360D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and therefore preferably not needed by graphics processing engines 2331-2332, N) in the cores' caches 2362A-2362D, 2356 and system memory 2314.

[0236] FIG. 23C shows another exemplary embodiment in which the accelerator integration circuitry 2336 is integrated within the processor 2307. In at least this embodiment, the graphics processing engines 2331-2332, N communicate directly with the accelerator integration circuitry 2336 via high-speed link 2340 via interface 2337 and interface 2335 (again, any form of bus or interface protocol can be utilized). The accelerator integration circuitry 2336 may perform the same operations as described with respect to FIG. 23B, but may potentially operate at a higher throughput given its proximity to the coherence bus 2364 and caches 2362A-2362D, 2356. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integration circuitry 2336 and a programming model controlled by the graphics acceleration module 2346.

[0237] In at least one embodiment, graphics processing engines 2331-2332, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 2331-2332, N, achieving virtualization within a VM / partition.

[0238] In at least one embodiment, the graphics processing engines 2331-2332, N may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize the graphics processing engines 2331-2332, N and allow access by each operating system. In a single-partition system without a hypervisor, the graphics processing engines 2331-2332, N are owned by the operating system. In at least one embodiment, the operating system may virtualize the graphics processing engines 2331-2332, N and provide access to each process or application.

[0239] In at least one embodiment, the graphics acceleration module 2346 or the individual graphics processing engines 2331-2332,N selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 2314 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engines 2331-2332,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0240] FIG. 23D illustrates an exemplary accelerator integration slice 2390. As used herein, a "slice" comprises a designated portion of the processing resources of the accelerator integration circuitry 2336. An application effective address space 2382 in system memory 2314 stores a process element 2383. In one embodiment, the process element 2383 is stored in response to a GPU call 2381 from an application 2380 executing on the processor 2307. The process element 2383 contains the process state of the corresponding application 2380. A work descriptor (WD) 2384 contained in the process element 2383 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 2384 is a pointer to a job request queue in the application's address space 2382.

[0241] The graphics acceleration module 2346 and / or the individual graphics processing engines 2331-2332, N may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD2384 to the graphics acceleration module 2346 to start a job in a virtualized environment.

[0242] In at least one embodiment, the dedicated process programming model is implementation specific, in which a single process owns the graphics acceleration module 2346 or an individual graphics processing engine 2331. Because the graphics acceleration module 2346 is owned by a single process, when the graphics acceleration module 2346 is allocated, the hypervisor initializes the accelerator integration circuitry 2336 for the owning partition, and the operating system initializes the accelerator integration circuitry 2336 for the owning process.

[0243] In operation, the WD fetch unit 2391 in the accelerator integrated slice 2390 fetches the next WD 2384, which contains an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 2346. As shown, data from the WD 2384 is stored in registers 2345 and may be used by the MMU 2339, the interrupt management circuit 2347, and / or the context management circuit 2348. For example, one embodiment of the MMU 2339 includes segment / page walk circuitry for accessing a segment / page table 2386 in the OS virtual address space 2385. The interrupt management circuit 2347 may process interrupt events 2392 received from the graphics acceleration module 2346. When performing graphics operations, the effective addresses 2393 generated by the graphics processing engines 2331-2332, N are translated into real addresses by the MMU 2339.

[0244] In one embodiment, the same set of registers 2345 may be replicated for each graphics processing engine 2331-2332, N, and / or graphics acceleration module 2346 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 2390. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 8]

[0245] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 9]

[0246] In one embodiment, each WD 2384 is specific to a particular graphics acceleration module 2346 and / or graphics processing engine 2331-2332, N. WD 2384 contains all the information the graphics processing engine 2331-2332, N needs to do its work, or it can be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0247] 23E shows further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 2398 in which a process element list 2399 is stored. The hypervisor real address space 2398 is accessible through a hypervisor 2396 that virtualizes the graphics acceleration module engine of the operating system 2395.

[0248] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 2346. There are two programming models in which the graphics acceleration module 2346 is shared by multiple processes and partitions: time-slice shared and graphics-directed shared.

[0249] In this model, the system hypervisor 2396 owns the graphics acceleration module 2346 and makes its functions available to all operating systems 2395. In order for the graphics acceleration module 2346 to support virtualization by the system hypervisor 2396, the graphics acceleration module 2346 may comply with the following: 1) an application's job request must be autonomous (i.e., no state needs to be maintained between jobs) or the graphics acceleration module 2346 must provide a mechanism for saving and restoring context. 2) the application's job request must be guaranteed by the graphics acceleration module 2346 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 2346 must provide the ability to preempt job processing. 3) the graphics acceleration module 2346 must ensure fairness between processes when operating in a specified shared programming model.

[0250] In at least one embodiment, the application 2380 must make a system call to the operating system 2395 with a graphics acceleration module 2346 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module 2346 type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module 2346 type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 2346 and may be in the form of a graphics acceleration module 2346 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by the graphics acceleration module 2346. In one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. If the implementation of the accelerator integrated circuit 2336 and the graphics acceleration module 2346 does not support a User Permission Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. The hypervisor 2396 may optionally apply the current Permission Mask Override Register (AMOR) value before placing the AMR in the process element 2383. In at least one embodiment, the CSRP is one of the registers 2345 that contains the effective address of an area in the application's address space 2382 for the graphics acceleration module 2346 to save and restore context state. This pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0251] Upon receiving the system call, the operating system 2395 may verify that the application 2380 is registered and authorized to use the graphics acceleration module 2346. The operating system 2395 then calls the hypervisor 2396 with the information shown in Table 3. [Table 10]

[0252] Upon receiving the hypervisor call, the hypervisor 2396 verifies that the operating system 2395 is registered and authorized to use the graphics acceleration module 2346. The hypervisor 2396 then places the process element 2383 into the process element linked list of the corresponding graphics acceleration module 2346 type. The process element may include the information shown in Table 4. [Table 11]

[0253] In at least one embodiment, the hypervisor initializes registers 2345 of multiple accelerator integrated slices 2390.

[0254] As shown in Figure 23F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memories 2301-2302 and GPU memories 2320-2323. In this implementation, operations performed on GPUs 2310-2313 utilize the same virtual / effective memory address space as those used to access processor memories 2301-2302, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 2301, a second portion is allocated to second processor memory 2302, a third portion is allocated to GPU memory 2320, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memories 2301-2302 and GPU memories 2320-2323, allowing either processor or GPU to access either physical memory, with virtual addresses mapped to physical memory.

[0255] In one embodiment, bias / coherence management circuits 2394A-2394E in one or more of the MMUs 2339A-2339E ensure cache coherence between the caches of one or more host processors (e.g., 2305) and the caches of the GPUs 2310-2313 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. While multiple instances of bias / coherence management circuits 2394A-2394E are shown in FIG. 23F, the bias / coherence circuits may also be implemented within the MMUs of one or more host processors 2305 and / or within the accelerator integration circuit 2336.

[0256] One embodiment allows the GPU-attached memory 2320-2323 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, the GPU-attached memory 2320-2323 can be accessed as system memory without cumbersome cache coherence overhead, providing a beneficial operating environment for GPU offload. This configuration allows the host processor 2305 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access the GPU-attached memory 2320-2323 without cache coherence overhead can be crucial to the execution time of the offloaded computation. For example, in cases where there is significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 2310-2313. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can be useful in determining the effectiveness of GPU offloading.

[0257] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (i.e., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU-attached memories 2320-2323, with or without a bias cache in the GPU 2310-2313 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, the bias table may be maintained entirely within the GPU.

[0258] In at least one embodiment, the bias table entry associated with each access to GPU-biased memory 2320-2323 is accessed prior to the actual access to the GPU memory, resulting in the following actions: First, a local request from a GPU 2310-2313 that finds its page in the GPU bias is forwarded directly to the corresponding GPU memory 2320-2323. A local request from a GPU that finds its page in the host bias is forwarded to the processor 2305 (e.g., via the high-speed link described above). In one embodiment, a request from the processor 2305 that finds the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 2310-2313. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, solely by a hardware-based mechanism.

[0259] One mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 2305 bias to GPU bias, but not for transitions in the opposite direction.

[0260] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages non-cacheable by the host processor 2305. To access these pages, the processor 2305 may request access from the GPU 2310, which may or may not immediately grant the access. Therefore, to reduce communication between the processor 2305 and the GPU 2310, it is beneficial for GPU-biased pages to be requested by the GPU but not by the host processor 2305, or vice versa.

[0261] To implement one or more embodiments, a hardware structure 1515 is used. Details regarding the hardware structure (x) 1515 are provided herein in conjunction with Figures 15A and / or 15B.

[0262] 24 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral device interface controllers, or general-purpose processor cores.

[0263] 24 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2400 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 2400 includes one or more application processors 2405 (e.g., CPUs), at least one graphics processor 2410, and may further include an image processor 2415 and / or a video processor 2420, any of which may be modular IP cores. In at least one embodiment, integrated circuit 2400 includes peripheral or bus logic including a USB controller 2425, a UART controller 2430, an SPI / SDIO controller 2435, and an I.sup.2S / I.sup.2C controller 2440. In at least one embodiment, integrated circuit 2400 may include a display device 2445 coupled to one or more of a high-definition multimedia interface (HDMI®) controller 2450 and a mobile industry processor interface (MIPI) display interface 2455. In at least one embodiment, storage may be provided by a flash memory subsystem 2460 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 2465 to access an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 2470.

[0264] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in integrated circuit 2400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0265] 25A-25B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0266] 25A-25B are block diagrams illustrating exemplary graphics processors for use within an SoC according to embodiments described herein. FIG. 25A illustrates an exemplary graphics processor 2510 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. FIG. 25B illustrates a further exemplary graphics processor 2540 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the graphics processor 2510 of FIG. 25A is a low-power graphics processor core. In at least one embodiment, the graphics processor 2540 of FIG. 25B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 2510, 2540 can be a variation of the graphics processor 2410 of FIG. 24.

[0267] In at least one embodiment, the graphics processor 2510 includes a vertex processor 2505 and one or more fragment processors 2515A-2515N (e.g., 2515A, 2515B, 2515C, 2515D-2515N-1, and 2515N). In at least one embodiment, the graphics processor 2510 can execute different shader programs through separate logic, such that the vertex processor 2505 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2515A-2515N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2505 executes the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processors 2515A-2515N generate a frame buffer that is displayed on a display device using the primitive and vertex data generated by vertex processor 2505. In at least one embodiment, fragment processors 2515A-2515N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0268] In at least one embodiment, graphics processor 2510 further includes one or more memory management units (MMUs) 2520A-2520B, caches 2525A-2525B, and circuit interconnects 2530A-2530B. In at least one embodiment, one or more MMUs 2520A-2520B provide virtual-to-physical address mapping for graphics processor 2510, including vertex processor 2505 and / or fragment processors 2515A-2515N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 2525A-2525B. In at least one embodiment, one or more MMUs 2520A-2520B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 2405, image processor 2415, and / or video processor 2420 of Figure 24, allowing each processor 2405-2420 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2530A-2530B enable graphics processor 2510 to interface with other IP cores in the SoC via an internal bus of the SoC or via a direct connection.

[0269] In at least one embodiment, graphics processor 2540 includes one or more MMUs 2520A-2520B, caches 2525A-2525B, and circuit interconnects 2530A-2530B of graphics processor 2510 of FIG. 25A. In at least one embodiment, graphics processor 2540 includes one or more shader cores 2555A-2555N (e.g., 2555A, 2555B, 2555C, 2555D, 2555E, 2555F-2555N-1, and 2555N), providing a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 2540 includes an inter-core task manager 2545 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2555A-2555N, and a tiling unit 2558 for accelerating tiling operations for tile-based rendering, where scene rendering operations are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0270] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in integrated circuits 25A and / or 25B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0271] 26A-26B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 26A illustrates a graphics core 2600, which, in at least one embodiment, may be included in graphics processor 2410 of Figure 24, or, in at least one embodiment, may be integrated shader cores 2555A-2555N, as in Figure 25B. Figure 26B illustrates a highly parallel, general-purpose graphics processing unit 2630 suitable for incorporation into a multi-chip module in at least one embodiment.

[0272] In at least one embodiment, graphics core 2600 includes a shared instruction cache 2602, a texture unit 2618, and a cache / shared memory 2620, which are common to execution resources within graphics core 2600. In at least one embodiment, graphics core 2600 may include multiple slices 2601A-2601N, or partitions per core, and a graphics processor may include multiple instances of graphics core 2600. Slices 2601A-2601N may include supporting logic, including local instruction caches 2604A-2604N, thread schedulers 2606A-2606N, thread dispatchers 2608A-2608N, and sets of registers 2610A-2610N. In at least one embodiment, slices 2601A-2601N may include a set of additional functional units (AFUs 2612A-2612N), floating point units (FPUs 2614A-2614N), integer arithmetic logic units (ALUs 2616-2616N), address calculation units (ACUs 2613A-2613N), double precision floating point units (DPFPUs 2615A-2615N), and matrix processing units (MPUs 2617A-2617N).

[0273] In at least one embodiment, the FPUs 2614A-2614N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 2615A-2615N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2616A-2616N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2617A-2617N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 2617A-2617N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support general matrix-matrix multiplication (GEMM) acceleration. In at least one embodiment, the AFUs 2612A-2612N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0274] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with FIG. 15A and / or FIG. 15B. In at least one embodiment, inference and / or training logic 1515 may be used in graphics core 2600 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0275] FIG. 26B illustrates a general-purpose processing unit (GPGPU) 2630, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 2630 can be directly linked to other instances of the GPGPU 2630 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 2630 includes a host interface 2632 to enable connection to a host processor. In at least one embodiment, the host interface 2632 is a PCI Express interface. In at least one embodiment, the host interface 2632 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 2630 receives commands from the host processor and, using a global scheduler 2634, distributes execution threads associated with these commands to a set of compute clusters 2636A-2636H. In at least one embodiment, compute clusters 2636A-2636H share cache memory 2638. In at least one embodiment, cache memory 2638 can act as a higher level cache for cache memories within compute clusters 2636A-2636H.

[0276] In at least one embodiment, GPGPU 2630 includes memory 2644A-2644B coupled to compute clusters 2636A-2636H via a set of memory controllers 2642A-2642B. In at least one embodiment, memory 2644A-2644B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0277] In at least one embodiment, compute clusters 2636A-2636H each include a set of graphics cores, such as graphics core 2600 of FIG. 26A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 2636A-2636H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0278] In at least one embodiment, multiple instances of GPGPU 2630 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2636A-2636H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 2630 communicate through host interface 2632. In at least one embodiment, GPGPU 2630 includes I / O hub 2639, which couples GPGPU 2630 to GPU link 2640, which enables direct connection to other instances of GPGPU 2630. In at least one embodiment, GPU link 2640 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2630. In at least one embodiment, GPU link 2640 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2630 are located in separate data processing systems and communicate via a network device accessible via host interface 2632. In at least one embodiment, GPU link 2640 can be configured to allow connection to a host processor in addition to, or instead of, host interface 2632.

[0279] In at least one embodiment, the GPGPU 2630 can be configured to train a neural network. In at least one embodiment, the GPGPU 2630 can be used within an inference platform. In at least one embodiment, when the GPGPU 2630 is used for inference, the GPGPU may include fewer compute clusters 2636A-2636H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with memories 2644A-2644B may be different for the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2630 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0280] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, the inference and / or training logic 1515 may be used in the GPGPU 2630 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0281] 27 is a block diagram illustrating a computing system 2700 according to at least one embodiment. In at least one embodiment, computing system 2700 includes a processing subsystem 2701 having one or more processors 2702 and system memory 2704 that communicate via an interconnection path that may include a memory hub 2705. In at least one embodiment, memory hub 2705 may be a separate component within a chipset component or may be integrated within one or more processors 2702. In at least one embodiment, memory hub 2705 is coupled to an I / O subsystem 2711 via communication link 2706. In at least one embodiment, I / O subsystem 2711 includes an I / O hub 2707 that can enable computing system 2700 to receive input from one or more input devices 2708. In at least one embodiment, the I / O hub 2707 can enable a display controller, which may be included in one or more processors 2702 and provide output to one or more display devices 2710A. In at least one embodiment, the one or more display devices 2710A coupled to the I / O hub 2707 can include local, internal, or embedded display devices.

[0282] In at least one embodiment, processing subsystem 2701 includes one or more parallel processors 2712 coupled to memory hub 2705 via a bus or other communication link 2713. In at least one embodiment, communication link 2713 may be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 2712 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processors 2712 form a graphics processing subsystem that can output pixels to one of one or more display devices 2710A coupled via I / O hub 2707. In at least one embodiment, the one or more parallel processors 2712 may also include a display controller and display interface (not shown) that allows for direct connection to one or more display devices 2710B.

[0283] In at least one embodiment, a system storage unit 2714 may be connected to an I / O hub 2707 to provide a storage mechanism for the computing system 2700. In at least one embodiment, an I / O switch 2716 may be used to provide an interface mechanism to enable communication between the I / O hub 2707 and other components, such as a network adapter 2718 and / or a wireless network adapter 2719, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 2720. In at least one embodiment, the network adapter 2718 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2719 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0284] In at least one embodiment, computing system 2700 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2707. In at least one embodiment, the communication paths interconnecting the various components of FIG. 27 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface, such as an NV-Link high-speed interconnect, or other interconnection protocol.

[0285] In at least one embodiment, one or more parallel processors 2712 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2712 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 2700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2712, memory hub 2705, processor 2702, and I / O hub 2707 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2700 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2700 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0286] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, the inference and / or training logic 1515 may be used in the system of Figure 2700 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0287] Processor 28A illustrates a parallel processor 2800 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2800 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2800 is a variation of one or more parallel processors 2712 shown in FIG. 27 according to an example embodiment.

[0288] In at least one embodiment, parallel processor 2800 includes parallel processing units 2802. In at least one embodiment, parallel processing units 2802 include I / O units 2804 that enable communication with other devices, including other instances of parallel processing units 2802. In at least one embodiment, I / O units 2804 may be directly connected to other devices. In at least one embodiment, I / O units 2804 are connected to other devices through the use of a hub or switch interface, such as memory hub 2705. In at least one embodiment, the connection between memory hub 2705 and I / O units 2804 forms communication link 2713. In at least one embodiment, I / O units 2804 are connected to host interface 2806 and memory crossbar 2816, where host interface 2806 receives commands directed to the execution of processing operations and memory crossbar 2816 receives commands directed to the execution of memory operations.

[0289] In at least one embodiment, when host interface 2806 receives command buffers via I / O unit 2804, host interface 2806 can direct work operations to execute these commands to front end 2808. In at least one embodiment, front end 2808 is coupled to scheduler 2810, which is configured to distribute commands or other work items to processing cluster array 2812. In at least one embodiment, scheduler 2810 ensures that processing cluster array 2812 is properly configured and in a valid state before tasks are distributed to processing cluster array 2812 of processing cluster array 2812. In at least one embodiment, scheduler 2810 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2810 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularity, allowing rapid preemption and context switching of threads executing in the processing array 2812. In at least one embodiment, host software can signal the scheduling workload in the processing array 2812 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 2812 by scheduler 2810 logic in the microcontroller that includes the scheduler 2810.

[0290] In at least one embodiment, processing cluster array 2812 can include up to “N” processing clusters (e.g., cluster 2814A, cluster 2814B through cluster 2814N). In at least one embodiment, each cluster 2814A through 2814N of processing cluster array 2812 can execute a large number of simultaneous threads. In at least one embodiment, scheduler 2810 can allocate work to clusters 2814A through 2814N of processing cluster array 2812 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2810 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 2812. In at least one embodiment, different clusters 2814A through 2814N of processing cluster array 2812 can be allocated to process different types of programs or perform different types of computations.

[0291] In at least one embodiment, processing cluster array 2812 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2812 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2812 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0292] In at least one embodiment, processing cluster array 2812 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2812 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, processing cluster array 2812 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2802 may transfer data from system memory via I / O unit 2804 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2822) during processing and then written back to system memory.

[0293] In at least one embodiment, when graphics processing is performed using parallel processing unit 2802, scheduler 2810 may be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 2814A-2814N of processing cluster array 2812. In at least one embodiment, portions of processing cluster array 2812 may be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2814A-2814N may be stored in a buffer so that the intermediate data can be transmitted between clusters 2814A-2814N for further processing.

[0294] In at least one embodiment, processing cluster array 2812 can receive processing tasks to be performed via scheduler 2810, which receives commands defining the processing tasks from front end 2808. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, scheduler 2810 can be configured to fetch the index corresponding to the task or can receive the index from front end 2808. In at least one embodiment, front end 2808 can be configured to ensure that processing cluster array 2812 is configured to a valid state before a workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0295] In at least one embodiment, each of one or more instances of parallel processing unit 2802 can be coupled to parallel processor memory 2822. In at least one embodiment, parallel processor memory 2822 can be accessed via memory crossbar 2816, which can receive memory requests from processing cluster array 2812 as well as I / O unit 2804. In at least one embodiment, memory crossbar 2816 can access parallel processor memory 2822 via memory interface 2818. In at least one embodiment, memory interface 2818 can include multiple partition units (e.g., partition unit 2820A, partition unit 2820B through partition unit 2820N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 2822. In at least one embodiment, the number of partition units 2820A-2820N is configured to equal the number of memory units, such that a first partition unit 2820A has a corresponding first memory unit 2824A, a second partition unit 2820B has a corresponding memory unit 2824B, and an Nth partition unit 2820N has a corresponding Nth memory unit 2824N. In at least one embodiment, the number of partition units 2820A-2820N does not have to equal the number of memory devices.

[0296] In at least one embodiment, the memory units 2824A-2824N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2824A-2824N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2822, render targets, such as frame buffers or texture maps, may be stored across the memory units 2824A-2824N, allowing the partition units 2820A-2820N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2822 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0297] In at least one embodiment, any one of the clusters 2814A-2814N in the processing cluster array 2812 can process data that is to be written to any one of the memory units 2824A-2824N in the parallel processor memory 2822. In at least one embodiment, the memory crossbar 2816 can be configured to forward the output of each cluster 2814A-2814N to any partition unit 2820A-2820N or to another cluster 2814A-2814N that can perform further processing operations on the output. In at least one embodiment, each cluster 2814A-2814N can communicate with a memory interface 2818 through the memory crossbar 2816 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2816 has connections to memory interface 2818 for communicating with I / O units 2804, as well as connections to local instances of parallel processor memory 2822, allowing processing units in different processing clusters 2814A-2814N to communicate with system memory or other memory not local to parallel processing units 2802. In at least one embodiment, memory crossbar 2816 can use virtual channels to separate traffic streams between clusters 2814A-2814N and partition units 2820A-2820N.

[0298] In at least one embodiment, multiple instances of parallel processing unit 2802 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2802 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2802 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2802 or parallel processor 2800 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0299] FIG. 28B is a block diagram of a partition unit 2820 according to at least one embodiment. In at least one embodiment, partition unit 2820 is an instance of one of partition units 2820A-2820N of FIG. 28A. In at least one embodiment, partition unit 2820 includes an L2 cache 2821, a frame buffer interface 2825, and a raster operations unit (ROP) 2826. L2 cache 2821 is a read / write cache configured to execute load and store operations received from memory crossbar 2816 and ROP 2826. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 2821 to frame buffer interface 2825 for processing. In at least one embodiment, updates are also sent to frames via frame buffer interface 2825 for processing. In at least one embodiment, frame buffer interface 2825 interfaces with one of the memory units of a parallel processor memory, such as memory units 2824A-2824N (eg, in parallel processor memory 2822) of FIG.

[0300] In at least one embodiment, ROP2826 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP2826 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2826 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a number of compression algorithms. The type of compression performed by ROP2826 can be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0301] In at least one embodiment, ROP 2826 is included within each processing cluster (e.g., clusters 2814A-2814N of FIG. 28) rather than within partition unit 2820. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2816. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 2710 of FIG. 27, may be routed for further processing by processor 2702, or may be routed for further processing by one of the processing entities in parallel processor 2800 of FIG. 28A.

[0302] FIG. 28C is a block diagram of a processing cluster 2814 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of processing clusters 2814A-2814N of FIG. 28. In at least one embodiment, processing cluster 2814 may be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0303] In at least one embodiment, operation of processing cluster 2814 may be controlled via a pipeline manager 2832, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, pipeline manager 2832 receives instructions from scheduler 2810 of FIG. 28 and manages the execution of those instructions via graphics multiprocessor 2834 and / or texture unit 2836. In at least one embodiment, graphics multiprocessor 2834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 2814. In at least one embodiment, one or more instances of graphics multiprocessor 2834 may be included within processing cluster 2814. In at least one embodiment, graphics multiprocessor 2834 may process data, and a data crossbar 2840 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2832 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through data crossbar 2840.

[0304] In at least one embodiment, each graphics multiprocessor 2834 in a processing cluster 2814 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0305] In at least one embodiment, instructions sent to processing cluster 2814 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in graphics multiprocessor 2834. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 2834. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 2834. In at least one embodiment, if a thread group includes more threads than the number of processing engines in graphics multiprocessor 2834, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on graphics multiprocessor 2834.

[0306] In at least one embodiment, the graphics multiprocessor 2834 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2834 can forgo the internal cache and use cache memory (e.g., L1 cache 2848) within the processing cluster 2814. In at least one embodiment, each graphics multiprocessor 2834 can also access an L2 cache within a partition unit (e.g., partition units 2820A-2820N in FIG. 28 ), which may be shared among all processing clusters 2814 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2834 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2802 may be used as global memory. In at least one embodiment, processing cluster 2814 includes multiple instances of graphics multiprocessor 2834 that can share common instructions and data, which may be stored in L1 cache 2848.

[0307] In at least one embodiment, each processing cluster 2814 may include an MMU 2845 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2845 may reside within memory interface 2818 of FIG. 28. In at least one embodiment, MMU 2845 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses for tiles (tiling is described in more detail) and optionally cache line indices. In at least one embodiment, MMU 2845 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 2834 or an L1 cache, or processing cluster 2814. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0308] In at least one embodiment, processing cluster 2814 may be configured such that each graphics multiprocessor 2834 is coupled to a texture unit 2836 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2834 and, as needed, fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2834 outputs processed tasks to data crossbar 2840 to provide the processed tasks to another processing cluster 2814 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2816. In at least one embodiment, a pre-ROP 2842 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2834 and direct the data to the ROP units, which may be located within partition units (e.g., partition units 2820A-2820N of FIG. 28 ) as described herein. In at least one embodiment, the pre-ROP 2842 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0309] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in graphics processing cluster 2814 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0310] 28D illustrates a graphics multiprocessor 2834 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2834 couples with a pipeline manager 2832 of a processing cluster 2814. In at least one embodiment, the graphics multiprocessor 2834 has an execution pipeline including, but not limited to, an instruction cache 2852, an instruction unit 2854, an address mapping unit 2856, a register file 2858, one or more general-purpose graphics processing unit (GPGPU) cores 2862, and one or more load / store units 2866. The GPGPU cores 2862 and the load / store units 2866 are coupled to a cache memory 2872 and a shared memory 2870 via a memory and cache interconnect 2868.

[0311] In at least one embodiment, instruction cache 2852 receives a stream of instructions to execute from pipeline manager 2832. In at least one embodiment, instructions are cached in instruction cache 2852 and dispatched for execution by instruction unit 2854. In at least one embodiment, instruction unit 2854 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group being assigned to a different execution unit within GPGPU core 2862. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 2856 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 2866.

[0312] In at least one embodiment, register file 2858 provides a set of registers to the functional units of graphics multiprocessor 2834. In at least one embodiment, register file 2858 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2862, load / store unit 2866) of graphics multiprocessor 2834. In at least one embodiment, register file 2858 is partitioned among the respective functional units, with each functional unit allocated a dedicated portion of register file 2858. In one embodiment, register file 2858 is partitioned among the different warps being executed by graphics multiprocessor 2834.

[0313] In at least one embodiment, GPGPU cores 2862 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for graphics multiprocessor 2834. GPGPU cores 2862 may have similar or different architectures. In at least one embodiment, a first portion of GPGPU core 2862 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or may enable variable-precision floating-point operations. In at least one embodiment, graphics multiprocessor 2834 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0314] In at least one embodiment, GPGPU core 2862 includes SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 2862 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may execute in parallel via a single SIMD8 logical unit.

[0315] In at least one embodiment, memory and cache interconnect 2868 is an interconnect network connecting each functional unit of graphics multiprocessor 2834 to register file 2858 and shared memory 2870. In at least one embodiment, memory and cache interconnect 2868 is a crossbar interconnect that allows load / store unit 2866 to implement load and store operations between shared memory 2870 and register file 2858. In at least one embodiment, register file 2858 can operate at the same frequency as GPGPU cores 2862, and therefore data transfers between GPGPU cores 2862 and register file 2858 have very low latency. In at least one embodiment, shared memory 2870 can be used to enable communication between threads executing in functional units within graphics multiprocessor 2834. In at least one embodiment, cache memory 2872 can be used, for example, as a data cache to cache texture data communicated between the functional units and texture unit 2836. In at least one embodiment, shared memory 2870 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 2862 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 2872.

[0316] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into the same package or chip as the core or may be communicatively coupled to the core via an internal (i.e., internal to the package or chip) processor bus / interconnect. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0317] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in graphics multiprocessor 2834 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0318] FIG. 29 illustrates a multi-GPU computing system 2900, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2900 may include a processor 2902 coupled to multiple general-purpose graphics processing units (GPGPUs) 2906A-D via a host interface switch 2904. In at least one embodiment, the host interface switch 2904 is a PCI Express switch device that couples the processor 2902 to a PCI Express bus, via which the processor 2902 can communicate with the GPGPUs 2906A-D. The GPGPUs 2906A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2916. In at least one embodiment, the GPU-to-GPU links 2916 are connected to each of the GPGPUs 2906A-D via dedicated GPU links. In at least one embodiment, P2P GPU link 2916 allows direct communication between each of GPGPUs 2906A-D without requiring communication through host interface bus 2904 to which processor 2902 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to P2P GPU link 2916, host interface bus 2904 remains available to allow access to system memory or to communicate with other instances of multi-GPU computing system 2900, for example, via one or more network devices. In at least one embodiment, GPGPUs 2906A-D are connected to processor 2902 through host interface switch 2904, and in at least one embodiment, processor 2902 includes direct support for P2P GPU link 2916 and can be directly connected to GPGPUs 2906A-D.

[0319] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, the inference and / or training logic 1515 may be used in the multi-GPU computing system 2900 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0320] 30 is a block diagram of a graphics processor 3000 according to at least one embodiment. In at least one embodiment, graphics processor 3000 includes a ring interconnect 3002, a pipeline front end 3004, a media engine 3037, and graphics cores 3080A-3080N. In at least one embodiment, ring interconnect 3002 couples graphics processor 3000 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 3000 is one of multiple processors integrated within a multi-core processing system.

[0321] In at least one embodiment, graphics processor 3000 receives batches of commands via ring interconnect 3002. In at least one embodiment, the incoming commands are interpreted by command streamer 3003 of pipeline front end 3004. In at least one embodiment, graphics processor 30000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 3080A-3080N. In at least one embodiment, for 3D geometry processing commands, command streamer 3003 supplies the commands to geometry pipeline 3036. In at least one embodiment, for at least some media processing commands, command streamer 3003 supplies the commands to video front end 3034, which is coupled to media engine 3037. In at least one embodiment, the media engine 3037 includes a Video Quality Engine (VQE) 3030 for video and image post-processing and a Multi-Format Encode / Decode (MFX) 3033 engine that provides hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 3036 and the media engine 3037 each spawn execution threads for thread execution resources provided by at least one graphics core 3080A.

[0322] In at least one embodiment, graphics processor 3000 includes scalable thread execution resources characterized by modular cores 3080A-3080N (sometimes referred to as core slices), each having multiple sub-cores 3050A-3050N, 3060A-3060N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 3000 can have any number of graphics cores 3080A-3080N. In at least one embodiment, graphics processor 3000 includes a graphics core 3080A having at least a first sub-core 3050A and a second sub-core 3060A. In at least one embodiment, graphics processor 3000 is a low-power processor having a single sub-core (e.g., 3050A). In at least one embodiment, graphics processor 3000 includes multiple graphics cores 3080A-3080N, each including a set of first sub-cores 3050A-3050N and a set of second sub-cores 3060A-3060N. In at least one embodiment, each of first sub-cores 3050A-3050N includes at least a first set of execution units 3052A-3052N and media / texture samplers 3054A-3054N. In at least one embodiment, each of second sub-cores 3060A-3060N includes at least a second set of execution units 3062A-3062N and samplers 3064A-3064N. In at least one embodiment, each sub-core 3050A-3050N, 3060A-3060N shares a set of shared resources 3070A-3070N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0323] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1515 are provided herein in conjunction with Figures 15A and / or 15B. In at least one embodiment, inference and / or training logic 1515 may be used in graphics processor 3000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0324] FIG. 31 is a block diagram illustrating the micro-architecture of a processor 3100 that may include logic circuits for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 3100 may execute instructions, including x86 instructions, AMR instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 3110 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 3110 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0325] In at least one embodiment, processor 3100 includes an in-order front end ("front end") 3101 that fetches instructions to be executed and prepares them for later use in the processor pipeline. In at least one embodiment, front end 3101 may include several units. In at least one embodiment, instruction prefetcher 3126 fetches instructions from memory and provides them to instruction decoder 3128, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 3128 decodes received instructions into one or more operations, called "microinstructions" or "micro-operations" (also called "micro-ops" or "uops"), that the machine can execute. In at least one embodiment, instruction decoder 3128 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 3130 may assemble the decoded uops into program-order sequences, or traces, in uop queue 3134 for execution. In at least one embodiment, when trace cache 3130 encounters a complex instruction, microcode ROM 3132 provides the uops necessary to complete the operation.

[0326] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 3128 may access the microcode ROM 3132 to execute the instruction. In at least one embodiment, the instruction may be decoded into a smaller number of micro-ops for processing in the instruction decoder 3128. In at least one embodiment, if an operation requires a large number of micro-ops to complete, the instruction may be stored in the microcode ROM 3132. In at least one embodiment, the trace cache 3130 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 3132, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 3132 has finished sequencing micro-ops for an instruction, the machine front end 3101 may resume fetching micro-ops from the trace cache 3130.

[0327] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 3103 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions, optimizing performance as instructions are scheduled for execution down the pipeline. Out-of-order execution engine 3103 includes, without limitation, allocator / register renamer 3140, memory uop queue 3142, integer / floating point uop queue 3144, memory scheduler 3146, fast scheduler 3102, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 3104, and simple floating point scheduler ("simple FP scheduler") 3106. In at least one embodiment, fast scheduler 3102, slow / general purpose floating point scheduler 3104, and simple floating point scheduler 3106 are also collectively referred to herein as "uop schedulers 3102, 3104, 3106." Allocator / register renamer 3140 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 3140 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 3140 also allocates each uop's entry to one of two uop queues: memory uop queue 3142 for memory operations and integer / floating point uop queue 3144 for non-memory operations, before memory scheduler 3146 and uop schedulers 3102, 3104, 3106. In at least one embodiment, uop schedulers 3102, 3104, 3106 determine when uops are ready to execute based on the readiness of the sources of their dependent input register operands and the availability of the execution resources required by the uop to complete their operations.In at least one embodiment, the fast scheduler 3102 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 3104 and simple floating point scheduler 3106 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 3102, 3104, 3106 arbitrate for dispatch ports to schedule uops for execution.

[0328] In at least one embodiment, execution block b11 includes, without limitation, integer register file / bypass network 3108, floating point register file / bypass network (“FP register file / bypass network”) 3110, address generation units (“AGUs”) 3112 and 3114, fast arithmetic logic units (ALUs) (“fast ALUs”) 3116 and 3118, slower arithmetic logic unit (“slower ALU”) 3120, floating point ALU (“FP”) 3122, and floating point move unit (“FP move”) 3124. In at least one embodiment, integer register file / bypass network 3108 and floating point register file / bypass network 3110 are also referred to herein as “register files 3108, 3110.” In at least one embodiment, AGUs 3112 and 3114, fast ALUs 3116 and 3118, slow ALU 3120, floating-point ALU 3122, and floating-point move unit 3124 are also referred to herein as "execution units 3112, 3114, 3116, 3118, 3120, 3122, and 3124." In at least one embodiment, execution block b11 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units, in any combination, without limitation.

[0329] In at least one embodiment, register files 3108, 3110 may be located between uop schedulers 3102, 3104, 3106 and execution units 3112, 3114, 3116, 3118, 3120, 3122, and 3124. In at least one embodiment, integer register file / bypass network 3108 performs integer operations. In at least one embodiment, floating point register file / bypass network 3110 performs floating point operations. In at least one embodiment, each of register files 3108, 3110 may include, without limitation, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 3108, 3110 may communicate data with each other. In at least one embodiment, integer register file / bypass network 3108 may include, without limitation, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, so floating-point register file / bypass network 3110 may include, without limitation, 128-bit wide entries.

[0330] In at least one embodiment, execution units 3112, 3114, 3116, 3118, 3120, 3122, and 3124 may execute instructions. In at least one embodiment, register files 3108 and 3110 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 3100 may include any number and combination of execution units 3112, 3114, 3116, 3118, 3120, 3122, and 3124, without limitation. In at least one embodiment, floating-point ALU 3122 and floating-point move unit 3124 may execute floating-point, MMX, SIMD, AVX, and other operations, including SEE, or special machine learning instructions. In at least one embodiment, the floating-point ALU 3122 may include, without limitation, a 64-bit floating-point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 3116, 3118. In at least one embodiment, the high-speed ALUs 3116, 3118 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 3120 may include, without limitation, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branching, with most complex integer operations proceeding to the low-speed ALU 3120. In at least one embodiment, memory load / store operations may be performed by the ALUs 3112, 3114. In at least one embodiment, fast ALU 3116, fast ALU 3118, and slow ALU 3120 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 3116, fast ALU 3118, and slow ALU 3120 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 3122 and floating-point move unit 3124 may be implemented to support wide operands having various bit widths.In at least one embodiment, the floating-point ALU 3122 and floating-point move unit 3124 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0331] In at least one embodiment, the uop schedulers 3102, 3104, 3106 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 3100, the processor 3100 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0332] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0333] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1515 are provided herein in conjunction with FIG. 15A and / or FIG. 15B . In at least one embodiment, some or all of the inference and / or training logic 1515 may be incorporated into the EXE block 3111 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the EXE block 3111. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the EXE block 3111 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0334] 32 illustrates a deep learning application processor 3200 according to at least one embodiment. In at least one embodiment, the deep learning application processor 3200 uses instructions that, when executed by the deep learning application processor 3200, cause the deep learning application processor 3200 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 3200 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 3200 performs a matrix multiplication operation, both "hard-wired" in hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 3200 includes, without limitation, processing clusters 3210(1)-3210(12), inter-chip links (“ICLs”) 3220(1)-3220(12), inter-chip controllers (“ICCs”) 3230(1)-3230(2), high-bandwidth memory second generation (“HBM2”) 3240(1)-3240(4), memory controllers (“Mem Ctrlrs”) 3242(1)-3242(4), high-bandwidth memory physical layers (“HBM 3244(1)-3244(4), a management-controller central processing unit ("management-controller CPU") 3250, a serial peripheral interface, inter-integrated circuit, and general-purpose input / output block ("SPI, I2C, GPIO") 3260, a peripheral component interconnect express controller and direct memory access block ("PCIe controller and DMA") 3270, and a 16-lane peripheral component interconnect express port ("PCI Express x16") 3280.

[0335] In at least one embodiment, the processing clusters 3210 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including the techniques described herein. In at least one embodiment, each processing cluster 3210 may include any number and types of processors, without limitation. In at least one embodiment, the deep learning application processor 3200 may include any number and types of processing clusters 3200. In at least one embodiment, the inter-chip link 3220 is bidirectional. In at least one embodiment, the inter-chip link 3220 and the inter-chip controller 3230 enable multiple deep learning application processors 3200 to exchange information, including activation information resulting from the execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 3200 may include any number and types (including zero) of ICLs 3220 and ICCs 3230.

[0336] In at least one embodiment, the HBM2 3240 provides a total of 32 Gigabytes (GB) of memory. An HBM2 3240(i) is associated with both a memory controller 3242(i) and an HBM PHY 3244(i). In at least one embodiment, any number of HBM2 3240s may provide any type and total amount of high-bandwidth memory and may be associated with any number and types of memory controllers 3242 and HBM PHYs 3244 (including zero). In at least one embodiment, the SPI, I2C, GPIO 3260, PCIe controller and DMA 3270, and / or PCIe 3280 may be replaced with any number and types of blocks enabling any number and types of communication standards in any technically feasible manner.

[0337] Inference and / or training logic 1515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1515 are provided herein in conjunction with FIG. 15A and / or FIG. 15B . In at least one embodiment, the deep learning application processor 3200 is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 3200. In at least one embodiment, the deep learning application processor 3200 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 3200. In at least one embodiment, the processor 3200 may be used to perform one or more neural network use cases described herein.

[0338] FIG. 33 is a block diagram of a neuromorphic processor 3300, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 3300 receives one or more inputs from sources external to the neuromorphic processor 3300. In at least one embodiment, these inputs may be sent to one or more neurons 3302 within the neuromorphic processor 3300. In at least one embodiment, the neurons 3302 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 3300 may include, without limitation, thousands or millions of instances of neurons 3302, although any suitable number of neurons 3302 may be used. In at least one embodiment, each instance of a neuron 3302 may include a neuron input 3304 and a neuron output 3306. In at least one embodiment, the neuron 3302 may generate an output, which may be sent to an input of another instance of the neuron 3302. For example, in at least one embodiment, neuron input 3304 and neuron output 3306 may be interconnected via synapse 3308.

[0339] In at least one embodiment, neurons 3302 and synapses 3308 may be interconnected such that neuromorphic processor 3300 operates to process or analyze information received by neuromorphic processor 3300. In at least one embodiment, neuron 3302 may send an output pulse (or "fire" or "spike") when input received via neuron input 3304 exceeds a threshold. In at least one embodiment, neuron 3302 may sum or integrate signals received at neuron input 3304. For example, in at least one embodiment, neuron 3302 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 3302 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 3304 into a membrane potential and may apply a decay factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 3304 quickly enough to exceed a threshold (i.e., before the membrane potential decays too little to cause firing). In at least one embodiment, neuron 3302 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 3302 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron 3306 when the result of applying the transfer function to neuron 3304 exceeds a threshold. In at least one embodiment, neuron 3302 may ignore previously received input information, for example, by resetting the membrane potential to 0 or another suitable default value, once it fires.In at least one embodiment, once the membrane potential is reset to zero, neuron 3302 may resume normal operation after a suitable period (or refractory period).

[0340] In at least one embodiment, neurons 3302 may be interconnected through synapses 3308. In at least one embodiment, synapses 3308 may operate to transmit a signal from an output of a first neuron 3302 to an input of a second neuron 3302. In at least one embodiment, neurons 3302 may transmit information through two or more instances of synapses 3308. In at least one embodiment, one or more instances of neuron outputs 3306 may be connected to instances of neuron inputs 3304 of the same neuron 3302 through instances of synapses 3308. In at least one embodiment, an instance of neuron 3302 that generates an output to be transmitted through an instance of synapse 3308 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 3308. In at least one embodiment, an instance of neuron 3302 that receives an input to be transmitted through an instance of synapse 3308 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 3308. In at least one embodiment, an instance of neuron 3302 may receive input from one or more instances of synapse 3308 and may send output through one or more instances of synapse 3308, so that a single instance of neuron 3302 may therefore be both a "pre-synaptic neuron" and a "post-synaptic neuron" with respect to various instances of synapse 3308.

[0341] In at least one embodiment, neurons 3302 may be organized into one or more layers. Each instance of neuron 3302 may have one neuron output 3306 that can fan out to one or more neuron inputs 3304 through one or more synapses 3308. In at least one embodiment, neuron output 3306 of neuron 3302 in a first layer 3310 may be connected to neuron input 3304 of neuron 3302 in a second layer 3312. In at least one embodiment, layer 3310 may be referred to as a "feed-forward" layer. In at least one embodiment, each instance of neuron 3302 in an instance of first layer 3310 may fan out to each instance of neuron 3302 in the second layer 3312. In at least one embodiment, first layer 3310 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of neuron 3302 in the second layer 3312 may fan out to fewer than all instances of neuron 3302 in the third layer 3314. In at least one embodiment, the second layer 3312 may be referred to as a "sparsely connected feed-forward layer." In at least o...

Claims

1. determining a first pose of the hand from an image of the hand; translating the first pose of the hand into a corresponding second pose of the robot hand by performing a kinematic retargeting of joint angles of the robot hand determined based on the first pose; determining a set of movements for repositioning the robot hand from a first pose of the robot hand to the second pose and determining a motion path of the robot hand for translating the robot hand to the second pose; causing the robot hand to execute the set of movements based on the motion path; Including, A computer-implemented method, wherein the step of determining the motion path includes a step of kinematically adjusting the robot hand by minimizing a cost function for the kinematic retargeting based on a vector originating from the tip of any one of the index finger, middle finger, and ring finger of the robot hand and directed toward the tip of the thumb of the robot hand, and a vector between the tips of the index finger, middle finger, and ring finger of the robot hand.

2. acquiring said image from a depth camera; determining a point cloud of the hand from the image; determining the first pose of the hand from the point cloud; The computer-implemented method of claim 1 , further comprising:

3. The computer-implemented method of claim 2 , wherein the depth camera is an RGB depth camera, a radar imager, or a LIDAR system.

4. the first pose of the hand includes information identifying a location of each of five fingers of the hand; The computer-implemented method of claim 1 , wherein the first pose of the hand includes information identifying locations of one or more joints of the hand.

5. The computer-implemented method of claim 1 , wherein the set of moves is determined using a Riemann motion policy.

6. The computer-implemented method of claim 1 , wherein the robotic hand is an articulated robotic hand or a robotic gripper.

7. the robotic hand includes one or more tactile sensors that provide tactile sensor information; The computer-implemented method of claim 1 , wherein the tactile sensor information comprises a two-dimensional array of force values ​​for fingers of the robotic hand.

8. one or more processors; a computer-readable memory storing executable instructions; A system comprising: The instructions, when executed by the one or more processors, provide the system with: determining a first pose of an appendage from an image of the appendage performing a task; determining a second pose of the robot gripper based at least in part on the first pose of the appendage by performing kinematic retargeting of joint angles of the robot gripper determined based on the first pose; determining a set of movements to reposition the robot gripper from a first pose of the robot gripper to the second pose and determining a motion path of the robot hand to translate the robot hand to the second pose; performing the set of movements based on the motion path to position the robot gripper in the second pose and cause the robot gripper to perform the task; Let them do so, determining the motion path includes kinematically adjusting the robot gripper by minimizing a cost function for the kinematic retargeting based on a vector originating from a tip of one of the index finger, middle finger, and ring finger of the robot gripper and pointing to a tip of a thumb of the robot gripper, and a vector between the tips of the index finger, middle finger, and ring finger of the robot gripper; A system that allows the user to:

9. The executable instructions may include instructions for: generating a point cloud from the images of the appendage; and determining the first pose from the point cloud; The system of claim 8 , further comprising:

10. The system of claim 8 , wherein the set of moves is executed according to a Riemann motion policy.

11. The system of claim 8 , wherein the appendage is a human hand.

12. 9. The system of claim 8, wherein the executable instructions further cause the system to apply a scaling factor to the first pose of the appendage to determine the second pose of the robotic gripper.

13. The system of claim 8 , wherein the first pose of the appendage specifies a set of hand segmentation and joint angles.

14. The system of claim 13 , wherein the second pose specifies a set of target joint angles and a position of the robot gripper.

15. The system of claim 14 , wherein the second pose is determined using a subset of the first poses.

16. When executed by one or more processors of a computer system, the computer system: determining a first pose of an appendage of a human from an image of the human performing a task; translating the first pose of the appendage into a corresponding second pose of a robotic hand by performing a kinematic retargeting of joint angles of the robotic hand determined based on the first pose; determining a set of movements to reposition the robot hand from a first pose of the robot hand to the second pose and determining a motion path of the robot hand to translate the robot hand to the second pose; causing the robotic hand to perform the set of movements based on the motion path; Let them do so, executing the set of movements includes kinematically adjusting the robotic hand by minimizing a cost function for the kinematic retargeting based on a vector originating from a tip of any one of the index finger, middle finger, and ring finger of the robotic hand and pointing to a tip of a thumb of the robotic hand, and a vector between the tips of the index finger, middle finger, and ring finger of the robotic hand; A computer-readable medium storing instructions to cause a

17. The instructions provide to the computer system: acquiring said image from a depth camera; determining a point cloud of the appendage from the image; and determining the first pose of the appendage from the point cloud; The computer readable medium of claim 16 , further comprising:

18. 20. The computer-readable medium of claim 17, wherein the depth camera is an RGB depth camera, a radar imager, or a LIDAR system.

19. the first pose of the appendage includes information identifying a location of each of five fingers of a hand; 17. The computer-readable medium of claim 16, wherein the first pose of the appendage includes information identifying a location of one or more joints of the hand.

20. the robotic hand includes one or more tactile sensors that provide tactile sensor information; 20. The computer-readable medium of claim 16, wherein the tactile sensor information comprises a two-dimensional array of force values ​​for fingers of the robotic hand.

21. 17. The computer-readable medium of claim 16, wherein the robotic hand is an articulated robotic hand or a robotic gripper.

22. The computer-readable medium of claim 16 , wherein the first pose of the robotic hand is a current pose of the robotic hand.

23. A robot controlled by a computer system, a robotic hand including a plurality of articulated members linked by one or more servo motors connected to the computer system; A computer readable medium according to claim 16; the one or more processors of the computer system coupled to the computer-readable medium and capable of executing instructions stored on the computer-readable medium; A robot comprising:

Images