Semiconductor device and method for manufacturing the same

Abstract

To improve the good quality rate in the manufacturing process in semiconductor devices.SOLUTION: A semiconductor device 10 has a resin case 300, a lead terminal 400a extending from the inside of the resin case 300 to the outside, and a power semiconductor chip 102a disposed in a space SP located inside the resin case 300. The resin case 300 includes an inner wall portion WAL from a wall surface WS defining the space SP to a side surface SD near the space SP in the lead terminal 400a, and a coating portion COV covering at least a part of an upper surface TP1 of an enclosing portion ENV of the lead terminal 400a.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] There is known a semiconductor device in which a semiconductor chip including a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) is housed in a resin case. In this type of semiconductor device, a plurality of lead terminals for external connection are formed on the resin case. Patent Document 1 discloses a semiconductor device in which an electronic component to be connected to the semiconductor chip is disposed on a predetermined one of the plurality of lead terminals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-38019 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device as described above, there is a demand for improving the yield rate in the manufacturing process. [Means for solving the problem]

[0005] A semiconductor device according to a preferred embodiment of the present invention comprises a resin case, a lead terminal extending from the inside to the outside of the resin case, and a first semiconductor chip arranged in a space located inside the resin case, wherein the resin case includes an inner wall portion extending from a wall surface defining the space to a side surface of the lead terminal closest to the space, and a covering portion covering at least a portion of an upper surface of a first portion of the lead terminal.

[0006] A manufacturing method for a semiconductor device according to a preferred embodiment of the present invention is a manufacturing method for a semiconductor device including a resin case, a lead terminal extending from the inside to the outside of the resin case, and a first semiconductor chip arranged in a space located inside the resin case, and includes a first step of inserting a lead frame including the lead terminal into a mold for the resin case, and a second step of forming the resin case by injecting resin into the mold and hardening the resin so as to include an inner wall portion from a wall surface defining the space to a side surface of the lead terminal closest to the space, and a covering portion covering at least a portion of an upper surface of the first portion of the lead terminal. Effect of the Invention

[0007] The semiconductor device and the method for manufacturing the semiconductor device of the present invention have the effect of improving the yield rate in the manufacturing process. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a semiconductor device according to a first embodiment. [Diagram 2] 2 is an explanatory diagram for explaining an inner wall portion and a covering portion shown in FIG. 1. [Diagram 3] 2 is an explanatory diagram for explaining a manufacturing method of the semiconductor device shown in FIG. [Figure 4] FIG. 11 is an explanatory diagram for explaining an example of a semiconductor device according to a second embodiment. [Diagram 5] FIG. 13 is an explanatory diagram for explaining an example of a semiconductor device according to a third embodiment. [Figure 6] FIG. 13 is an explanatory diagram for explaining an example of a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 11 is an explanatory diagram for explaining an example of a semiconductor device according to a first modified example. [Figure 8] 1A and 1B are explanatory diagrams for explaining an example of a semiconductor device according to an application example; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments of the present invention will be described with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, since the embodiments described below are preferred specific examples of the present invention, various technically preferable limitations are attached, but the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited.

[0010] A. Embodiment DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an example of an outline of a semiconductor device 10 according to a first embodiment of the present invention will be described with reference to FIG.

[0011] A1: First embodiment FIG. 1 is a schematic diagram of a semiconductor device 10 according to the first embodiment.

[0012] For convenience of explanation, a three-axis Cartesian coordinate system having an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other will be introduced below. Hereinafter, the direction indicated by the X-axis arrow will be referred to as the +X direction, and the opposite direction of the +X direction will be referred to as the -X direction. Hereinafter, the direction indicated by the Y-axis arrow will be referred to as the +Y direction, and the opposite direction of the +Y direction will be referred to as the -Y direction. Hereinafter, the +Y direction and the -Y direction will be referred to as the Y direction without any particular distinction, and the +X direction and the -X direction will be referred to as the X direction without any particular distinction. Hereinafter, the +Z direction and the -Z direction will be referred to as the Z direction without any particular distinction. Hereinafter, the +Z direction will be referred to as the upward or upper side, and the -Z direction will be referred to as the downward or lower side. In this embodiment, the Y direction is an example of a "first direction," and the X direction is an example of a "second direction perpendicular to the first direction." However, "perpendicular" does not only mean strictly perpendicular, but also includes substantially perpendicular (for example, perpendicular within a margin of error).

[0013] In addition, hereinafter, viewing an object from a specific direction may be referred to as a planar view. Fig. 1 shows a plan view of semiconductor device 10 viewed from the +Z direction, and a cross-sectional view of semiconductor device 10 taken along line A1-A2 in the plan view. In the following, the planar view from the +Z direction may be simply referred to as a "planar view." Note that the planar view from the +Z direction corresponds to a planar view from a direction perpendicular to the top surface TP1 (see Fig. 2) of lead terminal 400a.

[0014] The semiconductor device 10 is a power semiconductor device including power semiconductor elements such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor). An example of the power semiconductor device is an inverter device including switching elements such as a power MOSFET and an IGBT and a control circuit that controls the switching elements. In this embodiment, the semiconductor device 10 may be an IPM (Intelligent Power Module) in which the switching elements, the control circuit, and the like are housed in one package.

[0015] For example, the semiconductor device 10 has a plurality of chip pairs 100, a plurality of control chips 200, a resin case 300, and a plurality of lead terminals 400 (400a, 400b, and 400c). Furthermore, the semiconductor device 10 has a circuit layer 120, a connection portion 130, an insulating metal substrate 140, a plurality of wires 500 (500a, 500b, 500c, and 500d), and a sealing resin 700. The chip pair 100 is a set of a power semiconductor chip 102a and a power semiconductor chip 102b. Hereinafter, the power semiconductor chips 102a and 102b may be collectively referred to as a power semiconductor chip 102. In the plan view of FIG. 1, the resin case 300 is indicated by shading.

[0016] The power semiconductor chip 102a is an example of a "first semiconductor chip." For example, the power semiconductor chip 102a is a semiconductor chip on which switching elements such as power MOSFETs and IGBTs are formed. Also, for example, the power semiconductor chip 102b is a semiconductor chip on which a diode such as a free wheeling diode (FWD) is formed and connected in anti-parallel to the switching element formed on the power semiconductor chip 102a. The diode being connected in anti-parallel to the switching element means that the diode is connected in parallel to the switching element such that the forward direction of the diode is opposite to the forward direction of the switching element. Note that a set of the switching element and the diode may be formed on one semiconductor chip as a so-called RC-IGBT (Reverse Conducting IGBT).

[0017] In the example shown in FIG. 1, the chip pairs 100 are arranged at intervals in the Y direction, and are connected to the lead terminals 400c by the wires 500c. The power semiconductor chips 102a and 102b included in each of the chip pairs 100 are arranged on the circuit layer 120 at intervals in the X direction. The circuit layer 120 is a layer on which a wiring pattern or the like is formed. For example, as shown in the cross-sectional view of FIG. 1, the chip pairs 100 are connected to the circuit layer 120 by the connection parts 130. The connection parts 130 may be a conductive brazing material containing a metal material such as silver or a solder material. The circuit layer 120 is arranged on an insulated metal substrate 140 (more specifically, an insulating layer 144 described later). The insulated metal substrate 140 includes a metal substrate 142 formed of a metal material and an insulating layer 144 formed on the metal substrate 142 by an insulating material. For example, the insulating layer 144 is a ceramic substrate, and the metal substrate 142 functions as a heat sink for dissipating heat generated by the chip pair 100 .

[0018] The control chip 200 is an example of a "second semiconductor chip." The control chip 200 controls the power semiconductor chips 102a and 102b. For example, the control chip 200 is a semiconductor chip on which an integrated circuit that controls the conduction and non-conduction of the power semiconductor chips 102a and 102b is formed. In this embodiment, the control chip 200 may be a High Voltage Integrated Circuit (HVIC). Note that, assuming a circuit in which two switching elements are connected in series between two wirings, for example, the HVIC is an integrated circuit that drives the gate of a switching element connected to the wiring with the higher voltage of the two wirings. Note that the integrated circuit that drives the gate of a switching element connected to the wiring with the lower voltage of the two wirings is also called a Low Voltage Integrated Circuit (LVIC).

[0019] The lead terminals 400 are formed of, for example, a metal material. For example, the lead terminals 400 are integrally formed with the resin case 300 by insert molding. As a result, the lead terminals 400 are disposed in the resin case 300. For example, each of the lead terminals 400 includes an end portion located on the resin case 300 and an end portion located outside the resin case 300 in a plan view. That is, the lead terminals 400 extend from the inside to the outside of the resin case 300.

[0020] Each of the plurality of lead terminals 400b extends, for example, in the X direction. The plurality of lead terminals 400b are arranged in the Y direction at the edge of the resin case 300 in the +X direction. Each of the plurality of lead terminals 400c extends, for example, in the X direction. The plurality of lead terminals 400c are arranged in the Y direction at the edge of the resin case 300 in the -X direction. For example, the plurality of chip pairs 100 are arranged between the plurality of lead terminals 400b and the plurality of lead terminals 400c. The lead terminal 400a is formed so as to pass through the edge of the resin case 300 in the +X direction from the region between the plurality of chip pairs 100 and the plurality of lead terminals 400b. That is, the lead terminal 400a includes a portion extending in the arrangement direction (Y direction) of the plurality of chip pairs 100 on the resin case 300. The portion of the lead terminal 400a extending in the Y direction includes a "first portion". In the present embodiment, the “first portion” of the lead terminal 400a is a region (portion) of the lead terminal 400a whose top surface and side surfaces are fixed by the resin case 300. Specifically, in the present embodiment, the “first portion” may be an enclosed portion ENV that is enclosed by the resin case 300.

[0021] In addition, in the portion of the lead terminal 400a extending in the Y direction, the multiple control chips 200 are arranged at intervals from each other in the Y direction. For example, each of the multiple control chips 200 is arranged on the resin case 300 so as to overlap the lead terminal 400a (in the example shown in FIG. 1, the surrounded portion ENV of the lead terminal 400a) in a plan view. The control chip 200 is connected to the lead terminal 400a by a wire 500a, connected to the lead terminal 400b by a wire 500b, and connected to the power semiconductor chip 102a by a wire 500d. As a result, the control chip 200 is electrically connected to the lead terminal 400a, etc. A voltage such as a ground voltage common to the multiple control chips 200 is supplied to the lead terminal 400a. The wire 500 is formed of a metal material.

[0022] In this manner, in the present embodiment, since the control chip 200 is disposed on the lead terminal 400a, the semiconductor device 10 can be made smaller than when the control chip 200 is disposed in the resin case 300 so as not to overlap with the lead terminal 400a in a plan view. Also, in the present embodiment, since the control chip 200 is disposed on the lead terminal 400a, the distance between the control chip 200 and the lead terminals 400a and 400b, and the distance between the control chip 200 and the power semiconductor chip 102a, etc. can be prevented from increasing. As a result, in the present embodiment, the wires 500a, 500b, 500d, etc. connected to the control chip 200 can be prevented from becoming long.

[0023] The resin case 300 is an example of a "resin case". For example, the resin case 300 is a case in which a plurality of chip pairs 100 are arranged in a space SP located inside the resin case 300. The resin case 300 is formed of, for example, a thermoplastic resin. Examples of the thermoplastic resin include polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, and acrylonitrile butadiene styrene (ABS) resin.

[0024] For example, the resin case 300 is formed with an inner wall portion WAL and a covering portion COV as shown in the cross-sectional view of Fig. 1. The inner wall portion WAL and the covering portion COV of the resin case 300 will be described later with reference to Fig. 2.

[0025] Here, for example, the resin case 300 is grasped as a rectangular frame surrounding the multiple chip pairs 100 in a plan view. For example, as shown in the cross-sectional view of FIG. 1, the resin case 300 is composed of a first frame-shaped portion FR1, a second frame-shaped portion FR2, and a third frame-shaped portion FR3. The second frame-shaped portion FR2 is a rectangular frame-shaped portion in which an opening is formed. The first frame-shaped portion FR1 is a rectangular frame-shaped portion protruding in the +Y direction from the periphery of the first surface SF1 of the second frame-shaped portion FR2. The third frame-shaped portion FR3 is a rectangular frame-shaped portion protruding in the -Y direction from the periphery of the second surface SF2 of the second frame-shaped portion FR2.

[0026] The lead terminals 400b and 400c are disposed between the first frame portion FR1 and the second frame portion FR2. A plurality of chip pairs 100 are located in a space SP in the opening of the second frame portion FR2. The inner wall surface of the second frame portion FR2 corresponds to a wall surface WS that defines the space SP. The control chip 200 is disposed on the first surface SF1 (more specifically, the portion surrounded by the first frame portion FR1) of the second frame portion FR2. The second frame portion FR2 has a covering portion COV at a position between the control chip 200 and the lead terminals 400a. The insulating metal substrate 140 is connected to the second surface SF2 (more specifically, the portion surrounded by the third frame portion FR3) of the second frame portion FR2 by a connecting portion not shown. As a result, the insulating metal substrate 140 is disposed in the space in the opening of the third frame portion FR3. In this manner, the resin case 300 is joined to the insulated metal substrate 140 so that the chip pairs 100 (power semiconductor chips 102a and 102b) are positioned within the space SP. In the following description, the connection portion that connects the insulated metal substrate 140 to the resin case 300 (more specifically, the second surface SF2 of the second frame portion FR2) is also referred to as a substrate joint portion.

[0027] By joining the insulating metal substrate 140 to the resin case 300, for example, the lower opening of the resin case 300 is blocked, and the material of the sealing resin 700 can be injected into the space in the resin case 300 from the upper opening. The material of the sealing resin 700 is, for example, a thermosetting resin such as an epoxy resin. The space in the resin case 300 is, for example, a space surrounded by the first frame-shaped part FR1 and the second frame-shaped part FR2. The sealing resin 700 is filled into the space in the resin case 300 from the upper opening of the resin case 300, and the circuit layer 120, the chip pair 100 (the power semiconductor chips 102a and 102b), the control chip 200, the wires 500, and the like are sealed with the sealing resin 700. The shape of the resin case 300 is not limited to the above example. For example, the shape of the case may be such that the third frame-shaped part FR3 is not frame-shaped, and has a bottom shape that blocks the opening of the second frame-shaped part FR2.

[0028] Next, the inner wall portion WAL and the covering portion COV of the resin case 300 will be described with reference to FIG.

[0029] FIG. 2 is an explanatory diagram for explaining the inner wall portion WAL and the covering portion COV shown in FIG. 1. The plan view of FIG. 2 is a plan view of the region AR1 surrounded by a dashed line shown in the plan view of FIG. 1. The A1-A2 cross-sectional view shows a cross section of the semiconductor device 10 along the A1-A2 line in the plan view of the region AR1, and the B1-B2 cross-sectional view shows a cross section of the semiconductor device 10 along the B1-B2 line in the plan view of the region AR1. The A1-A2 cross-sectional view also shows a cross-sectional view of the region AR2 including a cross section of the lead terminal 400a and the control chip 200 tilted with respect to the XY plane as an explanatory diagram for explaining an example in which the control chip 200 is tilted. In FIG. 2, the wires 500 and the like are omitted in order to make the drawing easier to see.

[0030] In this embodiment, as shown in the plan view of the region AR1, the part of the lead terminal 400a that overlaps with the control chip 200 in a plan view is located within the range of the surrounded portion ENV in the Y direction. That is, the surrounded portion ENV of the lead terminal 400a includes the entire part of the lead terminal 400a that overlaps with the control chip 200 in a plan view. In addition, a plurality of covered portions COV are formed at intervals from each other along the Y direction in which the lead terminal 400a extends. As shown in the A1-A2 cross-sectional view, the covered portion COV covers at least a part of the upper surface of the surrounded portion ENV of the lead terminal 400a. Specifically, the covered portion COV is located between the surrounded portion ENV of the lead terminal 400a and the control chip 200.

[0031] As shown in the A1-A2 cross-sectional view, the lead terminal 400a has a top surface TP1 facing the control chip 200, two side surfaces, and a bottom surface opposite to the top surface TP1. For example, the top surface TP1, two side surfaces, and the bottom surface of the lead terminal 400a are covered by the resin case 300 in a specific cross section of the semiconductor device 10 (for example, a cross section of the semiconductor device 10 along the A1-A2 line). That is, the lead terminal 400a is surrounded by the resin case 300 in the specific cross section. The part of the lead terminal 400a that is surrounded by the resin case 300 corresponds to the surrounded portion ENV. In addition, the part of the resin case 300 that surrounds the surrounded portion ENV of the lead terminal 400a includes the inner wall portion WAL and the covering portion COV. For example, the inner wall portion WAL is a portion of the second frame-shaped portion FR2 of the resin case 300 from a wall surface WS that defines the space SP to a side surface SD of the lead terminal 400a that is close to the space SP. Also, the covering portion COV is a portion of the second frame-shaped portion FR2 of the resin case 300 that covers the upper surface TP1 of the lead terminal 400a.

[0032] Here, for example, since the lead frame including the multiple lead terminals 400 is planar, the lead terminals 400a and 400b are located in the same plane. Therefore, in the second frame-shaped part FR2 of the resin case 300, a step is formed between the surface of the covering part COV and the surface of the part other than the covering part COV. In the part other than the covering part COV in the second frame-shaped part FR2, for example, the lead terminal 400 and the first surface SF1 of the second frame-shaped part FR2 are continuous without a step. In addition, of the two side surfaces of the covering part COV along the Y direction, the side surface EP far from the space SP is located between the area where the lead terminal 400a is arranged and the area where the multiple lead terminals 400b are arranged. Of the two side surfaces of the covering part COV along the Y direction, the side surface close to the space SP forms a part of the wall surface WS. That is, the range of the covering part COV in the X direction is the range from the position between the area where the lead terminal 400a is arranged and the area where the multiple lead terminals 400b are arranged to the wall surface WS. The control chip 200 is attached to the surface of the covering portion COV with an insulating adhesive 600 .

[0033] In this manner, in this embodiment, the control chip 200 is adhered to the covered portion COV of the resin case 300 by the adhesive 600, and therefore the covered portion COV of the resin case 300 and the adhesive 600 are present between the control chip 200 and the lead terminal 400a. For example, the thickness of the adhesive 600 is determined by the diameter of the filler (not shown) contained in the adhesive 600. For this reason, if there is a bias in the distribution of the filler diameter in the adhesive 600, there will be a portion where the thickness of the adhesive 600 is thin, and the control chip 200 may tilt (see example ex1 of the A1-A2 cross-sectional view).

[0034] For example, in a configuration in which the resin case 300 does not have the covering portion COV formed thereon (hereinafter also referred to as the first comparative example), the distance between the control chip 200 and the lead terminal 400a is shortened in the portion where the thickness of the adhesive 600 is thin, and there is a risk that insulation between the control chip 200 and the lead terminal 400a is not ensured. If insulation between the control chip 200 and the lead terminal 400a is not ensured, the withstand voltage between the control chip 200 and the lead terminal 400a decreases. That is, in the first comparative example, there is a risk that the withstand voltage between the control chip 200 and the lead terminal 400a is not ensured. The withstand voltage is, for example, a durability performance that maintains electrical insulation even when a high voltage is applied to an insulator. Note that in a configuration in which the filler in the adhesive 600 is limited to a filler having a diameter equal to or greater than a predetermined value, thereby preventing the thickness of the adhesive 600 from becoming equal to or less than a predetermined thickness, the cost of the adhesive 600 increases.

[0035] In contrast, in this embodiment, the covering portion COV located between the control chip 200 and the lead terminal 400a ensures the distance between the control chip 200 and the lead terminal 400a even in the portion where the thickness of the adhesive 600 is thin. Therefore, in this embodiment, the control chip 200 and the lead terminal 400a can be reliably insulated from each other without increasing the cost of the adhesive 600. As a result, in this embodiment, the withstand voltage between the control chip 200 and the lead terminal 400a can be reliably ensured.

[0036] In this embodiment, the side surface SD of the lead terminal 400a close to the space SP is covered by the inner wall portion WAL. For example, the covering portions COV are formed at intervals along the Y direction, whereas the inner wall portion WAL is continuous with a substantially constant width W30 over the entire portion of the lead terminal 400a extending in the Y direction. In addition, for example, the surface of the inner wall portion WAL in the -X direction constitutes a part of the wall surface WS that defines the space SP (the wall surface WS located in the +X direction among the wall surfaces WS along the Y direction). In this embodiment, since the inner wall portion WAL is formed, in the process of integrally forming the lead terminal 400a with the resin case 300 by insert molding, it is possible to prevent the lead terminal 400a from getting caught in a die when the die for forming the resin case 300 is removed.

[0037] For example, in a configuration in which the inner wall portion WAL is not formed in the resin case 300 (hereinafter also referred to as a second comparative example), in a process of integrally forming the lead terminal 400a with the resin case 300 by insert molding, the side surface SD of the lead terminal 400a comes into contact with a mold. Therefore, in the second comparative example, when the mold is removed, the lead terminal 400a may get caught on the mold, and the lead terminal 400a caught on the mold may be pulled upwardly away from the resin case 300.

[0038] In contrast, in this embodiment, since the side surface SD of the lead terminal 400a is covered by the inner wall portion WAL, the lead terminal 400a is prevented from being caught on the mold when the mold is removed. As a result, in this embodiment, the lead terminal 400a is prevented from being pulled upward from the resin case 300 when the mold is removed.

[0039] In addition, in this embodiment, the side surface SD of the lead terminal 400a close to the space SP is covered by the inner wall portion WAL of the resin case 300, so that the creepage distance between the lead terminal 400a and the insulating metal substrate 140 can be made larger than in the second comparative example. As a result, in this embodiment, the withstand voltage between the lead terminal 400a and the insulating metal substrate 140 can be improved compared to the second comparative example.

[0040] In this embodiment, as shown in the A1-A2 cross-sectional view, the surrounded portion ENV of the lead terminal 400a is surrounded by a portion of the resin case 300 including the inner wall portion WAL and the covering portion COV in a cross section perpendicular to the Y direction. The Y direction is the direction in which the lead terminal 400a extends in the surrounded portion ENV. In this embodiment, even if the lead terminal 400a is pulled upward when the mold is removed, the surrounded portion ENV of the lead terminal 400a is surrounded by the resin case 300, so that the lead terminal 400a is prevented from being peeled upward from the resin case 300.

[0041] In this embodiment, as shown in the plan view of the region AR1 and the A1-A2 cross-sectional view, the maximum width (e.g., width W10) in the X direction of the portion of the lead terminal 400a covered by the covering portion COV of the resin case 300 is narrower than the maximum width (e.g., width W20) in the X direction of the control chip 200. As a result, for example, in the process of integrally forming the lead terminal 400a with the resin case 300 by insert molding, the distance (the width W10 in the X direction of the upper surface TP1) when the resin (material of the resin case 300) such as PPS resin wraps around the upper surface TP1 of the lead terminal 400a is reduced. As a result, in this embodiment, in the process of integrally forming the lead terminal 400a with the resin case 300 by insert molding, the resin (material of the resin case 300) can be efficiently filled up to the upper surface TP1 of the lead terminal 400a.

[0042] In addition, when focusing on the wraparound of resin such as PPS resin, the thickness T1 of the covering portion COV of the resin case 300 is preferably about 30 μm or more, and the width W30 of the inner wall portion WAL of the resin case 300 is preferably about 200 μm or more. That is, the thickness T1 of the covering portion COV may be smaller than the width W30 of the inner wall portion WAL. From the viewpoint of ensuring insulation between the control chip 200 and the lead terminals 400a, when the material of the resin case 300 is PPS resin, the thickness T1 of the covering portion COV of the resin case 300 may be about 20 μm.

[0043] As shown in the plan view of region AR1 and the B1-B2 cross-sectional view, an upper surface TP1 of the lead terminal 400a other than the surrounded portion ENV is not covered by the covering portion COV and is exposed from the resin case 300. A wire 500a is connected to the lead terminal 400a other than the surrounded portion ENV. Next, a manufacturing method of the semiconductor device 10 will be described with reference to FIG.

[0044] FIG. 3 is an explanatory diagram for explaining a manufacturing method of the semiconductor device 10 shown in FIG.

[0045] First, in a first step S100, a lead frame including a plurality of lead terminals 400 is inserted into a mold for a resin case 300.

[0046] Next, in the second step S200, insert molding is performed to form the multiple lead terminals 400 together with the resin case 300. For example, in the second step S200, a resin such as PPS resin is injected into a mold into which a lead frame is inserted, and the lead frame is divided into multiple lead terminals 400 after the resin is cured, thereby forming the resin case 300 into which the multiple lead terminals 400 are inserted. In this manner, the resin case 300 into which the multiple lead terminals 400 are inserted is formed by curing the resin injected into the mold. For example, the resin case 300 is formed so as to include an inner wall portion WAL from a wall surface WS that defines the space SP to a side surface SD of the lead terminal 400a that is close to the space SP, and a covering portion COV that covers at least a part of the upper surface TP1 of the surrounded portion ENV of the lead terminal 400a. In this embodiment, the covering portion COV covers the upper surface TP1 of the lead terminal 400a that faces the control chip 200. The lead terminal 400a is formed such that the surrounded portion ENV of the lead terminal 400a is surrounded by a portion of the resin case 300 including the inner wall portion WAL and the covering portion COV in a cross section perpendicular to the Y direction.

[0047] Next, in a third step S300, an insulating adhesive 600 is applied to a portion of the resin case 300 where the control chip 200 is to be disposed, and the control chip 200 is disposed on the portion to which the adhesive 600 is applied.

[0048] Next, in a fourth step S400, the insulated metal substrate 140 is bonded to close the opening on the lower side of the resin case 300. Before the fourth step S400 is performed, the circuit layer 120 may be disposed on the insulated metal substrate 140, and a plurality of chip pairs 100 (power semiconductor chips 102a and 102b) may be bonded to the circuit layer 120. Note that a heat curing process may be appropriately included when bonding with the adhesive 600 or when bonding the substrate bonding portion.

[0049] Next, in the fifth step S500, wire bonding is performed to connect the wire 500 to the terminals of the power semiconductor chip 102a, the terminals of the power semiconductor chip 102b, the terminals of the control chip 200, the lead terminals 400, etc. For example, in wire bonding, a load is applied to the connection portion of the wire 500 with the lead terminals 400, etc., and ultrasonic waves are applied. Here, in this embodiment, since the surrounded portion ENV of the lead terminal 400a is surrounded by the resin case 300, it is possible to suppress the vibration of the lead terminal 400a during wire bonding. When the vibration of the lead terminal 400a is large, the ultrasonic waves applied to the wire 500 are dispersed compared to when the vibration of the lead terminal 400a is small, and it is highly likely that the connection between the lead terminal 400a and the wire 500 becomes unstable. In this embodiment, since the vibration of the lead terminal 400a during wire bonding can be suppressed, it is possible to suppress the connection between the lead terminal 400a and the wire 500 from becoming unstable.

[0050] Next, in a sixth step S600, a sealing process is performed to seal the circuit layer 120, the chip pair 100 (power semiconductor chips 102a and 102b), the control chip 200, the wires 500, and the like with sealing resin 700. For example, in the sealing process, a liquid resin (material of the sealing resin 700) is injected into the space inside the resin case 300 from an opening on the upper side of the resin case 300, and a heat curing process is performed to heat and harden the resin injected into the resin case 300. As a result, the semiconductor device 10 shown in FIG. 1 is obtained.

[0051] As described above, in this embodiment, the semiconductor device 10 includes the power semiconductor chip 102a, the control chip 200 that controls the power semiconductor chip 102a, the resin case 300 in which the space SP in which the power semiconductor chip 102a is located is formed, and the lead terminal 400a. The lead terminal 400a is disposed in the resin case 300 and is electrically connected to the power semiconductor chip 102a. The resin case 300 includes an inner wall portion WAL extending from a wall surface WS that defines the space SP to a side surface SD of the lead terminal 400a that is close to the space SP, and a covering portion COV that covers an upper surface TP1 of the lead terminal 400a that faces the control chip 200. The surrounded portion ENV of the lead terminal 400a is surrounded by a portion of the resin case 300 including the inner wall portion WAL and the covering portion COV in a cross section perpendicular to the Y direction in which the lead terminal 400a extends in the surrounded portion ENV.

[0052] Thus, in this embodiment, the resin case 300 has a covering portion COV that covers the upper surface TP1 of the lead terminal 400a. Therefore, in this embodiment, the covering portion COV located between the control chip 200 and the lead terminal 400a can ensure insulation between the control chip 200 and the lead terminal 400a, and can ensure a withstand voltage between the control chip 200 and the lead terminal 400a. As a result, in this embodiment, the reliability of the semiconductor device 10 in which a semiconductor chip such as the control chip 200 is arranged on the lead terminal can be improved. Therefore, an effect of improving the yield rate in the manufacturing process is achieved.

[0053] In addition, in this embodiment, since the side surface SD of the lead terminal 400a is surrounded by the inner wall portion WAL, it is possible to prevent the lead terminal 400a from being caught on a die when the die is removed in insert molding in which the lead terminal 400a is integrally formed with the resin case 300. As a result, in this embodiment, it is possible to prevent the lead terminal 400a from being peeled upward from the resin case 300 when the die is removed.

[0054] In addition, in this embodiment, the lead terminal 400a includes an enclosed portion ENV surrounded by the resin case 300 (a portion including the inner wall portion WAL and the covering portion COV). Therefore, in this embodiment, even if the lead terminal 400a is pulled upward when the mold is removed, the enclosed portion ENV of the lead terminal 400a is fixed to the resin case 300, so that the lead terminal 400a can be prevented from being peeled upward from the resin case 300. In this way, in this embodiment, since the lead terminal 400a can be prevented from being peeled upward from the resin case 300, the yield during manufacturing of the semiconductor device 10 in which the control chip 200 is arranged on the lead terminal 400a can be improved. Therefore, an effect of improving the non-defective product rate in the manufacturing process is achieved.

[0055] Furthermore, in this embodiment, since the lead terminal 400a is fixed to the resin case 300 by the enclosed portion ENV, it is possible to suppress vibration of the lead terminal 400a during wire bonding, and to suppress the connection between the lead terminal 400a and the wire 500 from becoming unstable. As a result, in this embodiment, when the control chip 200 is placed on the lead terminal 400a, it is possible to improve the reliability of the semiconductor device 10 and the yield rate during the manufacture of the semiconductor device 10. This has the effect of improving the yield rate in the manufacturing process.

[0056] In this embodiment, the surrounded portion ENV of the lead terminal 400a includes, in a plan view, the entire portion of the lead terminal 400a that overlaps with the control chip 200. In this case, it is possible to reduce the portion that may catch the mold when removing the mold, and it is possible to prevent the lead terminal 400a from being pulled upward from the resin case 300.

[0057] In this embodiment, the maximum width in the X direction perpendicular to the Y direction of the portion of the lead terminal 400a covered by the covering portion COV of the resin case 300 is narrower than the maximum width in the X direction of the control chip 200. In this case, in the insert molding in which the lead terminal 400a is integrally formed with the resin case 300, a resin such as PPS resin (the material of the resin case 300) can be efficiently filled up to the upper surface TP1 of the lead terminal 400a.

[0058] A2: Second embodiment In the above-described first embodiment, the surrounded portion ENV of the lead terminal 400a extends in the Y direction with a substantially constant width W10. In contrast, in the second embodiment, as shown in Fig. 4, the surrounded portion ENV1 of the lead terminal 400a includes a wide portion LP1 having a wide width W12 in the X direction and a narrow portion NP having a width W11 narrower than the width W12 of the wide portion LP1.

[0059] FIG. 4 is an explanatory diagram for explaining an example of the semiconductor device 10 according to the second embodiment. The plan view of FIG. 4 is an example of a plan view of the region AR1 (a region corresponding to the region AR1 surrounded by a dashed line in the plan view of FIG. 1) of the semiconductor device 10 according to the second embodiment, and corresponds to the plan view of FIG. 2. The A1-A2 cross-sectional view shows a cross section of the semiconductor device 10 along the A1-A2 line in the plan view of the region AR1, and the B1-B2 cross-sectional view shows a cross section of the semiconductor device 10 along the B1-B2 line in the plan view of the region AR1. In FIG. 4, the wires 500 and the like are omitted in order to make the drawing easier to see. The same elements as those described in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted. In FIG. 4, the surrounded portion ENV is also referred to as the surrounded portion ENV1.

[0060] The semiconductor device 10 shown in Fig. 4 is similar to the semiconductor device 10 shown in Fig. 1, except that the shape of the surrounded portion ENV1 of the lead terminal 400a is different from the shape of the surrounded portion ENV shown in Fig. 2. The following will mainly explain the main differences between the semiconductor device 10 shown in Fig. 4 and the semiconductor device 10 shown in Fig. 1.

[0061] In this embodiment, as shown in the plan view of the region AR1, the lead terminal 400a includes a wide portion LP1 having a wide width W12 in the X direction and a narrow portion NP having a width W11 narrower than the width W12 of the wide portion LP1. In the following, the portion of the narrow portion NP of the lead terminal 400a covered by the covering portion COV is also referred to as a narrow portion NPa. In this embodiment, the surrounded portion ENV1 of the lead terminal 400a includes the wide portion LP1 and the narrow portion NPa. That is, in the lead terminal 400a of this embodiment, the wide portion LP1 is the surrounded portion ENV1, and a part of the narrow portion NP (narrow portion NPa) is also the surrounded portion ENV1. The wide portion LP1 of the surrounded portion ENV1 includes the entire portion of the lead terminal 400a that overlaps with the control chip 200 in a plan view. The narrow portion NPa of the surrounded portion ENV1 does not overlap with the control chip 200 in a plan view.

[0062] That is, as shown in the A1-A2 cross-sectional view, the control chip 200 is adhered by the adhesive 600 to the portion of the covering portion COV that covers the upper surface TP1 of the wide portion LP1. Therefore, the covering portion COV of the resin case 300 and the adhesive 600 are present between the wide portion LP1 of the lead terminal 400a and the control chip 200. In addition, since the wide portion LP1 is a part of the surrounded portion ENV1, it is surrounded by a portion including the inner wall portion WAL and the covering portion COV, similar to the surrounded portion ENV shown in FIG. 2. In the example shown in FIG. 4, in order to ensure the width (width in the X direction) of the inner wall portion WAL, the side surface SD of the wide portion LP1 is located in the +X direction (direction away from the space SP) from the side surface of the control chip 200 that is closer to the space SP. However, as long as the width of the inner wall portion WAL is ensured to be equal to or greater than a predetermined value, the side surface SD of the wide portion LP1 may be located in the -X direction from the side surface closer to the space SP in the control chip 200, or may overlap with the side surface closer to the space SP in the control chip 200 in a planar view.

[0063] Also, as shown in the A1-A2 cross-sectional view, of the two side surfaces along the Y direction in the covering portion COV of the resin case 300, the side surface EP farther from the space SP is inclined so that the area of ​​the upper surface TP2 of the covering portion COV is smaller than the area of ​​the lower surface BT. The upper surface TP2 of the covering portion COV is the surface facing the control chip 200 in the covering portion COV, and the lower surface BT of the covering portion COV is the surface opposite to the upper surface TP2 in the covering portion COV. Although not shown in the A1-A2 cross-sectional view, the two side surfaces along the X direction in the covering portion COV of the resin case 300 may also be inclined so that the area of ​​the upper surface TP2 of the covering portion COV is smaller than the area of ​​the lower surface BT. In this way, the side surface EP of the covering portion COV of the resin case 300 may be inclined so that the area of ​​the upper surface TP2 facing the control chip 200 in the covering portion COV is smaller than the area of ​​the lower surface BT opposite to the upper surface TP2 in the covering portion COV.

[0064] Moreover, the cross section of the semiconductor device 10 shown in the B1-B2 cross section is similar to the cross section of the semiconductor device 10 shown in the B1-B2 cross section shown in Fig. 2. For example, the top surface TP1 of the lead terminal 400a other than the surrounded portion ENV1 is exposed from the resin case 300 without being covered by the covering portion COV in order to enable connection between the wire 500a and the lead terminal 400a.

[0065] As described above, in this embodiment, the maximum width in the X direction of the surrounded portion ENV1 of the lead terminal 400a (e.g., width W12 of the wide portion LP1) is made larger than the maximum width in the X direction of the surrounded portion ENV of the lead terminal 400a shown in Fig. 2 (e.g., width W10). In this embodiment as well, the same effects as those of the first embodiment described above can be obtained.

[0066] In addition, in this embodiment, the side surface EP of the covering portion COV of the resin case 300 is inclined so that the area of ​​the upper surface TP2 of the covering portion COV of the resin case 300 is smaller than the area of ​​the lower surface BT. Therefore, in this embodiment, the sealing resin 700 can be easily injected up to the boundary between the covering portion COV and the portion other than the covering portion COV. Therefore, in this embodiment, it is possible to suppress the occurrence of voids where the sealing resin 700 does not exist near the boundary between the covering portion COV and the portion other than the covering portion COV. As a result, in this embodiment, the reliability of the semiconductor device 10 can be improved. Note that, in the above-mentioned first embodiment, the covering portion COV of the resin case 300 may be formed so that the side surface EP is inclined, similar to the covering portion COV shown in FIG. 4. Alternatively, in this embodiment, the covering portion COV of the resin case 300 may be formed so that the side surface EP is not inclined, similar to the covering portion COV shown in FIG. 2.

[0067] A3: Third embodiment In the above-described embodiment, the entire side surface SD of the lead terminal 400a close to the space SP is covered by the inner wall portion WAL. In contrast, in the third embodiment, as shown in FIG. 5, a part of the side surface SD of the lead terminal 400a close to the space SP is exposed to the space SP.

[0068] FIG. 5 is an explanatory diagram for explaining an example of the semiconductor device 10 according to the third embodiment. The plan view of FIG. 5 is an example of a plan view of the region AR1 (a region corresponding to the region AR1 surrounded by a dashed line shown in the plan view of FIG. 1) of the semiconductor device 10 according to the third embodiment, and corresponds to the plan view of FIG. 2. The A1-A2 cross-sectional view shows a cross section of the semiconductor device 10 along the A1-A2 line in the plan view of the region AR1, and the C1-C2 cross-sectional view shows a cross section of the semiconductor device 10 along the C1-C2 line in the plan view of the region AR1. In FIG. 5, the wires 500 and the like are omitted in order to make the drawing easier to see. The same elements as those described in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted. In FIG. 5, the surrounded portion ENV is also referred to as the surrounded portion ENV2.

[0069] The semiconductor device 10 shown in Fig. 5 is similar to the semiconductor device 10 shown in Fig. 4, except that the positional relationship between the surrounded portion ENV2 of the lead terminal 400a and the control chip 200 is different from the positional relationship between the surrounded portion ENV1 and the control chip 200 shown in Fig. 4. The following will mainly explain the main differences between the semiconductor device 10 shown in Fig. 5 and the semiconductor device 10 shown in Fig. 4.

[0070] In this embodiment, as shown in the plan view of the region AR1, the part of the lead terminal 400a covered by the covering part COV of the resin case 300 includes the surrounded part ENV2 and the wide part LP2 whose width W12 in the X direction is wider than the width W11 of the surrounded part ENV2. That is, in the lead terminal 400a of this embodiment, a part (narrow part NPa) of the narrow part NP whose width W11 is narrower than the width W12 of the wide part LP2 is the surrounded part ENV2. Also, the wide part LP2 of the lead terminal 400a includes the whole part of the lead terminal 400a overlapping with the control chip 200 in a plan view. In the example shown in FIG. 5, the inner wall part WAL is formed so as to cover the side surface SD close to the space SP in the part of the lead terminal 400a except for the wide part LP2. That is, the side surface SD close to the space SP in the wide part LP2 of the lead terminal 400a is not covered by the inner wall part WAL. Therefore, the lead terminal 400a has the surrounded portion ENV2 at a position that does not overlap with the control chip 200 in a plan view.

[0071] As shown in the A1-A2 cross-sectional view, the control chip 200 is adhered by the adhesive 600 to the portion of the covering portion COV that covers the upper surface TP1 of the wide portion LP2. Therefore, the covering portion COV of the resin case 300 and the adhesive 600 are present between the wide portion LP2 of the lead terminal 400a and the control chip 200. In addition, in the example shown in Fig. 5, the side surface SD of the wide portion LP2 of the lead terminal 400a that is close to the space SP is not covered by the inner wall portion WAL and is therefore exposed to the space SP. That is, in the example shown in Fig. 5, the wide portion LP2 of the lead terminal 400a is not included in the surrounded portion ENV2.

[0072] As shown in the C1-C2 cross-sectional view, the surrounded portion ENV2 of the lead terminal 400a is surrounded by the portion including the inner wall portion WAL and the covering portion COV. Therefore, in this embodiment as well, the lead terminal 400a can be prevented from being peeled upward from the resin case 300 when the mold is removed.

[0073] In addition, the portion of the covering portion COV that covers the upper surface TP1 of the surrounded portion ENV2 of the lead terminal 400a is formed integrally with the inner wall portion WAL. That is, the covering portion COV covers both the surrounded portion ENV2 and the wide portion LP2 of the lead terminal 400a, and is formed integrally with the inner wall portion WAL. This prevents the portion of the covering portion COV that covers the upper surface TP1 of the wide portion LP2 of the lead terminal 400a from peeling off from the wide portion LP2 of the lead terminal 400a. If the covering portion COV to which the control chip 200 is bonded peels off from the lead terminal 400a, the control chip 200 becomes unstable without being fixed, making it difficult to stably perform wire bonding to connect the wire 500 to the control chip 200. In this embodiment, the side surface SD of the wide portion LP2 of the lead terminal 400a is exposed to the space SP, but the covering portion COV is prevented from peeling off from the lead terminal 400a, thereby preventing the connection between the control chip 200 and the wire 500 from becoming unstable.

[0074] 4, the side surface EP of the covered portion COV of the resin case 300 is inclined so that the area of ​​the top surface TP2 of the covered portion COV is smaller than the area of ​​the bottom surface BT. Note that, in this embodiment, the covered portion COV of the resin case 300 may be formed without inclining the side surface EP, similar to the covered portion COV shown in FIG.

[0075] The upper surface TP1 of the lead terminal 400a excluding the wide portion LP2 and the surrounded portion ENV2 is exposed from the resin case 300 without being covered by the covering portion COV in order to enable connection between the wire 500a and the lead terminal 400a.

[0076] As described above, in this embodiment, the maximum width in the X direction of the wide portion LP2 of the lead terminal 400a is made larger than the maximum width in the X direction of the wide portion LP1 of the lead terminal 400a shown in Fig. 4. Note that, in this embodiment as well, the same effects as those of the first and second embodiments described above can be obtained.

[0077] A4: Fourth embodiment In the above-described embodiment, the entire upper surface TP1 of the lead terminal 400a overlapping with the control chip 200 in a plan view is covered by the covering portion COV. In contrast, in the fourth embodiment, as shown in Fig. 6, the covering portion COV1 of the resin case 300 is formed such that a part of the upper surface TP1 of the lead terminal 400a overlapping with the control chip 200 in a plan view is exposed from the resin case 300.

[0078] FIG. 6 is an explanatory diagram for explaining an example of the semiconductor device 10 according to the fourth embodiment. FIG. 6 is an example of a plan view showing the periphery of the region in which the control chip 200 is arranged in the semiconductor device 10 according to the fourth embodiment. In FIG. 6, the control chip 200, the adhesive 600, the wires 500, etc. are omitted in order to make the drawing easier to see. The rectangle of the dashed dotted line in FIG. 6 indicates the chip arrangement region AR3 in which the control chip 200 is arranged. The same elements as those described in FIG. 1 to FIG. 5 are given the same reference numerals, and detailed description is omitted. In FIG. 6, the covering portion COV is also referred to as the covering portion COV1, and the surrounded portion ENV is also referred to as the surrounded portion ENV3.

[0079] The semiconductor device 10 shown in Fig. 6 is similar to the semiconductor device 10 shown in Fig. 2, except that the covered portion COV1 of the resin case 300 is different from the covered portion COV shown in Fig. 2. The following description will focus on the main differences between the semiconductor device 10 shown in Fig. 6 and the semiconductor device 10 shown in Fig. 2.

[0080] As shown in FIG. 6, the covering portion COV1 of the resin case 300 includes a plurality of first covering portions COVf extending in the X direction. The plurality of first covering portions COVf are arranged at intervals in the Y direction on the upper surface of the first portion of the lead terminal 400a so as to overlap the control chip 200 in a plan view. In this manner, a plurality of first covering portions COVf are formed as covering portions COV1 in the resin case 300 on the lower side (-Z direction) of one control chip 200. That is, the lead terminal 400a has a plurality of surrounded portions ENV3 for each chip arrangement area AR3. Note that in this embodiment, the first portion may be a portion overlapped by the control chip 200, or may be a region including (surrounding) the plurality of surrounded portions ENV3.

[0081] 6, two first covering portions COVf are arranged under one control chip 200, but three or more first covering portions COVf may be arranged under one control chip 200. Alternatively, one covering portion COV1 whose length in the Y direction is shorter than the length of the control chip 200 in the Y direction (for example, one covering portion COV1 filling the gap between the two first covering portions COVf shown in FIG. 6) may be arranged under the control chip 200.

[0082] In addition, the surrounded portion ENV3 of the lead terminal 400a is surrounded by a portion of the resin case 300 that includes the inner wall portion WAL and multiple first covered portions COVf in a cross section perpendicular to the Y direction, similar to the surrounded portion ENV shown in Figure 2.

[0083] 6, the maximum width in the X direction of the lead terminal 400a covered by the first covering portions COVf of the resin case 300 (e.g., width W10) is narrower than the maximum width in the X direction of the control chip 200 (e.g., width W20). The lead terminal 400a may have a wide portion LP1 and a narrow portion NP, for example, like the lead terminal 400a shown in FIG. 4. That is, the maximum width in the X direction of the lead terminal 400a covered by the first covering portions COVf of the resin case 300 may be the same as the maximum width in the X direction of the control chip 200, or may be greater than the maximum width in the X direction of the control chip 200.

[0084] Also in this embodiment, the multiple first covered portions COVf of the resin case 300 may be formed without inclining the side surface EP, similar to the covered portion COV shown in FIG. 2, or may be formed with inclined side surface EP, similar to the covered portion COV shown in FIG. 4.

[0085] As described above, in this embodiment, the same effects as those of the first, second and third embodiments can be obtained. In this embodiment, the covering portion COV1 of the resin case 300 is formed so that a part of the upper surface TP1 of the lead terminal 400a that overlaps with the control chip 200 in a plan view is exposed from the resin case 300. For this reason, in this embodiment, for example, it is expected that the adhesive 600 applied to the chip arrangement area AR3 will enter the gap between the lead terminal 400a and the resin case 300 from the part where the lead terminal 400a is exposed from the resin case 300. When the adhesive 600 applied to the chip arrangement area AR3 enters the gap between the lead terminal 400a and the resin case 300, the adhesion between the lead terminal 400a and the resin case 300 is improved. Therefore, in this embodiment, the adhesion between the lead terminal 400a and the resin case 300 can be improved. Note that the first covering portion COVf only needs to cover at least a part of the upper surface TP1 of the first part of the lead terminal 400a. For example, the following configuration may be used. As described above, in FIG. 6, the multiple first covered portions COVf are arranged at intervals in the Y direction on the upper surface of the first portion of the lead terminal 400a so as to overlap the control chip 200 in a plan view. Also, the multiple first covered portions COVf in FIG. 6 are rectangular in shape with the elongated direction in the X direction in a plan view. In contrast, for example, the multiple first covered portions COVf may be rectangular in shape with the elongated direction in the Y direction in a plan view. And, for example, the multiple first covered portions COVf may be arranged at intervals in the X direction on the upper surface of the first portion of the lead terminal 400a so as to overlap the control chip 200 in a plan view. That is, the multiple first covered portions COVf may be provided scattered in the X direction.

[0086] B: Variation The above-described embodiment may be modified in various ways. Specific modified aspects that may be applied to the above-described embodiment are illustrated below. Two or more aspects selected from the following examples may be combined to the extent that they are not mutually contradictory.

[0087] B1: First modified example For example, in the above-described embodiment, a semiconductor chip on which an integrated circuit (eg, LVIC) different from the integrated circuit (eg, HVIC) formed on the control chip 200 is formed may be disposed on the lead terminals 400a.

[0088] Fig. 7 is an explanatory diagram for explaining an example of the semiconductor device 10 according to the first modification. Fig. 7 is a plan view of the semiconductor device 10 according to the first modification when viewed from the +Z direction. Elements similar to those described in Figs. 1 to 6 are given the same reference numerals, and detailed description thereof will be omitted.

[0089] The semiconductor device 10 shown in Fig. 7 is similar to the semiconductor device 10 shown in Fig. 1, except that the control chip 220 is disposed on the lead terminal 400a. Note that in Fig. 7, the power semiconductor chip 102, wires 500, lead terminals 400, etc. connected to the control chip 220 are omitted for ease of viewing. The following description will focus on the main differences between the semiconductor device 10 shown in Fig. 7 and the semiconductor device 10 shown in Fig. 1.

[0090] In this modification, it is assumed that the integrated circuit formed in the control chip 200 is an HVIC, and the integrated circuit formed in the control chip 220 is an LVIC. In the example shown in Fig. 7, the control chip 220 is bonded to the lead terminal 400a by a conductive connection portion without going through the covered portion COV of the resin case 300. In other words, the covered portion COV of the resin case 300 is not formed below the control chip 220.

[0091] Note that the control chip 220 may be attached to the covering portion COV covering the upper surface TP1 of the lead terminal 400a by an adhesive 600, and connected to the lead terminal 400a by a wire 500a, similar to the control chip 200. In this case, the control chip 220 is another example of the "second semiconductor chip."

[0092] As described above, in this modified example as well, the same effects as those of the above-described embodiment can be obtained.

[0093] B2: Second variant In the above-described embodiment, for example, the portion between the surrounded portions ENV of the lead terminal 400a shown in FIG. 2 may be a wide portion whose width in the X direction is wider than the width (e.g., width W10) of the surrounded portion ENV. In this case, the entire narrow portion of the lead terminal 400a whose width is narrower than the width of the wide portion corresponds to the surrounded portion ENV. Alternatively, of the wide portion LP1 and narrow portion NP shown in FIG. 4, only a portion of the wide portion LP1 may be covered by the covered portion COV. In this case, a portion of the wide portion LP1 of the lead terminal 400a (the portion covered by the covered portion COV) corresponds to the surrounded portion ENV. As described above, the same effects as those of the above-described embodiment can be obtained in this modified example as well.

[0094] C: Application examples FIG. 8 is an explanatory diagram for explaining an example of the semiconductor device 10 according to the application example. The plan view of FIG. 8 is an example of a plan view of the region AR1 (a region corresponding to the region AR1 surrounded by a dashed line shown in the plan view of FIG. 1) of the semiconductor device 10 according to the application example, and corresponds to the plan view of FIG. 2. The A1-A2 cross-sectional view shows a cross section of the semiconductor device 10 along the A1-A2 line in the plan view of the region AR1, and the C1-C2 cross-sectional view shows a cross section of the semiconductor device 10 along the C1-C2 line in the plan view of the region AR1. In FIG. 8, the wires 500 and the like are omitted in order to make the drawing easier to see. The same elements as those described in FIG. 1 to FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted. In FIG. 8, the covering portion COV is also referred to as the covering portion COV2.

[0095] The semiconductor device 10 shown in Fig. 8 is similar to the semiconductor device 10 shown in Fig. 5, except that the covered portion COV2 of the resin case 300 is different from the covered portion COV shown in Fig. 5. The following will mainly describe the main differences between the semiconductor device 10 shown in Fig. 8 and the semiconductor device 10 shown in Fig. 5.

[0096] In the application example, as shown in the plan view of the region AR1, the lead terminal 400a includes a wide portion LP2 having a wide width W12 in the X direction, and a narrow portion NP having a width W11 narrower than the width W12 of the wide portion LP2. In the example shown in Fig. 8, the wide portion LP2 of the lead terminal 400a includes the entire portion of the lead terminal 400a that overlaps with the control chip 200 in a plan view, and the narrow portion NP of the lead terminal 400a does not overlap with the control chip 200 in a plan view.

[0097] As shown in the A1-A2 cross-sectional view, the control chip 200 is attached to the covering portion COV2 covering the upper surface TP1 of the wide portion LP2 by the adhesive 600. Therefore, the covering portion COV2 of the resin case 300 and the adhesive 600 are present between the wide portion LP2 of the lead terminal 400a and the control chip 200. Note that the side surface SD of the wide portion LP2 of the lead terminal 400a close to the space SP is not covered by the inner wall portion WAL and is exposed to the space SP. In the example shown in FIG. 8, the covering portion COV2 of the resin case 300 is formed with an inclined side surface EP like the covering portion COV shown in FIG. 4, but may be formed without an inclined side surface EP like the covering portion COV shown in FIG. 2.

[0098] As shown in the plan view and the C1-C2 cross-sectional view of the region AR1, an upper surface TP1 of an edge portion (an edge portion connected to the narrow portion NP) of the wide portion LP2 of the lead terminal 400a along the X direction is not covered by the covering portion COV2 and is exposed from the resin case 300. A cross section perpendicular to the Y direction in the narrow portion NP of the lead terminal 400a is similar to the cross section shown in the B1-B2 cross-sectional view of Fig. 2. That is, in the narrow portion NP of the lead terminal 400a, a side surface SD close to the space SP is covered by the inner wall portion WAL, and an upper surface TP1 of the narrow portion NP is not covered by the covering portion COV2 and is exposed from the resin case 300.

[0099] Thus, in the application example, the resin case 300 includes a covering portion COV2 that covers the upper surface TP1 of the lead terminal 400a facing the control chip 200. Also, the insulating adhesive 600 that bonds the control chip 200 to the resin case 300 is located at least between the covering portion COV2 of the resin case 300 and the control chip 200. Note that the covering portion COV2 of the resin case 300 may have a plurality of first covering portions COVf for each control chip 200, similar to the covering portion COV1 shown in FIG.

[0100] The following aspects can be understood from the above application examples.

[0101] The semiconductor device 10 includes a power semiconductor chip 102a, a control chip 200 that controls the power semiconductor chip 102a, and a resin case 300 in which a space SP is formed in which the power semiconductor chip 102a is located. The semiconductor device 10 further includes a lead terminal 400a that is disposed in the resin case 300 and electrically connected to the power semiconductor chip 102a, and an insulating adhesive 600 that bonds the control chip 200 to the resin case 300. The resin case 300 includes a covering portion COV that covers an upper surface TP1 of the lead terminal 400a that faces the control chip 200. The adhesive 600 is located between the covering portion COV of the resin case 300 and the control chip 200.

[0102] As described above, in the application example as well, similarly to the above-mentioned embodiment and modified example, insulation between the control chip 200 and the lead terminal 400a can be ensured by the covering portion COV2 located between the control chip 200 and the lead terminal 400a. Therefore, in the application example as well, the withstand voltage between the control chip 200 and the lead terminal 400a can be ensured, and the reliability of the semiconductor device 10 can be improved.

[0103] However, in the application example, the covering portion COV2 of the resin case 300 is not formed integrally with the inner wall portion WAL.

[0104] In the application example, the covering portion COV2 of the resin case 300 may be formed such that a part of the upper surface TP1 of the lead terminal 400a overlapping with the control chip 200 in a plan view is exposed from the resin case 300. For example, the covering portion COV2 of the resin case 300 may have a plurality of first covering portions COVf on the lower side of the control chip 200, similar to the covering portion COV1 shown in Fig. 6. In this case, it is expected that the adhesive 600 applied to the chip arrangement area AR3 will enter the gap between the lead terminal 400a and the resin case 300 from the part where the lead terminal 400a is exposed from the resin case 300.

[0105] Therefore, even in the application example, when the covering portion COV2 located on the lower side of the control chip 200 is formed so that a part of the upper surface TP1 of the lead terminal 400a is exposed from the resin case 300, it is expected that the adhesion between the lead terminal 400a and the resin case 300 will be improved. Moreover, when the covering portion COV2 located on the lower side of the control chip 200 is formed so that a part of the upper surface TP1 of the lead terminal 400a is exposed from the resin case 300, the covering portion COV2 is covered with the adhesive 600 applied to the chip arrangement area AR3. In this case, it is possible to suppress the covering portion COV2 from peeling off from the lead terminal 400a. [Explanation of symbols]

[0106] 10...semiconductor device, 100...chip pair, 102...power semiconductor chip, 120...circuit layer, 130...connection portion, 140...insulated metal substrate, 142...metal substrate, 144...insulating layer, 200...control chip, 300...resin case, 400...lead terminal, 500...wire, 600...adhesive, 700...sealing resin, COV, COV1, COV2...covered portion, COVf...first covered portion, ENV, ENV1, ENV2, ENV3...surrounded portion, FR1...first frame-shaped portion, FR2...second frame-shaped portion, FR3...third frame-shaped portion, LP1, LP2...wide portion, NP, NPa...narrow portion, SP...space.

Claims

1. A resin case and a lead terminal extending from the inside to the outside of the resin case; a first semiconductor chip disposed in a space located inside the resin case; a second semiconductor chip disposed above a first portion of the lead terminal and controlling the first semiconductor chip; Equipped with the resin case includes an inner wall portion extending from a wall surface that defines the space to a side surface of the lead terminal that is close to the space, and a covering portion that covers at least a part of an upper surface of the first portion of the lead terminal, the covering portion is interposed between the first portion and the second semiconductor chip; Semiconductor device.

2. the first portion of the lead terminal is surrounded by a portion of the resin case including the inner wall portion and the covering portion in a cross section perpendicular to a first direction in which the lead terminal extends in the first portion; The semiconductor device according to claim 1 .

3. the first portion of the lead terminal includes an entire portion of the lead terminal that overlaps with the second semiconductor chip in a plan view from a direction perpendicular to an upper surface of the lead terminal, The semiconductor device according to claim 2 .

4. a maximum width in a second direction perpendicular to the first direction of the lead terminal that is covered by the covering portion of the resin case is narrower than a maximum width in the second direction of the second semiconductor chip; The semiconductor device according to claim 3 .

5. the covering portion includes a plurality of first covering portions arranged at intervals on an upper surface of the first portion of the lead terminal so as to overlap the second semiconductor chip in a plan view from a direction perpendicular to an upper surface of the lead terminal, The semiconductor device according to claim 1 .

6. The lead terminal includes, in the first portion, a wide portion having a large width in a second direction perpendicular to a first direction in which the lead terminal extends, and a narrow portion having a width smaller than that of the wide portion. The semiconductor device according to claim 1 .

7. At least a part of the wide portion of the lead terminal is the first portion. The semiconductor device according to claim 6.

8. At least a part of the narrow portion of the lead terminal is the first portion.

8. The semiconductor device according to claim 6 or 7.

9. The side surface of the covering portion is inclined. The semiconductor device according to claim 1 .

10. A method for manufacturing a semiconductor device including a resin case, lead terminals extending from the inside to the outside of the resin case, a first semiconductor chip disposed in a space located inside the resin case, and a second semiconductor chip disposed above a first portion of the lead terminals and controlling the first semiconductor chip, a first step of inserting a lead frame including the lead terminals into a mold for the resin case; a second step of injecting a resin into the mold and hardening the resin to form the resin case so as to include an inner wall portion extending from a wall surface defining the space to a side surface of the lead terminal that is close to the space, and a covering portion covering at least a part of an upper surface of the first portion of the lead terminal; a third step of disposing the second semiconductor chip above the covering portion; Including, 4. A method for manufacturing a semiconductor device comprising the steps of:

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