Boost-Buck Protection for Power Converters

Abstract

In the illustrated example, a device (100) includes a power converter (110) having an input coupled to a first node and an output coupled to an output terminal adapted to be coupled to a battery (112). A blocking transistor (106) is coupled between a second node and the first node. A regulator (114) has inputs coupled to the first node and the second node and an output coupled to a control node of the blocking transistor (106). The regulator (114) controls the blocking transistor (106) to adjust a voltage drop across the blocking transistor (106) based on a voltage at the first node and a voltage at the second node, and is configured to turn off the blocking transistor (106) in response to the voltage at the first node exceeding the voltage at the second node by at least a threshold value, thereby blocking a boost-buck current flowing from the output terminal to the second node.

Description

[Technical field]

[0001] This application relates generally to electronic circuitry, and more particularly to reducing boost-buck in power converters. [Background technology]

[0002] Various types of power converters can be designed to convert a DC power source from one voltage level to another. As an example, a buck converter is a type of switched mode power supply that typically includes transistors configured to step down an input voltage across one or more storage elements, such as capacitors and / or inductors, to provide a corresponding output voltage. A common application of a buck converter is a battery charger. For example, a battery charger is configured to inject energy into a battery by forcing a current through the battery. In normal operation, a synchronous buck converter draws current from the input and pushes current from the output. In some applications, forced continuous conduction mode (CCM) operation is desirable due to its frequency response and design simplicity. However, in this mode, the controller may request a current in the reverse (negative) direction. A negative current is called boost-buck and is generally undesirable in a buck regulator.

[0003] As an example, boost-buck can be categorized into two general types: regulated boost-buck and unregulated boost-buck. The regulated boost-buck condition occurs when the converter demands a negative current and is able to find a stable regulation point. The unregulated boost-buck occurs when the converter demands a negative current but is unable to reach a stable operating point. This condition can cause uncontrolled voltage and / or current runaway on the converter's input and can damage other components of the device or system. The regulation loops in the converter that most often contribute to unregulated boost-buck are output voltage regulation and temperature regulation. For temperature regulation, if the ambient temperature exceeds the target junction regulation point, this regulation loop will drive the output current below zero and continue to drive the current lower (more negative). This condition is a positive feedback condition and is undesirable because the more negative current the converter pushes out, the more heat the device will dissipate. Summary of the Invention

[0004] In a first example, a device includes a power converter having an input coupled to a first node and an output coupled to an output terminal adapted to be coupled to a battery. A blocking transistor is coupled between a second node and the first node. A regulator has inputs coupled to the first node and the second node and an output coupled to a control node of the blocking transistor. The regulator is configured to control the blocking transistor to regulate a voltage drop across the blocking transistor based on a voltage between the first node and the second node, and to turn off the blocking transistor in response to the voltage at the first node exceeding the voltage at the second node by a threshold value to interrupt the boost-back current flowing from the output terminal to the second node.

[0005] In another example, a system includes a power converter configured to provide a charge current to an output terminal in response to one or more control signals and based on a voltage at a first node. A blocking transistor is coupled between a second node and an input node of the power converter. A regulator is configured to adjust a voltage drop across the blocking transistor based on the voltage at the first node and the voltage at the second node, and the regulator is configured to turn off the blocking transistor in response to the voltage at the first node exceeding the voltage at the second node by a threshold value such that current from the output terminal to the second node is blocked by the blocking transistor. An input detector is configured to discharge the second node in response to the blocking transistor being turned off. A boost-buck detector is configured to turn off the power converter in response to detecting a boost-buck state of the power converter.

[0006] In yet another example, a method includes controlling a charge current to an output terminal adapted to be coupled to a battery based on a voltage at a first node and a control signal. The method also includes regulating a voltage across a blocking transistor coupled between a second node and the first node based on a reference voltage. The method also includes turning off the blocking transistor and discharging the second node in response to detecting that the voltage at the first node exceeds the voltage at the second node. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram of an example of a system for charging a battery including boost-buck protection.

[0008] [Diagram 2] FIG. 1 is a diagram of a bidirectional power converter.

[0009] [Diagram 3] FIG. 2 is a diagram of a unidirectional power converter.

[0010] [Figure 4] FIG. 2 is a diagram of an example of a power converter for charging a battery.

[0011] [Diagram 5] FIG. 1 is a diagram of an example of a typical system for charging a battery.

[0012] [Figure 6] FIG. 1 is a diagram of a unidirectional power converter including boost-buck protection.

[0013] [Figure 7] FIG. 1 is a block diagram of a typical power converter with means for preventing buck-boost at the output.

[0014] [Figure 8] FIG. 2 is a diagram of another example of a power converter system for charging a battery including boost-buck protection.

[0015] [Figure 9] 9 is a graph plotting the signal of the system of FIG. 8 as a function of time.

[0016] [Figure 10] 1 is a graph plotting a signal for detecting an unregulated boost-buck condition as a function of time.

[0017] [Figure 11] 4 is a flow chart illustrating an example method for providing boost-buck protection. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The present disclosure relates to systems and circuits for reducing boost-buck in power converters, such as step-down converters (e.g., forced continuous conduction mode (CCM) step-down converters). In the examples disclosed herein, the systems and methods are described in the context of a power converter implemented in a battery charger, but the systems and circuits disclosed herein can also be used to reduce boost-buck in other applications of power converters.

[0019] As an example, a power converter has an input coupled to a first node. A blocking transistor is coupled between the first node to which a power source for providing an input voltage is coupled and a second node. A regulator is configured to adjust a voltage drop across the blocking transistor to control a voltage and a current provided to an input of the power converter at the first node. For example, the regulator is configured to control the blocking transistor to adjust a voltage across the blocking transistor based on a comparison of an input voltage from the power source and a voltage at the input of the power converter. An input detector is configured to discharge the second node in response to detecting that the blocking transistor is turned off. A boost-buck detector is configured to generate a fault signal based on the input voltage from the power source and a voltage at a first node at the input of the power converter. For example, the power converter can be turned off in response to the fault signal. And / or the first node can be discharged in response to the fault signal.

[0020] The blocking transistor allows the system to monitor and protect against boost-back, which can occur when the voltage at the input of the power converter exceeds the input voltage from the power supply. The regulator further operates the blocking transistor as an ideal diode, such as by regulating the voltage drop across the blocking transistor to be a small voltage (e.g., less than 100 mV, such as about 20 mV). This allows for higher overall power efficiency than can be achieved with a pn junction diode. For example, by implementing the regulator to control the blocking transistor in this manner, the regulator can quickly turn off the blocking transistor during boost-back, such as when the input voltage is removed (e.g., in response to the AC power being unplugged or disconnected). Also, because the boost-back protection is implemented at the power supply input, as opposed to within the power stage of the power converter, this approach can be implemented without requiring additional circuitry to compensate for discontinuous conduction that can occur in power converters that control the low-side FET to reduce boost-back. For example, some existing designs turn off the low-side FET to reduce the boost-buck condition, which can result in discontinuous conduction mode and increased ripple at the output, thus increasing the complexity to reduce such undesirable results and ensure stability of all regulation loops across their various operating modes.

[0021] FIG. 1 shows a block diagram of a system 100 including a power converter 110 for charging a battery 112. The system 100 is configured to reduce (or cut off) boost-back, which may occur when a control signal indicates a negative I charge current. As described herein, boost-back corresponds to a condition when reverse current flows from the output of the power converter (e.g., coupled to the battery terminals) to prevent undesired power delivery from the battery 112 to the system 100. In some examples, boost-back may occur when the battery voltage exceeds the input voltage at 104. In other examples, boost-back may occur when the battery voltage is less than the input voltage but is boosted to deliver power in a negative direction.

[0022] In some examples, system 100 represents a battery charger. System 100, or portions thereof, may be implemented as an integrated circuit (IC) chip or as multiple IC chips (e.g., a multi-chip module) mounted on a circuit board and operating in conjunction with each other. As an example, system 100 is implemented on a mobile device, such as a smartphone, a notebook or laptop computer, an Internet of Things (IoT) device, etc. However, system 100 may alternatively be utilized in any power converter system, such as a step-down converter, configured to charge a battery 112.

[0023] System 100 includes a power supply 102 that generates a bus voltage VBUS on a node, such as what is described herein as a bus voltage node 104. Bus voltage node 104 represents a voltage rail (or power bus) for system 100. Bus voltage node 104 is coupled to provide the bus voltage VBUS to an input node (e.g., a source) of a blocking transistor 106.

[0024] For example, the blocking transistor 106 is implemented as a metal oxide semiconductor field effect transistor (MOSFET). In the illustrated example, the blocking transistor is shown as an n-channel enhancement mode MOSFET (NMOS). However, in other examples, other types of transistors, such as p-channel enhancement mode MOSFET (PMOS), may be used as the blocking transistor 106. Also, in other examples, different types of transistors, such as III-V transistors (e.g., as gallium nitride (GaN) transistors), insulated gate bipolar transistors (IGBT), bipolar junction transistors (BJT), and silicon carbide (SiC) transistors, may be used. The bus voltage node 104 is coupled to an input node (e.g., source) of the blocking transistor 106. An output node (e.g., drain) of the blocking transistor 106 is coupled to an input power node 108 of the power converter 110. In this example, the voltage at the input power node 108 is referred to as a converter input voltage (PMID).

[0025] Power converter 110 is configured to convert an input voltage PMID to provide a corresponding output voltage that provides a charge current ICHARGE at an output terminal. For example, battery 112 may be configured to generate a charge current ICHARGE for charging the battery based on the converter input voltage PMID and control signals CONTROL SIGNALS that are input to power converter 110.

[0026] As an example, the CONTROL SIGNALS vary based on data provided by external sources and / or sensors. The external sources and / or sensors providing the control signals CONTROL SIGNALS may include the temperature of the system 100, the temperature of the battery 112, the input current to the battery 112, the output current to the battery 112, the input voltage to the battery 112, and the output voltage to the battery 112. Other types of CONTROL SIGNALS may be provided as part of respective regulation loops for controlling the charging of the battery 112. A filter element (not shown) may be provided between the output of the power converter 110 and the battery 112 to reduce switching and other noise in the current signal provided to charge the battery.

[0027] A regulator 114 is coupled to a control node (e.g., gate) of the blocking transistor 106. The regulator 114 is also coupled to the bus voltage node 104 and the input power node 108 of the power converter 110. The regulator 114 is configured to adjust the voltage across the blocking transistor 106. For example, the regulator 114 is configured to apply a control voltage to the control node (e.g., gate) of the blocking transistor 106 to adjust the voltage across the blocking transistor 106 in response to a potential difference between the bus voltage VBUS at the bus voltage node 104 and the converter input voltage PMID at the input power node 108. In one example, the regulator 114 is configured to adjust the voltage drop across the blocking transistor 106 to a small voltage (e.g., less than 100 mV, such as 10 mV or 4 mV). The regulator 114 is also configured to turn off the blocking transistor 106 (e.g., operate in the cutoff region) in response to the PMID exceeding VBUS by a voltage threshold such that the blocking transistor blocks reverse current from flowing from the battery 112 to the bus voltage node 104 during the boost-buck state.

[0028] An input detector 116 is coupled to the bus voltage node 104 and to the control node of the blocking transistor 106. The input detector 116 is configured to compare the bus voltage VBUS to the output of the regulator 114. The input detector 116 is further configured to discharge the bus voltage VBUS at the bus voltage node 104 when the blocking transistor 106 is turned off in response to the bus voltage VBUS exceeding the converter input voltage PMID by a threshold voltage. The threshold voltage may be a negative voltage or a positive voltage. For example, the input detector 116 may include a switch device coupled between the bus voltage node and an electrically neutral (or lower potential) node, such as ground. The input detector 116 may thus activate a switch in response to detecting that the blocking transistor is turned off.

[0029] An unregulated boost-buck detector 118 includes inputs coupled to the bus voltage node 104 and the input power node 108. The unregulated boost-buck detector 118 is configured to generate a fault signal FAULT based on V at the bus voltage node 104 exceeding the voltage at the input power node 108 by a threshold level. The fault signal may be applied to the power converter 110 in response to detecting the unregulated boost-buck condition. The power converter 110 is configured to turn off (e.g., not provide ICHARGE to the battery 112) in response to the fault signal. Also, the input power node 108 may be discharged in response to the fault signal. For example, a switch device coupled between the input power node 108 and electrical ground may be activated in response to the fault signal.

[0030] The power converter 110 is configured to provide a charge current ICHARGE to the battery 112 to regulate the voltage at the output terminal to prevent overcharging of the battery 112 based on a converter input voltage PMID and CONTROL SIGNALS provided by external sources and / or sensors (e.g., temperature, voltage, and current sensors). The system 100 is further configured to apply a control voltage to a control node of the blocking transistor 106 based on a difference between the bus voltage VBUS and the converter input voltage PMID. The blocking transistor 106 is turned off (e.g., operates in a cutoff region) when the bus voltage VBUS exceeds the converter input voltage PMID by a threshold value to block reverse power flow from the battery 112, thereby preventing undesired discharge by the battery 112. The system 100 is further configured to shut off the power converter 110 to prevent unregulated boost-back, which may result in unregulated voltages and currents in the power converter 110.

[0031] System 100 exhibits improved boost-buck protection compared to typical power converters. For example, by configuring blocking transistor QBLK to operate as an ideal diode at the input of the power converter (rather than as a circuit element at the output), system 100 may better protect the input power source from boost-buck currents than many existing approaches. This protection is implemented by the regulator quickly turning off the blocking transistor in response to detecting a boost-buck condition. Also, the voltage VBUS at input bus voltage node 104 and the voltage PMID at input power node 108 may each be quickly discharged to help reduce the effects of undesirable boost-buck.

[0032] 2 shows a block diagram of a bidirectional power converter designed to convert a voltage at an input to provide an output voltage at an output (e.g., forward powering) and to perform power conversion and delivery from the output to the input (e.g., reverse powering). Due to the design of the bidirectional power converter, there is no unwanted power delivery. The bidirectional power converter includes circuit elements and control circuits configured to provide bidirectional power conversion and delivery. As such, bidirectional power converters are more complex, expensive and larger than unidirectional power converters.

[0033] 3 shows a block diagram of a unidirectional power converter designed to provide one-way power supply, i.e., from input to output (e.g., forward power supply). In a unidirectional power converter, any power supply from output to input (e.g., reverse power supply) is undesirable. Undesirable power supplies, such as boost-buck currents, can damage circuit elements at the input and / or output of the power converter, or the power converter itself.

[0034] FIG. 4 illustrates an example of a unidirectional power converter implemented as the battery charger of FIG. 3. Thus, FIG. 4 shows an input power source (e.g., a power supply) and an output power device (e.g., a battery). Unwanted power supply (e.g., reverse power supply) from the output power device, such as in response to the input power source being disconnected, can result in draining the output power device (e.g., a battery) and also damage the power converter circuit. In addition to the problems of unidirectional power converters, when an unwanted power supply is present, the output power source does not fully charge.

[0035] FIG. 5 shows an example of a unidirectional power converter configured to reduce reverse power supply (e.g., boost-buck condition) by implementing a diode D1 at the output of the converter. Thus, the diode is configured to detect and block negative current from the output. However, such an approach typically increases design complexity, increases device cost, and / or reduces device performance. Monitoring undesired power supply at the output of the unidirectional power converter increases design complexity, device cost, and reduces performance. For example, by including a diode at the output as shown in FIG. 5, the power converter may enter discontinuous conduction mode. Thus, various regulation control loops must be able to compensate for this or other undesired conditions (e.g., by implementing pulse frequency modulation). Using additional circuit elements and DCM tends to reduce bandwidth and increase ripple at the output.

[0036] FIG. 6 illustrates a block diagram of an example unidirectional power converter configured to reduce unwanted reverse power supply by implementing a diode D2 at the input, rather than at the output, as in FIG. 5. For example, the unidirectional power converter 600 includes a diode D2 coupled between an input voltage source VIN and the unidirectional power converter to block a boost-buck condition. By monitoring for unwanted power supply at the input, complexity and / or device cost may be reduced and may exhibit improved performance compared to the approach of FIG. 5. For example, monitoring at the input of the unidirectional power converter may allow a system (e.g., system 100 of FIG. 1) to monitor whether an input source (e.g., power source 102 of FIG. 1) has been removed. Monitoring at the input of the unidirectional power converter may also allow the system to turn off the power converter more quickly if a boost-buck condition is detected. For example, ripple at the output is reduced. However, in practice, the diode exhibits a voltage drop that reduces the overall efficiency of the power converter.

[0037] FIG. 7 illustrates an example block diagram of a unidirectional power converter system 700 according to the approach of FIG. 6 including a blocking transistor QBLK at the input to reduce reverse power supply (e.g., boost-buck state) through a power converter 708. The system 700 includes a power supply 702 that provides an input voltage VINPUT to an input node (e.g., source) 715 of the blocking transistor QBLK. The power converter 708 is configured to convert the input voltage VINPUT to a corresponding output voltage according to a converter topology. The power converter 708 further provides a charge current ICHARGE at an output power node 716. The blocking transistor QBLK may be implemented as a MOSFET, a bipolar junction transistor, or other type of transistor device. In this example, the charge pump 704 is powered by a supply voltage VINPUT to drive a control node (e.g., gate) of the blocking transistor QBLK. An output node (e.g., drain) of the blocking transistor QBLK provides a converter input voltage PMID at an input power node 714 to the power converter 708. The power converter 708 includes a pulse wave modulator (PWM) converter 710 configured to provide a PWM signal to a power stage 712. The PWM control signal is based on CONTROL SIGNALS for one or more regulation loops. For example, the regulation loops monitor the temperature, input voltage VINPUT, voltage output, input current, and output current of the system 700.

[0038] The power stage 712 is configured to provide a high-side drive signal HSCTRL to the high-side transistor QHSFET and a low-side drive signal LSCTRL to the low-side transistor QLSFET. The high-side drive signal HSCTRL and the low-side control signal LSCTRL are complementary signals such that when the high-side control signal HSCTRL has a logic 1 value, the low-side drive signal LSCTRL has a logic 0 value, and when the high-side drive signal HSCTRL has a logic 0 value, the low-side drive signal LSCTRL has a logic 1 value. In the charging mode, in response to the high-side drive signal HSCTRL having a high voltage (e.g., logic 1), the high-side transistor QHSFET is turned on (e.g., operating in saturation), while in response to the low-side drive signal LSCTRL being provided as a low voltage (e.g., logic 0), the low-side transistor QLSFET is turned off (e.g., operating in cutoff). In the non-charging mode, the high-side transistor QHSFET is turned off (e.g., operating in cutoff) in response to the high-side drive signal HSCTRL having a logic 0, while the low-side transistor QLSFET is turned off (e.g., operating in saturation) in response to the low-side control signal LSCTRL having a logic 1.

[0039] System 700 prevents reverse powering in a unidirectional power converter. However, system 700 exhibits performance degradation due to the voltage drop across blocking transistor QBLK. Also, the system cannot respond quickly to boost-buck conditions due to the passive control of blocking transistor QBLK. Instead, blocking transistor QBLK is turned off (e.g., operates in the cutoff region) only after input voltage VINPUT is removed or falls well below the gate voltage provided by the charge pump. System 700 also tends to be sensitive to the operation of the regulation loop that provides CONTROL SIGNALS to power converter 710.

[0040] Figure 8 illustrates an example of a power converter system 800 configured to reduce boost-buck conditions. In the example of Figure 8, the system is shown for charging a battery 802 connected to an output, such as corresponding to system 100 of Figure 1. System 800 addresses problems present in system 700 of Figure 7. System 800 is implemented in some examples as an IC chip or multiple IC chips mounted on a circuit board with associated circuit elements. As an example, system 800 is implemented on a portable electronic device such as a smartphone, notebook, or laptop computer.

[0041] The system 800 includes a power supply 804 (e.g., power supply 102 of FIG. 1) configured to provide power to a voltage node (e.g., a voltage rail or bus) 808. The power supply 804 thus provides an input voltage VINPUT to the node 808. The node 808 represents an input voltage rail that may provide power to various circuit elements, including those illustrated with respect to the system 800. In some examples, the battery 802 is configured to provide power to an external circuit 806.

[0042] Node 808 is coupled to a terminal of a blocking transistor QBLK (e.g., corresponding to blocking transistor 106 of FIG. 1). Blocking transistor QBLK may be implemented as a MOSFET, a bipolar junction transistor, or other transistor device. In the example of FIG. 8, blocking transistor QBLK is an NMOS, and node 808 is coupled to a source (e.g., an input node) of blocking transistor QBLK. A drain (e.g., an output node) of blocking transistor QBLK is coupled to an input node 810 of a power converter 812, and the voltage at node 810 is referred to as a converter input voltage (PMID).

[0043] In one example, the regulator 820 includes an amplifier 821 (e.g., an op-amp) having an inverting input coupled to the PMID node 810. A voltage source is coupled between the node 808 and the non-inverting input of the amplifier 821. The voltage source is configured to provide a reference voltage (VREF) used to regulate the voltage drop across the blocking transistor QBLK. As an example, the reference voltage VREF is set to a low voltage (e.g., the reference voltage can be less than 100 mV, such as about 20 mV or 4 mV). The output of the amplifier 821 is coupled to the gate of the blocking transistor to control operation, including regulation and blocking modes, as described herein. Thus, in addition to regulating the drop across the blocking transistor QBLK, the regulator 820 is also configured to turn off the blocking transistor QBLK to block the boost-back current flowing from the output terminal to the second node in response to the voltage PMID exceeding (e.g., by at least a threshold) the voltage VINPUT at the second node.

[0044] As a further example, a charge pump 823 is also coupled to the control node (e.g., gate) of the blocking transistor QBLK. The charge pump 823 is configured to drive the blocking transistor QBLK to facilitate its operation, including during regulation as well as when it is turned off to block. Thus, the voltage regulator 820 and the charge pump 823 are configured to coordinate and control the operation of the blocking transistor QBLK to operate as an ideal diode with a very small voltage drop across it as determined by a reference voltage, and with fast operation to turn off and block current (e.g., from PMID to VINPUT). For example, as described above, the voltage drop can be regulated to a voltage much smaller than a typical diode drop, such as a voltage of less than 100 mV (e.g., about 20 mV or 4 mV or less).

[0045] Power converter 812 (e.g., corresponding to power converter 110 in FIG. 1 ) is configured to provide a charge current ICHARGE and an output voltage VBAT at an output power node 818, which may be applied to charge battery 802 during a charging mode. For example, the power converter is implemented as a step-down power converter configured to operate in a forced continuous conduction mode.

[0046] As an example, the power converter 812 includes a pulse width modulation (PWM) generator 814 configured to provide a PWM signal to the power stage 816 in response to one or more CONTROL SIGNALS. The power stage 816 is configured to apply a high side control signal HSCTRL to the high side transistor QHSFET and a low side control signal LSCTRL to the low side transistor QLSFET based on the PWM signal. The power stage 816 may provide the high side control signal HSCTRL and the control signal LSCTRL as complementary drive signals such that when one control signal asserts a logic 1, the other control signal asserts a logic 0. The CONTROL SIGNALS may be provided from external sources and / or sensors input to the PWM generator 814, such as corresponding to respective regulation loops. For example, the CONTROL SIGNALS may include the temperature of the battery charger, the temperature of the battery 802, and the state of charge of the battery 802. The state of charge of the battery 802 is based on the input and / or output current and voltage of the battery 802. In some examples, power converter 812 operates in a non-charging mode to prevent overcharging when battery 802 is fully charged. In other examples, power converter 812 operates in a non-charging mode in response to detecting that system 800 and / or battery 802 exceed a temperature threshold. In yet another example, power stage 816 is configured to operate in a non-charging mode in response to receiving a fault signal from boost-buck detector 826.

[0047] As a further example, the power stage applies a high-side control signal HSCTRL to a control node (e.g., gate) of the high-side transistor QHSFET and a low-side control signal LSCTRL to a control node (e.g., gate) of the low-side transistor QLSFET. The high-side transistor QHSFET and the low-side transistor QLSFET may be implemented as MOSFETs or bipolar junction transistors. In the example of FIG. 8, NMOS devices are used. An input node (e.g., drain) of the high-side transistor QHSFET is coupled to an input power node 810, and an output node (e.g., source) of the high-side transistor QHSFET is coupled to an output power node 818. An input node (e.g., drain) of the low-side transistor QLSFET is coupled to an output power node 818, and an output node (e.g., source) of the low-side transistor QLSFET is coupled to a neutral node (e.g., electrical ground). Each of the QHSFETs and QLSFETs is configured to be on when the corresponding control signal is a logic one and off when the corresponding control signal is a logic zero. The power stage 816 is configured to apply a high side control signal HSCTRL and a low side control signal LSCTRL based on the CONTROL SIGNALS applied to the PWM generators 814 , 812 .

[0048] The power converter 812 is configured to operate in a charging mode when the high-side transistor QHSFET is turned on and the low-side transistor QLSFET is turned off, such that a charge current ICHARGE is applied to the battery 802 to provide a corresponding battery voltage VBAT. The power converter 812 may further be configured to operate in a non-charging or discharging mode when the high-side transistor QHSFET is turned off and the low-side transistor QLSFET is turned on or operates in the triode region. In the discharging mode, the charge current ICHARGE and the output voltage VBAT at the output power node 818 may be discharged to a neutral node coupled to the output node of the low-side transistor QLSFET.

[0049] The regulator is also configured to provide a regulator output voltage VCR to an input detector 824 (e.g., corresponding to input detector 116 in FIG. 1). The input detector 824 has inputs coupled to a control node 822 corresponding to a voltage VBUS and to node 808. The input detector 824 is configured to sink current from node 808 in response to detecting that the blocking transistor has been turned off based on the voltages at VBUS and the control node 822.

[0050] As an example, the input detector 824 includes a switch device QID coupled between the node 808 and a neutral node (e.g., electrical ground), which may be connected in series with a resistor to dissipate current during discharge, for example. The switch device may be implemented as a transistor device, such as a MOSFET (e.g., NMOS or PMOS) or a bipolar junction transistor. A comparator 825 has a first input coupled to a control node 822 of the blocking transistor QBLK and an output coupled to a control input (e.g., gate) of the switch device QID. A voltage source VTH is coupled between the node 808 (e.g., the drain of QID) and a second input of the comparator. The voltage source VTH is configured to apply a threshold voltage at the second input of the comparator. The comparator is configured to control the switch device QID based on comparing the voltage at the node 808 to the voltage VCR at the control node 822. For example, the comparator 825 is configured to activate (e.g., turn on) the switch device QID to discharge the VBUS node 808 in response to the voltage VCR at the control node 822 of the blocking transistor QBLK falling below the voltage at the second node by at least the threshold voltage VTH. This may occur during a boost-buck state, including when the power source 804 is disconnected from the VBUS node 808. The power source 804 may be disconnected by opening the switch SW or otherwise (e.g., by removing the plug from the AC outlet).

[0051] Boost-buck detector 826 (e.g., corresponding to unregulated boost-buck detector 118 of FIG. 1) is configured to generate a fault signal indicative of an unregulated boost-buck condition based on the voltage PMID and the voltage VBUS. Boost-buck detector 826 has inputs coupled to PMID node 810 for receiving the voltage PMID and to node 808 for receiving the voltage VBUS. Boost-buck detector 826 is configured to provide a fault signal that turns off the power converter in response to the voltage at PMID node 810 exceeding the voltage at VBUS node 808 by a fault threshold (VFAULT).

[0052] In the example of FIG. 8, boost-buck detector 826 includes a comparator 827 having a first input (e.g., a non-inverting input) coupled to a node corresponding to voltage PMID. An output of comparator 827 is coupled to provide a boost-buck detector voltage VBD to a control input of switch device QBD and to a fault input of power converter 812. The boost-buck detector voltage VBD at node 828 also corresponds to a fault signal. Switch device QBD is coupled between PMID node 810 and a neutral node (e.g., electrical ground). For example, switch device QBD is a transistor device such as a MOSFET (e.g., NMOS or PMOS), a bipolar junction transistor, or other type of transistor device. In the example of FIG. 8, a voltage source is coupled between VBUS node 808 and a second input (e.g., an inverting input) of comparator 827. The voltage source is configured to apply a fault threshold voltage at the second input to provide a boosted buck detector voltage VBD at node 828 and to control switch device QBD based on comparing the voltages VBUS and PMID to the fault threshold voltage. The boosted buck detector voltage is applied to a control node (e.g., a gate) of transistor device QBD. For example, comparator 827 is configured to provide a fault signal at node 828 to activate switch device QBD and discharge the first node in response to the voltage at PMID node 810 exceeding the voltage at VBUS node 808 by at least the fault threshold voltage.

[0053] As a further example, switch device QBD is an NMOS having a drain coupled to VBUS node 808 and a source coupled to a neutral node (e.g., electrical ground). The output of comparator 827 is coupled to the gate of QBD. Boost-buck detector 826 is configured to turn on transistor QBD by applying a boost-buck detector voltage VBD (e.g., a FAULT signal) to the gate of transistor QBD in response to the bus voltage VBUS at 808 exceeding the PMID voltage at 810 by at least a fault threshold voltage VFAULT. In response to turning on transistor QBD, the PMID voltage at 808PMID at input power node 810 is discharged to a neutral node (e.g., electrical ground). The boost-buck detector voltage VBD is also applied to power stage 816 of power converter 812 as a FAULT signal. The FAULT signal is operable to turn off the power stage 816 of the power converter 812 (eg, not provide ICHARGE to the battery 802) during a detected boost-buck condition.

[0054] In view of the above, the system 800 of FIG. 8 is configured to overcome the problems of some power systems, such as the system 700 of FIG. 7. In particular, the system 800 provides improved boost-buck protection by implementing enhanced control (e.g., by the regulator 820) over the blocking transistor QBLK. For example, the regulator 820 controls the blocking transistor QBLK to operate as an ideal diode at the input of the power converter 812 with a very low voltage drop (e.g., less than 100 mV, such as 4 mV) that can be turned off quickly during a boost-buck event. Also, as disclosed herein, the system 800 allows the bus voltage VBUS to be discharged (e.g., via the input detector 824) and the converter input voltage PMID to be discharged (e.g., via the boost-buck detector 826). Furthermore, the system 800 also generates a FAULT signal (e.g., by the boost-buck detector 826) to the power stage 816 of the power converter 812 in response to the converter input voltage PMID exceeding the bus voltage VBUS by a threshold voltage.

[0055] As shown in Figures 9 and 10, the system 800 exhibits increased stability of the charge current ICHARGE (e.g., reduced ripple) and a drop in the converter input voltage PMID when the input voltage VINPUT is removed. Figure 9 shows a transient analysis of a power converter system such as the system 800 of Figure 8. In particular, Figure 9 shows a graph 900 illustrating various waveforms from the system 800 as a function of time for an example when the power source (e.g., power source 804 of Figure 8) is disconnected from the unidirectional power converter while power is being delivered to the output (e.g., battery 802 of Figure 8). For example, the power source may be disconnected in response to opening a switch SW or unplugging the adapter from an AC outlet.

[0056] FIG. 9 illustrates the removal of the input voltage VINPUT at time t1. As the power converter system continues to provide power to the output, the converter input voltage PMID and the bus voltage VBUS decrease (e.g., from about 4.2V to about −0.2V). The charge current ICHARGE increases and decreases between time t1 and time t2, indicating reverse powering from the output (e.g., corresponding to a boost-buck state). In response to the reverse powering, the system begins regulating the converter input voltage PMID starting at time t2, and VDPM increases (e.g., from about −0.1V to about 1.pV). Time t2 illustrates the power at the output power node 818 of FIG. 8 beginning to discharge to the neutral node (e.g., ground), as indicated by the decrease in ICHARGE. Thus, by time t4, the charge current ICHARGE and the converter input voltage PMID are fully discharged. Also, the converter input voltage PMID thus decreases from time t1 to time t2, and finally stabilizes (e.g., to about 4V) at time t3. At time t5, blocking transistor QBLK of FIG. 8 is turned off by regulator 820 based on VGS of QBLK. At time t5, transistor QID of input detector 824 is also turned on, resulting in the voltage VBUS at node 808 being discharged to a neutral node (e.g., ground) through a resistor. In response to VGS of QBLK being pulled low, comparator 821 goes high (shown at 902). At time t6, power stage 816 of FIG. 8 is turned off (e.g., in response to a FAULT signal provided by boost-buck detector 826) and stops providing power to the output. Thus, at time t6, output 822 of comparator 821 goes low, as does VDPM and the output of the power stage at 818. In the illustrated example, the time between time t1 and time t6 is about 0.34 ms.

[0057] FIG. 10 is a graph 1000 illustrating example waveforms for a typical power converter system when the input power source is removed in an example system (e.g., system 700 of FIG. 7) that does not implement boost-buck protection as disclosed herein. In FIG. 10, the battery voltage VBAT increases at time t1 in response to unregulated boost-buck and exceeds the battery regulation voltage. The charge current ICHARGE decreases between time t1 and time t2. At time t2, the oscillation of the charge current ICHARGE begins to increase until time t5 where there is a current swing of about 2 A, at which the power converter system is turned off. At time t2, the converter input voltage PMID also begins to increase as the system attempts to charge the battery. The voltage difference VBUS-PMID also decreases from time t1 until PMID increases above VBUS at time t4. The blocking transistor (e.g., blocking transistor QBLK in FIG. 5 or FIG. 7) is turned off at time t3 in response to the VGS of QBLK going low, as shown at 1002. However, in the example of FIG. 10 (as opposed to FIG. 9), the charge current ICHARGE continues to oscillate even after the blocking transistor is turned off. This is because the converter input voltage PMID increases from about 4V (at time t2) to about 8.4V when the power converter system is turned off (at time t6). The converter input voltage PMID remains in the power converter system when the power converter system is turned off. At time t5, a fault signal FAULT is applied to turn off the power stage, stopping the power converter system from trying to charge the output of the power converter system. The power converter system illustrated in FIG. 10 takes about 0.2 ms to turn off. Exceeding the battery regulation voltage, the oscillation of the charge current ICHARGE, and the uncontrolled increase in the converter input voltage PMID can cause damage due to overheating and excessive voltage in the power converter system and / or the battery.

[0058] In comparison, the operation of the power converter system shown in Figure 9 provides a charge current ICHARGE and power stage output with minimal amplitude oscillations compared to the typical power converter system shown in Figure 10. The waveforms shown in Figure 9 also show that when the input voltage VINPUT is removed, the converter input voltage PMID discharges, rather than increasing and maintaining voltage until the power stage is turned off (e.g., not converting), as in the approach shown in Figure 10. Thus, the systems of Figures 1 and 8 as disclosed herein thus exhibit improved performance compared to typical systems.

[0059] 11 is a flow chart illustrating an example method 1100 for protecting a power converter (e.g., a unidirectional buck power converter). The method 1100 is described with respect to the system 800 of FIG. 8, and reference may be made back to FIG. 8 for additional context.

[0060] In step 1102, the method includes controlling a charge current (e.g., ICHARGE) to an output terminal (e.g., corresponding to node 818) adapted to be coupled to a battery (e.g., battery 802) based on a voltage at a first node (e.g., PMID node 810) and a control signal. For example, the PWM converter 814 and the power stage 816 control the QHSFET and the QLSFET to provide the charge current ICHARGE. In step 1104, a voltage across a blocking transistor (e.g., QBLK) is adjusted. The blocking transistor QBLK is coupled between a second node (e.g., VBUS node 808) and a first node (e.g., PMID node 810). For example, the regulator 820 is configured to adjust a voltage potential across QBLK based on the voltages VBUS and PMID. Thus, the voltage adjustment (e.g., by the regulator 820) across QBLK is operable to set a voltage at the PMID node 810 based on the voltage at the VBUS node 808. In step 1106, the voltages at the first node and the second node are detected to determine whether the voltage at the first node exceeds the voltage at the second node by a threshold. For example, the regulator is configured to compare the voltages at the VBUS node 808 and the PMID node 810 against a threshold VREF. In step 1108, in response to detecting that the voltage at the first node exceeds the voltage at the second node by a threshold, the blocking transistor is turned off. For example, the regulator 820 is configured to turn off the blocking transistor QBLK when the voltage at the PMID node 810 exceeds the voltage at the VBUS node 808. Also, in step 1108, the second node is discharged. For example, the input detector 824 is configured to discharge the voltage VBUS at the node 808 based on the voltage at the gate of QBLK and the voltage at the VBUS node (e.g., gate-to-source voltage).If the determination at step 1106 is negative, indicating that a boost-back condition does not exist, the method returns to step 1102 and repeats the actions at 1102 and 1104 .

[0061] In some examples, the method 1100 may further include generating a fault signal (e.g., by the boost-buck detector 826) in response to detecting an unregulated boost-buck condition of the blocking transistor QBLK based on the voltage at the first node relative to the voltage at the second node. For example, the boost-buck detector 826 is configured to compare the voltages at the VBUS node 808 and the PMID node 810 against a threshold VFAULT and provide a FAULT signal in response to detecting an unregulated boost-buck condition. For example, an unregulated boost-buck condition may be detected by the boost-buck detector 826 when the voltage (PMID) exceeds the bus voltage VBUS by at least a fault threshold (VFAULT), as disclosed herein. In response to generating the fault signal, the charge current may be disabled (e.g., by turning off a power stage of the power converter) and / or the first node may be discharged (e.g., by enabling a switch of the boost-buck detector 826).

[0062] As another example, blocking transistor QBLK is implemented as a MOSFET device (e.g., an NMOS). Thus, adjusting the voltage across blocking transistor QBLK may include adjusting the drain-to-source voltage across the blocking transistor based on a reference voltage (e.g., voltage VREF) such that the blocking transistor is configured to operate as an ideal diode based on the voltage at VBUS node 808 and the voltage at PMID node 810.

[0063] As used herein, the term "based on" means based at least in part on. Variations in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A device, comprising: a power converter having an input coupled to a first node and an output coupled to an output terminal adapted to be coupled to a battery; a blocking transistor coupled between a second node and the first node along a path between the second node and the output terminal; a regulator having a first input coupled to the first node, a second input coupled to the second node, and an output coupled to a control node of the blocking transistor, the regulator being configured to control the blocking transistor to adjust a voltage across the blocking transistor based on a voltage between the first node and the second node, and configured to turn off the blocking transistor in response to a first voltage at the first node exceeding a second voltage at the second node by a threshold value to interrupt a boost-back current flowing along the path from the output terminal to the second node; an input detector having a first input coupled to the control node and a second input coupled to the second node, the input detector configured to sink power from the second node in response to detecting that the blocking transistor is turned off; Including, the device.

2. 2. The device of claim 1, the blocking transistor comprises a field effect transistor having a drain coupled to the first node and a source coupled to the second node; The device, wherein the regulator is configured to adjust the voltage drop from the source to the drain based on a reference voltage such that the blocking transistor operates as an ideal diode.

3. 3. The device of claim 2, The regulator, an amplifier having an inverting input coupled to the first node, a non-inverting input, and an output coupled to the gate of the blocking transistor; a voltage source coupled between the second node and a non-inverting input of the amplifier, the voltage source configured to provide the reference voltage; Including, the device.

4. 2. The device of claim 1, The input detector includes: a switch device coupled between the second node and a neutral node; a comparator having a first input coupled to a control node of the blocking transistor, a second input, and an output coupled to a control input of the switch device; a voltage source coupled between the second node and a second input of the comparator, the voltage source configured to apply a threshold voltage to the second input; Including, the comparator is configured to enable the switch device to discharge the second node in response to a voltage at the control node of the blocking transistor dropping below the voltage at the second node by at least the threshold voltage.

5. 2. The device of claim 1, 23. The device of claim 22, further comprising: a boost-buck detector having a first input coupled to the first node and a second input coupled to the second node, the boost-buck detector being configured to provide a fault signal to turn off the power converter in response to the voltage at the first node exceeding the voltage at the second node by a fault threshold.

6. 6. The device of claim 5, The boost-buck detector, a switch device coupled between the first node and a neutral node; a comparator having a first input coupled to the first node, a second input, and an output coupled to a control input of the switch device and a fault input of the power converter; a voltage source coupled between the second node and a second input of the comparator, the comparator configured to apply the fault threshold voltage to the second input such that, in response to a voltage at the first node exceeding the voltage at the second node by at least a fault threshold voltage, the comparator enables the switch device to discharge the first node; Including, the device.

7. 2. The device of claim 1, The device, wherein the power converter is configured as a step-down power converter configured to operate in a forced continuous conduction mode.

8. 2. The device of claim 1, the power converter: a pulse width modulator configured to generate a pulse width modulated (PWM) signal with a duty cycle that varies as a function of one or more control signals; a power stage converter configured to generate first and second drive signals based on the PWM signal; a high-side transistor coupled between the first node and an output of the power converter, a state of the high-side transistor being controlled based on the first drive signal; a low-side transistor coupled between the output and a neutral node of the power converter, the state of the low-side transistor being controlled by the second drive signal; Including, A charge current flows through the output terminal to charge the battery.

9. 2. The device of claim 1, a boost-buck detector configured to provide a fault signal at a fault output in response to detecting an unregulated boost-buck condition via the blocking transistor; The device, wherein the power converter includes a power stage having a fault input coupled to a fault output of the boost-buck detector, the device being configured to turn off the power stage based on the fault signal.

10. 1. A system comprising: a power converter configured to provide a charge current to an output terminal based on a voltage at a first node in response to one or more control signals; a blocking transistor coupled between a second node and an input node of the power converter; a regulator configured to adjust a voltage drop across the blocking transistor based on a voltage at the first node and a voltage at the second node, the regulator being further configured to turn off the blocking transistor in response to the voltage at the first node exceeding a voltage at the second node by a threshold such that current from the output terminal to the second node is blocked by the blocking transistor; an input detector configured to discharge the second node in response to the blocking transistor being turned off; a boost-buck detector configured to turn off the power converter in response to detecting a boost-buck condition of the blocking transistor; Including, the system.

11. 11. The system of claim 10, the blocking transistor comprises a field effect transistor having a drain coupled to the first node and a source coupled to the second node; the regulator is configured to adjust the voltage drop from the source to the drain based on a reference voltage such that the blocking transistor is configured to operate as an ideal diode based on the voltage at the second node and the voltage at the first node.

12. 12. The system of claim 11, The regulator, an amplifier having an inverting input coupled to the first node, a non-inverting input, and an output coupled to the gate of the blocking transistor; a voltage source coupled between the second node and a non-inverting input of the amplifier, the voltage source configured to provide the reference voltage; Including, the system.

13. 11. The system of claim 10, The boost-buck detector, a comparator configured to provide a fault signal in response to the voltage at the first node exceeding the voltage at the second node by at least a fault threshold voltage; a switch device coupled between the first node and a neutral node, the switch device configured to discharge the second node in response to the fault signal; Including, The system, wherein the power converter is further configured to turn off in response to the fault signal.

14. 11. The system of claim 10, The input detector includes: a switch device coupled between the second node and a neutral node; a comparator configured to enable the switch device to discharge the second node in response to a voltage at a control node of the blocking transistor dropping below a voltage at the second node by at least a threshold voltage; Including, the system.

15. 11. The system of claim 10, The system further includes a power supply configured to provide a voltage at the second node.

16. 11. The system of claim 10, a battery coupled to the output terminal; The system, wherein the power converter is further configured to provide the charge current to charge the battery.

17. 1. A method comprising: controlling a charge current to an output terminal adapted to be coupled to a battery in response to one or more control signals based on a voltage at the first node; adjusting a voltage across a blocking transistor coupled between a second node and the first node based on a reference voltage; monitoring a voltage at the first node and a voltage at the second node; turning off the blocking transistor in response to the voltage at the first node exceeding the voltage at the second node by a threshold; discharging the second node; and A method comprising:

18. 20. The method of claim 17, generating a fault signal in response to detecting an unregulated boost-buck condition of the blocking transistor based on a voltage at the first node relative to a voltage at the second node; disabling a power converter in response to the fault signal; discharging the first node in response to the fault signal; The method further comprises:

19. 20. The method of claim 17, the blocking transistor is a field effect transistor; adjusting the voltage across the blocking transistor such that the blocking transistor is configured to operate as an ideal diode based on a voltage at the second node and a voltage at the first node includes adjusting a source-drain voltage across the blocking transistor based on the reference voltage.

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