BUS BAND CONTROL DEVICE AND BUS BAND CONTROL METHOD

Abstract

The purpose of the present invention is to achieve a bus band control device and a bus band control method that prevent impairment of resource availability.　A bus band control device (100) comprises a resource isolation mechanism (150) that is connected to a bus and determines the range of resources that can be accessed by respective programs, a hardware timer (130) that interrupts a CPU core set (111) at predetermined timing, shared memory (120), and a bus band suppression program (105) that performs occupation processing for the CPU core set (111) when there has been an interruption and, when the occupation processing is complete, returns the processing of the CPU core set (111) to before the interruption. The resource isolation mechanism (150) allows only the bus band suppression program (105) to access the hardware timer (130), a vector table (121), and a storage area (122) used by the bus band suppression program (105).

Description

[Technical field]

[0001] The present application relates to a bus bandwidth control device and a bus bandwidth control method. [Background technology]

[0002] In computer configurations, there are bus masters that actively initiate data transfers, and bus slaves that passively wait for requests from the bus master. For example, a CPU (Central Processing Unit) functions as a bus master, and hardware resources such as memory, storage, and other peripheral devices function as bus slaves, i.e., resources. The CPU and each resource are connected via a bus. In addition, a CPU may have multiple CPU cores, and multiple software programs (hereinafter simply referred to as programs) running on each CPU core may share and use the resources. When multiple programs share and use resources, the resource usage range is divided into a range or unit where the influence between programs is to be diluted, taking into account the processing contents, services, and security of each program in the system. There is also a method of dividing the resource usage range for each CPU core on which each software runs. In such a method, the resource usage range must be considered in the design and implementation of the programs running on each CPU core so as not to interfere with the operation of other CPU cores.

[0003] Programs that run on CPU cores include communication programs that connect to the outside of the system. Because such communication programs maintain connections to the outside of the system by enabling access from the outside, there is a possibility that unknown security holes could be exploited to hijack the CPU core on which the communication program runs. A hijacked CPU core may execute unintended processes, but it is difficult to completely counter unknown security holes, so even if one CPU core is hijacked, it is necessary to prevent the effects of the hijack from spreading to other CPU cores.

[0004] In order to protect other CPU cores from the effects of takeover, it is necessary to limit or control access to resources shared by multiple CPU cores. For example, Patent Document 1 discloses a bus system that allows access to a shared memory only when a condition is satisfied, such as a match between key data for receiving access permission and unique data held by the CPU, by a bus access control unit provided in a bus bridge circuit that relays data transfer between an internal bus and a peripheral bus. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-293536 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, the technology of Patent Document 1 has a problem that when a CPU core is hijacked, the availability of resources by other CPU cores may be impaired. First, in the technology of Patent Document 1, connections to resources other than the shared memory are not made via the bus access control unit, and access to resources other than the shared memory is not controlled. Even if connections to resources other than the shared memory are made via the bus access control unit, the hijacked CPU core may satisfy the access permission conditions in the method described in Patent Document 1. This is because the unique data held by the CPU is not changed by the hijacking of the CPU core, and bus access cannot be blocked in response to the hijacking. If the hijacked CPU core is given access permission to a specific resource, the hijacked CPU core may frequently access the resource, which may put a strain on the bus bandwidth of the bus connecting the CPU core and the resource, and may inhibit access to the resource by other CPU cores. If access to a resource is inhibited in this way, the availability of the resource is impaired.

[0007] The present application has been made to solve the above-mentioned problems, and has an object to provide a bus bandwidth control device and a bus bandwidth control method that prevent the availability of resources from being impaired. [Means for solving the problem]

[0008] The bus bandwidth control device disclosed in the present application is a bus bandwidth control device that controls the bus bandwidth used by programs in a system in which a CPU core set executing multiple programs and multiple resources are connected via a bus, and includes a resource isolation mechanism that is connected to the bus and determines the range of resources that each program can access, a hardware timer that interrupts the CPU core set at a predetermined timing, a shared memory that is one of the resources and has a memory area allocated to each of the multiple programs by the resource isolation mechanism, and a bus bandwidth suppression program that is executed by the CPU core set and that, when an interrupt occurs, executes an exclusive process for the CPU core set and, when the exclusive process ends, returns the processing of the CPU core set to before the interrupt, the memory area includes a vector table that indicates the process to be executed when an interrupt occurs, and a memory area used by the bus bandwidth suppression program, and the resource isolation mechanism allows only the bus bandwidth suppression program to access the hardware timer, the vector table, and the memory area used by the bus bandwidth suppression program.

[0009] In addition, the bus bandwidth control method disclosed in the present application is a bus bandwidth control method for controlling the bandwidth of the bus used by a program in a system in which a CPU core set executing multiple programs and multiple resources are connected via a bus, and includes a step of a hardware timer interrupting the CPU core set at a predetermined timing, a step of executing exclusive processing for the CPU core set when the interrupt occurs, and a step of returning the processing of the CPU core set to the state before the interrupt when the exclusive processing is completed, and the memory area of ​​a shared memory, which is one of the resources, includes a vector table indicating the processing to be executed when an interrupt occurs, and a memory area used by a bus bandwidth suppression program that executes the exclusive processing, and access to the hardware timer, the vector table, and the memory area used by the bus bandwidth suppression program is permitted only to the bus bandwidth suppression program. Effect of the Invention

[0010] According to the bus bandwidth control device and the bus bandwidth control method disclosed in the present application, it is possible to prevent the availability of resources from being impaired. but can. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic configuration diagram showing a bus bandwidth control device according to a first embodiment. [Diagram 2] 4 is a block diagram showing a bus bandwidth throttling program according to the first embodiment. FIG. [Diagram 3] 4 is a flow chart showing the operation of the bus bandwidth control device in the first embodiment. [Figure 4] FIG. 11 is a schematic configuration diagram showing a bus bandwidth control device according to a second embodiment. [Diagram 5] FIG. 11 is a block diagram showing a bus bandwidth throttling program according to the second embodiment. [Figure 6] FIG. 11 is a flow chart showing the operation of the bus bandwidth control device in the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Embodiment 1 A first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a schematic configuration diagram showing a bus access control device in the first embodiment. In a system having a CPU core set 111 and a CPU core set 112, each of which executes a plurality of programs 101, 109 and is connected to a plurality of resources via a resource separation mechanism 140 and an interconnect 150 (Interconnect in Fig. 1), a bus bandwidth control device 100 controls the bandwidth of a bus (bus bandwidth) used by a program 101 executed in the CPU core set 111. Note that the "resources" in the first embodiment include a shared memory 120, a hardware timer 130, and a non-controllable resource 190.

[0013] The program 101 executed in the CPU core set 111 includes a communication program 102 for communicating with the outside of the system, and a bus bandwidth throttling program 105. On the other hand, the program 109 executed in the CPU core set 112 does not include the communication program 102 or the bus bandwidth throttling program 105.

[0014] The shared memory 120 is shared by the program 101 executed in the CPU core set 111 and the program 109 executed in the CPU core set 112, and the memory area (accessible area) used by each program 101 is allocated by the resource separation mechanism 140. In FIG. 1, only the memory area allocated to the bus bandwidth throttling program 105 is illustrated. Of the memory areas of the shared memory 120, the memory areas allocated to the bus bandwidth throttling program 105 are the memory area in which the vector table 121 is stored and the memory area 122 used by the bus bandwidth throttling program 105. The vector table 121 registers an address indicating a process to be executed by the CPU core set 111 when the hardware timer 130 interrupts the CPU core set 111, and in the first embodiment, the address of the bus bandwidth throttling program 105 is registered.

[0015] The hardware timer 130 issues an interrupt to the CPU core set 111 at a predetermined timing. This interrupt causes the bus bandwidth throttling program 105 to start operating, and the bus bandwidth throttling program 105 executes an occupation process. The bus bandwidth throttling program 105 will be described in detail later.

[0016] The resource isolation mechanism 140 determines the range of resources that each program 101 can access, and is configured, for example, by an IOMMU (Input Output Memory Management Unit). The resource isolation mechanism 140 may also be configured using a hardware module that has a register for storing setting information and permits or prohibits access to the bus when a bus master (CPU core set) accesses a bus slave (shared memory, etc.) according to the setting information.

[0017] The resource separation mechanism 140 in the first embodiment allows only the program having a preset key ID among the programs 101 executed in the CPU core set 111 to access the configuration shown by double lines in Fig. 1, that is, the vector table 121, the memory area 122, and the hardware timer 130. In the first embodiment, the above-mentioned "preset key ID" is held only by the bus bandwidth throttling program 105. Therefore, the vector table 121, the memory area 122, and the hardware timer 130 can be accessed only by the bus bandwidth throttling program 105. However, since the object of the access control by the resource separation mechanism 140 is the program 101 executed in the CPU core set 111 (hatched in Fig. 1), access by the program 109 executed in the CPU core set 112 to the hardware timer 130 and the like (configuration shown by double lines) is not restricted.

[0018] The CPU core set 111 and the resource separation mechanism 140 are connected by a controlled system bus 181. The CPU core set 112 and the resource separation mechanism 140 are connected by a non-controlled system bus 182.

[0019] The resource separation mechanism 140 is connected to each resource via an interconnect 150 (Interconnect in FIG. 1). The resource separation mechanism 140 is connected to the shared memory 120 and the hardware timer 130 via a controlled external bus 183. The resource separation mechanism 140 is connected to the non-controlled resource 190 via a non-controlled external bus 184.

[0020] 1, there are configurations shown by solid lines and configurations shown by dashed lines, and the configurations shown by solid lines are targets of access control by the bus bandwidth control device 100, while the configurations shown by dashed lines are not targets of access control by the bus bandwidth control device 100. That is, the program 101 (including the communication program 102 and the bus bandwidth throttling program 105) executed in the CPU core set 111, the shared memory 120, the hardware timer 130, the resource separation mechanism 140, the controlled system bus 181, and the controlled external bus 183 are targets of control. On the other hand, the program 109 executed in the CPU core set 112, the non-controlled resource 190, the non-controlled system bus 182, and the non-controlled external bus 184 are not targets of control.

[0021] 2 is a block diagram showing a bus bandwidth throttling program according to the first embodiment. The bus bandwidth throttling program 105 starts operation when an interrupt from the hardware timer 130 is triggered. The hardware timer 130 performs an interrupt by transmitting an interrupt notification IN. The interrupt notification IN is received by an interrupt reception unit 1112 provided in the CPU core set 111. The CPU core set 111 that receives the interrupt notification IN refers to the vector table 121 and starts processing of the bus bandwidth throttling program 105. The processing executed by the bus bandwidth throttling program 105 includes a bus access frequency acquisition process 1051 that acquires a bus access frequency F to the buses to be controlled (the controlled system bus 181 and the controlled external bus 183), an occupation time setting process 1052 that sets an occupation time T that is a time for performing an occupation process based on the bus access frequency F, an occupation process 1053 that occupies the processing time of the CPU core set 111 only for the occupation time T, and a return process 1059.

[0022] The bus access frequency acquisition process 1051 is a process for, for example, reading the register content R stored in the register 1111 of the CPU core set 111, and acquiring the bus access frequency F to the bus to be controlled from the count number of instructions related to bus access, such as LD / ST instructions (load / store instructions) to the bus to be controlled from the previous interrupt to the current interrupt, from the register content R. The acquired bus access frequency F is also used in the next interrupt, and is therefore retained until the next interrupt.

[0023] The occupancy time setting process 1052 includes, for example, a process of setting the occupancy time T to be proportional to the bus access frequency F. It may also include a process of setting a specific occupancy time T depending on whether the bus access frequency F is less than a predetermined threshold or equal to or greater than a threshold. The occupancy time setting process 1052 may be a combination of the process of making the occupancy time T proportional to the bus access frequency F as described above, and a process of determining the occupancy time T based on a threshold.

[0024] The occupancy time setting process 1052 may also include a process for setting the next interrupt time TN and adjusting the frequency at which the interrupt and occupancy processes are performed. When the occupancy time setting process 1052 sets the next interrupt time TN, the next interrupt time TN is transmitted to the hardware timer 130 as shown in FIG.

[0025] After the occupation process 1053 ends, the bus bandwidth throttle program 105 executes a return process 1059 to return the processing of the CPU core set 111 to the state before the interruption.

[0026] Note that specific examples of the occupancy process 1053 include a process whose processing time can be set, such as a sleep process, or a combination of processes whose processing time can be measured in advance. The occupancy process 1053 is not particularly limited as long as it occupies the processing time of the CPU core set 111 to prevent the execution of processing of programs 101 other than the bus bandwidth suppression program 105. By preventing the execution of processing of programs 101 other than the bus bandwidth suppression program 105, the bus bandwidth of the bus to be controlled is prevented from being used by programs 101 other than the bus bandwidth suppression program 105. In other words, during the occupancy time T during which the occupancy process 1053 is executed, the use of the bus bandwidth of the bus to be controlled is suppressed.

[0027] In addition, the bus access frequency F may be obtained not from the number of LD / ST instructions counted as described above, but from the proportion of the number of LD / ST instructions (load / store instructions) counted among a certain number of instructions around the program counter address immediately before the interrupt, that is, the proportion of load instructions and store instructions among a certain number of instructions centered on the program counter address when the interrupt was performed.

[0028] Moreover, since it is sufficient for the occupation processing 1053 to be able to adjust how much it is executed in a certain period of time, it is acceptable to set either the occupation time T or the next interrupt time TN by the occupation time setting process 1052, or to perform both. That is, the time of the occupation processing 1053 in one interrupt may be adjusted by setting the occupation time T, or the frequency of the interrupt and the occupation processing 1053 may be adjusted by setting the next interrupt time TN while fixing the time of the occupation processing 1053 in one interrupt.

[0029] In order to prevent the influence of the occupancy process 1053 by the bus bandwidth throttling program 105 from affecting other components such as the CPU core set 112, the occupancy time T may be modified according to the overall system status, for example, the operating status of each component constituting the system (startup processing, normal operation, abnormal processing, termination processing, stopped, etc.). In addition, the occupancy process 1053 may be determined whether to execute it. For example, if a specific component is starting up or termination processing, the occupancy process 1053 may not be executed. As a method for determining the overall system status, for example, the operating status such as the CPU utilization rate of the program 101 operating in the CPU core set 111 and the utilization status of resources by the program 101 operating in the CPU core set 111 may be acquired. In addition, the occupancy time T or the next interrupt time TN may be randomized to make it difficult to predict the timing and time of executing the occupancy process 1053.

[0030] Next, the operation will be described. Fig. 3 is a flow diagram showing the operation of the bus bandwidth control device, that is, the bus bandwidth control method, in the first embodiment. First, before an interrupt by the hardware timer 130, the CPU core set 111 executes normal processing (step ST01).

[0031] When the CPU core set 111 is executing normal processing, at a predetermined timing (at the next interrupt time TN if the next interrupt time TN is set), the hardware timer 130 issues an interrupt to the CPU core set 111 (step ST02). This causes the bus bandwidth throttling program 105 to start operating. As described above, the resource separation mechanism 140 allows only the bus bandwidth throttling program 105 to access the vector table 121, the memory area 122, and the hardware timer 130, and other programs 101 of the CPU core set 111 (programs other than the bus bandwidth throttling program 105) cannot physically access them, and therefore cannot be involved in subsequent processing.

[0032] Next, the bus access frequency F is obtained by the bus bandwidth suppression program 105 (step ST03).

[0033] Next, the occupation time T is set. In the first embodiment, as shown in Fig. 3, the bus access frequency F obtained in the previous interrupt is compared with the bus access frequency F obtained this time (step ST04), and if the bus access frequency F has increased compared to the previous time, the occupation time T is set longer than the previous time (step ST05). Conversely, if the bus access frequency has decreased compared to the previous time, the occupation time T is set shorter than the previous time (step ST06). If the bus access frequency F is the same as the previous time, the occupation time T at the time of the previous interrupt is used, and therefore the processes of steps ST05 and ST06 described above are omitted.

[0034] In the process of step ST04, when the occupancy time T is set, the bus access frequency F obtained in the previous interrupt is used as a threshold value. However, the threshold value may be a value that has been set in advance.

[0035] After the occupancy time T is set, the bus bandwidth suppression program 105 executes an occupancy process for the occupancy time T (step ST07).

[0036] When the occupation process is completed, the bus bandwidth throttle program 105 executes a return process for returning the process of the CPU core set 111 to the state before the interrupt (step ST08).

[0037] There may be a plurality of CPU core sets that execute the bus bandwidth throttling program 105. In this case, the operation shown in Fig. 3 is performed for each CPU core set. The CPU core set that executes the bus bandwidth throttling program 105 is not particularly limited, but since the program that causes the takeover is the communication program 102, the bus bandwidth throttling program 105 is usually also executed in the CPU core set that executes the communication program 102.

[0038] According to the first embodiment, it is possible to prevent the availability of resources from being impaired. butMore specifically, in a system in which a CPU core set that executes a plurality of programs and a plurality of resources are connected via a bus, the bus bandwidth control device includes a resource isolation mechanism that is connected to the bus and determines the range of resources that each program can access, a hardware timer that interrupts the CPU core set at a predetermined timing, a shared memory that is one of the resources and has a storage area allocated to each of the plurality of programs by the resource isolation mechanism, and a bus bandwidth throttling program that is executed by the CPU core set and executes an exclusive process for the CPU core set when an interrupt occurs and returns the processing of the CPU core set to the state before the interrupt when the exclusive process ends, the storage area of ​​the shared memory includes a vector table that indicates the process to be executed when an interrupt occurs and a storage area used by the bus bandwidth throttling program, and the resource isolation mechanism permits only the bus bandwidth throttling program to access the hardware timer, the vector table, and the storage area used by the bus bandwidth throttling program. As a result, programs other than the bus bandwidth throttling program cannot access the storage area used by the hardware timer, the vector table, and the bus bandwidth throttling program, so that programs other than the bus bandwidth throttling program cannot be involved in the execution of the exclusive process by the bus bandwidth throttling program from the notification of the interrupt by the hardware timer. For this reason, even if a CPU core set is taken over and there is a risk that other programs will perform unintended processing, the bus bandwidth suppression program will reliably perform its exclusive processing and occupy the processing time of the CPU core set. As a result, the use of bus bandwidth by the taken over CPU core set is suppressed, and bus bandwidth is secured for other CPU core sets to use resources, preventing a loss of resource availability.

[0039] Embodiment 2 Next, the second embodiment will be described with reference to Figs. 4 to 6. The same or corresponding components as those shown in Figs. 1 to 3 are denoted by the same reference numerals, and the description thereof will be omitted. The second embodiment shows a case where a shared memory is accessed via another bus slave, for example, when there is a DMA (Direct Memory Access) controller. Fig. 4 is a schematic diagram showing a bus bandwidth control device in the second embodiment. The bus bandwidth control device 200 has a basically same configuration as the bus bandwidth control device 100 shown in the first embodiment, but the system includes a DMA controller 250, and the CPU core set 111 and the CPU core set 112 may issue commands to the shared memory 120 via the DMA controller 250. For this reason, as described later, the configuration of the bus bandwidth throttling program 205 is different from that of the bus bandwidth throttling program 105. The DMA controller 250 is connected to the resource separation mechanism 140 by a dynamically controlled external bus 285.

[0040] 5 is a block diagram showing a bus bandwidth throttling program according to the second embodiment. The bus bandwidth throttling program 205, like the bus bandwidth throttling program 105, is triggered by an interrupt notification IN from the hardware timer 130 to start operating. The interrupt notification IN is received by an interrupt reception unit 1112 provided in the CPU core set 111. The CPU core set 111 that has received the interrupt notification IN refers to the vector table 121 and executes the bus bandwidth throttling program 205. The processing executed by the bus bandwidth throttling program 205 includes a bus access frequency acquisition process 2051 that acquires a bus access frequency F and a bus access instruction frequency FT for a bus to be controlled, an occupation time setting process 1052 that sets an occupation time T that is a time for performing an occupation process based on the bus access frequency F, an occupation process 1053 that occupies the processing time of the CPU core set 111 only for the occupation time T, a return process 1059, and a DMA access permission determination process 2054 that permits or prohibits the DMA controller 250 from accessing the shared memory 120 based on the bus access instruction frequency FT.

[0041] The bus access frequency acquisition process 2051 is a process for acquiring a bus access frequency F for the bus to be controlled, as in the first embodiment, and acquiring a DMA transfer command for the DMA controller 250 by scanning a certain number of commands around the program counter address immediately before the interrupt. In the bus access frequency acquisition process 2051, a bus access command frequency FT for the bus to be controlled via the DMA controller 250 is acquired from the contents of the acquired transfer command. Note that, although the second embodiment describes the case of a DMA controller, the command to be acquired is a command to access the bus by operating another bus slave, such as a DMA transfer command. By acquiring the bus access frequency F and the bus access command frequency FT, not only the frequency of bus access by the CPU core set 111 but also the frequency of bus access via another bus slave (the DMA controller 250 in the second embodiment) can be grasped, and the bandwidth usage status of the bus to be controlled can be grasped more accurately.

[0042] The occupancy time setting process 1052 and the occupancy process 1053 are the same as those in the first embodiment.

[0043] The DMA access permission determination process 2054 is a process for determining whether or not the DMA controller 250 is allowed to access the shared memory 120 based on whether or not the bus access command frequency FT is equal to or greater than a predetermined threshold. If the bus access command frequency FT is equal to or greater than the threshold, the DMA controller 250 is blocked from accessing the shared memory 120. More specifically, the resource isolation mechanism 140 is sent setting information CF for prohibiting the DMA controller 250 from accessing the shared memory 120, and the setting information of the resource isolation mechanism 140 is updated. The resource isolation mechanism 140 blocks the dynamically controlled external bus 285 in order to prohibit access to the shared memory 120 by programs other than those having a preset key ID. If the bus access command frequency FT is less than the threshold, the resource isolation mechanism 140 is sent setting information CF for permitting the DMA controller 250 to access the shared memory 120. If the dynamically controlled external bus 285 is blocked, the resource isolation mechanism 140 releases the blocking.

[0044] The dynamic control target external bus 285 is cut off in order to ensure the effectiveness of the occupation process 1053 , and is performed in accordance with the occupation process 1053 .

[0045] Next, the operation will be described. Fig. 6 is a flow diagram showing the operation of the bus bandwidth control device in the second embodiment, that is, the bus bandwidth control method. First, the processes from step ST01 to step ST06 explained in the first embodiment (Fig. 3) are performed (step ST11). That is, the process from the interrupt by the hardware timer 130 to the setting of the occupancy time T is the same as in the first embodiment.

[0046] Next, the bus access command frequency FT is obtained by the bus bandwidth throttling program 205 (step ST12).

[0047] Next, it is determined whether the DMA controller 250 is allowed to access the shared memory 120. As described above, based on whether the bus access command frequency FT is equal to or greater than a predetermined threshold value, (Step ST13) , it judges whether the DMA controller 250 is allowed to access the shared memory 120. If the bus access command frequency FT is equal to or greater than a predetermined threshold, it updates the setting information of the resource isolation mechanism 140 to block the DMA controller 250 from accessing the shared memory 120. (Step ST14) If the bus access command frequency FT is less than a predetermined threshold, the DMA controller 250 is permitted to access the shared memory 120. (Step ST15) .

[0048] Next, the bus bandwidth throttling program 205 executes the occupancy process for the occupancy time T (step ST16), and when the occupancy process ends, it performs a return process to return the process of the CPU core set 111 to the state before the interrupt (step ST17). Also, if the access to the shared memory 120 by the DMA controller 250 is blocked, the blockage is released.

[0049] According to the second embodiment, the same effects as those of the first embodiment can be obtained. In addition, it is possible to more reliably secure bus bandwidth for other CPU core sets to use resources. More specifically, the system is configured to grasp the frequency of bus access commands to the DMA controller for the bus to be controlled, and determine whether access by the DMA controller is permitted (permitted or blocked) based on the frequency of bus access commands. This prevents not only direct pressure on bus bandwidth caused by the CPU core set, but also indirect pressure on bus bandwidth via the bus slave (DMA controller). This makes it possible to more reliably secure bus bandwidth.

[0050] Although the present application describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in this application, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. [Explanation of symbols]

[0051] 100, 200 bus bandwidth control device, 101, 109 program, 102 communication program, 105, 205 bus bandwidth suppression program, 111, 112 CPU core set, 120 shared memory, 121 vector table, 122 memory area, 130 hardware timer, 140 resource separation mechanism, 181 controlled system bus, 182 non-controlled system bus, 183 controlled external bus, 184 non-controlled external bus, 190 non-controlled resource, 250 DMA controller, 285 dynamically controlled external bus, 1111 register, 1112 interrupt acceptance unit, 1051, 2051 bus access frequency acquisition process, 1052 occupancy time setting process, 1053 occupancy process, 1059 return process, 2054 DMA access permission determination process, CF setting information, F bus access frequency, FT bus access command frequency, IN interrupt notification, R Register contents, T Occupancy time, TN Interrupt time

Claims

1. 1. A bus bandwidth control device for controlling a bandwidth of a bus used by a plurality of programs in a system in which a CPU core set for executing a plurality of programs and a plurality of resources are connected via a bus, comprising: a resource isolation mechanism connected to the bus and determining a range of the resources that each of the programs can access; a hardware timer that interrupts the CPU core set at a predetermined timing; a shared memory, which is one of the resources and has a storage area allocated to each of the plurality of programs by the resource isolation mechanism; a bus bandwidth throttling program which is executed by the CPU core set, and which, when the interrupt occurs, causes an exclusive process to be executed for the CPU core set, and which, when the exclusive process ends, returns the process of the CPU core set to a state before the interrupt; the storage area includes a vector table indicating a process to be executed when the interrupt occurs, and a storage area used by the bus bandwidth throttling program; A bus bandwidth control device, characterized in that the resource isolation mechanism permits access to the hardware timer, the vector table, and an area used by the bus bandwidth throttling program only to the bus bandwidth throttling program.

2. The bus bandwidth throttling program a bus access frequency acquisition process for acquiring a content of a register of the CPU core set and acquiring a bus access frequency to the bus from the content of the register; 2. The bus bandwidth control device according to claim 1, further comprising an occupancy time setting process for setting an occupancy time for said occupancy process based on said bus access frequency.

3. When there is a bus slave that accesses the resource by an instruction of the CPU core set, the bus bandwidth throttling program 3. A bus bandwidth control device as described in claim 2, which executes a process of acquiring a frequency of bus access commands to the bus slave, a process of determining whether the frequency of the bus access commands is equal to or greater than a predetermined threshold, and a process of causing the resource isolation mechanism to block access from the bus slave to the resource in accordance with the occupancy process if the frequency of the bus access commands is equal to or greater than the predetermined threshold.

4. 3. The bus bandwidth control device according to claim 2, wherein the bus access frequency acquisition process includes a process of acquiring the bus access frequency based on a load instruction and a store instruction included in the contents of the register.

5. 3. A bus bandwidth control device as described in claim 2, wherein the bus access frequency acquisition process includes a process of acquiring the bus access frequency based on the ratio of load instructions and store instructions among a certain number of instructions centered on the program counter address when the interrupt occurs.

6. A bus bandwidth control device as described in any one of claims 1 to 5, wherein the bus bandwidth suppression program adjusts the frequency of the interrupts during a certain period of time so as to modify the frequency of the occupancy processing during the certain period of time depending on the operating status of the program executed on the CPU core set or the utilization status of the resources by the program.

7. 6. The bus bandwidth control device according to claim 2, wherein the occupancy time setting process includes a process of setting the occupancy time in proportion to the bus access frequency.

8. 6. The bus bandwidth control device according to claim 2, wherein the occupancy time setting process includes a process of setting the occupancy time depending on whether the bus access frequency is equal to or greater than a predetermined threshold value.

9. A bus bandwidth control device as described in any one of claims 1 to 5. When there is another CPU core set in the system, the bandwidth of the bus is controlled by treating the program executed by the CPU core set as the control object, and the program executed by the other CPU core set is not controlled.

10. 1. A bus bandwidth control method for controlling a bandwidth of a bus used by a plurality of programs in a system in which a CPU core set for executing a plurality of programs and a plurality of resources are connected via a bus, comprising: A step of causing a hardware timer to interrupt the CPU core set at a predetermined timing; executing an occupation process for the CPU core set when the interrupt occurs; when the occupation process is completed, returning the process of the CPU core set to a state before the interrupt; a storage area of ​​a shared memory that is one of the resources includes a vector table that indicates a process to be executed when the interrupt occurs, and a storage area used by a bus bandwidth throttling program that executes the occupancy process; A bus bandwidth control method, characterized in that access to the hardware timer, the vector table, and the memory area used by the bus bandwidth suppression program is permitted only to the bus bandwidth suppression program.

11. acquiring a content of a register of the CPU core set when the interrupt occurs, and acquiring a bus access frequency to the bus from the content of the register; 11. The bus bandwidth control method according to claim 10, further comprising the step of: setting an occupation time for said occupancy process based on said bus access frequency.

12. When there is a bus slave that accesses the resource by an instruction of the CPU core set, obtaining a frequency of bus access commands to the bus slave when the interrupt occurs; determining whether a frequency of the bus access command is equal to or greater than a predetermined threshold; 12. The bus bandwidth control method according to claim 11, further comprising the step of blocking access from the bus slave to the resource in accordance with the occupancy process when a frequency of the bus access command is equal to or greater than the predetermined threshold value.

13. 12. The bus bandwidth control method according to claim 11, wherein in the step of acquiring the bus access frequency, the bus access frequency is acquired based on a load instruction and a store instruction included in the contents of the register.

14. 12. A bus bandwidth control method as described in claim 11, wherein in the step of acquiring the bus access frequency, the bus access frequency is acquired based on the ratio of load instructions and store instructions among a certain number of instructions centered on the program counter address at the time the interrupt was generated.

15. A bus bandwidth control method described in any one of claims 10 to 14, further comprising a step of adjusting the frequency of the interrupts during a certain period of time so as to modify the frequency of the occupancy processing during the certain period of time depending on the operating status of the program executed on the CPU core set or the utilization status of the resources by the program.

16. 15. The bus bandwidth control method according to claim 11, wherein in the step of setting the occupancy time, the occupancy time is set in proportion to the bus access frequency.

17. 15. The bus bandwidth control method according to claim 11, wherein in the step of setting the occupancy time, the occupancy time is set depending on whether the bus access frequency is equal to or higher than a predetermined threshold value.

18. A bus bandwidth control method according to any one of claims 10 to 14, wherein when there is another CPU core set in the system, the bandwidth of the bus is controlled with only the program executed by the CPU core set as the control object, and the program executed by the other CPU core set is not controlled.

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