Semiconductor Module

Abstract

To provide a semiconductor module having a module configuration preferable for reducing parasitic inductance components.SOLUTION: A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; a plurality of first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and a plurality of second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal opposite in polarity to the first input terminal; and an output terminal opposite from the first and second input terminals in the first direction and electrically connected to the second conductive portion. The semiconductor module further includes: a first conducting member connected to the plurality of first semiconductor elements and the second conductive portion; and a second conducting member connected to the plurality of second semiconductor elements and the second input terminal.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor module. [Background technology]

[0002] Conventionally, semiconductor modules equipped with power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are known. Such semiconductor modules are mounted in various electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 discloses a conventional semiconductor module (power module). The semiconductor module described in Patent Document 1 includes a semiconductor element and a support substrate (ceramic substrate). The semiconductor element is, for example, an IGBT made of Si (silicon). The support substrate supports the semiconductor element. The support substrate includes an insulating base material and conductor layers laminated on both sides of the base material. The base material is, for example, made of ceramic. Each conductor layer is, for example, made of Cu (copper), and a semiconductor element is bonded to one of the conductor layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-220382 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been a demand for electronic devices to be more energy efficient, perform better, and be more compact. To achieve this, it is necessary to improve the performance and reduce the size of the semiconductor modules mounted in the electronic devices.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor module having a module structure that is favorable for equalizing parasitic inductance components in paths of main circuit currents and for equalizing the amounts of currents to semiconductor elements. [Means for solving the problem]

[0006] The semiconductor module provided by the present disclosure includes a conductive substrate having a main surface and a back surface spaced apart from each other in a thickness direction, at least one semiconductor element electrically connected to the main surface and having a switching function, a conductive member forming a path of a main circuit current switched by the semiconductor element, a first input terminal and a second input terminal arranged on one side of the conductive substrate in a first direction perpendicular to the thickness direction, and at least one output terminal arranged on the other side of the conductive substrate in the first direction. The conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other in the first direction. The at least one semiconductor element includes a plurality of first semiconductor elements electrically connected to the first conductive portion and a plurality of second semiconductor elements electrically connected to the second conductive portion. The plurality of first semiconductor elements are spaced apart from each other along a second direction perpendicular to both the thickness direction and the first direction. The plurality of second semiconductor elements are spaced apart from each other along the second direction. The first input terminal is electrically connected to the first conductive portion. The second input terminal has a polarity opposite to that of the first input terminal. The output terminal is electrically connected to the second conductive portion. The conductive member includes a first conductive member connected to the plurality of first semiconductor elements and the second conductive portion, and a second conductive member connected to the plurality of second semiconductor elements and the second input terminal. Effect of the Invention

[0007] According to the above-mentioned configuration, it is possible to provide a module structure that is preferable for equalizing the parasitic inductance components in the paths of the main circuit currents and for equalizing the amounts of currents flowing to the semiconductor elements. [Brief description of the drawings]

[0008] [Figure 1] 1 is a perspective view of a semiconductor module according to a first embodiment. [Diagram 2] 2 is a perspective view of FIG. 1 in which the sealing resin, the resin portion, and the resin filling portion are omitted. [Diagram 3] 3 is a perspective view of FIG. 2 in which the conductive member is omitted. [Figure 4] FIG. 1 is a plan view showing a semiconductor module according to a first embodiment. [Diagram 5] 5 is a plan view of FIG. 4 in which the sealing resin, the resin portion, and the resin filling portion are indicated by imaginary lines. [Figure 6] FIG. 6 is a partially enlarged view of a portion of FIG. 5, in which imaginary lines for the sealing resin, the resin portion, and the resin filled portion are omitted. [Figure 7] FIG. 7 is a partially enlarged view of a part of FIG. 6. [Figure 8] 6 is a plan view of the conductive member shown in FIG. 5, with a portion of the conductive member indicated by an imaginary line. [Figure 9] FIG. 1 is a front view showing a semiconductor module according to a first embodiment. [Figure 10] FIG. 2 is a bottom view showing the semiconductor module according to the first embodiment. [Figure 11] FIG. 2 is a left side view showing the semiconductor module according to the first embodiment. [Figure 12] FIG. 2 is a right side view showing the semiconductor module according to the first embodiment. [Figure 13] FIG. 6 is a cross-sectional view taken along line XIII-XIII in FIG. 5. [Figure 14] FIG. 6 is a cross-sectional view taken along line XIV-XIV in FIG. 5. [Figure 15] FIG. 15 is a partially enlarged view of a part of FIG. [Figure 16] FIG. 6 is a cross-sectional view taken along line XVI-XVI in FIG. 5. [Figure 17] FIG. 6 is a cross-sectional view taken along line XVII-XVII in FIG. 5. [Figure 18] FIG. 6 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5. [Figure 19] FIG. 6 is a cross-sectional view taken along line XIX-XIX in FIG. 5. [Figure 20] 2 is an example of a circuit configuration of a semiconductor module according to a first embodiment. [Figure 21] 2 is a plan view showing a step of the method for manufacturing the semiconductor module according to the first embodiment. FIG. [Figure 22] 2 is a schematic cross-sectional view showing a step of a method for manufacturing the semiconductor module according to the first embodiment. FIG. [Diagram 23] 2 is a plan view showing a step of the method for manufacturing the semiconductor module according to the first embodiment. FIG. [Figure 24] 14 is a cross-sectional end view showing a step of the manufacturing method according to the first embodiment, corresponding to the cross section shown in FIG. 13. [Diagram 25] 14 is an enlarged cross-sectional view of a main part showing a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 13. [Figure 26] 15 is an enlarged cross-sectional view of a main part showing a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 14. [Figure 27] 15 is an enlarged cross-sectional view of a main part showing a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 14. [Figure 28] 14 is an enlarged cross-sectional view of a main part showing a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 13. [Figure 29] 15 is an enlarged cross-sectional view of a main part showing a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 14. [Diagram 30] 6 is a plan view similar to FIG. 5, showing a semiconductor module according to a second embodiment. [Diagram 31] FIG. 31 is a partially enlarged view of a portion of FIG. 30, in which imaginary lines for the sealing resin, the resin portion, and the resin filling portion are omitted. [Diagram 32] FIG. 32 is a partially enlarged view of a part of FIG. 31. [Diagram 33] 7 is a plan view similar to FIG. 5, showing a semiconductor module according to a third embodiment. [Diagram 34] FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV in FIG. 33. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor module according to a preferred embodiment of the present disclosure will be described below with reference to the drawings. In the following description, identical or similar components are designated by the same reference numerals and redundant description will be omitted.

[0010] 1 to 20 show a semiconductor module A1 according to a first embodiment. The semiconductor module A1 includes a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, a plurality of output terminals 44, a plurality of control terminals 45, a control terminal support body 5, a conductive member 6, a first conductive bonding material 71, a second conductive bonding material 72, a plurality of wires 731 to 735, a sealing resin 8, a resin portion 87, and a resin filling portion 88.

[0011] FIG. 1 is a perspective view showing a semiconductor module A1. FIG. 2 is a perspective view of FIG. 1 with the sealing resin 8, the resin portion 87, and the resin filling portion 88 omitted. FIG. 3 is a perspective view of FIG. 2 with the conductive member 6 omitted. FIG. 4 is a plan view showing a semiconductor module A1. FIG. 5 is a plan view of FIG. 4 with the sealing resin 8, the resin portion 87, and the resin filling portion 88 indicated by imaginary lines. FIG. 6 is a partial enlarged view of FIG. 5. In FIG. 6, the sealing resin 8, the resin portion 87, and the resin filling portion 88 are omitted by imaginary lines. FIG. 7 is a partial enlarged view of FIG. 6. FIG. 8 is a plan view of FIG. 5 with the part of the conductive member 6 (a second conductive member 62 described later) indicated by imaginary lines. FIG. 9 is a front view of the semiconductor module A1. FIG. 10 is a bottom view of the semiconductor module A1. FIG. 11 is a left side view of the semiconductor module A1. FIG. 12 is a right side view of the semiconductor module A1. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 5. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 5. FIG. 15 is a partially enlarged view of FIG. 14. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 5. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 5. Note that a plurality of wires 731 to 735 are omitted in FIGS. 2, 3, 7, 14, and 18. FIG. 20 is a circuit configuration example of the semiconductor module A1. In the circuit diagram of FIG. 20, only one each of a plurality of first semiconductor elements 10A (described later) and a plurality of second semiconductor elements 10B (described later) is shown, and the other first semiconductor elements 10A and the other second semiconductor elements 10B are omitted.

[0012] For ease of explanation, three mutually perpendicular directions, namely, the x direction, the y direction, and the z direction, will be referred to. The z direction is the thickness direction of the semiconductor module A1. The x direction is the left-right direction in the plan view of the semiconductor module A1 (see FIG. 4). The y direction is the up-down direction in the plan view of the semiconductor module A1 (see FIG. 4). One of the x directions is the x1 direction, and the other x direction is the x2 direction. This also applies to the y direction and the z direction. In the following explanation, "when viewed in the z direction" is also referred to as "planar view." The x direction is an example of a "first direction," and the y direction is an example of a "second direction."

[0013] Each of the semiconductor elements 10 is a functional core of the semiconductor module A1. The constituent material of each semiconductor element 10 is a semiconductor material mainly made of, for example, SiC (silicon carbide). This semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride). Each semiconductor element 10 has a switching function unit Q1 (see FIG. 20) constituted of, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The switching function unit Q1 is not limited to a MOSFET, and may be other transistors such as a field effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a bipolar transistor such as an IGBT. Each semiconductor element 10 is the same element. Each semiconductor element 10 is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0014] 15, each semiconductor element 10 has an element main surface 101 and an element back surface 102. In each semiconductor element 10, the element main surface 101 and the element back surface 102 are spaced apart in the z direction. The element main surface 101 faces the z2 direction, and the element back surface 102 faces the z1 direction.

[0015] The multiple semiconductor elements 10 include multiple first semiconductor elements 10A and multiple second semiconductor elements 10B. In this embodiment, the semiconductor module A1 includes three first semiconductor elements 10A and three second semiconductor elements 10B, but the number of the first semiconductor elements 10A and the number of the second semiconductor elements 10B are not limited to this configuration and are appropriately changed according to the performance required of the semiconductor module A1. In the example of FIG. 8, three first semiconductor elements 10A and three second semiconductor elements 10B are arranged. The number of the first semiconductor elements 10A and the second semiconductor elements 10B may be one or two, or four or more. The number of the first semiconductor elements 10A and the number of the second semiconductor elements 10B may be equal to or different from each other. The number of the first semiconductor elements 10A and the second semiconductor elements 10B is determined by the current capacity handled by the semiconductor module A1.

[0016] As shown in Fig. 20, the semiconductor module A1 is configured as, for example, a half-bridge type switching circuit. In this case, the multiple first semiconductor elements 10A configure an upper arm circuit of the semiconductor module A1, and the multiple second semiconductor elements 10B configure a lower arm circuit. In the upper arm circuit, the multiple first semiconductor elements 10A are connected in parallel to each other, and in the lower arm circuit, the multiple second semiconductor elements 10B are connected in parallel to each other. Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B are connected in series to configure a bridge layer.

[0017] Each of the multiple first semiconductor elements 10A is mounted on a conductive substrate 2, as shown in Fig. 8, Fig. 16, etc. In the example shown in Fig. 8, the multiple first semiconductor elements 10A are lined up, for example, in the y direction and spaced apart from one another. Each of the first semiconductor elements 10A is conductively bonded to the conductive substrate 2 (a first conductive portion 2A described below) via a second conductive bonding material 72. When each of the first semiconductor elements 10A is bonded to the first conductive portion 2A, the element back surface 102 faces the first conductive portion 2A.

[0018] Each of the second semiconductor elements 10B is mounted on the conductive substrate 2 as shown in FIG. 8, FIG. 17, etc. In the example shown in FIG. 8, the second semiconductor elements 10B are arranged, for example, in the y direction and spaced apart from each other. Each of the second semiconductor elements 10B is conductively bonded to the conductive substrate 2 (a second conductive portion 2B described later) via a second conductive bonding material 72. When each of the second semiconductor elements 10B is bonded to the second conductive portion 2B, the element back surface 102 faces the second conductive portion 2B. As can be seen from FIG. 8, the first semiconductor elements 10A and the second semiconductor elements 10B overlap each other when viewed in the x direction, but the present disclosure is not limited to this.

[0019] Each of the multiple semiconductor elements 10 (multiple first semiconductor elements 10A and multiple second semiconductor elements 10B) has a first principal surface electrode 11, a second principal surface electrode 12, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, and the back surface electrode 15 described below are common to each semiconductor element 10. The first principal surface electrode 11 and the second principal surface electrode 12 are provided on the element principal surface 101. The first principal surface electrode 11 and the second principal surface electrode 12 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0020] The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the semiconductor element 10 is input. In each semiconductor element 10, the second principal surface electrode 12 is, for example, a source electrode through which a source current flows. The back surface electrode 15 is, for example, a drain electrode through which a drain current flows. The back surface electrode 15 covers substantially the entire area of ​​the element back surface 102. The back surface electrode 15 is, for example, formed by Ag plating.

[0021] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode) by the switching function unit Q1, each semiconductor element 10 switches between a conductive state and a cut-off state in response to the drive signal. The operation of switching between the conductive state and the cut-off state is called a switching operation. In the conductive state, a current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the cut-off state, the current does not flow. That is, each semiconductor element 10 performs a switching operation by the switching function unit Q1. The semiconductor module A1 converts a first power supply voltage (DC voltage) input between one input terminal 41 and two input terminals 42, 43, for example, into a second power supply voltage (AC voltage) by the switching function units Q1 of the multiple semiconductor elements 10, and outputs the second power supply voltage from the output terminal 44. The input terminals 41 to 43 and the output terminal 44 are all power supply terminals that handle power supply voltages. The input terminals 41 to 43 are first power supply terminals to which a first power supply voltage is input, and the output terminal 44 is a second power supply terminal that outputs a second power supply voltage.

[0022] Some of the semiconductor elements 10 (two in the example shown in FIG. 8) further have a diode function unit D1 (see FIG. 20) in addition to the switching function unit Q1. In the semiconductor module A1, one of the first semiconductor elements 10A (the first semiconductor element 10A arranged closest to the y2 direction in FIG. 8) and one of the second semiconductor elements 10B (the second semiconductor element 10B arranged closest to the y1 direction in FIG. 8) include the diode function unit D1 in addition to the switching function unit Q1. The function and role of the diode function unit D1 are not particularly limited, but may be, for example, a temperature detection diode. The diode D2 shown in FIG. 20 is, for example, a parasitic diode component of the switching function unit Q1.

[0023] 8, the semiconductor element 10 having the diode functional unit D1 further has a third principal surface electrode 13, a fourth principal surface electrode 14, and a fifth principal surface electrode 16 in addition to the first principal surface electrode 11, the second principal surface electrode 12, and the back surface electrode 15. The configurations of the third principal surface electrode 13, the fourth principal surface electrode 14, and the fifth principal surface electrode 16 described below are common to each semiconductor element 10 having the diode functional unit D1. The third principal surface electrode 13, the fourth principal surface electrode 14, and the fifth principal surface electrode 16 are formed on the element principal surface 101. In the semiconductor element 10 having the diode functional unit D1, the third principal surface electrode 13 and the fourth principal surface electrode 14 are electrically connected to the diode functional unit D1. The fifth principal surface electrode 16 is, for example, a source sense electrode through which a source current in the switching functional unit Q1 flows.

[0024] As shown in FIG. 7, each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in a plan view. FIG. 7 shows the first semiconductor element 10A arranged in the center in the y direction among the multiple first semiconductor elements 10A arranged in the y direction, but the other first semiconductor elements 10A also have the first side 191, the second side 192, the third side 193, and the fourth side 194. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is an edge on the x2 direction side in a plan view, and the second side 192 is an edge on the x1 direction side in a plan view. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is an edge on the y2 direction side in a plan view, and the fourth side 194 is an edge on the y1 direction side in a plan view. Since each first semiconductor element 10A has a rectangular shape in a plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 form approximately right angles in a plan view. The four corners do not overlap with the conductive member 6 (first conductive member 61 and second conductive member 62 described below) in a plan view, as shown in Fig. 7. The lengths of the third side 193 and the fourth side 194 are greater than the lengths of the first side 191 and the second side 192.

[0025] The conductive substrate 2 is also called a lead frame. The conductive substrate 2 supports a plurality of semiconductor elements 10. The conductive substrate 2 is joined onto a support substrate 3 via a first conductive bonding material 71. The conductive substrate 2 has, for example, a rectangular shape in a plan view. The conductive substrate 2, together with the conductive member 6, constitutes a path of a main circuit current that is switched by the plurality of semiconductor elements 10.

[0026] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each a plate-shaped member made of metal. The metal is, for example, Cu (copper) or a Cu alloy. The first conductive portion 2A and the second conductive portion 2B, together with the input terminals 41 to 43 and the output terminals 44, form a conductive path to the semiconductor elements 10. As shown in Figs. 13 to 18, the first conductive portion 2A and the second conductive portion 2B are each bonded onto the support substrate 3 via a first conductive bonding material 71. A plurality of first semiconductor elements 10A are each bonded to the first conductive portion 2A via a second conductive bonding material 72. A plurality of second semiconductor elements 10B are each bonded to the second conductive portion 2B via a second conductive bonding material 72. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction as shown in Figs. 3, 8, 13, and 14. In the examples shown in these figures, the first conductive portion 2A is located further in the x2 direction than the second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each, for example, rectangular in a plan view. The first conductive portion 2A and the second conductive portion 2B overlap when viewed in the x direction. The first conductive portion 2A and the second conductive portion 2B each have, for example, a dimension in the x direction of 15 mm to 25 mm (preferably about 20 mm), a dimension in the y direction of 30 mm to 40 mm (preferably about 35 mm), and a dimension in the z direction of 1.5 mm to 3.0 mm (preferably about 2.0 mm).

[0027] The conductive substrate 2 has a main surface 201 and a back surface 202. The main surface 201 and the back surface 202 are spaced apart in the z direction as shown in FIG. 13, FIG. 14, and FIG. 16 to FIG. 18. The main surface 201 faces the z2 direction, and the back surface 202 faces the z1 direction. The main surface 201 is a combination of the upper surface of the first conductive portion 2A and the upper surface of the second conductive portion 2B. The back surface 202 is a combination of the lower surface of the first conductive portion 2A and the lower surface of the second conductive portion 2B. The back surface 202 is joined to the support substrate 3 so as to face the support substrate 3. As shown in FIG. 5, FIG. 8, and FIG. 13, a plurality of recesses 201a are formed in the main surface 201. Each recess 201a is a portion recessed in the z direction from the main surface 201. The recess degree (depth) of each recess 201a is, for example, more than 0 μm and 100 μm or less. Each recess 201a is formed, for example, during molding, which will be described later. The multiple recesses 201a include those formed on the main surface 201 of the first conductive portion 2A and those formed on the main surface 201 of the second conductive portion 2B. The two recesses 201a formed on the main surface 201 of the first conductive portion 2A are spaced apart in the y direction and overlap when viewed in the y direction. The two recesses 201a formed on the main surface 201 of the second conductive portion 2B are spaced apart in the y direction and overlap when viewed in the y direction.

[0028] The conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B) includes a base material 21, a main surface bonding layer 22, and a back surface bonding layer 23, which are stacked on top of each other. The base material 21 is a plate-shaped member made of metal. This metal is Cu or a Cu alloy. The main surface bonding layer 22 is formed on the upper surface of the base material 21. The main surface bonding layer 22 is a surface layer on the z2 direction side of the conductive substrate 2. The upper surface of the main surface bonding layer 22 corresponds to the main surface 201 of the conductive substrate 2. The main surface bonding layer 22 is, for example, Ag plating. The back surface bonding layer 23 is formed on the lower surface of the base material 21. The back surface bonding layer 23 is a surface layer on the z1 direction side of the conductive substrate 2. The lower surface of the back surface bonding layer 23 corresponds to the back surface 202 of the conductive substrate 2. The back surface bonding layer 23 is, for example, Ag plating, similar to the main surface bonding layer 22.

[0029] The supporting substrate 3 supports the conductive substrate 2. The supporting substrate 3 is, for example, a DBC (Direct Bonded Copper) substrate. The supporting substrate 3 includes an insulating layer 31, a first metal layer 32, a first bonding layer 321, and a second metal layer 33.

[0030] The insulating layer 31 is, for example, a ceramic having excellent thermal conductivity. An example of such a ceramic is AlN (aluminum nitride). The insulating layer 31 is not limited to ceramics, and may be an insulating resin sheet or the like. The insulating layer 31 has, for example, a rectangular shape in a plan view.

[0031] The first metal layer 32 is formed on the upper surface (surface facing the z2 direction) of the insulating layer 31. The constituent material of the first metal layer 32 includes, for example, Cu. The constituent material may include Al instead of Cu. The first metal layer 32 includes a first portion 32A and a second portion 32B. The first portion 32A and the second portion 32B are spaced apart in the x direction. The first portion 32A is located on the x2 direction side of the second portion 32B. The first conductive portion 2A is joined to the first portion 32A and supports the first conductive portion 2A. The second portion 32B is joined to the second conductive portion 2B and supports the second conductive portion 2B. The first portion 32A and the second portion 32B are each, for example, rectangular in a plan view.

[0032] The first bonding layer 321 is formed on the upper surface of the first metal layer 32 (each of the first portion 32A and the second portion 32B). The first bonding layer 321 is, for example, Ag plating. The first bonding layer 321 is provided to improve bonding with the first conductive bonding material 71 by solid-phase diffusion.

[0033] The second metal layer 33 is formed on the lower surface (surface facing the z1 direction) of the insulating layer 31. The constituent material of the second metal layer 33 is the same as the constituent material of the first metal layer 32. In the example shown in FIG. 10, the lower surface of the second metal layer 33 (bottom surface 302 described below) is exposed from the sealing resin 8, for example. The lower surface may be covered by the sealing resin 8 without being exposed from the sealing resin 8. The second metal layer 33 overlaps both the first portion 32A and the second portion 32B in a plan view.

[0034] As shown in FIGS. 13 to 18, the support substrate 3 has a support surface 301 and a bottom surface 302. The support surface 301 and the bottom surface 302 are spaced apart in the z direction. The support surface 301 faces the z2 direction, and the bottom surface 302 faces the z1 direction. The bottom surface 302 is exposed from the sealing resin 8 as shown in FIG. 10. The support surface 301 is the upper surface of the first bonding layer 321, and is a combination of the upper surface of the first portion 32A and the upper surface of the second portion 32B. The support surface 301 faces the conductive substrate 2, and the conductive substrate 2 is bonded to the support surface 301. The bottom surface 302 is the lower surface of the second metal layer 33. A heat dissipation member (for example, a heat sink) (not shown) can be attached to the bottom surface 302. The dimension of the support substrate 3 in the z direction (the distance along the z direction from the support surface 301 to the bottom surface 302) is, for example, 0.7 mm to 2.0 mm.

[0035] The input terminals 41-43 and the output terminals 44 are each made of a plate-shaped metal plate. The metal plate is made of, for example, Cu or a Cu alloy. In the example shown in FIGS. 1-5, 8 and 10, the semiconductor module A1 has three input terminals 41-43 and two output terminals 44.

[0036] A power supply voltage is applied between the three input terminals 41 to 43. In this embodiment, the input terminal 41 is a positive electrode (P terminal), and the two input terminals 42 and 43 are each a negative electrode (N terminal). Alternatively, the input terminal 41 may be a negative electrode (N terminal), and the two input terminals 42 and 43 may each be a positive electrode (P terminal). In this case, the wiring inside the package may be appropriately changed in accordance with the change in the polarity of the terminals. Each of the three input terminals 41 to 43 and the two output terminals 44 includes a portion covered with the sealing resin 8 and a portion exposed from the resin side surface of the sealing resin 8.

[0037] As shown in FIG. 14, the input terminal 41 is integrally formed with the first conductive portion 2A. Unlike this configuration, the input terminal 41 may be separated from the first conductive portion 2A and conductively joined to the first conductive portion 2A. As shown in FIG. 8 and other figures, the input terminal 41 is located on the x2 direction side with respect to the multiple first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2). The input terminal 41 is conductive to the first conductive portion 2A and is conductive to the back electrode 15 (drain electrode) of each first semiconductor element 10A via the first conductive portion 2A. The input terminal 41 is an example of a "first input terminal."

[0038] The input terminal 41 has an input side joint surface 411 and an input side surface 412. The input side joint surface 411 faces the z2 direction and extends in the x2 direction. The input side surface 412 is located on the periphery of the input side joint surface 411 when viewed in the z direction, and faces a direction intersecting the input side joint surface 411. In this embodiment, the input side surface 412 includes a tip surface 413 and a pair of side surfaces 414. The tip surface 413 is located at the x2 direction end of the input terminal 41 and faces the x2 direction. The pair of side surfaces 414 are located at both ends of the input terminal 41 in the y direction and face the y1 direction and the y2 direction. At least one of the tip surface 413 and the pair of side surfaces 414 of the input side side surface 412 has an input side processing mark. The input side processing mark is formed by cutting the lead frame, which will be described later.

[0039] As shown in FIG. 8, the two input terminals 42, 43 are each spaced apart from the first conductive portion 2A. A second conductive member 62 is joined to each of the two input terminals 42, 43. As shown in FIG. 8 and other figures, each of the two input terminals 42, 43 is located on the x2 direction side with respect to the multiple first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2). Each of the two input terminals 42, 43 is electrically connected to the second conductive member 62 and is electrically connected to the second principal surface electrode 12 (source electrode) of each second semiconductor element 10B via the second conductive member 62. The input terminal 42 is an example of a "second input terminal," and the input terminal 43 is an example of a "third input terminal."

[0040] The input terminals 42 and 43 have input side bonding surfaces 421 and 431 and input side surfaces 422 and 432. The input side bonding surfaces 421 and 431 face the z2 direction and extend in the x2 direction. The input side surfaces 422 and 432 are located on the periphery of the input side bonding surfaces 421 and 431 when viewed in the z direction, and face a direction intersecting the input side bonding surfaces 421 and 431. In this embodiment, the input side surface 422 includes a tip surface 423 and a pair of side surfaces 424. The tip surface 423 is located at the x2 direction end of the input terminal 42 and faces the x2 direction. The pair of side surfaces 424 are located at both ends of the input terminal 42 in the y direction and face the y1 direction and the y2 direction. In the input side side surface 422, at least one of the tip surface 423 and the pair of side surfaces 424 has an input side processing mark. The input side processing mark is formed by cutting the lead frame, which will be described later. The input side surface 432 includes a tip surface 433 and a pair of side surfaces 434. The tip surface 433 is located at the x2-direction side end of the input terminal 43 and faces the x2 direction. The pair of side surfaces 434 are located at both ends of the input terminal 43 in the y direction and face the y1 and y2 directions. In the input side side surface 432, at least one of the tip surface 433 and the pair of side surfaces 434 has an input-side processing mark. The input-side processing mark is formed by cutting the lead frame, which will be described later.

[0041] As shown in FIGS. 1 to 5, 8, and 10, the three input terminals 41 to 43 each protrude in the x2 direction from the sealing resin 8 in the semiconductor module A1. The three input terminals 41 to 43 are spaced apart from one another. The two input terminals 42, 43 are positioned on opposite sides of the input terminal 41 in the y direction. The input terminal 42 is positioned on the y2-direction side of the input terminal 41, and the input terminal 43 is positioned on the y1-direction side of the input terminal 41. The three input terminals 41 to 43 overlap one another when viewed in the y direction.

[0042] As can be seen from FIG. 8 and FIG. 14, the two output terminals 44 are each integrally formed with the second conductive portion 2B. Unlike this configuration, the output terminal 44 may be separated from the second conductive portion 2B and conductively joined to the second conductive portion 2B. As shown in FIG. 8 and other figures, the two output terminals 44 are each located on the x1 direction side with respect to the multiple second semiconductor elements 10B and the second conductive portion 2B (conductive substrate 2). Each output terminal 44 is conductive to the second conductive portion 2B and is also conductive to the back electrode 15 (drain electrode) of each second semiconductor element 10B via the second conductive portion 2B. The two output terminals 44 are examples of the "first output terminal" and the "second output terminal", respectively.

[0043] The output terminal 44 has an output-side joint surface 441 and an output-side side surface 442. The output-side joint surface 441 faces the z2 direction and extends in the x1 direction. The output-side side surface 442 is located on the periphery of the output-side joint surface 441 when viewed in the z direction, and faces a direction intersecting the output-side joint surface 441. In this embodiment, the output-side side surface 442 includes a tip surface 443 and a pair of side surfaces 444. The tip surface 443 is located at the end of the x1 direction of the output terminal 44 and faces the x1 direction. The pair of side surfaces 444 are located at both ends of the output terminal 44 in the y direction and face the y1 direction and the y2 direction. In the output-side side surface 442, at least one of the tip surface 443 and the pair of side surfaces 444 has an output-side processing mark. The output-side processing mark is formed by cutting the lead frame, which will be described later. The number of output terminals 44 is not limited to two, and may be, for example, one, or three or more. For example, when there is one output terminal 44, it is desirable that it be connected to the center part in the y direction of second conductive part 2B.

[0044] Each of the control terminals 45 is a pin-shaped terminal for controlling each of the semiconductor elements 10. The control terminals 45 include a plurality of first control terminals 46A-46E and a plurality of second control terminals 47A-47D. The first control terminals 46A-46E are used to control each of the first semiconductor elements 10A. The second control terminals 47A-47D are used to control each of the second semiconductor elements 10B.

[0045] The multiple first control terminals 46A-46E are arranged at intervals in the y direction. As shown in Figures 8 and 14, each of the first control terminals 46A-46E is supported by the first conductive portion 2A via a control terminal support body 5 (a first support portion 5A described below). As shown in Figures 5 and 8, each of the first control terminals 46A-46E is located between the multiple first semiconductor elements 10A and the three input terminals 41-43 in the x direction.

[0046] The first control terminal 46A is a terminal (gate terminal) for inputting a drive signal for the multiple first semiconductor elements 10A. A drive signal for driving the multiple first semiconductor elements 10A is input to the first control terminal 46A (for example, a gate voltage is applied).

[0047] The first control terminal 46B is a terminal (source sense terminal) for detecting source signals of the multiple first semiconductor elements 10A. The first control terminal 46B detects a voltage (a voltage corresponding to a source current) applied to each of the second principal surface electrodes 12 (source electrodes) of the multiple first semiconductor elements 10A.

[0048] The first control terminal 46C and the first control terminal 46D are terminals that are electrically connected to the diode functional unit D1. The first control terminal 46C is electrically connected to the third principal surface electrode 13 of the first semiconductor element 10A having the diode functional unit D1, and the first control terminal 46D is electrically connected to the fourth principal surface electrode 14 of the first semiconductor element 10A having the diode functional unit D1.

[0049] The first control terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the multiple first semiconductor elements 10A. The first control terminal 46E detects a voltage (a voltage corresponding to a drain current) applied to each back electrode 15 (drain electrode) of the multiple first semiconductor elements 10A.

[0050] The second control terminals 47A-47D are arranged at intervals in the y direction. As shown in Figures 5 and 18, each of the second control terminals 47A-47D is supported by the second conductive portion 2B via a control terminal support body 5 (a second support portion 5B described below). As shown in Figures 5 and 8, each of the second control terminals 47A-47D is located between the second semiconductor elements 10B and two output terminals 44 in the x direction.

[0051] Each of the plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D) includes a holder 451 and a metal pin 452.

[0052] The holder 451 is made of a conductive material. As shown in FIG. 15, the holder 451 is joined to the control terminal support 5 (first metal layer 52 described later) via a conductive bonding material 459. The holder 451 includes a cylindrical portion, an upper end flange, and a lower end flange. The upper end flange is connected to the upper part of the cylindrical portion, and the lower end flange is connected to the lower part of the cylindrical portion. A metal pin 452 is inserted through at least the upper end flange and the cylindrical portion of the holder 451. The upper surface of the upper end flange is exposed from the sealing resin 8 (second protruding portion 852 described later) and is covered with a resin portion 87.

[0053] The metal pin 452 is a rod-shaped member extending in the z direction. The metal pin 452 is supported by being press-fitted into the holder 451. The metal pin 452 is electrically connected to the control terminal support body 5 (a first metal layer 52 described later) at least via the holder 451. As in the example shown in FIG. 15, when the lower end (the end on the z1 direction side) of the metal pin 452 is in contact with the conductive bonding material 459 in the insertion hole of the holder 451, the metal pin 452 is electrically connected to the control terminal support body 5 via the conductive bonding material 459.

[0054] The control terminal support body 5 supports a plurality of control terminals 45. The control terminal support body 5 is interposed between the main surface 201 (conductive substrate 2) and the plurality of control terminals 45.

[0055] The control terminal support 5 includes a first support portion 5A and a second support portion 5B. The first support portion 5A is disposed on the first conductive portion 2A of the conductive substrate 2, and supports the first control terminals 46A to 46E of the control terminals 45. The first support portion 5A is bonded to the first conductive portion 2A via a bonding material 59, as shown in FIG. 15. The bonding material 59 may be conductive or insulating, and may be, for example, solder. The second support portion 5B is disposed on the second conductive portion 2B of the conductive substrate 2, and supports the second control terminals 47A to 47D of the control terminals 45. The second support portion 5B is bonded to the second conductive portion 2B via the bonding material 59.

[0056] The control terminal support 5 (each of the first support portion 5A and the second support portion 5B) is made of, for example, a DBC substrate. The control terminal support 5 has an insulating layer 51, a first metal layer 52, and a second metal layer 53 stacked on top of each other.

[0057] The insulating layer 51 is made of, for example, ceramics and has, for example, a rectangular shape in plan view.

[0058] As shown in FIG. 15 and other figures, the first metal layer 52 is formed on the upper surface of the insulating layer 51. Each control terminal 45 is provided upright on the first metal layer 52. The first metal layer 52 is, for example, Cu or a Cu alloy. As shown in FIG. 8 and other figures, the first metal layer 52 includes a first portion 521, a second portion 522, a third portion 523, a fourth portion 524, and a fifth portion 525. The first portion 521, the second portion 522, the third portion 523, the fourth portion 524, and the fifth portion 525 are spaced apart from each other and insulated from each other.

[0059] A plurality of wires 731 are joined to the first portion 521, and the first portion 521 is electrically connected to the first principal surface electrode 11 (gate electrode) of each semiconductor element 10 via each wire 731. As shown in Fig. 8, a first control terminal 46A is joined to the first portion 521 of the first support portion 5A, and a second control terminal 47A is joined to the first portion 521 of the second support portion 5B.

[0060] A plurality of wires 732 are joined to the second portion 522, and the second portion 522 is electrically connected to the second principal surface electrode 12 (source electrode) of each semiconductor element 10 via each wire 732. As shown in Fig. 8, a first control terminal 46B is joined to the second portion 522 of the first support portion 5A, and a second control terminal 47B is joined to the second portion 522 of the second support portion 5B.

[0061] A wire 733 is joined to the third portion 523, and the third portion 523 is electrically connected to the third principal surface electrode 13 of the semiconductor element 10 having the diode functional portion D1 via the wire 733. As shown in Fig. 8, a first control terminal 46C is joined to the third portion 523 of the first support portion 5A, and a second control terminal 47C is joined to the third portion 523 of the second support portion 5B.

[0062] A wire 734 is joined to the fourth portion 524, and is electrically connected to the fourth principal surface electrode 14 of the semiconductor element 10 having the diode functional portion D1 via the wire 734. As shown in Fig. 8, a first control terminal 46D is joined to the fourth portion 524 of the first support portion 5A, and a second control terminal 47D is joined to the fourth portion 524 of the second support portion 5B.

[0063] A wire 735 is joined to the fifth portion 525 of the first support portion 5A, and the fifth portion 525 is electrically connected to the first conductive portion 2A via the wire 735. The fifth portion 525 of the second support portion 5B is not electrically connected to other components. As shown in Fig. 8, a first control terminal 46E is joined to the fifth portion 525 of the first support portion 5A.

[0064] 15 and the like, the second metal layer 53 is formed on the lower surface of the insulating layer 51. The second metal layer 53 of the first support portion 5A is joined to the first conductive portion 2A via a bonding material 59 as shown in Fig. 15. The second metal layer 53 of the second support portion 5B is joined to the second conductive portion 2B via a bonding material 59.

[0065] The conductive member 6, together with the conductive substrate 2, constitutes a path of the main circuit current switched by the plurality of semiconductor elements 10. The conductive member 6 is spaced from the main surface 201 (conductive substrate 2) in the z2 direction and overlaps the main surface 201 in a plan view. In this embodiment, the conductive member 6 is made of a metal plate material. The metal is, for example, Cu or a Cu alloy. Specifically, the conductive member 6 is a folded metal plate material. Not limited to this, the conductive member 6 may be made of a metal foil material. In this embodiment, the conductive member 6 includes a plurality of first conductive members 61 and second conductive members 62. The main circuit current includes a first main circuit current and a second main circuit current. The first main circuit current is a current that flows through a path between the input terminal 41 and the output terminal 44. The second main circuit current is a current that flows through a path between the output terminal 44 and the input terminals 42 and 43.

[0066] Each of the first conductive members 61 is bonded to the second principal surface electrode 12 (source electrode) and the second conductive portion 2B of each first semiconductor element 10A, and electrically connects the second principal surface electrode 12 and the second conductive portion 2B of each first semiconductor element 10A. Each of the first conductive members 61 and the second principal surface electrode 12 (see FIG. 8) of each first semiconductor element 10A, and each of the first conductive members 61 and the second conductive portion 2B are bonded via a conductive bonding material 69. The conductive bonding material 69 is, for example, solder, a metal paste material, or a sintered metal. Each of the first conductive members 61 is strip-shaped extending along the x-direction in a plan view, as shown in FIG. 8.

[0067] In this embodiment, as shown in FIG. 6 and the like, an opening 61h is formed in a rectangular portion of each first conductive member 61 connecting each first semiconductor element 10A and the second conductive portion 2B. The opening 61h is preferably formed in the center of the rectangle in a plan view, and is, for example, a through hole penetrating in the z direction. The opening 61h is formed to facilitate the flow of the resin material between the upper side (z2 direction side) and the lower side (z1 direction side) in the vicinity of each first conductive member 61 when injecting a fluid resin material to form a sealing resin. The planar shape of the opening 61h may be a perfect circle, or may be another shape such as an ellipse or a rectangle. The shape of the first conductive member 61 is not limited to this configuration, and for example, the opening 61h may not be formed.

[0068] In this embodiment, three first conductive members 61 are provided corresponding to the number of first semiconductor elements 10A. As a modified example, one first conductive member 61 common to the multiple first semiconductor elements 10A may be used regardless of the number of the multiple first semiconductor elements 10A.

[0069] The second conductive member 62 electrically connects the second main surface electrodes 12 of each second semiconductor element 10B to each input terminal 42, 43. The second conductive member 62 has a maximum dimension in the x direction of, for example, 25 mm to 40 mm (preferably about 32 mm) and a maximum dimension in the y direction of, for example, 30 mm to 45 mm (preferably about 38 mm). As shown in FIG. 6, the second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624.

[0070] The first wiring portion 621 is connected to the input terminal 42. The first wiring portion 621 and the input terminal 42 are joined by a conductive bonding material 69. The first wiring portion 621 is a strip-shaped portion extending in the x-direction in a plan view.

[0071] The second wiring portion 622 is connected to the input terminal 43. The second wiring portion 622 and the input terminal 43 are joined by a conductive bonding material 69. The second wiring portion 622 is a strip-shaped portion extending in the x direction in a plan view. The first wiring portion 621 and the second wiring portion 622 are spaced apart in the y direction and arranged substantially parallel to each other. The second wiring portion 622 is located in the y1 direction relative to the first wiring portion 621.

[0072] The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622. The third wiring portion 623 is a strip-shaped portion extending in the y direction in a plan view. As can be seen from FIG. 6, the third wiring portion 623 overlaps with a plurality of second semiconductor elements 10B in a plan view. The third wiring portion 623 is connected to each of the second semiconductor elements 10B as shown in FIG. 17. The third wiring portion 623 has a plurality of recessed regions 623a. As shown in FIG. 17, each recessed region 623a protrudes in the z1 direction more than other portions of the third wiring portion 623. Each recessed region 623a of the third wiring portion 623 is bonded to each of the second semiconductor elements 10B. Each recessed region 623a of the third wiring portion 623 and the second principal surface electrode 12 (see FIG. 8) of each of the second semiconductor elements 10B are bonded via a conductive bonding material 69.

[0073] The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. The fourth wiring portion 624 is also connected to the third wiring portion 623. The fourth wiring portion 624 is located on the x2 direction side of the third wiring portion 623. As can be seen from FIG. 6, the fourth wiring portion 624 overlaps with the multiple first semiconductor elements 10A in a planar view. The fourth wiring portion 624 includes a first strip portion 625 and multiple second strip portions 626.

[0074] The first strip portion 625 is spaced apart from the third wiring portion 623 in the x direction, and is a strip-shaped portion of the fourth wiring portion 624 in a plan view. The first strip portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622. The first strip portion 625 overlaps a plurality of first semiconductor elements 10A in a plan view. The first strip portion 625 has a plurality of convex regions 625a. As shown in FIG. 16, each of the convex regions 625a protrudes in the z2 direction from other portions of the first strip portion 625. As shown in FIG. 6, each of the convex regions 625a overlaps each of the first semiconductor elements 10A in a plan view. Since the first strip portion 625 has a plurality of convex regions 625a, a region for joining each of the first conductive members 61 is provided on each of the first semiconductor elements 10A, as shown in FIG. 16. This prevents the first strip portion 625 from coming into contact with the first conductive members 61.

[0075] Each of the second strip portions 626 is connected to the first strip portion 625 and the third wiring portion 623. Each of the second strip portions 626 is strip-shaped extending in the x direction in a plan view. The second strip portions 626 are spaced apart in the y direction and arranged substantially parallel to each other. In a plan view, each of the second strip portions 626 has one end connected to a space between two first semiconductor elements 10A adjacent to each other in the y direction in the first strip portion 625, and the other end connected to a space between two second semiconductor elements 10B adjacent to each other in the y direction in the third wiring portion 623.

[0076] The first strip portion 625 has a first edge 627 and a second edge 628. As shown in FIG. 7, the first edge 627 is located in the x1 direction from the first side 191 in a plan view, and extends in the y direction at least from the third side 193 to the fourth side 194. As a result, in a plan view, two corners 171, 172 on the x2 direction side of each first semiconductor element 10A do not overlap the second conductive member 62. The two corners are the angle 171 between the first side 191 and the third side 193, and the angle 172 between the first side 191 and the fourth side 194. Therefore, in each first semiconductor element 10A, a part of each of the two sides sandwiching the corners 171, 172 is visible in a plan view (more specifically, when viewed as shown in FIG. 7; the same applies below). 7, the second edge 628 is located in the x2 direction from the second side 192 in a plan view, and extends in the y direction at least from the third side 193 to 194. As a result, in a plan view, two corners 173, 174 on the x1 direction side of each first semiconductor element 10A do not overlap with the second conductive member 62. The two corners are the angle 173 between the second side 192 and the third side 193, and the angle 174 between the second side 192 and the fourth side 194. Therefore, in each first semiconductor element 10A, a part of each of the two sides sandwiching the corners 173, 174 is visible in a plan view.

[0077] In each of the corners 171, 172, 173, and 174, the two sides sandwiching the corners 171, 172, 173, and 174 may be seen to have a length of more than 0 μm and less than 200 μm in a plan view. In addition, in a plan view, the length of the part visible on the two sides sandwiching the corners 171, 172, 173, and 174 is preferably 5 μm or more and 150 μm or less. When the length of the part visible on the two sides sandwiching the corners 171, 172, 173, and 174 is 2 μm or more, the corners of the first semiconductor element 10A can be detected, and when the length of the part visible on the two sides is 5 μm or more, the corners of the first semiconductor element 10A can be reliably detected. Note that, when the length of the part visible on the two sides exceeds 200 μm, the bonding area between the first conductive member 61 and the first semiconductor element 10A becomes smaller than necessary, which is not preferable. If the upper limit of the length of the visible portion of the two sides is 150 μm or less, this is preferable because it prevents the bonding area between the first conductive member 61 and the first semiconductor element 10A from becoming too small.

[0078] 6, the conductive member 6 (first conductive member 61 and second conductive member 62) has a first portion 601. The first portion 601 is a region that overlaps with the semiconductor element 10 (either the multiple first semiconductor elements 10A or the multiple second semiconductor elements 10B) in a planar view. In the second conductive member 62, a portion of the fourth wiring portion 624 (a region that overlaps with the multiple first semiconductor elements 10A in a planar view) and a portion of the third wiring portion 623 (a region that overlaps with the multiple second semiconductor elements 10B in a planar view) configure the first portion 601.

[0079] As shown in FIG. 6 and FIG. 8, the principal surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A (the first semiconductor element 10A having the diode functional portion D1) are arranged side by side along the y direction at the end of the first semiconductor element 10A on the x2 direction side. In a plan view, the first conductive member 61 and the second conductive member 62 do not overlap any of the principal surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A and the corners 171 and 172 on the x2 direction side. In addition, in a plan view, the first conductive member 61 and the second conductive member 62 do not overlap at least one of the corners 173 and 174 on the x1 direction side (the side opposite to the side on which the principal surface electrodes are arranged) of the first semiconductor element 10A. As a result, in a plan view, at least three corners of the four corners 171, 172, 173, and 174 of the semiconductor element 10A are visible. This makes it possible to inspect by automatic visual inspection whether semiconductor element 10A is correctly mounted in a state in which semiconductor element 10A, first conductive member 61, and second conductive member 62 are mounted on conductive substrate 2. In a plan view, all four corners 171, 172, 173, and 174 of semiconductor element 10A may be visible. Note that principal surface electrodes 11, 13, 14, and 16 of first semiconductor element 10A described above are examples of "one-side principal surface electrodes."

[0080] 6, each second semiconductor element 10B is also rectangular in plan view like the first semiconductor element 10A, and has four corners 181, 182, 183, 184 corresponding to the four corners 171, 172, 173, 174 of the first semiconductor element 10A. The above-mentioned relationship between the four corners 171, 172, 173, 174 of each first semiconductor element 10A and the first conductive member 61 and the second conductive member 62 in plan view is also the same as the relationship between the four corners 181, 182, 183, 184 of each second semiconductor element 10B and the second conductive member 62 in plan view.

[0081] As shown in FIG. 5, the second conductive member 62 includes a first portion 62A and a second portion 62B. The first portion 62A overlaps the main surface 201 (the main surface 201 of the first conductive portion 2A or the second conductive portion 2B) of the conductive substrate 2 in a plan view, and does not overlap any of the multiple semiconductor elements 10 in a plan view. The second portion 62B overlaps the main surface 201 in a plan view, and overlaps any of the multiple semiconductor elements 10 in a plan view. In FIG. 5, the first portion 62A is hatched with a rightward upward slope, and the second portion 62B is hatched with a rightward downward slope. The first portion 62A has an opening 63. The opening 63 is a portion that is partially cut out in a plan view, as shown in FIG. 5 and FIG. 13. In this embodiment, the opening 63 is located at a position that overlaps the main surface 201 of the first conductive portion 2A (conductive substrate 2) in a plan view, and does not overlap any of the multiple semiconductor elements 10 in a plan view. The opening 63 is, for example, a through hole penetrating in the z direction. The opening 63 may be formed in the first wiring portion 621 or in the second wiring portion 622. The opening 63 is provided near at least two of the four corners of the conductive substrate 2 in a plan view, and is provided, for example, near the x2 direction side in each of the first wiring portion 621 and the second wiring portion 622. The planar shape of the opening 63 is not limited, and may be a hole as in this embodiment, or may be a notch unlike this embodiment. The opening 63 may be manufactured by, for example, electroforming. In this case, the second conductive member 62 has an opening 63 made of a portion where the metal is not electrodeposited, rather than an opening 63 made of a portion where the metal is removed.

[0082] In the second conductive member 62, an opening 625h is formed in a rectangular portion overlapping each of the first semiconductor elements 10A in a plan view. In this embodiment, the opening 625h is preferably formed overlapping the center of each of the first semiconductor elements 10A in a plan view. The opening 625h is, for example, a through hole formed in each of the convex regions 625a of the first strip portion 625 (fourth wiring portion 624) (see FIG. 6). The opening 625h is used to optically check the state of bonding from above when bonding the first conductive member 61 and the first semiconductor element 10A.

[0083] In the second conductive member 62, an opening 623h is formed in a rectangular portion overlapping each second semiconductor element 10B in a plan view. In this embodiment, the opening 623h is preferably formed to overlap the center of the second semiconductor element 10B in a plan view. The opening 623h is, for example, a through hole formed in each recessed region 623a of the third wiring portion 623. The opening 623h is used when positioning the second conductive member 62 with respect to the conductive substrate 2. The planar shape of the two types of openings 623h, 625h may be a perfect circle, or may be another shape such as an ellipse or a rectangle.

[0084] The shape of the second conductive member 62 is not limited to this configuration, and for example, the second conductive member 62 does not have to include the fourth wiring portion 624. However, in order to reduce the inductance value due to the current flowing through the second conductive member 62, it is preferable to provide the second conductive member 62 with the fourth wiring portion 624.

[0085] The first conductive bonding material 71 is interposed between the conductive substrate 2 and the support substrate 3, and conductively bonds the conductive substrate 2 and the support substrate 3. There are two types of first conductive bonding material 71: one that conductively bonds the first conductive portion 2A to the first portion 32A, and one that conductively bonds the second conductive portion 2B to the second portion 32B. As shown in Fig. 15, the first conductive bonding material 71 has a first base layer 711, a first layer 712, and a second layer 713 that are stacked on top of each other.

[0086] As shown in FIG. 15, it is most preferable that the side of the first conductive bonding material 71 and the side of the first metal layer 32, which is the uppermost layer of the support substrate 3, are flush with each other. It is preferable that the side of the first metal layer 32 is located slightly inside the side of the first conductive bonding material 71 in a plan view. That is, in a plan view, the side of the first metal layer 32 is bonded so as not to protrude outside the side of the first conductive bonding material 71. If the side of the first metal layer 32 protrudes outside the side of the first conductive bonding material 71 in a plan view, the creepage distance between the first metal layer 32 and the second metal layer 33 becomes small, which is not preferable. Note that, in a plan view, the side of the first metal layer 32 is located outside the side of the base material 21 of the conductive substrate 2.

[0087] The first base layer 711 is made of a metal, and the metal is, for example, Al (aluminum) or an Al alloy. The first base layer 711 is a sheet material. The Young's modulus of Al, which is the material of the first base layer 711, is 70.3 GPa.

[0088] The first layer 712 is formed on the upper surface of the first base layer 711. The first layer 712 is interposed between the first base layer 711 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The first layer 712 is, for example, Ag plating. The first layer 712 is bonded to each of the back surface bonding layers 23 of the first conductive portion 2A and the second conductive portion 2B by, for example, solid-phase diffusion of metal. That is, the first layer 712 and each of the back surface bonding layers 23 of the first conductive portion 2A and the second conductive portion 2B are bonded by solid-phase diffusion bonding. As a result, the first layer 712 and each of the back surface bonding layers 23 are bonded in a state in which they are in direct contact with each other at the bonding interface. In this disclosure, "A and B are bonded by solid-phase diffusion bonding" means a mode in which A and B are fixed to each other in a state in which they are in direct contact with each other at the bonding interface as a result of the solid-phase diffusion bonding, and it can be said that a solid-phase diffusion bonding layer is formed by A and B. When solid-state diffusion bonding is performed under ideal conditions, the bonding interface may not be clearly present due to the diffusion of metal elements. On the other hand, if there are inclusions such as oxide films on the surfaces of A and B, or if there is a gap between A and B, these inclusions or gaps may exist at the bonding interface.

[0089] The second layer 713 is formed on the lower surface of the first base layer 711. The second layer 713 is interposed between the first base layer 711 and the support substrate 3 (each of the first portion 32A and the second portion 32B). The second layer 713 is, for example, Ag plating. The second layer 713 is bonded to the first bonding layer 321 formed on each of the first portion 32A and the second portion 32B by, for example, solid-phase diffusion of metal. That is, the second layer 713 and the first bonding layer 321 are bonded by solid-phase diffusion bonding, and are bonded in a state where they are in direct contact with each other at the bonding interface. The Young's modulus of Ag (silver), which is the constituent material of the first layer 712 and the second layer 713, is 82.7 GPa.

[0090] In the first conductive bonding material 71, the constituent material of the first base layer 711 and the constituent materials of the first layer 712 and the second layer 713 are as described above, and therefore the Young's modulus of the first base layer 711 is smaller than the Young's modulus of the first layer 712 and the second layer 713. The thickness (z-direction dimension) of the first base layer 711 is larger than the thicknesses of the first layer 712 and the second layer 713.

[0091] In the first conductive bonding material 71, the end surface of the first base layer 711, which is Al or an Al alloy, is not Ag-plated, and the end surface of the first base layer 711 is exposed. However, the end surface of the first base layer 711 may be Ag-plated. From the viewpoint of reducing the manufacturing cost of the first conductive bonding material 71, it is preferable to manufacture the first conductive bonding material 71 by forming Ag plating on both sides of a large-area sheet material and then cutting the Ag-plated sheet material. From this viewpoint, it is preferable that the end surface of the first base layer 711 is not Ag-plated.

[0092] The second conductive bonding material 72 is interposed between the conductive substrate 2 and each semiconductor element 10, and conductively bonds the conductive substrate 2 and each semiconductor element 10. There are two types of second conductive bonding material 72: one that conductively bonds each first semiconductor element 10A to the first conductive portion 2A, and one that conductively bonds each second semiconductor element 10B to the second conductive portion 2B. As shown in FIG. 15, the second conductive bonding material 72 includes a second base layer 721, a third layer 722, and a fourth layer 723 that are stacked on top of each other.

[0093] The second base layer 721 is made of a metal, for example, Al or an Al alloy. The second base layer 721 is a sheet material.

[0094] The third layer 722 is formed on the upper surface of the second base layer 721. The third layer 722 is interposed between the second base layer 721 and each semiconductor element 10. The third layer 722 is, for example, Ag plating. The third layer 722 is bonded to the back electrode 15 of each semiconductor element 10 by, for example, solid-state diffusion of metal. That is, the third layer 722 and the back electrode 15 are bonded by solid-state diffusion bonding, and are bonded in a state in which they are in direct contact with each other at the bonding interface.

[0095] The fourth layer 723 is formed on the lower surface of the second base layer 721. The fourth layer 723 is interposed between the second base layer 721 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The fourth layer 723 is, for example, Ag plating. The fourth layer 723 is bonded to each of the main surface bonding layers 22 of the first conductive portion 2A and the second conductive portion 2B by, for example, solid-state diffusion of metal. That is, the fourth layer 723 and each of the main surface bonding layers 22 are bonded by solid-state diffusion bonding, and are bonded in a state in which they are in direct contact with each other at the bonding interface.

[0096] In the second conductive bonding material 72, the constituent material of the second base layer 721 and the constituent materials of the third layer 722 and the fourth layer 723 are as described above, and therefore the Young's modulus of the second base layer 721 is smaller than the Young's modulus of the third layer 722 and the fourth layer 723. The thickness (z-direction dimension) of the second base layer 721 is larger than the thicknesses of the third layer 722 and the fourth layer 723.

[0097] In the second conductive bonding material 72, the end surface of the second base layer 721, which is Al or an Al alloy, is not Ag-plated, and the end surface of the second base layer 721 is exposed. However, the end surface of the second base layer 721 may be Ag-plated. From the viewpoint of reducing the manufacturing cost of the second conductive bonding material 72, it is preferable to manufacture the second conductive bonding material 72 by forming Ag plating on both sides of a large-area sheet material and then cutting the Ag-plated sheet material. From this viewpoint, it is preferable that the end surface of the second base layer 721 is not Ag-plated.

[0098] Each of the wires 731 to 735 provides electrical continuity between two parts spaced apart from each other. Each of the wires 731 to 735 is, for example, a bonding wire. The material of each of the wires 731 to 735 includes, for example, any one of Au (gold), Al, and Cu.

[0099] As shown in FIG. 8, the wires 731 are bonded to the first principal surface electrode 11 (gate electrode) of each semiconductor element 10 and the first portion 521 (first metal layer 52) of each control terminal supporter 5, respectively, to conduct them. As shown in FIG. 8, the wires 731 include a plurality of first wires 731a and a plurality of second wires 731b. The plurality of first wires 731a are connected to the first principal surface electrode 11 (gate electrode) of each first semiconductor element 10A and the first portion 521 (first metal layer 52) of the first support portion 5A, respectively. As a result, the first control terminal 46A is conducted to the first principal surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first wire 731a. The plurality of second wires 731b are connected to the first principal surface electrode 11 (gate electrode) of each second semiconductor element 10B and the first portion 521 (first metal layer 52) of the second support portion 5B, respectively. As a result, the second control terminal 47A is electrically connected to the first surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second wire 731b.

[0100] 8, the multiple wires 732 are bonded to the second principal surface electrode 12 (source electrode) of each semiconductor element 10 and the second portion 522 (first metal layer 52) of each control terminal support body 5, and provide electrical continuity therebetween. However, in each semiconductor element 10 having a diode function portion D1, each wire 732 is bonded to the fifth principal surface electrode 16 (source sense electrode) instead of the second principal surface electrode 12 (source electrode).

[0101] As shown in FIG. 8, each of the multiple wires 733 is joined to the third principal surface electrode 13 of each semiconductor element 10 having a diode functional portion D1 and the third portion 523 (first metal layer 52) of each control terminal support body 5, thereby providing electrical conductivity therebetween.

[0102] As shown in FIG. 8, each of the multiple wires 734 is joined to the fourth principal surface electrode 14 of each semiconductor element 10 having a diode functional portion D1 and the fourth portion 524 (first metal layer 52) of each control terminal support body 5, thereby providing electrical conductivity therebetween.

[0103] As shown in FIG. 8, wire 735 is joined to main surface 201 of first conductive portion 2A (conductive substrate 2) and fifth portion 525 (first metal layer 52) of first support portion 5A (control terminal support body 5), providing electrical continuity therebetween.

[0104] The sealing resin 8 covers the semiconductor elements 10, the conductive substrate 2, the support substrate 3 (except the bottom surface 302), a portion of each of the input terminals 41-43, a portion of each of the output terminals 44, a portion of each of the control terminals 45, the control terminal support 5, the conductive member 6, and the wires 731-735. The sealing resin 8 is made of, for example, a black epoxy resin. The sealing resin 8 is formed, for example, by molding, which will be described later. The sealing resin 8 has, for example, a dimension in the x direction of about 35 mm to 60 mm, a dimension in the y direction of about 35 mm to 50 mm, and a dimension in the z direction of about 4 mm to 15 mm. These dimensions are the sizes of the maximum portions along each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 831-834.

[0105] The resin main surface 81 and the resin back surface 82 are spaced apart in the z direction, as shown in FIG. 9, FIG. 11, FIG. 12, etc. The resin main surface 81 faces the z2 direction, and the resin back surface 82 faces the z1 direction. A plurality of control terminals 45 (a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D) protrude from the resin main surface 81. The resin back surface 82 is frame-shaped in plan view surrounding the bottom surface 302 (the lower surface of the second metal layer 33) of the support substrate 3, as shown in FIG. 10. The bottom surface 302 of the support substrate 3 is exposed from the resin back surface 82, and is, for example, flush with the resin back surface 82. The plurality of resin side surfaces 831 to 834 are connected to both the resin main surface 81 and the resin back surface 82, and are sandwiched between them in the z direction. As shown in FIG. 4, etc., the resin side surface 831 and the resin side surface 832 are spaced apart in the x direction. Resin side surface 831 faces the x1 direction, and resin side surface 832 faces the x2 direction. Two output terminals 44 protrude from resin side surface 831, and three input terminals 41 to 43 protrude from resin side surface 832. As shown in Fig. 4 etc., resin side surface 833 and resin side surface 834 are spaced apart in the y direction. Resin side surface 833 faces the y1 direction, and resin side surface 834 faces the y2 direction.

[0106] 4, a plurality of recesses 832a are formed on the resin side surface 832. Each recess 832a is a portion recessed in the x-direction in a plan view. The plurality of recesses 832a include those formed between the input terminal 41 and the input terminal 42 and those formed between the input terminal 41 and the input terminal 43 in a plan view. The plurality of recesses 832a are provided to increase the creepage distance along the resin side surface 832 between the input terminal 41 and the input terminal 42 and the creepage distance along the resin side surface 832 between the input terminal 41 and the input terminal 43.

[0107] The sealing resin 8 has a plurality of first protruding portions 851, a plurality of second protruding portions 852, and a resin cavity portion 86, as shown in FIG. 13, FIG.

[0108] Each of the first protrusions 851 protrudes in the z direction from the resin main surface 81. The first protrusions 851 are disposed near the four corners of the sealing resin 8 in a plan view. A first protrusion end surface 851a is formed at the tip (end in the z2 direction) of each of the first protrusions 851. Each of the first protrusion end surfaces 851a of the first protrusions 851 is substantially parallel to the resin main surface 81 and is on the same plane (xy plane). Each of the first protrusions 851 is, for example, a bottomed hollow truncated cone. The first protrusions 851 are used as spacers when the semiconductor module A1 is mounted on a control circuit board or the like of an apparatus that uses the power generated by the semiconductor module A1. Each of the first protrusions 851 has a recess 851b and an inner wall surface 851c formed in the recess 851b. The shape of each of the first protrusions 851 may be columnar, and is preferably cylindrical. It is preferable that the shape of the recess 851b is cylindrical, and that the inner wall surface 851c is a single perfect circle in plan view.

[0109] The semiconductor module A1 may be mechanically fixed to a control circuit board or the like by a method such as screwing. In this case, a female screw thread may be formed on the inner wall surface 851c of the recess 851b of the first protrusions 851. An insert nut may be embedded in the recess 851b of the first protrusions 851.

[0110] As shown in FIG. 14 and other figures, the multiple second protrusions 852 protrude in the z direction from the resin main surface 81. The multiple second protrusions 852 overlap the multiple control terminals 45 in a plan view. Each metal pin 452 of the multiple control terminals 45 protrudes from each second protrusion 852. A part of the holder 451 (upper surface of the upper end flange) is exposed from the upper end surface of each second protrusion 852. Each second protrusion 852 is frustum-shaped. A resin part 87 is disposed on each second protrusion 852.

[0111] 13, the resin void 86 leads in the z direction from the resin main surface 81 to a recess 201a formed in the main surface 201 of the conductive substrate 2. The resin void 86 is formed in a tapered shape with a cross-sectional area decreasing from the resin main surface 81 to the recess 201a in the z direction. A resin void edge 861 in the resin void 86 that contacts the main surface 201 and a recess edge 201b in the recess 201a that contacts the main surface 201 coincide with each other. The resin void 86 is formed during molding, which will be described later, and is a portion where the sealing resin 8 is not formed during the molding.

[0112] The resin portion 87 is provided on the second protruding portion 852 of the sealing resin 8. In each control terminal 45, the resin portion 87 covers a part of the holder 451 (the upper surface of the upper end flange) exposed from the sealing resin 8 and a part of the metal pin 452. The resin portion 87 is made of, for example, an epoxy resin like the sealing resin 8, but may be made of a different material from the sealing resin 8.

[0113] The resin filling portion 88 is filled in the resin void portion 86 so as to fill the resin void portion 86. The resin filling portion 88 is made of, for example, an epoxy resin like the sealing resin 8, but may be made of a different material from the sealing resin 8.

[0114] Next, a method for manufacturing the semiconductor module A1 will be described with reference to FIGS. 21 to 29. FIG. 21 is a plan view showing one step of the method for manufacturing the semiconductor module A1. FIG. 22 is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor module A1. FIG. 23 is a plan view showing one step of the method for manufacturing the semiconductor module A1. FIG. 24 is a cut end view showing one step of the method for manufacturing the semiconductor module A1. FIG. 24 corresponds to the cross section shown in FIG. 13. FIGS. 25 and 28 are enlarged cross-sectional views of a main part showing one step of the method for manufacturing the semiconductor module A1, and correspond to the enlarged view of a part of the cross section shown in FIG. 13. FIGS. 26, 27, and 29 are enlarged cross-sectional views of a main part showing one step of the method for manufacturing the semiconductor module A1, and correspond to the enlarged view of a part of the cross section shown in FIG. 14.

[0115] First, a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, and a plurality of output terminals 44 are prepared. The configurations of the plurality of semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are as described above. At the stage of preparing these, the plurality of semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are prepared individually and are not joined to each other. In addition, as shown in FIG. 21, the conductive substrate 2, the plurality of input terminals 41 to 43, and the plurality of output terminals 44 are connected to each other and are formed, for example, of the same lead frame. Furthermore, as shown in FIG. 21, the main surface 201 of the conductive substrate 2 does not have a recess 201a formed thereon.

[0116] 22, the conductive substrate 2 is placed on the support substrate 3 with a first conductive bonding material 71 sandwiched therebetween, and then each semiconductor element 10 is placed on the conductive substrate 2 with a second conductive bonding material 72 sandwiched therebetween. Thereafter, while the lower surface of the support substrate 3 and the upper surface of each semiconductor element 10 are held (see the thick arrows in FIG. 22), heat is applied to bond each semiconductor element 10 to the conductive substrate 2 by solid-phase diffusion, and also bond the conductive substrate 2 to the support substrate 3 by solid-phase diffusion. Specifically, the first bonding layer 321 (support substrate 3) on the first metal layer 32 and the second layer 713 (first conductive bonding material 71), the first layer 712 (first conductive bonding material 71) and the back surface bonding layer 23 (conductive substrate 2), the fourth layer 723 (second conductive bonding material 72) and the main surface bonding layer 22 (conductive substrate 2), and the third layer 722 (second conductive bonding material 72) and the back surface electrode 15 of each semiconductor element 10 are all bonded together by solid-phase diffusion. In terms of the conditions for solid-phase diffusion, the heating temperature during bonding may be in the range of 200° C. or more and 350° C. or less, and the pressure applied during bonding (the clamping force) may be in the range of 1 MPa or more and 100 MPa or less. Although the solid-phase diffusion is assumed to be performed in the atmosphere, it may also be performed in a vacuum. As a result, the conductive substrate 2 is bonded to the support substrate 3 via the first conductive bonding material 71, and each semiconductor element 10 is bonded to the conductive substrate 2 via the second conductive bonding material 72. The bonding between the conductive substrate 2 and the support substrate 3, and the bonding between the conductive substrate 2 and each semiconductor element 10 may be processed separately rather than collectively. However, processing them collectively is preferable in terms of improving manufacturing efficiency.

[0117] When placing each semiconductor element 10 on the conductive substrate 2 with the second conductive bonding material 72 sandwiched therebetween, an individual second conductive bonding material 72 is disposed corresponding to each semiconductor element 10, as shown in Fig. 16 and Fig. 17. However, without being limited thereto, one second conductive bonding material 72 may be disposed commonly corresponding to the three semiconductor elements 10 shown in Fig. 16.

[0118] 23, the control terminal support body 5 is joined, the holders 451 of the control terminals 45 are joined, the wires 731 to 735 are wire-bonded, the first conductive members 61 are joined, and the second conductive members 62 are joined. The order of these steps is not limited.

[0119] Next, the sealing resin 8 is formed. The sealing resin 8 is formed, for example, by molding. As shown in FIG. 24, a metal mold 91 used in molding is provided with a pressing pin 911 as a pressing member. The tip of the pressing pin 911 is in contact with the main surface 201 of the conductive substrate 2. At this time, a pressing force of the pressing pin 911 on the main surface 201 forms a recess 201a in the main surface 201. The depression degree (depth) of the recess 201a varies depending on the magnitude of the pressing force. In addition, the pressing pin 911 in contact with the main surface 201 of the first conductive part 2A is inserted into the opening 63 of the second conductive member 62. Then, a fluid resin material is injected into the cavity space 919 of the metal mold 91 through a resin flow path and a resin injection port (both not shown in the figure) in this order. The injected fluid resin material is solidified to form the sealing resin 8. As shown in FIG. 25 and FIG. 26, the formed sealing resin 8 has the first protruding portion 851, the second protruding portion 852, and the resin void portion 86. As shown in FIG. 25, a resin void portion edge 861 that contacts the main surface 201 in the resin void portion 86 and a recessed portion edge 201b that contacts the main surface 201 in the recessed portion 201a coincide with each other. As shown in FIG. 26, the upper surface of the holder 451 is exposed from the second protruding portion 852 and is flush with the upper surface of the second protruding portion 852. As can be seen from FIG. 24 and FIG. 25, the resin void portion 86 is formed by preventing the fluid resin material from being filled by the pressing pin 911. The pressing pin 911 may be a movable pin. In this case, it is preferable that the pressing pin 911 is provided in a hole formed in the mold 91 and is elastically supported. Not limited to a pin-shaped pressing member, a block-shaped pressing member may be used.

[0120] Next, the mold 91 is opened to take out a molded body including the lead frame including the conductive substrate 2 and the sealing resin 8. After that, the sealing resin 8 is separated from the resin solidified in the resin flow path and the resin injection port. In this process, resin separation marks are formed in any of the following positions on the resin side surface 831 on the x1 direction side of the sealing resin 8. The first position is at least one of two positions close to both ends in the y direction on the resin side surface 831 shown in FIG. 1, or at least one of the corners on both ends. When resin separation marks are formed on the corners on both ends, resin separation marks are formed on the surface formed on the corner (the part that is C-chamfered in a plan view). The above-mentioned inclined surface is included in the resin side surface 831 on the x1 direction side of the sealing resin 8. The second position is between the two output terminals 44 on the resin side surface 831 shown in FIG. 1. These resin separation marks correspond to the position of the resin injection port of the mold 91, and are formed by separating the sealing resin 8 from the resin solidified at the resin injection port. In order to suppress bias in the wraparound of the resin, it is preferable to inject the resin from the center position in the y direction. In this case, a resin separation mark is formed between the two output terminals 44.

[0121] Next, as shown in FIG. 27, each metal pin 452 of the multiple control terminals 45 is press-fitted into each holder 451. Specifically, each metal pin 452 having a cross-sectional dimension slightly larger than the inner diameter of the cylindrical portion (see FIG. 26) of each holder 451 is inserted while applying an insertion pressure. As a result, each holder 451 and each metal pin 452 are mechanically fixed and electrically connected. Each holder 451 and each metal pin 452 may be electrically connected using, for example, solder. Thereafter, as shown in FIG. 28 and FIG. 29, a resin portion 87 and a resin-filled portion 88 are formed. The resin portion 87 and the resin-filled portion 88 are formed, for example, by potting.

[0122] Next, the lead frame is appropriately cut to separate the input terminals 41 to 43 and the output terminal 44. In the input terminals 41 to 43 and the output terminal 44 shown in FIG. 21, the vicinity of the connection portion between each terminal and the outer frame portion of the lead frame (portions shown by dashed lines in FIG. 21) may be cut using a mold or the like. Here, the input terminals 41 to 43 have tip surfaces 413, 423, and 433 formed as input-side processing marks. The output terminal 44 has a tip surface 443 formed as an output-side processing mark. In the case where the lead frame has a tie bar connecting the terminals adjacent in the y direction in the y direction, the tie bar may be cut using a mold or the like. In this case, processing marks are formed on two side surfaces facing the y direction in each terminal. Through the above steps, the semiconductor module A1 shown in FIGS. 1 to 20 is manufactured.

[0123] The semiconductor module A1 is mounted on a control circuit board or the like. Here, each metal pin 452 is inserted into a pin hole of the circuit board on which the semiconductor module A1 is mounted, and connected to a terminal around the pin hole. The input terminals 41, 42, and 43 have input side bonding surfaces 411, 421, and 431 facing one side in the z direction (z2 direction), respectively. Each output terminal 44 has an output side bonding surface 441 facing one side in the z direction (z2 direction). The input side bonding surfaces 411, 421, and 431 and the output side bonding surface 441 are connected to a terminal of the circuit board on which the semiconductor module A1 is mounted, for example, by using solder.

[0124] In the semiconductor module A1 of this embodiment, the current path from the input terminal 41 to the output terminal 44 will be described below. The first main circuit current flows through the input terminal 41, the first conductive portion 2A, each first semiconductor element 10A, the first conductive member 61, the second conductive portion 2B, and each output terminal 44. The first main circuit current flows along the x direction between the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 2B via each first conductive member 61. In the second conductive portion 2B, the first main circuit current flows along the x direction and a direction slightly tilted from the x direction between a portion where each first conductive member 61 is joined and each output terminal 44.

[0125] The current path from the output terminal 44 to the input terminals 42 and 43 will be described below. The second main circuit current flows through the output terminal 44, the second conductive portion 2B, each second semiconductor element 10B, the second conductive member 62, the input terminals 42 and 43. The path of the second main circuit current is possessed by the second conductive member 62, and the second main circuit current flows through both the third wiring portion 623 extending in the y direction and the first wiring portion 621 and the second wiring portion 622 connected to both ends of the third wiring portion 623 and extending in the x2 direction. Furthermore, the second main circuit current flows through the first wiring portion 621 and the second wiring portion 622 via a route passing through two second strip portions 626 arranged between the first wiring portion 621 and the second wiring portion 622 and extending in the x-direction, and a first strip portion 625 arranged between the first wiring portion 621 and the second wiring portion 622 and extending in the y-direction.

[0126] A second main circuit current flows between the input terminals 42 and 43 and the second principal surface electrodes 12 of each second semiconductor element 10B via the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, the two second strip portions 626, and the first strip portion 625 included in each second conductive member 62. In the first wiring portion 621, the second wiring portion 622, and the two second strip portions 626, the second main circuit current flows along the x direction. The direction in which the first main circuit current flows is opposite to the direction in which the second main circuit current flows.

[0127] The direction in which the first main circuit current flows in the first conductive member 61 and the direction in which the second main circuit current flows in the first wiring portion 621, the second wiring portion 622, and the two second strip portions 626 included in the second conductive member 62 are both in the x direction.

[0128] The semiconductor module A1 has the following advantages.

[0129] The semiconductor module A1 includes a conductive substrate 2, a plurality of input terminals 41 to 43, an output terminal 44, and a conductive member 6. The conductive substrate 2 includes a first conductive portion 2A to which a plurality of first semiconductor elements 10A are joined, and a second conductive portion 2B to which a plurality of second semiconductor elements 10B are joined. The input terminal 41 is connected to the first conductive portion 2A, and is electrically connected to the plurality of first semiconductor elements 10A via the first conductive portion 2A. The input terminal 42 and the input terminal 43 are electrically connected to the plurality of second semiconductor elements 10B via a second conductive member 62 (conductive member 6). The output terminal 44 is connected to the second conductive portion 2B, and is electrically connected to the plurality of second semiconductor elements 10B via the second conductive portion 2B. The conductive member 6 includes a first conductive member 61 that electrically connects each of the first semiconductor elements 10A to the second conductive portion 2B, and a second conductive member 62 that electrically connects each of the second semiconductor elements 10B to each of the input terminals 42, 43. The input terminals 41 to 43 are arranged on the x2 direction side with respect to the conductive substrate 2, and the output terminal 44 is arranged in the x1 direction with respect to the conductive substrate 2. The two input terminals 42, 43 are arranged on opposite sides of the input terminal 41 in the y direction. In a semiconductor module having a different configuration from the semiconductor module A1, if the input terminal 43 is not provided and the input terminals 41 and 42 are arranged side by side in the y direction, there is a possibility that the path of the current flowing from the input terminal 41 to the output terminal 44 via each of the first semiconductor elements 10A will vary, and the path of the current flowing from the output terminal 44 to each of the input terminals 42 via each of the second semiconductor elements 10B will vary. Therefore, the semiconductor module A1 is provided with two input terminals 42, 43, and by sandwiching the input terminal 41 between the two input terminals 42, 43, it is possible to reduce the variation in the path of the current flowing from the input terminal 41 to the output terminal 44 via each of the first semiconductor elements 10A, and also to reduce the variation in the path of the current flowing from the output terminal 44 to each of the input terminals 42, 43 via each of the second semiconductor elements 10B. This makes it possible to reduce the parasitic inductance component of the semiconductor module A1. In other words, the semiconductor module A1 has a package structure that is preferable for reducing the parasitic inductance component.

[0130] In the semiconductor module A1, the upper arm current path and the lower arm current path overlap in a plan view. The upper arm current path is a path of current flowing from the input terminal 41 to each output terminal 44 via the first conductive portion 2A, each first semiconductor element 10A, each first conductive member 61, and the second conductive portion 2B, and in this embodiment, it is along from the x2 direction side to the x1 direction side as can be seen from FIG. 5. The lower arm current path is a path of current flowing from the output terminal 44 to the input terminal 42 via each second semiconductor element 10B and the second conductive member 62, and in this embodiment, it is along from the x1 direction side to the x2 direction side as can be seen from FIG. 5. With this configuration, the magnetic field generated by the current along the upper arm current path and the magnetic field generated by the current along the lower arm current path cancel each other out, so that the parasitic inductance component can be reduced. In particular, in the semiconductor module A1, by configuring the conductive members 6 (each of the plurality of first conductive members 61 and second conductive members 62) with a metal plate material, it is possible to appropriately ensure an overlapping area between the upper arm current path and the lower arm current path in a plan view. In other words, the semiconductor module A1 has a preferable package structure for reducing the parasitic inductance component.

[0131] In the semiconductor module A1, the second conductive member 62 constituting the lower arm current path includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to the input terminals 42, 43 arranged on opposite sides of each other in the y direction with the input terminal 41 in between, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the multiple second semiconductor elements 10B. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622, and overlaps with the multiple first semiconductor elements 10A in a plan view. The second conductive member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623 and the fourth wiring portion 624 is disposed at a distance from the main surface 201 (conductive substrate 2) in the z direction and overlaps with a wide range of the main surface 201 in a plan view. This configuration appropriately reduces the variation in the path of the current flowing from the output terminal 44 to the input terminals 42, 43 via the second semiconductor elements 10B, which is suitable for reducing the parasitic inductance component.

[0132] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x direction. With this configuration, it is possible to prevent the size in the y direction of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged from increasing, thereby enabling the semiconductor module A1 to be miniaturized.

[0133] The fourth wiring portion 624 of the second conductive member 62 has a first strip portion 625 and a plurality of second strip portions 626. The first strip portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is a portion that overlaps with the plurality of first semiconductor elements 10A in a planar view. Each of the plurality of second strip portions 626 is connected to the first strip portion 625 and the third wiring portion 623 and is a strip extending in the x direction in a planar view. The plurality of second strip portions 626 are spaced apart in the y direction and arranged approximately parallel to each other. In a planar view, each of the plurality of second strip portions 626 has one end connected between two first semiconductor elements 10A adjacent to each other in the y direction of the first strip portion 625, and the other end connected between two second semiconductor elements 10B adjacent to each other in the y direction of the third wiring portion 623. According to this configuration, it is possible to ensure that the size of the fourth wiring portion 624 (the second conductive member 62) in a plan view is larger, which is preferable in terms of reducing the parasitic inductance component.

[0134] The first strip portion 625 has multiple convex regions 625a that protrude in the z2 direction further than other portions. Each convex region 625a overlaps with a corresponding first semiconductor element 10A in a plan view. The configuration in which the first strip portion 625 has multiple convex regions 625a makes it possible to prevent the first strip portion 625 from inappropriately contacting the first conductive member 61 bonded onto the first semiconductor element 10A.

[0135] The third wiring portion 623 has multiple recessed regions 623a that protrude in the z1 direction further than other portions. Each recessed region 623a is joined to one of the multiple second semiconductor elements 10B. This configuration makes it possible to ensure a large size of the third wiring portion 623 (second conductive member 62) in a plan view while appropriately conducting the third wiring portion 623 (second conductive member 62) and the multiple second semiconductor elements 10B.

[0136] The semiconductor module A1 includes the conductive member 6 (first conductive member 61 and second conductive member 62) configured as described above, as well as a plurality of first control terminals 46A-46E and a plurality of second control terminals 47A-47D for controlling the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The plurality of first control terminals 46A-46E and the plurality of second control terminals 47A-47D are each arranged to extend along the z direction on the main surface 201 of the conductive substrate 2. The semiconductor module A1 configured in this way can be made compact in plan view, and is therefore suitable for making the module compact in plan view while reducing the parasitic inductance component.

[0137] The first control terminals 46A-46E are supported by the first conductive portion 2A and are disposed on the x2 side of the first semiconductor elements 10A. The second control terminals 47A-47D are supported by the second conductive portion 2B and are disposed on the x1 side of the second semiconductor elements 10B. The first control terminals 46A-46E and the second control terminals 47A-47D are disposed at intervals in the y direction. As a result, the first control terminals 46A-46E and the second control terminals 47A-47D are appropriately disposed in regions corresponding to the first semiconductor elements 10A constituting the upper arm circuit and the second semiconductor elements 10B constituting the lower arm circuit. The semiconductor module A1 having such a configuration is more preferable in terms of reducing the parasitic inductance component and miniaturizing the module.

[0138] The first semiconductor element 10A and the second semiconductor element 10B each have a first principal surface electrode 11 (gate electrode) facing the z2 direction. The first control terminal 46A is connected to the first principal surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first wire 731a. The second control terminal 47A is connected to the first principal surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second wire 731b. This allows a drive signal for driving the first semiconductor element 10A (second semiconductor element 10B) having a switching function to be appropriately input to the first principal surface electrode 11 via the first control terminal 46A (second control terminal 47A) and the first wire 731a (second wire 731b).

[0139] When the semiconductor module A1 is mounted on a circuit board, each metal pin 452 is inserted into a pin hole of the circuit board on which the semiconductor module A1 is mounted, and connected to a terminal around the pin hole. The input terminals 41, 42, and 43 have input side bonding surfaces 411, 421, and 431 facing one side in the z direction (z2 direction), respectively. Each output terminal 44 has an output side bonding surface 441 facing one side in the z direction (z2 direction). The input side bonding surfaces 411, 421, and 431 and the output side bonding surface 441 are connected to the terminal of the circuit board on which the semiconductor module A1 is mounted, for example, by using solder. With the above-mentioned configuration, the power system circuit board to which the input terminals 41 to 43 and the output terminal 44 are connected and the control system circuit board to which the metal pins 452 are connected can be arranged apart in the z direction. As a result, firstly, the degree of freedom regarding the arrangement of the signal terminals in the semiconductor module A1 is improved. Second, the degree of freedom regarding the routing and length of signal wiring in the semiconductor module A1 is improved. Third, when using the semiconductor module A1, the degree of freedom regarding the layout of the circuit board by the user is improved.

[0140] In the semiconductor module A1, each control terminal 45 protrudes from the resin main surface 81 and extends along the z direction. In a configuration different from the semiconductor module A1, each control terminal 45 may be arranged to extend along a plane (xy plane) perpendicular to the z direction. In this configuration, there is a limit to how compact the semiconductor module A1 can be in a planar view. Therefore, by arranging each control terminal 45 to extend along the z direction as in the semiconductor module A1, it is possible to make the semiconductor module A1 compact in a planar view. In other words, the semiconductor module A1 has a package structure that is preferable for making the module compact in a planar view.

[0141] In the semiconductor module A1 of this embodiment, a control terminal support body 5 is interposed between each control terminal 45 and the main surface 201 (conductive substrate 2). The control terminal support body 5 has an insulating layer 51, and each control terminal 45 is supported on the conductive substrate 2 via the control terminal support body 5. With such a configuration including the control terminal support body 5, the control terminal 45 can be appropriately supported on the conductive substrate 2 while ensuring insulation between the control terminal 45 and the conductive substrate 2.

[0142] The control terminal support body 5 is a laminated structure having an insulating layer 51, a first metal layer 52, and a second metal layer 53, which are laminated on one another. The control terminal 45 is bonded to the first metal layer 52 formed on the upper surface of the control terminal support body 5 via a conductive bonding material 459. With this configuration, it is possible to conductively bond the control terminal 45 to the control terminal support body 5 (first metal layer 52) while using a ready-made laminated structure (e.g., a DBC board, etc.) as the control terminal support body 5.

[0143] The semiconductor element 10 has an element principal surface 101 facing the z2 direction, and an element rear surface 102 facing the z1 direction. A first principal surface electrode 11 (gate electrode) is disposed on the element principal surface 101. The first principal surface electrode 11 and the first metal layer 52 (first portion 521) of each semiconductor element 10 are connected by a conductive wire 731. This allows a drive signal for driving the semiconductor element 10 having a switching function to be appropriately input to the first principal surface electrode 11 via the control terminal 45, the first metal layer 52, and the wire 731.

[0144] Each control terminal 45 includes a holder 451 and a metal pin 452. The holder 451 is made of a conductive material and includes a cylindrical portion. The metal pin 452 is a rod-shaped member extending in the z-direction and is press-fitted into the holder 451. A part of the holder 451 (the upper surface of the upper flange) is exposed from the sealing resin 8. According to this configuration, the holder 451 is covered with the sealing resin 8 except for a part of it (the upper end surface) by forming (molding) the sealing resin 8, and the upper end surface of the holder 451 is exposed from the sealing resin 8. This makes it possible to insert the metal pin 452 into the holder 451 after the sealing resin 8 is formed. Therefore, according to the configuration in which the control terminal 45 includes the above-mentioned holder 451 and the metal pin 452, it is possible to avoid the mold 91 used in the molding from becoming complicated, and this is suitable for efficiently manufacturing the semiconductor module A1.

[0145] The semiconductor module A1 of this embodiment includes a resin part 87 joined to the sealing resin 8. The resin part 87 covers a part of the holder 451 (the upper surface of the upper end flange) exposed from the sealing resin 8 and a part of the metal pin 452. This configuration can prevent foreign matter from entering the connection part between the holder 451 and the metal pin 452. The semiconductor module A1 having the above configuration is preferable in terms of improving durability and reliability.

[0146] The sealing resin 8 has a plurality of second protrusions 852 protruding from the resin main surface 81. The plurality of second protrusions 852 surround the plurality of control terminals 45 in a plan view. Each metal pin 452 of the plurality of control terminals 45 protrudes from each second protrusion 852. A resin portion 87 is disposed on each second protrusion 852. With this configuration, it is possible to increase the creepage distance along the resin main surface 81 of the adjacent control terminals 45. This is preferable in terms of increasing the withstand voltage of the adjacent control terminals 45.

[0147] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B spaced apart from each other in the x direction. The first conductive portion 2A is located further in the x2 direction than the second conductive portion 2B. The semiconductor elements 10 include a first semiconductor element 10A joined to the first conductive portion 2A and a second semiconductor element 10B joined to the second conductive portion 2B. The control terminals 45 include first control terminals 46A-46E and second control terminals 47A-47D. The first control terminals 46A-46E are supported by the first conductive portion 2A and are located between the first semiconductor element 10A and the input terminals 41, 42, etc. in the x direction. The second control terminals 47A-47D are located between the second semiconductor element 10B and the output terminal 44 in the x direction. According to this configuration, the multiple control terminals 45 (first control terminals 46A-46E and second control terminals 47A-47D) are appropriately arranged in regions corresponding to the first semiconductor element 10A constituting the upper arm circuit and the second semiconductor element 10B constituting the lower arm circuit. This configuration is preferable in terms of miniaturizing the semiconductor module A1.

[0148] The sealing resin 8 has a plurality of first protruding portions 851 protruding from the resin main surface 81. A first protruding end surface 851a is formed at the tip of each of the first protruding portions 851. Each of the first protruding end surfaces 851a of the plurality of first protruding portions 851 is substantially parallel to the resin main surface 81 and is on the same plane (xy plane). With this configuration, in an apparatus that uses the power generated by the semiconductor module A1, a predetermined gap can be secured between the surface of the control circuit board on which the semiconductor module A1 is mounted and the resin main surface 81. As a result, even if various functional components are mounted on the surface of the control circuit board facing the semiconductor module A1, the functional components are prevented from coming into inappropriate contact with the sealing resin 8.

[0149] The semiconductor module A1 includes a conductive substrate 2 to which each semiconductor element 10 is bonded. With this configuration, heat generated by energizing each semiconductor element 10 is transferred to the conductive substrate 2, and the heat transferred from each semiconductor element 10 is diffused by the conductive substrate 2. Therefore, the semiconductor module A1 has a package structure that is preferable for improving the heat dissipation performance of each semiconductor element 10.

[0150] In the semiconductor module A1, the conductive substrate 2 and the support substrate 3 are bonded via a first conductive bonding material 71. The first conductive bonding material 71 includes a first layer 712 and a second layer 713. The first layer 712 is bonded to the conductive substrate 2 by solid-phase diffusion of metal, and the two are bonded in a state of direct contact with each other at the bonding interface. The second layer 713 is bonded to the support substrate 3 by solid-phase diffusion of metal, and the two are bonded in a state of direct contact with each other at the bonding interface. With this configuration, the bonding strength between the conductive substrate 2 and the support substrate 3 can be increased compared to when the conductive substrate 2 and the support substrate 3 are bonded by a bonding material such as solder. Therefore, the semiconductor module A1 has a package structure that is preferable for suppressing peeling between the conductive substrate 2 and the support substrate 3.

[0151] In the semiconductor module A1, each semiconductor element 10 and the conductive substrate 2 are bonded via a second conductive bonding material 72. The second conductive bonding material 72 includes a third layer 722 and a fourth layer 723. The third layer 722 is bonded to each semiconductor element 10 (rear electrode 15) by solid-phase diffusion of metal, and the semiconductor elements 10 and the conductive substrate 2 are bonded in a state of direct contact with each other at the bonding interface. The fourth layer 723 is bonded to the conductive substrate 2 by solid-phase diffusion of metal, and the semiconductor elements 10 and the conductive substrate 2 are bonded in a state of direct contact with each other at the bonding interface. With this configuration, the bonding strength between each semiconductor element 10 and the conductive substrate 2 can be increased compared to when the semiconductor elements 10 and the conductive substrate 2 are bonded by a bonding material such as solder. Therefore, the semiconductor module A1 has a package structure that is preferable for suppressing peeling between each semiconductor element 10 and the conductive substrate 2.

[0152] In the semiconductor module A1 of the present embodiment, the Young's modulus of the first base layer 711 in the first conductive bonding material 71 is smaller than the Young's modulus of each of the constituent materials of the first layer 712 and the second layer 713. With this configuration, when the first conductive bonding material 71 is bonded to the conductive substrate 2 and the support substrate 3 by solid-state diffusion, the relatively soft first base layer 711 relieves stress, and the bonded boundary can be smoothed. As a result, the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3 are bonded more firmly by solid-state diffusion.

[0153] In this embodiment, the thickness of the first base layer 711 is greater than the thickness of each of the first layer 712 and the second layer 713. This allows the pressure acting on the boundary between the first layer 712 and the conductive substrate 2 (rear surface bonding layer 23) and the boundary between the second layer 713 and the support substrate 3 (first bonding layer 321) to be more uniform during bonding by solid-phase diffusion. This allows the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3 to be more firmly bonded to each other.

[0154] The constituent material of each of the first layer 712 and the second layer 713 contains silver. With this configuration, during bonding by solid-phase diffusion using the first conductive bonding material 71, oxidation of the first layer 712 and the second layer 713 is suppressed, enabling good solid-phase diffusion bonding. In addition, each of the back surface bonding layer 23 and the first bonding layer 321 bonded to the first layer 712 and the second layer 713 also contains silver, enabling better solid-phase diffusion bonding.

[0155] In this embodiment, the Young's modulus of the second base layer 721 in the second conductive bonding material 72 is smaller than the Young's modulus of each of the constituent materials of the third layer 722 and the fourth layer 723. With this configuration, when the second conductive bonding material 72 is bonded to the semiconductor element 10 (rear electrode 15) and the conductive substrate 2 by solid-phase diffusion, the stress is relieved by the relatively soft second base layer 721, and the bonding boundary can be smoothed. As a result, the third layer 722 and the semiconductor element 10 (rear electrode 15), and the fourth layer 723 and the conductive substrate 2 are bonded more firmly by solid-phase diffusion.

[0156] In this embodiment, the thickness of the second base layer 721 is greater than the thickness of each of the third layer 722 and the fourth layer 723. This allows the pressure acting on the boundary between the third layer 722 and the semiconductor element 10 (rear electrode 15) and the boundary between the fourth layer 723 and the conductive substrate 2 (main surface bonding layer 22) to be more uniform during bonding by solid-phase diffusion. This allows the third layer 722 and the semiconductor element 10 (rear electrode 15), and the fourth layer 723 and the conductive substrate 2 to each be in a stronger conductive bonded state.

[0157] The constituent material of each of the third layer 722 and the fourth layer 723 contains silver. With this configuration, during bonding by solid-phase diffusion using the second conductive bonding material 72, oxidation of the third layer 722 and the fourth layer 723 is suppressed, enabling good solid-phase diffusion bonding. In addition, each of the back electrode 15 and the main surface bonding layer 22 bonded to the third layer 722 and the fourth layer 723 also contains silver, enabling better solid-phase diffusion bonding.

[0158] The first conductive bonding material 71 is configured by laminating a first layer 712 and a second layer 713, which are Ag-plated layers, on the surface (both sides) of a first base layer 711 made of a sheet material containing Al. Similarly, the second conductive bonding material 72 is configured by laminating a third layer 722 and a fourth layer 723, which are Ag-plated layers, on the surface (both sides) of a second base layer 721 made of a sheet material containing Al. With this configuration, the first conductive bonding material 71 and the second conductive bonding material 72 can be easily prepared.

[0159] In the semiconductor module A1, an opening 63 is formed in the second conductive member 62. The opening 63 overlaps the main surface 201 (conductive substrate 2) in a plan view, and does not overlap each semiconductor element 10 in a plan view. With this configuration, in a molding process (a process for forming the sealing resin 8) in the manufacturing process of the semiconductor module A1, a pressing pin 911 provided on the mold 91 can be inserted into the opening 63. This allows the pressing pin 911 to press the conductive substrate 2 without interfering with the second conductive member 62, and therefore warping of the support substrate 3 to which the conductive substrate 2 is bonded can be suppressed. The warping occurs, for example, such that both outer sides of the support substrate 3 in the y direction are positioned higher than the center side in the y direction. If the support substrate 3 were to warp, there is a risk that the bonding strength between the conductive substrate 2 and the support substrate 3 may decrease. Furthermore, during molding, a part of the sealing resin 8 may be formed on the bottom surface 302 due to resin leakage, which causes poor bonding of a heat dissipation member (e.g., a heat sink) that may be bonded to the bottom surface 302. Therefore, the semiconductor module A1 has a preferable package structure for improving the bonding strength between the conductive substrate 2 and the support substrate 3 by suppressing warping of the support substrate 3, and also for suppressing leakage of the sealing resin 8 to unintended positions.

[0160] The conductive substrate 2 includes a first conductive portion 2A to which a plurality of first semiconductor elements 10A are bonded and a second conductive portion 2B to which a plurality of second semiconductor elements 10B are bonded. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction, and the first conductive portion 2A is located in the x2 direction from the second conductive portion 2B. The second conductive member 62 is connected to the plurality of second semiconductor elements 10B and the input terminals 42 and 43, and an opening 63 provided in the second conductive member 62 overlaps with the main surface 201 of the first conductive portion 2A in a plan view. With this configuration, even if the size of the second conductive member 62 in a plan view is secured to be large, when the sealing resin 8 is formed (when molding), the conductive substrate 2 can be held down by a pressing pin 911 provided in the mold 91 while avoiding interference with the second conductive member 62. By increasing the size of the second conductive member 62 in a plan view, it is possible to suppress the parasitic resistance component of the second conductive member 62 (conductive member 6) that constitutes the path of the main circuit current.

[0161] The second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to the input terminals 42, 43 arranged on opposite sides in the y direction with the input terminal 41 in between, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the second semiconductor elements 10B. The openings 63 are formed closer to the x2 direction in each of the first wiring portion 621 and the second wiring portion 622. As a result, the openings 63 are provided in the vicinity of two corners on both outer sides in the y direction of the conductive substrate 2 (first conductive portion 2A) in a plan view. Therefore, the openings 63 are provided in the vicinity of two corners on both outer sides in the y direction of the support substrate 3 that supports the conductive substrate 2 (first conductive portion 2A) in a plan view. According to this configuration, the size of the second conductive member 62 in a plan view can be secured to be relatively large, while when the sealing resin 8 is formed (molding), the pressing pins 911 provided on the die 91 can be inserted into the openings 63 to press the vicinity of the corners on both outer sides in the y direction of the conductive substrate 2 (first conductive portion 2A). As described above, warping of the support substrate 3 to which the conductive substrate 2 is bonded occurs such that both outer sides in the y direction of the support substrate 3 are positioned higher than the center side in the y direction, but according to the above configuration, warping of the support substrate 3 during molding can be effectively suppressed.

[0162] In this embodiment, the conductive member 6 (the first conductive member 61 and the second conductive member 62) is made of a metal plate material. This makes it possible to easily form the opening 63 in the second conductive member 62. Furthermore, the conductive member 6 (the first conductive member 61 and the second conductive member 62) made of a metal plate material can be easily made into various shapes and sizes, and by ensuring a sufficient joint area with other parts, the reliability of the joint with other parts can be improved.

[0163] Recesses 201a are formed in portions of main surface 201 of conductive substrate 2 (first conductive portion 2A) that overlap with each opening 63 in a plan view. Each recess 201a is a trace of a pressing force applied to main surface 201 by pressing pins 911 during molding. In this embodiment, by devising an arrangement of second conductive member 62 and openings 63 formed therein, it is possible to press conductive substrate 2 (first conductive portion 2A) at appropriate positions with pressing pins 911 during molding while avoiding interference with functional elements such as semiconductor element 10.

[0164] The sealing resin 8 has a resin void 86 that extends from the resin main surface 81 to the recess 201a. The resin void 86 is tapered, and the cross-sectional area decreases from the resin main surface 81 toward the recess 201a. Such a resin void 86 is formed during molding (when the sealing resin 8 is formed). After the molding, the surface of the recess 201a of the main surface 201 of the conductive substrate 2 is exposed from the sealing resin 8. In this embodiment, the resin void 86 is filled with a resin filling portion 88 so as to fill the resin void 86. This configuration can prevent foreign matter (including moisture) from entering the recess 201a exposed from the sealing resin 8. The semiconductor module A1 having the above configuration is preferable in terms of improving durability and reliability.

[0165] In this embodiment, each opening 63 formed in the second conductive member 62 (conductive member 6) is a through hole penetrating in the z direction. With this configuration, in the second conductive member 62 (conductive member 6) constituting the path of the main circuit current, bias in the current path due to the formation of the openings 63 is suppressed.

[0166] The semiconductor module A1 includes a conductive member 6. The conductive member 6 forms a path of a main circuit current switched by each semiconductor element 10. The conductive member 6 includes a first conductive member 61 connected to each first semiconductor element 10A and a second conductive member 62 connected to each second semiconductor element 10B. The conductive member 6 (each of the first conductive member 61 and the second conductive member 62) is made of a metal plate material. The main circuit current may have a relatively large value. In this case, suppressing the parasitic resistance component in the conductive member 6, which is the path of the main circuit current, is preferable in terms of reducing the power consumption of the semiconductor module A1. Therefore, in the semiconductor module A1, as described above, the conductive member 6 is made of a metal plate material instead of a bonding wire, thereby suppressing the parasitic resistance component in the conductive member 6. In other words, the semiconductor module A1 has a package structure preferable in terms of suppressing the parasitic resistance component.

[0167] In the semiconductor module A1, each of the first semiconductor elements 10A is rectangular in plan view, and the four corners of the first semiconductor element 10A do not overlap the second conductive member 62 in plan view. With this configuration, in the manufacturing process of the semiconductor module A1, before the process of forming the sealing resin 8, it is possible to perform a visual inspection of whether or not each of the first semiconductor elements 10A is properly bonded. That is, the semiconductor module A1 can perform a visual inspection of the bonded state of each of the first semiconductor elements 10A during the manufacturing process (for example, the state shown in FIG. 23), so it is possible to determine whether or not each of the first semiconductor elements 10A is properly bonded. For example, the distances at the four corners of the first semiconductor element 10A are measured by a laser distance measuring method, and if the difference in the measured distances at the four corners is small, it can be determined that the first semiconductor element 10A is properly bonded. Therefore, since the semiconductor module A1 can be visually inspected during the manufacturing process, it has a package structure that is preferable for improving reliability. When performing the visual inspection, it is sufficient that at least three of the four corners of the first semiconductor element 10A in a planar view can be confirmed, and therefore the three corners need only be configured not to overlap the second conductive member 62. Similarly, as shown in Fig. 5, the four corners of each second semiconductor element 10B in a planar view do not overlap the second conductive member 62, so that in the manufacturing process of the semiconductor module A1, a visual inspection can be performed to check whether each second semiconductor element 10B is properly bonded before the process of forming the sealing resin 8. The visual inspection may be an automatic visual inspection using imaging and image processing.

[0168] The second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to the input terminals 42, 43 arranged on opposite sides of the input terminal 41 in the y direction, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the multiple second semiconductor elements 10B. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. The fourth wiring portion 624 is located on the x2 direction side with respect to the third wiring portion 623, and overlaps with the multiple first semiconductor elements 10A in a plan view. The second conductive member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623 and the fourth wiring portion 624 overlaps a wide range of the main surface 201 in a plan view and has a relatively large size in a plan view. Increasing the size of the second conductive member 62 in a plan view in this manner is preferable in terms of suppressing the parasitic resistance component of the second conductive member 62 (conductive member 6) that constitutes the path of the main circuit current.

[0169] Each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in a plan view. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is an edge on the x2 direction side in a plan view, and the second side 192 is an edge on the x1 direction side in a plan view. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is an edge on the y2 direction side in a plan view, and the fourth side 194 is an edge on the y1 direction side in a plan view. Since each first semiconductor element 10A has a rectangular shape in a plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are approximately right angles in a plan view. On the other hand, the fourth wiring portion 624 (first strip portion 625) of the second conductive member 62 has a first edge 627 and a second edge 628. The first edge 627 is an edge located in the x2 direction in the fourth wiring portion 624, and is located in the x1 direction from the first side 191 in a plan view. The first edge 627 also extends in the y direction at least from the third side 193 to the fourth side 194. As a result, in a plan view, the two corners 171, 172 on the x2 direction side of each first semiconductor element 10A do not overlap the second conductive member 62. The second edge 628 is an edge located in the x1 direction in the fourth wiring portion 624 (first strip portion 625), and is located in the x2 direction from the second side 192 in a plan view. The second edge 628 also extends in the y direction at least from the third side 193 to the fourth side 194. As a result, in a plan view, two corners 173, 174 of each of the first semiconductor elements 10A on the x1 direction side do not overlap the second conductive member 62. In such a configuration, by securing an area of ​​the fourth wiring portion 624 that overlaps with each of the first semiconductor elements 10A in a plan view, the size of the second conductive member 62 in a plan view is increased, while the four corners of the first semiconductor element 10A in a plan view do not overlap the second conductive member 62. Therefore, the parasitic resistance component of the second conductive member 62 (conductive member 6) can be effectively suppressed, and a visual inspection of the bonding state of each of the first semiconductor elements 10A can be performed during the manufacture of the semiconductor module A1.

[0170] The fourth wiring portion 624 (first strip portion 625) has a plurality of convex regions 625a that protrude in the z2 direction further than other portions. Each of the convex regions 625a overlaps with each of the first semiconductor elements 10A in a plan view. The configuration in which the fourth wiring portion 624 has a plurality of convex regions 625a makes it possible to prevent the fourth wiring portion 624 from making inappropriate contact with the first conductive member 61 bonded onto the first semiconductor element 10A.

[0171] The third wiring portion 623 has multiple recessed regions 623a that protrude in the z1 direction further than other portions. Each recessed region 623a is joined to one of the multiple second semiconductor elements 10B. This configuration makes it possible to ensure a large size of the third wiring portion 623 (second conductive member 62) in a plan view while appropriately conducting the third wiring portion 623 (second conductive member 62) and the multiple second semiconductor elements 10B.

[0172] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x direction. With this configuration, it is possible to prevent the size in the y direction of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged from increasing, thereby enabling the semiconductor module A1 to be miniaturized.

[0173] The semiconductor module A1 includes a conductive substrate 2, two input terminals 41, 42 (or two input terminals 41, 43), an output terminal 44, and a conductive member 6. The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B arranged in the x direction in a plan view. A plurality of first semiconductor elements 10A are electrically connected to the first conductive portion 2A. A plurality of second semiconductor elements 10B are electrically connected to the second conductive portion 2B. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are respectively arranged at intervals along the y direction. The two input terminals 41, 42 (or the two input terminals 41, 43) are located in the x2 direction with respect to the first conductive portion 2A. The input terminal 41 is a positive electrode and is connected to the first conductive portion 2A. The input terminal 42 (or the input terminal 43) is a negative electrode. The output terminal 44 is located in the x1 direction with respect to the second conductive portion 2B. The conductive member 6 includes a first conductive member 61 connected to the multiple first semiconductor elements 10A and the second conductive portion 2B, and a second conductive member 62 connected to the multiple second semiconductor elements 10B and the input terminal 42 (or the input terminal 43). With this configuration, the path of the main circuit current switched by the multiple semiconductor elements 10 (the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B) is configured to be along the x direction in a plan view, and the symmetry axis (see the auxiliary line L1 in FIG. 5) in the planar structure of the semiconductor module A1 is configured to be along the y direction in a plan view. In other words, the symmetry axis and the path of the main circuit current are perpendicular to each other. This makes it possible to reduce the difference in the current path to the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B in the main circuit current input from the two input terminals 41, 42 (or the two input terminals 41, 43) and output from the output terminal 44. That is, the semiconductor module A1 can suppress variations in parasitic inductance components and current variations. Therefore, the semiconductor module A1 has a preferable package structure for equalizing the parasitic inductance components in the paths of the main circuit current and the amount of current to each semiconductor element 10.

[0174] The first semiconductor elements 10A and the second semiconductor elements 10B are spaced apart in the x direction. The first semiconductor elements 10A and the second semiconductor elements 10B are arranged in the y direction. Therefore, the direction in which the semiconductor elements 10 are arranged is perpendicular to the direction in which the first main circuit current or the second main circuit current flows. This prevents a difference in the length of the current path of the first main circuit current from occurring among the three first semiconductor elements 10A when multiple switching elements are connected in parallel as in this embodiment. This makes it possible to suppress a parasitic resistance component in the conductive member 6, which is the path of the main circuit current.

[0175] The region through which the first main circuit current flows and the region through which the second main circuit current flows are configured to overlap in a plan view. That is, the second conductive member 62, which connects the output terminal 44 to the first input terminal 42 and the second input terminal 43, which are negative terminals, in order to pass the second main circuit current, is disposed above the region through which the first main circuit current flows (the first conductive part 2A, the first conductive member 61, and the second conductive part 2B). The direction through which the first main circuit current flows is opposite to the direction through which the second main circuit current flows. Therefore, with the above-mentioned arrangement, the magnetic field generated by the first main circuit current and the magnetic field generated by the second main circuit current can cancel each other out, thereby reducing the inductance.

[0176] The semiconductor module A1 of the present embodiment includes two input terminals 42, 43. These input terminals 42, 43 are both negative electrodes, and sandwich the input terminal 41 in the y direction. In addition, the two input terminals 42, 43 are connected to a second conductive member 62. With this configuration, it is possible to further reduce the variation in the path of the current flowing from the output terminal 44 through each second semiconductor element 10B and the second conductive member 62 to each input terminal 42, 43.

[0177] In the semiconductor module A1, the second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to the input terminals 42, 43 arranged on opposite sides in the y direction with the input terminal 41 in between, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the second semiconductor elements 10B. The fourth wiring portion 624 is located on the x2 direction side of the third wiring portion 623, and is connected to all of the first wiring portion 621, the second wiring portion 622, and the third wiring portion 623. The second conductive member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 overlaps a wide range of the main surface 201 in a plan view, and a large size in a plan view can be ensured. With this configuration, the variation in the path of the current flowing from the output terminal 44 to the input terminals 42, 43 via the second semiconductor elements 10B and the second conductive member 62 is appropriately reduced. Therefore, the semiconductor module A1 of this embodiment is more preferable in terms of equalizing the parasitic inductance components in the path of the main circuit current (the second conductive member 62) and equalizing the amount of current to each second semiconductor element 10B.

[0178] The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622, and overlaps with a plurality of first semiconductor elements 10A in a planar view. The fourth wiring portion 624 (first strip portion 625) has a plurality of convex regions 625a protruding in the z2 direction from other portions. Each of the convex regions 625a overlaps with a corresponding one of the first semiconductor elements 10A in a planar view. This configuration makes it possible to ensure a large size of the fourth wiring portion 624 (second conductive member 62) in a planar view, while preventing the fourth wiring portion 624 from coming into inappropriate contact with the first conductive member 61 bonded onto the first semiconductor element 10A.

[0179] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x direction. With this configuration, it is possible to prevent the size in the y direction of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged from increasing, thereby enabling the semiconductor module A1 to be miniaturized.

[0180] 30 to 32 show a semiconductor module according to the second embodiment. In a semiconductor module A2 of this embodiment, the configuration of a second conductive member 62 is different from that of the semiconductor module A1 of the above embodiment.

[0181] In this embodiment, the area occupied by the fourth wiring portion 624 of the second conductive member 62 is different from the above embodiment. Specifically, the dimension in the x direction of the first strip portion 625 is larger than that of the semiconductor module A1. As shown in FIGS. 31 and 32, the position of the second edge 628 of the first strip portion 625 is located on the x1 direction side compared to the semiconductor module A1. As shown in FIG. 32, the second edge 628 is located in the x1 direction further than the second side 192 of the first semiconductor element 10A in a plan view. As a result, two corners of each first semiconductor element 10A on the x1 direction side in a plan view overlap the second conductive member 62 (first strip portion 625).

[0182] The semiconductor module A2 of this embodiment also provides the same advantageous effects as the semiconductor module A1 of the above embodiment. Moreover, in the semiconductor module A2, the size of the first strip portion 625 (second conductive member 62) of the fourth wiring portion 624 in a plan view can be made larger. This is preferable in terms of reducing the parasitic inductance component.

[0183] 33 and 34 show a semiconductor module according to the third embodiment. A semiconductor module A3 of this embodiment differs from the semiconductor module A1 of the above embodiment mainly in the configuration of the second conductive member 62.

[0184] In the semiconductor module A3, unlike the above-described embodiment, the second conductive member 62 does not have the opening 63. When manufacturing the semiconductor module A3, the die 91 used for forming (molding) the sealing resin 8 does not have the pressing pin 911. As a result, as shown in FIG. 34, the resin void portion 86 is not formed in the sealing resin 8, and the recess 201a is not formed in the main surface 201 of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B). In addition, since the resin void portion 86 is not formed in the sealing resin 8, the semiconductor module A3 of this embodiment does not have the resin filling portion 88 used to fill the resin void portion 86 in the above-described embodiment.

[0185] The semiconductor module A3 of this embodiment also provides the same advantageous effects as the semiconductor module A1 of the above embodiment.

[0186] The semiconductor module according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor module according to the present disclosure can be freely modified in various ways.

[0187] In the above embodiment, the configuration is described in which two input terminals 42, 43 (N terminals) are provided and the second conductive member 62 is connected to these input terminals 42, 43, but the present invention is not limited to this. A configuration may also be used in which only one input terminal 42 (N terminal) is provided and the second conductive member 62 is connected to the input terminal 42.

[0188] In the above embodiment, the control terminals 45 (the first control terminals 46A-46E and the second control terminals 47A-47D) are arranged to extend along the z direction, but the present invention is not limited to this. For example, the control terminals 45 may be arranged to extend along a plane (xy plane) perpendicular to the z direction.

[0189] In the above embodiment, an example was shown in which the second conductive member 62 is provided with two second strip-shaped portions 626 and two first strip-shaped portions 625, but the two second strip-shaped portions 626 and two first strip-shaped portions 625 are not necessary. However, by providing the two second strip-shaped portions 626 and the first strip-shaped portions 625, it is possible to suppress misalignment between the multiple semiconductor elements 10 and to further reduce inductance, compared to a configuration in which the two second strip-shaped portions 626 and the two first strip-shaped portions 625 are not provided.

[0190] The present disclosure includes the configurations described in the following appendices.

[0191] Appendix 1. a conductive substrate having a main surface and a back surface spaced apart from each other in a thickness direction; At least one semiconductor element electrically connected to the main surface and having a switching function; a conductive member that constitutes a path of a main circuit current that is switched by the semiconductor element; a first input terminal and a second input terminal disposed on one side of the conductive substrate in a first direction perpendicular to the thickness direction; at least one output terminal disposed on the other side of the conductive substrate in the first direction; the conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other in the first direction; the at least one semiconductor element includes a plurality of first semiconductor elements and a plurality of second semiconductor elements, the plurality of first semiconductor elements are electrically connected to the first conductive portion and spaced apart from one another in a second direction perpendicular to both the thickness direction and the first direction, the plurality of second semiconductor elements are electrically connected to the second conductive portion and spaced apart from one another in the second direction, the first input terminal is electrically connected to the first conductive portion, the second input terminal has a polarity opposite to that of the first input terminal; the output terminal is electrically connected to the second conductive portion, a semiconductor module, the conductive member including a first conductive member connected to the plurality of first semiconductor elements and the second conductive portion, and a second conductive member connected to the plurality of second semiconductor elements and the second input terminal. Appendix 2. the paths of the main circuit current include a first path of the main circuit current between the first input terminal and the output terminal, and a second path of the main circuit current between the output terminal and the second input terminal; 2. The semiconductor module according to claim 1, wherein a direction of the first main circuit current and a direction of the second main circuit current are opposite to each other. Appendix 3. A semiconductor module as described in Appendix 1 or 2, wherein a path of the main circuit current switched by the plurality of first semiconductor elements and the plurality of second semiconductor elements is configured to be along the first direction when viewed in the thickness direction. Appendix 4. 4. The semiconductor module according to claim 1, wherein the first conductive member includes a plurality of conductive portions respectively corresponding to the plurality of first semiconductor elements. Appendix 5. a third input terminal located on one side in the first direction with respect to the first semiconductor element and connected to the second conductive member, 5. The semiconductor module according to claim 1, wherein the first input terminal is disposed between the second input terminal and the third input terminal in the second direction. Appendix 6. The semiconductor module described in Appendix 5, wherein the second conductive member includes a first wiring portion connected to the second input terminal and extending in the first direction, a second wiring portion connected to the third input terminal and extending in the first direction, a third wiring portion connected to both the first wiring portion and the second wiring portion, extending in the second direction, and connected to each of the multiple second semiconductor elements, and a fourth wiring portion located on one side of the third wiring portion in the first direction and connected to all of the first wiring portion, the second wiring portion, and the third wiring portion. Appendix 7. 7. The semiconductor module according to claim 6, wherein the fourth wiring portion overlaps with the plurality of first semiconductor elements when viewed in the thickness direction. Appendix 8. The semiconductor module of claim 7, wherein the fourth wiring portion has a plurality of convex regions that protrude in the thickness direction more than other portions of the fourth wiring portion, and each convex region overlaps with a corresponding one of the plurality of first semiconductor elements when viewed in the thickness direction. Appendix 9. each of the first semiconductor elements and the second semiconductor elements has a source electrode and a drain electrode spaced apart from each other in the thickness direction; the first conductive member is connected to the source electrode of each of the first semiconductor elements; the first conductive portion is connected to the drain electrode of each first semiconductor element; the third wiring portion is connected to the source electrode of each of the second semiconductor elements; 9. The semiconductor module according to claim 6, wherein the second conductive portion is connected to the drain electrode of each second semiconductor element. Appendix 10. 10. The semiconductor module of claim 9, wherein the first semiconductor elements and the second semiconductor elements overlap each other when viewed in the first direction. Appendix 11. 11. The semiconductor module according to any one of claims 5 to 10, wherein the first input terminal, the second input terminal, and the third input terminal overlap each other when viewed in the second direction. Appendix 12. 12. The semiconductor module according to claim 1, wherein the first conductive member and the second conductive member are made of a metal plate. Appendix 13. a control terminal connected to one of the first semiconductor elements and the second semiconductor elements; 2. The semiconductor module of claim 1, wherein the control terminal is arranged on the main surface and extends along the thickness direction. Appendix 14. the first input terminal and the second input terminal each include an input-side bonding surface extending toward one side in the first direction and facing one side in the thickness direction; 14. The semiconductor module according to claim 1, wherein the output terminal extends toward the other side in the first direction and includes an output-side bonding surface facing one side in the thickness direction. Appendix 15. the first input terminal and the second input terminal each have an input-side side surface located on a periphery of the input-side joint surface when viewed in the thickness direction and facing a direction intersecting a normal to the input-side joint surface, and an input-side processing mark formed on the input-side side surface, 15. The semiconductor module of claim 14, wherein the output terminal has an output-side side surface located on the periphery of the output-side bonding surface when viewed in the thickness direction and facing a direction intersecting a normal to the output-side bonding surface, and an output-side processing mark formed on the output-side side surface. Appendix 16. 16. The semiconductor module of claim 1, further comprising a sealing resin covering at least a portion of each of the first and second conductive parts, the plurality of first semiconductor elements, the plurality of second semiconductor elements, the first conductive member, and the second conductive member. Appendix 17. The semiconductor module described in Appendix 16, wherein the sealing resin has a first resin side and a second resin side spaced apart from each other in the first direction, the second resin side is located closer to the second conductive portion than the first resin side, and the second resin side has two ends spaced apart from each other in the second direction, and a resin separation mark is formed on at least one of the ends. Appendix 18. the at least one output terminal includes a first output terminal and a second output terminal; 17. The semiconductor module according to claim 16, wherein the sealing resin has a resin side surface on which a resin separation mark is formed between the first output terminal and the second output terminal. Appendix 19. a conductive substrate having a main surface and a back surface spaced apart from each other in a thickness direction; At least one semiconductor element electrically connected to the main surface and having a switching function; a conductive member that forms a path of a main circuit current switched by the semiconductor element and is spaced apart from the main surface in the thickness direction; a first input terminal and a second input terminal disposed on one side of the conductive substrate in a first direction perpendicular to the thickness direction; an output terminal disposed on the other side of the conductive substrate in the first direction, the conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other in a first direction perpendicular to the thickness direction, the at least one semiconductor element includes a plurality of first semiconductor elements electrically connected to the first conductive portion and a plurality of second semiconductor elements electrically connected to the second conductive portion; the first semiconductor elements are spaced apart from one another along a second direction perpendicular to both the thickness direction and the first direction; The second semiconductor elements are spaced apart from one another along the second direction, the first input terminal is a positive electrode connected to the first conductive portion, the second input terminal is negative; the output terminal is connected to the second conductive portion, a semiconductor module, the conductive member including a first conductive member connected to the plurality of first semiconductor elements and the second conductive portion, and a second conductive member connected to the plurality of second semiconductor elements and the second input terminal. Appendix 20. a path of the main circuit current switched by the plurality of first semiconductor elements and the plurality of second semiconductor elements is configured to be along the first direction when viewed in the thickness direction, The semiconductor module of claim 19, wherein, when viewed in the thickness direction, the first semiconductor elements and the second semiconductor elements are arranged symmetrically with respect to an axis perpendicular to the first direction. Appendix 21. a third input terminal which is a negative electrode and is located on one side in the first direction with respect to the plurality of first semiconductor elements and to which the second conductive member is connected; 21. The semiconductor module according to claim 19, wherein the second input terminal and the third input terminal are respectively arranged on one side and the other side of the first input terminal in the second direction. Appendix 22. The semiconductor module of claim 21, wherein the second conductive member includes a first wiring portion connected to the second input terminal and extending in the first direction, a second wiring portion connected to the third input terminal and extending in the first direction, a third wiring portion connected to both the first wiring portion and the second wiring portion, extending in the second direction, and connected to each of the multiple second semiconductor elements, and a fourth wiring portion located on one side of the third wiring portion in the first direction, and connected to all of the first wiring portion, the second wiring portion, and the third wiring portion. Appendix 23. 23. The semiconductor module of claim 22, wherein the fourth wiring portion overlaps with the plurality of first semiconductor elements when viewed in the thickness direction. Appendix 24. The semiconductor module described in Appendix 23, wherein the fourth wiring portion has a plurality of convex regions protruding in the thickness direction more than other portions of the fourth wiring portion, and each convex region overlaps with a corresponding one of the plurality of first semiconductor elements when viewed in the thickness direction. Appendix 25. each of the first semiconductor elements and the second semiconductor elements has a source electrode and a drain electrode spaced apart from each other in the thickness direction; the first conductive member is connected to the source electrode of each of the first semiconductor elements; the first conductive portion is connected to the drain electrode of each first semiconductor element; the third wiring portion is connected to the source electrode of each of the second semiconductor elements; 25. The semiconductor module according to any one of claims 22 to 24, wherein the second conductive portion is connected to the drain electrode of each second semiconductor element. Appendix 26. 26. The semiconductor module of claim 25, wherein the first semiconductor elements and the second semiconductor elements overlap each other when viewed in the first direction. Appendix 27. 27. The semiconductor module according to any one of claims 21 to 26, wherein the first input terminal, the second input terminal, and the third input terminal overlap each other when viewed in the second direction. Appendix 28. 28. The semiconductor module according to claim 19, wherein the first conductive member and the second conductive member are made of a metal plate material. [Explanation of symbols]

[0192] A1, A2, A3: Semiconductor module 10: Semiconductor element 10A: First semiconductor element 10B: Second semiconductor element 101: element main surface 102: element back surface 11: First principal surface electrode (gate electrode) 12: Second principal surface electrode (source electrode) 13: third principal surface electrode 14: fourth principal surface electrode 15: Back electrode (drain electrode) 16: Fifth principal surface electrode 171,172,173,174: corner 181,182,183,184: corner 191: First side 192: Second side 193: 3rd side 194: 4th side 2: Conductive substrate 2A: First conductive part 2B: second conductive portion 201: main surface 201a: Recess 201b: Recess edge 202: Back surface 21: Base material 22: Main surface bonding layer 23: Back surface bonding layer 3: Support substrate 301: Support surface 302: Bottom surface 31: Insulating layer 32: First metal layer 32A: First part 32B: 2nd part 321: 1st bonding layer 33: Second metal layer 41: First input terminal 411: Input side joint surface 412: Input side surface 413: Tip surface 414: Lateral surface 42: Second input terminal 421: Input side joint surface 422: Input side 423: Tip surface 424: Side 43: 3rd input terminal 431: Input side joint surface 432: Input side surface 433: Tip surface 434: Lateral surface 44: Output terminal 441: Output side joint surface 442: Output side 443: Tip surface 444: Side 45: Control terminal 451: Holder 452: Metal pin 459: Conductive bonding material 46A, 46B, 46C, 46D, 46E: First control terminal 47A, 47B, 47C, 47D: Second control terminal 5: Control terminal support 51: Insulating layer 52: 1st metal layer 521: 1st part 522: Part 2 523: Part 3 524: Part 4 525: Part 5 53: Second metal layer 59: Bonding material 6: Conductive member 601: Part 1 61: first conductive member; 61h: opening 62: second conductive member 62A: first part 62B: 2nd part 621: 1st wiring part 622: Second wiring section 623: Third wiring section 623a: Concave area 623h: Opening 624: Fourth wiring section 625: First belt section 625a: Convex area 625h: Opening 626: Second band 627: First edge 628: Second edge 63: Opening 69: Conductive bonding material 71: First conductive bonding material 711: 1st base layer 712: 1st layer 713: Second layer 72: Second conductive adhesive material 721: 2nd base layer 722: 3rd layer 723: 4th layer 731: Wire 731a: First wire 731b: Second wire 732, 733, 734, 735: Wire 8: Sealing resin 81: Resin main surface 82: Resin back surface 831, 832: Resin side surface 832a: Recess 833, 834: Resin side surface 851: First protrusion 851a: First protrusion end surface 851b: Recess 851c: Inner wall surface 852: Second protrusion 86: Resin cavity 861: Resin gap edge 87: Resin part 88: Resin filling section 91: Mold 911: Presser pin

Claims

1. a conductive substrate having a main surface and a back surface spaced apart from each other in a thickness direction; At least one semiconductor element electrically connected to the main surface and having a switching function; a conductive member that constitutes a path of a main circuit current that is switched by the at least one semiconductor element; a first input terminal, a second input terminal, and a third input terminal arranged on one side of the conductive substrate in a first direction perpendicular to the thickness direction; at least one output terminal disposed on the other side of the conductive substrate in the first direction; at least one control terminal connected to the at least one semiconductor device; a control terminal support having an insulating layer and interposed between the main surface and the at least one control terminal; a sealing resin that covers at least a portion of the conductive substrate, the at least one semiconductor element, a portion of each of the first input terminal, the second input terminal, the third input terminal, and the at least one output terminal, a portion of the at least one control terminal, and a portion of the control terminal support; Equipped with the conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other in the first direction; the at least one semiconductor element includes a plurality of first semiconductor elements electrically connected to the first conductive portion and a plurality of second semiconductor elements electrically connected to the second conductive portion; the first input terminal is electrically connected to one of the first semiconductor elements and the second semiconductor elements; the second input terminal and the third input terminal are disposed on one side and the other side of the first input terminal in a second direction perpendicular to the thickness direction and the first direction, respectively, have a polarity opposite to that of the first input terminal, and are electrically connected to the other of the plurality of first semiconductor elements and the plurality of second semiconductor elements; the at least one output terminal is electrically connected to the second conductive portion; The first semiconductor elements are spaced apart from one another along the second direction, The second semiconductor elements are spaced apart from one another along the second direction, a first conductive member connected to the plurality of first semiconductor elements and the second conductive portion, and a second conductive member connected to the plurality of second semiconductor elements and the second input terminal and the third input terminal,

2. the paths of the main circuit current include a first path of the main circuit current between the first input terminal and the at least one output terminal, and a second path of the main circuit current between the at least one output terminal and the second input terminal; 2. The semiconductor module according to claim 1, wherein a direction of the first main circuit current and a direction of the second main circuit current are opposite to each other.

3. 2 . The semiconductor module according to claim 1 , wherein a path of the main circuit current switched by the plurality of first semiconductor elements and the plurality of second semiconductor elements is configured to be along the first direction when viewed in the thickness direction.

4. The semiconductor module according to claim 1 , wherein the first conductive member includes a plurality of conductive portions respectively corresponding to the plurality of first semiconductor elements.

5. each of the first semiconductor elements and the second semiconductor elements has a source electrode and a drain electrode spaced apart from each other in the thickness direction; the first conductive member is connected to the source electrode of each of the first semiconductor elements; the first conductive portion is connected to the drain electrode of each first semiconductor element; the second conductive member is connected to the source electrode of each second semiconductor element, The semiconductor module according to claim 4 , wherein the second conductive portion is connected to the drain electrode of each of the second semiconductor elements.

6. The semiconductor module according to claim 5 , wherein the plurality of first semiconductor elements and the plurality of second semiconductor elements overlap each other when viewed in the first direction.

7. The semiconductor module according to claim 5 , wherein the first input terminal, the second input terminal, and the third input terminal overlap each other when viewed in the second direction.

8. The semiconductor module according to claim 5 , wherein the first conductive member and the second conductive member are made of a metal plate material.

9. A semiconductor module as described in claim 5, wherein at least one control terminal is exposed from the sealing resin when viewed in the thickness direction.

10. each of the first input terminal, the second input terminal, and the third input terminal includes an input-side bonding surface facing one side in the thickness direction; The semiconductor module according to claim 1 , wherein the at least one output terminal includes an output-side bonding surface facing one side in the thickness direction.

11. the first input terminal, the second input terminal, and the third input terminal each have an input-side side surface that is located on a periphery of the input-side joint surface when viewed in the thickness direction and faces a direction intersecting a normal to the input-side joint surface, and an input-side processing mark formed on the input-side side surface, 11. The semiconductor module according to claim 10, wherein the at least one output terminal has an output side surface located on the periphery of the output side bonding surface when viewed in the thickness direction and facing a direction intersecting a normal to the output side bonding surface, and an output side processing mark formed on the output side side surface.

12. A semiconductor module described in any one of claims 1 to 11, wherein the sealing resin covers at least a portion of the first conductive portion, at least a portion of the second conductive portion, the multiple first semiconductor elements, the multiple second semiconductor elements, the first conductive member, and the second conductive member.

13. 13. The semiconductor module of claim 12, having a first resin side and a second resin side spaced apart from each other in the first direction, the second resin side being located closer to the second conductive portion than the first resin side, the second resin side having two ends spaced apart from each other in the second direction, and a resin separation mark formed on at least one of the ends.

14. the at least one output terminal includes a first output terminal and a second output terminal; The semiconductor module according to claim 12 , wherein the sealing resin has a resin side surface on which a resin separation mark is formed between the first output terminal and the second output terminal.

15. The at least one output terminal includes a first output terminal and a second output terminal, 12. The semiconductor module according to claim 1, wherein the first output terminal and the second output terminal are spaced apart from each other along the second direction.

16. The control terminal support has a metal layer arranged on an opposite side of the main surface with respect to the insulating layer in the thickness direction, 12. The semiconductor module according to claim 1, wherein the at least one semiconductor element and the at least one control terminal are electrically connected to each other via the metal layer.

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