Horizontal Gate-All-Around (hGAA) Nanowire and Nanoslab Transistors

Abstract

A horizontal gate-all-around device and method for fabricating the same are described. The horizontal gate-all-around device includes a doped semiconductor material between the source and drain regions of the device. The method includes doping a layer of semiconductor material between the source and drain regions of an electronic device.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly to horizontal gate-all-around device structures and methods and apparatus for forming horizontal gate-all-around device structures. [Background technology]

[0002] Transistors are key components of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to the transistor's gate width, so faster transistors generally require a larger gate width. Thus, there is a trade-off between transistor size and speed, and to address the conflicting goals of a transistor with maximum drive current and minimum size, "fin" field-effect transistors (finFETs) have been developed. FinFETs feature a fin-shaped channel region that significantly increases the size of a transistor without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, finFETs have their own drawbacks.

[0003] As transistor element feature sizes continue to shrink to achieve higher circuit density and higher performance, improved transistor element structures are needed to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor element structures include planar structures, fin field effect transistor (FinFET) structures, and horizontal gate all around (hGAA) structures. The structure of an hGAA element includes several lattice-matched channels separated in a stacked configuration with source / drain regions connecting them. The inventors believe that the hGAA structure provides good electrostatic control and may be widely adopted in complementary metal oxide semiconductor (CMOS) wafer fabrication.

[0004] The performance of logic gates is related to the properties of the materials used as well as the thickness and area of ​​the structural layers. However, challenges arise as some gate properties are tailored to accommodate device scaling. Additionally, space constraints between wires on horizontal gate-all-around (hGAA) devices limit the thickness of the gate dielectric material for I / O transistors.

[0005] State-of-the-art System on a Chip circuits require up to seven distinct threshold voltages for various circuits. This is currently achieved by either (i) doping the channel by implanting various doses into the channel followed by annealing, or (ii) modifying the work function by depositing, etching, and annealing multiple ultra-thin metal layers over the channel. The former introduces defects into the channel, while the latter is very expensive, prone to yield loss, and limited by space constraints.

[0006] Therefore, there is a need for an improved method for forming horizontal gate-all-around devices. Summary of the Invention

[0007] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device, wherein a superlattice structure including a plurality of first layers and a corresponding plurality of second layers alternating in a plurality of stacked pairs is selectively etched to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure and a plurality of layers of semiconductor material extending between source and drain regions, and the plurality of layers of semiconductor material are doped to form a doped semiconductor material layer.

[0008] Further embodiments of the present disclosure are directed to lateral gate-all-around devices that include multiple lateral layers of doped semiconductor material between source and drain regions.

[0009] A further embodiment of the present disclosure is directed to a computer readable medium having instructions stored thereon that, when executed, cause a method of forming a semiconductor device, the method including selectively etching a superlattice structure including a plurality of first layers and a corresponding plurality of second layers alternating in a plurality of stacked pairs to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure and a plurality of layers of semiconductor material extending between source and drain regions, and doping the plurality of layers of semiconductor material to form doped layers of semiconductor material.

[0010] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure, briefly summarized above, will be obtained by referring to the embodiments. Some embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure, since the present disclosure may admit of other equally effective embodiments, and therefore should not be considered as limiting the scope of the present disclosure. [Brief description of the drawings]

[0011] [Figure 1] 1 illustrates a flowchart of a method for forming a semiconductor device according to some embodiments of the present disclosure. [Figure 2A] 1 illustrates a manufacturing stage during a method of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 2B] 1 illustrates a manufacturing stage during a method of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 2C] 1 illustrates a manufacturing stage during a method of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 2D] 1 illustrates a manufacturing stage during a method of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 2E] 1 illustrates a manufacturing stage during a method of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 2F] 1 illustrates a manufacturing stage during a method of forming a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to each of the figures. The figures are not to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0013] Before describing certain example embodiments of the present disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following specification as the disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0014] As used herein and in the appended claims, the term "substrate" refers to a surface or portion of a surface on which processing is performed. It will also be appreciated by those skilled in the art that when reference is made to a substrate, it may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, when reference is made to deposition on a substrate, it may refer to both a bare substrate and a substrate on which one or more films or features have been deposited or formed.

[0015] As used herein, a "substrate" refers to any substrate on which a film treatment is performed during a manufacturing process, or any material surface formed on a substrate. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may be performed on an underlayer formed on the substrate, which is disclosed in more detail below. The term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0016] In this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0017] A transistor is a circuit component or element that is often formed on a semiconductor device. In addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, transistors are formed on the semiconductor device according to a circuit design. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is disposed over the channel region and includes a gate dielectric disposed between the gate electrode and the channel region in the substrate.

[0018] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is created by the voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), through which carriers enter the channel, the drain (D), through which carriers exit the channel, and the gate (G), which is the terminal that changes the conductivity of the channel. Traditionally, the current entering the channel at the source (S) is I S and the current entering the channel at the drain (D) is I D The drain-source voltage is V DS By applying a voltage to the gate (G), a current (i.e., I D ) can be controlled.

[0019] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). A metal-oxide-semiconductor field-effect transistor has an insulated gate, and the voltage on the insulated gate determines the conductivity of the device. This ability to change the conductivity with the amount of voltage applied is used to amplify or switch electronic signals. MOSFETs are based on the change in charge concentration due to the metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each of which is connected to a separate highly doped region separated by a body region. These regions can be either p-type or n-type, but both regions are of the same type, opposite the type of the body region. The source and drain (unlike the body) are highly doped, as indicated by the sign "+" after the doping type.

[0020] If the MOSFET is an n-channel or n-type MOS FET, the source and drain are n+ type regions and the body is a p-type region. If the MOSFET is a p-channel or p-type MOS FET, the source and drain are p+ type regions and the body is an n-type region. The source is so named because it is the source of charge carriers (electrons for an n-channel, holes for a p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0021] As used herein, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate with gates disposed on two or three sides of the channel, forming a double or triple gate structure. FinFET devices are given the collective name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0022] The term "gate all-around (GAA)" is used herein to refer to an electronic device, e.g., a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may include a nanowire or nanoslab, a bar-shaped channel, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device includes multiple vertically spaced horizontal nanowires or bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0023] In one or more embodiments, a horizontal gate-all-around (hGAA) transistor is a substrate having a top surface; a source region on an upper surface of the substrate, the source region having a source and a source contact; a drain region on an upper surface of the substrate, the drain region having a drain and a drain contact; a channel located between the source and drain, the channel having an axis substantially parallel to a top surface of the substrate; a gate surrounding a channel between the source region and the drain region; a thermal oxide layer overlying and in contact with one or more of the gate, source contact, or drain contact; a low-k dielectric layer overlying the thermal oxide layer; Includes. In one or more embodiments, the low-k dielectric layer has a thickness of less than about 5 nm.

[0024] One or more embodiments of the present disclosure are directed to a method of forming a horizontal gate-all-around device. Some embodiments advantageously provide a method of diffusing dopants into the active region to dope the channel and shift the threshold voltage (also called gate voltage). In some embodiments, the channel surface is exposed to a suitable dopant-containing gas (e.g., B2H6) followed by a suitable anneal (e.g., laser anneal at 800°C). Some embodiments advantageously provide a defect-free and simple method for forming a hGAA device. Some embodiments advantageously are not constrained by open spaces between nanowires or nanoslabs.

[0025] In some embodiments, the method of forming a hGAA device is enhanced to insert one or more processes between the wire release (etching the SiGe release layer to create space around the nanowires) and the replacement metal gate (deposition of gate dielectrics, work function metal films, and related material films). In some embodiments, the method exposes the wires to a dopant-containing gas and anneals the wafer (e.g., by laser annealing or spike annealing). Some embodiments advantageously provide an atomically clean (e.g., oxide-free) surface. In some embodiments, the doping of the channel and the resulting Vt are tuned by one or more of temperature or gas exposure.

[0026] Although embodiments of the present disclosure are described with respect to boron doping and nFETs, one skilled in the art will appreciate that the present disclosure is not limited to this type of transistor. In some embodiments, one or more methods for channel doping and threshold voltage of pFETs are disclosed using an appropriate p-type doping gas.

[0027] FIG. 1 shows a flow chart of a method 100 for forming a semiconductor device according to some embodiments of the present disclosure. The method 100 is described below with respect to FIGS. 2A-2H, which show fabrication stages of a semiconductor structure according to some embodiments of the present disclosure. The inventive method 100 may be part of a multi-step manufacturing process of a semiconductor device. Correspondingly, the method may be performed in any suitable processing chamber coupled to a cluster tool. The cluster tool may include processing chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used for fabricating semiconductor devices.

[0028] The method 100 begins at 102 by providing a substrate 200 having a top surface 202 (as shown in FIG. 2A). In some embodiments, the substrate 200 may be a bulk semiconductor substrate. The term bulk semiconductor substrate refers to a substrate composed entirely of a semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 200 may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In some embodiments, the semiconductor material may be a doped material, such as N-type doped silicon (n-Si) or P-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. In some embodiments, the substrate may be doped to provide a large amount of dopant at a first location on the surface of the substrate 200 to prevent turn-on of parasitic devices at the bottom. A superlattice structure is formed over the first location. For example, in some embodiments, the surface of the substrate is doped at about 10 18 atoms / cm 3 ~about 10 19 atoms / cm 3 The dopant density may be

[0029] At least one superlattice structure 204 is formed on the top surface 202 of the substrate 200 (as depicted in FIG. 2A). The superlattice structure 204 includes a plurality of first layers and a corresponding plurality of second layers alternating in a plurality of stacked pairs. In some embodiments, the plurality of stacked layers includes a group of silicon (Si) and silicon germanium (SiGe) and a group of indium phosphide (InP) and indium gallium phosphide (InGaP). In some embodiments, the plurality of first layers and the corresponding plurality of second layers can include any number of lattice-matched material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of first layers and the corresponding plurality of second layers include 2-50 pairs of lattice-matched materials.

[0030] Typically, parasitic elements will be present at the bottom of the superlattice structure 204. In some embodiments, implantation of dopants into the substrate is used to inhibit turn-on of the parasitic elements, as described above. In some embodiments, the substrate 200 is etched such that the bottom of the superlattice structure 204 includes portions of the substrate that are not removed, allowing the portions of the substrate to function as a bottom release layer for the superlattice structure 204.

[0031] In some embodiments, the thickness of the first layer and the second layer is in the range of about 2 nm to about 50 nm, or in the range of about 3 nm to about 20 nm, In some embodiments, the average thickness of the first layer is in the range of 0.5 to 2 times the average thickness of the second layer.

[0032] In some embodiments, dielectric material 246 is deposited on substrate 200 using conventional chemical vapor deposition methods. In some embodiments, dielectric material 246 is recessed below top surface 202 of substrate 200 such that the bottom of superlattice structure 204 is formed from substrate 200.

[0033] In some embodiments, a replacement gate structure (e.g., a dummy gate structure 208) is formed on the superlattice structure 204. The dummy gate structure 208 defines a channel region of a transistor element. The dummy gate structure 208 may be formed using any suitable conventional deposition and patterning process known in the art.

[0034] In some embodiments, sidewall spacers 210 are formed along the outer sidewalls of dummy gate structure 208. Sidewall spacers 210 in some embodiments comprise a suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, sidewall spacers 210 are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, or reduced pressure chemical vapor deposition.

[0035] In some embodiments, buried source and drain regions 232 and 234 are formed in the source and drain trenches, respectively. In some embodiments, the source region 232 is formed adjacent a first end of the superlattice structure 204, and the drain region 234 is formed adjacent an opposing second end of the superlattice structure. In the embodiment shown in FIG. 2A, one of the source region 232 or the drain region 234 is not shown on the front side of the superlattice structure 204. The other end of the superlattice structure 204 has the other of the source region 232 or the drain region 234. In some embodiments, the source region 232 and / or the drain region 234 are formed from any suitable semiconductor material, such as, but not limited to, silicon, germanium, silicon germanium, and the like. In some embodiments, the source region 232 and the drain region 234 can be formed using any suitable deposition process, such as an epitaxial deposition process.

[0036] In some embodiments, an inter-layer dielectric (ILD) layer 220 is blanket deposited over the substrate 200, the source / drain regions 232 / 234, the dummy gate structure 208, and the sidewall spacers 210. The ILD layer 220 may be deposited using conventional chemical vapor deposition methods (e.g., plasma enhanced chemical vapor deposition and reduced pressure chemical vapor deposition). In one embodiment, the ILD layer 220 is formed from any well-known dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. The ILD layer 220 is then polished back using conventional chemical mechanical planarization methods to expose the top of the dummy gate structure 208. In some embodiments, the ILD layer 220 is polished back to expose the top of the dummy gate structure 208 and the top of the sidewall spacers 210.

[0037] In the process 104, the dummy gate structure 208 is removed to expose the channel region 214 of the superlattice structure 204, as shown in FIG. 2B. The ILD layer 220 protects the source / drain regions 232 / 234 while the dummy gate structure 208 is removed. The dummy gate structure 208 may be removed using conventional etching methods, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 208 comprises polysilicon, and the dummy gate structure is removed by a selective etching process. In some embodiments, the dummy gate structure 208 comprises polysilicon, and the superlattice structure 204 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0038] In the process 106, the exfoliation layer 226 between the semiconductor material layers 224 in the superlattice structure 204 is selectively etched as shown in FIG. 2C. For example, if the superlattice structure 204 is composed of a silicon layer and a silicon germanium layer, the silicon germanium is selectively etched to form the channel nanowires 240. The exfoliation layer 226, e.g., silicon germanium, can be removed using any known etchant that is selective to the semiconductor material layer 224, where the etchant etches the exfoliation layer 226 at a significantly faster rate than the semiconductor material layer 224. In some embodiments, a selective dry etching or wet etching process can be used. In some embodiments, if the semiconductor material layer 224 is silicon and the exfoliation layer 226 is silicon germanium, the silicon germanium layer can be selectively removed using wet etchants such as, but not limited to, a carboxylic acid / nitric acid / HF solution and a citric acid / nitric acid / HF solution. Once the release layer 226 is removed, voids 228 remain between the layers of semiconductor material 224. The voids 228 between the layers of semiconductor material 224 are between about 3 nm and about 20 nm thick. The remaining layers of semiconductor material 224 form a vertical array of channel nanowires 240 coupled to source / drain regions 232 / 234. The channel nanowires 240 run parallel to the top surface 202 of the substrate 200 and are aligned with each other to form a single row of channel nanowires 240. The formation of the source and drain regions 232, 234, as well as the formation of an optional lateral etch stop layer (not shown), advantageously provides self-alignment and structural integrity in the formation of the channel structure.

[0039] In process 108, as shown in FIG. 2D, the exposed semiconductor material layer 224 in the channel region 214 is exposed to one or more doping processes to form a doped semiconductor material layer 245. In some embodiments, doping the exposed semiconductor material layer 224 is performed by exposing the semiconductor material layer 224 to a dopant gas. The dopant gas can be any suitable gas known to one of ordinary skill in the art that can react with the semiconductor material layer 224. In some embodiments, the dopant is an n-type dopant. In some embodiments, the dopant is a p-type dopant. In some embodiments, the dopant is selected from one or more of boron (B), aluminum (Al), indium (In), phosphorus (P), gallium (Ga), arsenic (As), nitrogen (N), or antimony (Sb). In some embodiments, the dopant gas includes B2H6. In some embodiments, the dopant gas consists essentially of B2H6. As used in this manner, the phrase "consists essentially of" means that the sum of the active dopant species is greater than or equal to about 95%, 98%, 99%, or 99.5% of the total doping species, excluding, for example, diluent and / or carrier gases that remain inert with respect to the semiconductor material layer 224 or other gaseous species.

[0040] In some embodiments, one or more of the doping processes include an annealing process. In one or more embodiments, by exposing the semiconductor material layer 224 to a dopant gas, a concentration gradient of the dopant is formed such that the dopant concentration at the outer edge of the doped semiconductor material layer 245 is higher than the concentration at the inner portion of the doped semiconductor material layer 245. In some embodiments, the dopant concentration remains non-uniform after annealing. Without being bound to any particular theory of operation, it is believed that the degree of dopant uniformity affects the gate voltage to turn on the device or the current carrying ability of the semiconductor portion. In some embodiments, the dopant concentration gradient is controlled to drop by an order of magnitude over the outermost 0.5 nm, 0.75 nm, 1 nm, 1.25 nm, 1.5 nm, 1.75 nm, or 2 nm.

[0041] In some embodiments, annealing causes the dopant concentration in doped semiconductor material layer 245 to become uniform or more uniformly distributed throughout the thickness of doped semiconductor material layer 245. In some embodiments, doped semiconductor material layer 245 has a dopant concentration that is within 50%, 60%, 70%, 80%, 90%, or 95% of the average dopant concentration at any given distance from the surface of the layer.

[0042] In some embodiments, the total dopant concentration in any of the doped semiconductor material layers 245 is about 10 17 ~10 21 atoms / cm 3 In some embodiments, the total dopant concentration in any of the doped semiconductor material layers 245 is in the range of about 10 18 ~10 19 atoms / cm 3 In some embodiments, the dopant is in the range of about 10 19 atoms / cm 3 The dopant concentration is 0.01 to 0.15.

[0043] Annealing of doped semiconductor material layer 245 may be performed by any suitable annealing process and conditions known to one of skill in the art, in some embodiments, the annealing includes one or more of a spike anneal or a laser anneal.

[0044] Process 110 of method 100 represents one or more post-doping processes according to some embodiments. The one or more post-doping processes may be performed by any process known to one of skill in the art to complete the hGAA device. With reference to Figures 2E and 2F, in some embodiments, an oxide layer 252 is formed or grown on the doped semiconductor material layer 245. The oxide layer 252 may be any suitable oxide formed by any suitable technique known to one of skill in the art.

[0045] In the illustrated embodiment, a high-k dielectric 254 is formed on the oxide layer 252. The high-k dielectric 254 may be any suitable high-k dielectric material deposited by any suitable deposition technique known to one of skill in the art. In some embodiments, the high-k dielectric 254 comprises hafnium oxide. In some embodiments, a conductive material 256, such as titanium nitride, tungsten, cobalt, aluminum, or the like, is present on the high-k dielectric 254. The conductive material 256 is formed using any suitable deposition process, such as atomic layer deposition (ALD), to ensure the formation of a layer having a uniform thickness around each doped semiconductor material layer 245.

[0046] In some embodiments, a gate electrode 242 is formed on the substrate 200 and surrounds each of the doped semiconductor material layers 245. The gate electrode 242 may be formed from any suitable gate electrode material known in the art. The gate electrode material is deposited using any suitable deposition process, such as atomic layer deposition (ALD), to ensure that the gate electrode 242 is formed around and between each of the doped semiconductor material layers 245. The resulting device formed using the methods described herein is a horizontal gate-all-around device according to an embodiment of the present disclosure. Some embodiments of the present disclosure are directed to a horizontal gate-all-around device that includes the doped semiconductor material layer 245 as a nanowire or nanosheet in a channel between a source region and a drain region.

[0047] Some embodiments are directed to a semiconductor device including a horizontal gate-all-around device having a gate voltage of about 0.400V or more. In some embodiments, the gate voltage of the device is about 0.425V or more, i.e., 0.450V. In some embodiments, the gate voltage required to turn on the device is about 140% or more of the gate voltage required to turn on a similar device without the dopant. In some embodiments, the gate voltage required to turn on the device is within a range of 1-2 times the gate voltage to turn on a similar device without the dopant. As used in this manner, a "similar device" is prepared in the same manner as the device of interest, without the doping process.

[0048] References throughout this specification to "one embodiment," "certain embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0049] Although the disclosure of this specification has been described with reference to specific embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device including a horizontal gate-all-around device, comprising: selectively etching a superlattice structure including a plurality of first layers and a corresponding plurality of second layers alternating in a plurality of stacked pairs to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure and a plurality of layers of semiconductor material extending between source and drain regions; doping the plurality of layers of semiconductor material with a dopant-containing gas by exposing the plurality of layers of semiconductor material to a dopant gas source to form a doped layer of semiconductor material, the dopant gas source forming a surface concentration of dopant on the layers of semiconductor material; exposing the layer of semiconductor material containing the surface concentration of dopant to an annealing environment to uniformize the concentration of dopant throughout a thickness of the layer of semiconductor material; A method comprising:

2. The method of claim 1 , wherein the annealing environment has a temperature of about 750° C. or greater.

3. 3. The method of claim 2, wherein the annealing is performed for about 5 seconds or less.

4. The concentration of the dopant through the thickness of the semiconductor material layer is about 10 １７ atoms / cm ３ ~about 10 ２１ atoms / cm ３ The method of claim 3, wherein the range is:

5. The dopant is about 10 １９ atoms / cm ３ The method of claim 4, comprising:

6. 5. The method of claim 4, wherein the semiconductor device comprises a horizontal gate-all-around device having a gate voltage of about 0.400V or greater.

7. 7. The method of claim 6, wherein the gate voltage required to turn on the device is greater than or equal to about 140% of the gate voltage required to turn on a device that does not contain the dopant.

8. 7. The method of claim 6, wherein the gate voltage required to turn on the device is within 1 to 2 times the gate voltage to turn on a device that does not contain the dopant.

9. The method of claim 1 , further comprising forming the superlattice structure on an upper surface of a substrate.

10. 10. The method of claim 9, further comprising forming the source region adjacent a first end of the superlattice structure and the drain region adjacent an opposing second end of the superlattice structure.

11. 2. The method of claim 1 , wherein the first layer comprises at least one group III-V material and the second layer comprises at least one group III-V material, the first layer and the second layer comprising different materials.

12. The method of claim 1 , wherein the first layer comprises silicon germanium (SiGe) and the second layer comprises silicon (Si).

13. 13. The method of claim 12, wherein selectively etching the superlattice structure comprises etching the first layer comprising silicon germanium (SiGe) and leaving the second layer comprising silicon (Si).

14. The method of claim 1 , wherein the first layer and the second layer each have a thickness of about 3 nm to about 20 nm.

15. 1. A computer readable medium having instructions stored thereon that, when executed by a semiconductor manufacturing equipment, cause a method of forming a semiconductor device including a horizontal gate-all-around device, the computer readable medium comprising: The method further comprising: selectively etching a superlattice structure including a plurality of first layers and a corresponding plurality of second layers alternating in a plurality of stacked pairs to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure and a plurality of layers of semiconductor material extending between source and drain regions; doping the plurality of layers of semiconductor material with a dopant-containing gas by exposing the plurality of layers of semiconductor material to a dopant gas source to form a doped layer of semiconductor material, the dopant gas source forming a surface concentration of dopant on the layers of semiconductor material; exposing the layer of semiconductor material containing the surface concentration of dopant to an annealing environment to uniformize the concentration of dopant throughout a thickness of the layer of semiconductor material; 13. A computer readable medium comprising:

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