Glass dielectric layer including patterning

Abstract

Embodiments of this disclosure may relate to systems, apparatus, and / or processes relating as a whole to a manufacturing process flow for packages comprising one or more glass layers, including conductive traces, RDLs, and patterning features such as vias within the package. In embodiments, the package may include a glass layer having a first face and a second face opposite to the first face, wherein the glass layer is a dielectric layer. The package may also include another layer bonded to the first face of the glass layer and a pattern on the second face of the glass layer that accepts a deposited material into at least a portion of the pattern.

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate generally to the field of package assemblies, and more particularly to package assemblies that include a dielectric layer. [Background technology]

[0002] The continuing reduction in final product size of portable electronic devices such as smart phones and ultrabooks is the driving force for the development of reduced size systems in package components. [Brief description of the drawings]

[0003] [Figure 1A] 1A-1D illustrate an example of a package assembly using a glass dielectric layer including patterning at various stages of a manufacturing process, according to an embodiment. [Figure 1B] 1A-1D illustrate an example of a package assembly using a glass dielectric layer including patterning at various stages of a manufacturing process, according to an embodiment. [Figure 1C] 1A-1D illustrate an example of a package assembly using a glass dielectric layer including patterning at various stages of a manufacturing process, according to an embodiment. [Figure 1D] 1A-1D illustrate an example of a package assembly using a glass dielectric layer including patterning at various stages of a manufacturing process, according to an embodiment. [Figure 1E] 1A-1D illustrate an example of a package assembly using a glass dielectric layer including patterning at various stages of a manufacturing process, according to an embodiment. [Diagram 2] FIG. 2 is an example of a top view showing a glass layer of a package including patterning, according to an embodiment. [Diagram 3] FIG. 2 is a three-dimensional view of an example showing a package having two glass dielectric layers including patterning, according to an embodiment. [Figure 4]FIG. 2 illustrates an example package with a silicon bridge die embedded in glass with a redistribution layer (RDL) at the mid-level interconnect (MLI) plane, according to an embodiment. [Diagram 5] FIG. 2 illustrates an example package with a silicon bridge die embedded in glass with an RDL on the first level interconnect (FLI) side, according to an embodiment. [Figure 6] FIG. 1 illustrates an example package having an RDL on a glass layer implemented as an organic-substrate hybrid architecture, according to an embodiment. [Figure 7] 1A-1C illustrate an example process for creating a glass dielectric layer with patterning in a package, according to an embodiment. [Figure 8] FIG. 2 is a schematic diagram illustrating a computing device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004]

[0004] Embodiments of the present disclosure may generally relate to systems, apparatus, and / or processes directed to a manufacturing process flow for a package including one or more glass layers that includes patterning features such as conductive traces, RDLs, and vias within the package. In an embodiment, the package may include a glass layer having a first side and a second side opposite the first side, the glass layer being a dielectric layer. The package may include another layer coupled to the first side of the glass layer and a pattern on the second side of the glass layer that receives a deposition material into at least a portion of the pattern.

[0005] Higher speed and bandwidth requirements for portable and high performance applications have driven the shrinking of the bump pitch (BP) of flip chip interconnects to levels below 30 μm. As a result, thermo-compression bonding (TCB) processes require tighter solder bump height variation targets, and substrate thickness variation targets within the die area. The substrate thickness variation target in the die area may be 2 μm or less.

[0006] Additionally, increased functionality of the substrate, such as enabling connections between dies through Embedded Multi-Die Interconnect Bridge (EMIB®) architectures, can make meeting substrate thickness variation targets more difficult. Compared to traditional monolithic organic substrate processes, encapsulating dielectric materials on silicon bridge dies is known to increase the risks of planarity control, resulting in even more difficult substrate thickness variation control.

[0007] Glass is known to have flatness benefits, and its thickness variation can be less than 2 microns within the die area. Traditionally, glass may be used as a patch to connect the base substrate and the die, for example, using through-glass vias (TGVs) or TGVs with embedded bridge dies. However, TGVs or TGVs with embedded bridge dies may be limited to legacy implementations with layer counts and design rules, since they cannot create multiple RDLs. Alternatively, glass may be used as a temporary carrier, allowing layers with less thickness variation to be stacked and patterned on top. However, the benefit of less thickness variation may be reduced after the glass carrier is peeled off.

[0008] To maximize the benefits of glass in substrate and packaging applications, one or more permanent glass layers with RDL capabilities may be implemented in organic non-EMIB or EMIB architectures. The embodiments are not limited to the two architectures mentioned above. The embodiments may include any substrate and packaging application that requires control of thickness variation.

[0009] The embodiments described herein may be directed to apparatus, systems, and processes that create patterns, e.g., traces and vias, in designated glass layers in a package to provide patterning and fan-out capabilities using the patterns as RDL layers and through-glass vias. These embodiments allow package components to maintain the flatness benefits of glass. Additionally, substrates and packages that include glass with RDL capabilities as part of their structure provide architectural design advantages. These advantages may be achieved by allowing flexible design rules that address yield challenges of the substrate and assembly process.

[0010] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, in which like numerals designate like parts throughout and which show by way of example embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0011] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0012] The descriptions may use perspective descriptions, such as, for example, top / bottom, inside / outside, above / below, etc. Such descriptions are used merely for ease of discussion and are not intended to limit application of the embodiments described herein to any particular orientation.

[0013] The description may use the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments. Additionally, terms such as "comprising," "including," and "having" are synonymous when used with respect to embodiments of the present disclosure.

[0014] The term "coupled to," along with its derivatives, may be used herein. "Coupled" may include one or more of the following: "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact.

[0015] Various operations may be described in sequence as multiple discrete operations in a manner that is most helpful in understanding the claimed subject matter, however, the order of description should not be construed as to imply that these operations are necessarily order dependent.

[0016] As used herein, the term "module" may refer to, be a part of, or include an ASIC, electronic circuitry, processors (shared, dedicated, or groups) and / or memories (shared, dedicated, or groups) executing one or more software or firmware programs, combinatorial logic circuitry, and / or other suitable components that provide the described functionality.

[0017] Various figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are shown as examples of relative positions of layers of different package assemblies. The layers are for illustrative purposes and are not drawn to scale. Thus, the relative sizes of layers should not be inferred from the drawings, and sizes, thicknesses, or dimensions may be inferred only for some embodiments specifically indicated or discussed.

[0018] 1A-1E show an example of a package assembly using a glass dielectric layer including patterning at various stages of a manufacturing process, according to an embodiment. FIG. 1A shows a package 100a at a substrate stage where a glass layer 104 is bonded to a base substrate 102. In an embodiment, the glass layer 104 may be laminated using a dielectric adhesive 106, which may be used to bond or laminate the glass layer 104 to the base substrate 102. In an embodiment, the glass layer 104 may be 40 μm thick. In an embodiment, the glass layer 104 may be 35 μm thick. The adhesive 106 may include Ajinomoto Build-Up Film (ABF) or a similar film. In an embodiment, the adhesive 106 may be permanently bonded after curing. In an embodiment, the adhesive 106 may be a dielectric adhesive. In an embodiment, the adhesive may be 5 μm thick. The base substrate 102 may be a substrate, a semi-finished substrate, a package core, or some other package component. In an embodiment, the substrate 102 may be a carrier substrate that is subsequently peeled off.

[0019] FIG. 1B shows the package 100b at the substrate stage where through-holes 108 may be patterned in the glass layer 104. In an embodiment, this patterning may be performed using laser etching, dry etching, wet etching, or some combination thereof. In an embodiment, the through-holes 108 may extend through the dielectric adhesive 106 to and / or into the base substrate 102. In an embodiment, if a laser or dry etching technique is used, the adhesive 106 may also be drilled or etched. In an embodiment, if a wet etching technique is used, additional laser drilling may be used to open the through-holes 108 further to the substrate 102, depending on the chemical resistance of the dielectric. A desmear technique may then be used to remove debris and clean the through-holes 108.

[0020] FIG. 1C shows package 100c at the substrate stage where glass surface patterning 110 is applied to glass layer 104. In an embodiment, glass surface patterning 110 may also be referred to as surface trench patterning. Laser etching, dry etching, or chemical etching processes may be used in conjunction with lithographic patterning. In an embodiment, surface trench patterning may be etched into the surface of glass 104 to a depth of up to 15 μm to accommodate buried copper traces as described further below. In an embodiment, glass surface patterning 110 may be bonded or overlapped through through holes 108. In an embodiment, glass surface patterning 110 may be at various depths within glass layer 104 and may be a layout pattern that matches traces and / or RDL patterns through the surface. Note: A view of an example embodiment from above is shown in diagram 200 of FIG. 2.

[0021] FIG. 1D shows package 100d at the substrate stage with the patterning including glass through holes 108 at least partially filled with material creating vias 113 and surface patterning 110 at least partially filled with material creating RDL 112. In an embodiment, the material may be a conductive material such as copper, copper alloy, or aluminum alloy. In an embodiment, the material may be placed using a sputtered titanium / copper seeding process by using a seed layer deposition. After the seed layer is formed, an electrolytic plating process may be used or a lithographic patterning process may be used to fill through holes 108 and surface patterning 110. In an embodiment, a plating process may be used. In an embodiment, through holes 108 may include a solid material to create solid vias 113 or in an embodiment, a sputtering process may be used to deposit material around the edges of through holes 108 to create hollow vias 113 that remain conductive. In an embodiment, the top of the glass layer 104a may be planarized following the material filling described above to obtain a flat surface. This planarization is important because subsequent glass sheets may not match the topological features.

[0022] 1E shows the package 100e at the substrate stage where the second layer 114 is placed on the glass layer 104. In an embodiment, the second layer 114 may include a second glass layer 118 that is bonded to the glass layer 104 using an adhesive 116. In an embodiment, the second glass layer 118 may include patterning that is used to create vias 121 and RDLs 120 using techniques such as those described above. Additionally, the vias 121 and RDLs 120 may use a pattern that, when filled with material, electrically couples them to the RDLs 112 and vias 113 of the glass layer 104. In this manner, multiple RDL layers 112, 120 may be formed in the package.

[0023] FIG 2 illustrates an example of a top view of a glass layer of a package including patterning, according to an embodiment. Diagram 200 illustrates a top view of glass layer 204, which may be similar to glass layer 104 of FIG 1A. Through glass electrodes 213, which may be similar to vias 113 of FIG 1D, and traces 212, which may be similar to traces 112 of FIG 1D, are created in glass layer 204, as shown. In an embodiment, traces 212 may include pads 212a, which may be used to connect to adjacent layers of the package.

[0024] FIG. 3 shows a three-dimensional view of an example of a package with two glass dielectric layers including patterning, according to an embodiment. Diagram 300 shows a three-dimensional view of two RDL layers using glass as a dielectric. A substrate 302, which may be similar to substrate 102 of FIG. 1A, may be bonded to a first glass layer 304 using adhesive 306, which may be similar to adhesive 106 and glass layer 104 of FIG. 1A. Within the first glass layer 304 may be vias 313 and RDL 312, which may be similar to vias 113 and traces 112 (RDL) of FIG. 1D.

[0025] Second glass layer 318 and adhesive 316, which may be similar to second glass layer 118 and adhesive 116 of Figure 1E, may be coupled to first glass layer 304. RDL 312 of first glass layer 304 may be electrically coupled to via 321 and RDL 320 in second glass layer 318, which may be similar to via 121 and RDL 120 of Figure 1E. In an embodiment, package 300 may be manufactured using one or more techniques such as those described above.

[0026] FIG. 4 illustrates an example of a package with a silicon bridge die embedded in glass with an RDL at the MLI side, according to an embodiment. Diagram 400 illustrates an example of a multi-layer glass RDL implementation incorporating an EMIB architecture. An EMIB die 425 is bonded to an organic dielectric layer 422 and electrically coupled to an RDL 424 on top of the organic dielectric layer 422 through pads 428 through vias 430. In an embodiment, the EMIB die 425 may be at least partially surrounded by a dielectric layer 426 or by some other material. The RDL 424 is further electrically coupled using a series of vias 421, which may be similar to vias 321, 313 of FIG. 3, that extend through multiple glass layers 418a, 418b, 418c to a bottom surface 419 of the package. This may correspond to the MLI side of the package. In an embodiment, the pads 428, vias 430, RDL 424, and vias 421 may comprise copper or a copper alloy. In an embodiment, glass layers 418b, 418c below the EMIB die 425 provide insulation and rigid support.

[0027] FIG. 5 illustrates an example of a package with a silicon bridge die embedded in glass with an RDL on the FLI side, according to an embodiment. Diagram 500 illustrates another example of a multi-layer glass RDL package incorporating an EMIB architecture. An EMIB die 525 may be electrically coupled from a pad 528 through a series of vias 530 and an intermediate RDL 523 to an FLI RDL 524, which may be similar to the RDL 424 of FIG. 4. The FLI RDL 524 may then be electrically coupled to the bottom 519 of the package through vias 521 through various glass layers 518a, 518b, 518c. In an embodiment, the pads 528, vias 530, intermediate RDL 523, FLI RDL 524, and vias 521 may comprise copper or a copper alloy. In an embodiment, the glass RDL technology may also be applied to through glass via patches with and without die embedding, which may be similar to diagram 400 of FIG. 4 and diagram 500 of FIG. 5.

[0028] FIG. 6 shows an example of a package with RDL on glass layer implemented as an organic-substrate hybrid architecture, according to an embodiment. Diagram 600 shows how glass RDL technology may be selectively applied to non-EMIB monolithic substrates. For example, a hybrid glass RDL layer with organic substrate may be fabricated, and the glass layer may be inserted at any layer of the substrate. Diagram 600 shows an example of two glass RDLs in the two top layers below the solder resist of the substrate, which may provide low substrate thickness variation characteristics.

[0029] The organic portion 634 of the package 600 may be electrically coupled to a first glass layer 618b, which includes a via 613 that electrically couples with the organic portion 634 of the package 600. The via 613 couples with the RDL 612 of the first layer 618b and may be electrically coupled with the via 613 of the second glass layer 618a. The glass layers 618a, 618b are coupled with an adhesive layer 606, sometimes also referred to as a dielectric adhesive. The via 613 electrically couples with the RDL layer 612 of the second glass layer 618a, which is in turn electrically coupled to solder 632 embedded in another organic layer 630. In an embodiment, the organic layer 630 may be a solder resist material.

[0030] 7 illustrates an example of a process for creating a glass dielectric layer including patterning in a package, according to an embodiment. Process 700 may be performed by one or more elements, techniques, or systems that may be found with respect to FIGS. 1A-6.

[0031] At block 702, the process may include bonding a first side of a glass layer having a second side opposite the first side to another layer. The glass layer may be similar to glass layer 104 of Figures 1A-1E, glass layer 204 of Figure 2, glass layer 304 of Figure 3, glass layers 418a, 418b, 418c of Figure 4, glass layers 518a, 518b, 518c of Figure 5, or glass layers 618a, 618b of Figure 6. The other layer may be similar to substrate 102 or adhesive layer 106 of Figures 1A-1E.

[0032] At block 704, the process may further include patterning the second surface of the glass layer to form a patterned structure. The patterning process may include drilling holes, laser drilling holes, dry etching, or wet etching, as described above. The patterned structure may be similar to the through-holes 108 and glass surface patterning 110 of Figures 1B-1C.

[0033] At block 706, the process may further include plating the second surface of the glass layer with a material, the material being contained within at least a portion of the patterned structure. The material may be a conductive material, such as copper or a copper alloy, as described above. The material plated into the patterned structure may take a form similar to RDL 112, 120 or via 113, 121 of Figures 1D-1E, trace 212, pad 212a, or via 213 of Figure 2, RDL 312, 320 or via 313, 321 of Figure 3, via 421 of Figure 4, RDL 524, 523, or via 521 of Figure 5, or RDL 612 or via 613 of Figure 6.

[0034] FIG. 8 is a schematic diagram of a computing device according to an embodiment. The computer system 800 (also referred to as electronic system 800) as shown may embody a glass dielectric layer including patterning according to any of the disclosed embodiments and their equivalents as described in this disclosure. The computer system 800 may be a portable device such as a netbook computer. The computer system 800 may be a portable device such as a wireless smartphone. The computer system 800 may be a desktop computer. The computer system 800 may be a handheld reader. The computer system 800 may be a server system. The computer system 800 may be a supercomputer or a high performance computing system.

[0035] In one embodiment, electronic system 800 is a computer system that includes a system bus 820 that electrically couples various components of electronic system 800. System bus 820 is a single bus or any combination of buses, according to various embodiments. Electronic system 800 includes a voltage source 830 that provides power to integrated circuit 810. In some embodiments, voltage source 830 supplies current to integrated circuit 810 through system bus 820.

[0036] The integrated circuit 810 is electrically coupled to the system bus 820 and includes any circuit or combination of circuits according to an embodiment. In one embodiment, the integrated circuit 810 includes a processor 812, which can be of any type. As used herein, the processor 812 may refer to any type of circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In one embodiment, the processor 812 includes or is coupled with a glass dielectric layer including patterning, as disclosed herein. In one embodiment, an embodiment of SRAM is found in the memory cache of the processor. Other types of circuits that can be included in the integrated circuit 810 are custom circuits or application specific integrated circuits (ASICs), such as communication circuits 814 for use in wireless devices such as cellular phones, smartphones, pagers, portable computers, two-way radios, and similar electronic systems, or communication circuits for servers. In one embodiment, the integrated circuit 810 includes on-die memory 816, such as static random access memory (SRAM). In one embodiment, the integrated circuit 810 includes embedded on-die memory 816, such as embedded dynamic random access memory (eDRAM).

[0037] In one embodiment, integrated circuit 810 is complemented by a subsequent integrated circuit 811. A useful embodiment includes dual processors 813 and dual communication circuits 815 and dual on-die memory 817, such as SRAM. In one embodiment, dual integrated circuit 810 includes embedded on-die memory 817, such as eDRAM.

[0038] In one embodiment, electronic system 800 also includes external memory 840, which in turn may include one or more memory elements suitable for a particular application, such as main memory 842 in the form of RAM, one or more hard drives 844, and / or one or more drives handling removable media 846, such as diskettes, compact discs (CDs), digital versatile discs (DVDs), flash memory drives, and other removable media known in the art. External memory 840 may also be embedded memory 848, such as a first die in a die stack, according to one embodiment.

[0039] In one embodiment, electronic system 800 also includes a display device 850, an audio output 860. In one embodiment, electronic system 800 includes an input device 870, such as a controller, which may be a keyboard, a mouse, a trackball, a game controller, a microphone, a voice recognition device, or any other input device that inputs information into electronic system 800. In one embodiment, input device 870 is a camera. In one embodiment, input device 870 is a digital recording device. In one embodiment, input device 870 is a camera and a digital recording device.

[0040] As shown herein, the integrated circuit 810 can be implemented in many different embodiments, including one or more methods of making a package substrate having a glass dielectric layer with patterning, electronic systems, computer systems, integrated circuits, and electronic assemblies including a package substrate having a glass dielectric layer with patterning, according to any of the disclosed embodiments as described herein in various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequences of operations can all be modified to suit specific I / O coupling requirements, including array contact numbers, array contact configurations for a microelectronic die embedded in a processor mounting substrate, according to any of the disclosed embodiments of a package substrate having a glass dielectric layer with patterning, according to any of the disclosed embodiments and their equivalents. An underlying substrate may be included, as represented by the dashed line in FIG. 8. Passive devices may also be included, as also shown in FIG. 8.

[0041] Working Example The following paragraphs describe examples of various embodiments.

[0042] Example 1 may be a package comprising a glass layer having a first surface and a second surface opposite the first surface, the glass layer being a dielectric layer, another layer coupled to the first surface of the glass layer, and a pattern on the second surface of the glass layer that receives a deposition material into at least a portion of the pattern.

[0043] Example 2 may include the package of Example 1, where the pattern includes traces etched into the glass or through-glass vias.

[0044] Example 3 may include the package of example 2, where the traces etched into the glass provide a redistribution layer (RDL).

[0045] Example 4 may include the package of example 3, where the RDL includes a fanout.

[0046] Example 5 may include the package of Example 1, where the deposited material includes copper or a copper alloy, or where the deposited material includes a seed layer.

[0047] Example 6 may include the package of Example 1, where the additional layer is selected from the group consisting of a substrate, an adhesive layer, or another glass layer.

[0048] Example 7 may include any one of the packages of Examples 1-6, further comprising: a second glass layer having a first surface and a second surface opposite the first surface, the glass layer being a first glass layer, the deposition material being a first deposition material, the second glass layer having a first surface and a second surface opposite the first surface, the first surface bonded to the second surface of the first glass layer; and a pattern on the second surface of the glass layer that receives the second deposition material in at least a portion of the pattern.

[0049] Example 8 may include the package of Example 7, where the other layer is a first other layer, and further includes a second other layer between the first surface of the second glass layer and the second surface of the first glass layer.

[0050] Example 9 may include the package of Example 7, further comprising a first deposition material and a second deposition material, wherein the first deposition material and the second deposition material are conductive or electrically coupled.

[0051] Example 10 may include the package of example 9, where the first deposition material and the second deposition material are different materials.

[0052] Example 11 may be a method comprising bonding a first surface of a glass layer having a second surface opposite the first surface to another layer, patterning the second surface of the glass layer to form a patterned structure, and plating the second surface of the glass layer with a material that is included within at least a portion of the patterned structure.

[0053] Example 12 may include the method of example 11, where patterning the second side of the glass layer further includes etching traces on the second side of the glass layer or drilling vias through the glass layer.

[0054] Example 13 may include the method of example 12, wherein the etched trace provides an RDL or the via provides an electrical connection between the first side of the glass layer and the second side of the glass layer.

[0055] Example 14 may include the method of example 11, wherein the material includes copper or a copper alloy.

[0056] Example 15 may include the method of any one of Examples 11-14, further comprising bonding a first side of a second glass layer, the second glass layer having a first side and a second side opposite the first side, to a second side of the first glass layer, where the glass layer is a first glass layer, the deposition material is a first deposition material, and the patterned structure is a first patterned structure, the second side of the second glass layer having a first side and a second side opposite the first side, patterning the second side of the second glass layer to create a second patterned structure, and plating the second side of the second glass layer with the second deposition material contained within at least a portion of the second patterned structure.

[0057] Example 16 may include the method of Example 15, where the other layer is a first dielectric layer, and the step of bonding a first surface of a second glass layer having a first surface and a second surface opposite the first surface to the second surface of the first glass layer further includes bonding the first surface of the second glass layer to the second dielectric layer and bonding the second surface of the first glass layer to the second dielectric layer.

[0058] Example 17 may include the method of example 11, further comprising bonding the dielectric layer to a substrate before bonding the first side of the glass layer to the dielectric layer.

[0059] Example 18 may be a system including a circuit board and a package coupled to the circuit board, the package having a glass layer having a first side and a second side opposite the first side, a dielectric layer coupled to the first side of the glass layer, a pattern on the second side of the glass layer, and deposited material within at least a portion of the pattern.

[0060] Example 19 may include the system of example 18, where the pattern includes traces etched into the glass that provide RDLs, fan-outs, or through-glass vias.

[0061] Example 20 may include the system of any one of Examples 18-19, wherein the dielectric layer is coupled to a substrate.

[0062] Various embodiments may include any suitable combination of the above-described embodiments, including alternative ("or") embodiments of the embodiments described above in conjunctive form ("and") (e.g., "and" may be "and / or"). Further, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon that, when executed, cause the operation of any of the above-described embodiments. Further, some embodiments may include an apparatus or system having any suitable means for performing various operations of the above-described embodiments.

[0063] The above description of example embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Although specific embodiments have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.

[0064] These modifications may be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and claims. Instead, the scope of the invention should be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. [Other possible claims] (Claim 1) a glass layer having a first surface and a second surface opposite to the first surface, the glass layer being a dielectric layer; another layer coupled to the first surface of the glass layer; a pattern on the second surface of the glass layer that receives a deposition material into at least a portion of the pattern; A package comprising: (Claim 2) The package of claim 1 , wherein the pattern comprises traces etched into glass or through-glass vias. (Claim 3) 3. The package of claim 2, wherein the traces etched into the glass provide a redistribution layer (RDL). (Claim 4) The package of claim 3 , wherein the RDL comprises a fan-out. (Claim 5) 5. The package of claim 1, 2, 3, or 4, wherein the deposited material comprises copper or a copper alloy, or the deposited material comprises a seed layer. (Claim 6) 5. The package of claim 1, 2, 3, or 4, wherein the other layer is selected from the group consisting of a substrate, an adhesive layer, or another glass layer. (Claim 7) the glass layer is a first glass layer and the deposition material is a first deposition material; a second glass layer having a first surface and a second surface opposite the first surface, the first surface being bonded to the second surface of the first glass layer; a pattern on the second surface of the glass layer that receives a second deposition material into at least a portion of the pattern; Further comprising: 5. The package of claim 1, 2, 3 or 4. (Claim 8) the other layer is a first other layer; a second glass layer between the first surface of the second glass layer and the second surface of the first glass layer; 8. The package of claim 7. (Claim 9) 8. The package of claim 7, further comprising the first deposition material and the second deposition material, wherein the first deposition material and the second deposition material are conductive or electrically coupled. (Claim 10) 11. The package of claim 9, wherein the first and second deposition materials are different materials. bonding a first surface of a glass layer having a second surface opposite the first surface to another layer; patterning the second surface of the glass layer to form a patterned structure; plating the second surface of the glass layer with a material contained within at least a portion of the patterned structure; A method comprising: (Claim 12) 12. The method of claim 11 , wherein patterning the second side of the glass layer further comprises etching traces on the second side of the glass layer or drilling vias through the glass layer. (Claim 13) 13. The method of claim 12, wherein the etched traces provide a RDL or the vias provide an electrical connection between the first side of the glass layer and the second side of the glass layer. (Claim 14) 14. The method of claim 11, 12, or 13, wherein the material comprises copper or a copper alloy. (Claim 15) the glass layer is a first glass layer, the deposition material is a first deposition material, and the patterned structure is a first patterned structure; bonding a first surface of a second ply of glass, the second ply of glass having a first surface and a second surface opposite the first surface, to the second surface of the first ply of glass; patterning the second surface of the second glass layer to create a second patterned structure; plating the second surface of the second glass layer with a second deposition material contained within at least a portion of the second patterned structure; Further comprising: 14. The method of claim 11, 12, or 13. (Claim 16) the other layer is a first dielectric layer; bonding a first surface of a second glass ply having a first surface and a second surface opposite the first surface to the second surface of the first glass ply; bonding the first surface of the second glass layer to a second dielectric layer; bonding the second surface of the first glass layer to the second dielectric layer; The method of claim 15 further comprising: (Claim 17) 14. The method of claim 11, 12, or 13, further comprising bonding the dielectric layer to a substrate prior to bonding the first surface of the glass layer to the dielectric layer. (Claim 18) A circuit board; a package coupled to the circuit board, the package comprising: a glass layer having a first surface and a second surface opposite the first surface; a dielectric layer coupled to the first surface of the glass layer; a pattern on the second surface of the glass layer; and a deposition material within at least a portion of the pattern; The system has: (Claim 19) 20. The system of claim 18, wherein the pattern comprises traces etched into glass providing RDLs, fan-outs, or through-glass vias. (Claim 20) 20. The system of claim 18 or 19, wherein the dielectric layer is bonded to a substrate.

Claims

1. a glass layer having a first surface and a second surface opposite to the first surface, the glass layer being a dielectric layer; another layer coupled to the first surface of the glass layer; a pattern on the second surface of the glass layer that receives a deposition material into at least a portion of the pattern; Equipped with the pattern comprises traces or through-glass vias etched into the glass; The package wherein traces etched into the glass provide multiple redistribution layers (RDL).

2. The package of claim 1 , wherein the RDL includes a fanout.

3. The package of claim 1 or 2, wherein the deposited material comprises copper or a copper alloy, or the deposited material comprises a seed layer.

4. The package of claim 1 or 2, wherein the other layer is selected from the group consisting of a substrate, an adhesive layer, or another glass layer.

5. the glass layer is a first glass layer, the deposition material is a first deposition material, a second glass layer having a first surface and a second surface opposite the first surface, the first surface of the second glass layer bonded to the second surface of the first glass layer; a pattern on the second surface of the glass layer that receives a second deposition material into at least a portion of the pattern; Further comprising:

3. A package according to claim 1 or 2.

6. the other layer is a first other layer; a second additional layer between the first surface of the second glass layer and the second surface of the first glass layer. The package of claim 5.

7. 6. The package of claim 5, further comprising the first deposition material and the second deposition material, wherein the first deposition material and the second deposition material are conductive or electrically coupled.

8. The package of claim 7 , wherein the first deposition material and the second deposition material are different materials.

9. bonding a first surface of a glass layer having a second surface opposite the first surface to another layer; patterning the second surface of the glass layer to form a patterned structure; plating the second surface of the glass layer with a material contained within at least a portion of the patterned structure; Equipped with patterning the second surface of the glass layer further comprises etching traces into the second surface of the glass layer; The method wherein the etched traces provide a RDL.

10. 10. The method of claim 9, wherein patterning the second surface of the glass layer further comprises drilling vias through the glass layer.

11. The method of claim 10 , wherein the via provides an electrical connection between the first side of the glass layer and the second side of the glass layer.

12. 12. The method of claim 9, 10, or 11, wherein the material comprises copper or a copper alloy.

13. the glass layer is a first glass layer, the deposition material is a first deposition material, and the patterned structure is a first patterned structure; bonding a first surface of a second glass ply having a first surface and a second surface opposite the first surface to the second surface of the first glass ply; patterning the second surface of the second glass layer to create a second patterned structure; plating the second surface of the second glass layer with a second deposition material contained within at least a portion of the second patterned structure; Further comprising:

12. The method of claim 9, 10, or 11.

14. the other layer being a first dielectric layer; bonding a first surface of a second glass ply having a first surface and a second surface opposite the first surface to the second surface of the first glass ply; bonding the first surface of the second glass layer to a second dielectric layer; bonding the second surface of the first glass layer to the second dielectric layer; The method of claim 13 further comprising:

15. 12. The method of claim 9, 10, or 11, further comprising bonding the further layer to a substrate prior to bonding the first surface of the glass layer to the further layer.

16. A circuit board; a package coupled to the circuit board, the package comprising: a glass layer having a first surface and a second surface opposite the first surface; a dielectric layer coupled to the first surface of the glass layer; a pattern on the second surface of the glass layer; a deposition material within at least a portion of the pattern; having The system, wherein the pattern includes traces etched into glass that provide the RDL.

17. 17. The system of claim 16, wherein the pattern includes traces etched into glass that provide fan-out or through-glass vias.

18. The system of claim 16 or 17, wherein the dielectric layer is bonded to a substrate.

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