Semiconductor Device

Abstract

To obtain a semiconductor device in which manufacturability can be improved.SOLUTION: A first circuit pattern 5 has a recessed part 7 in a plan view. A second circuit pattern 6 is arranged on the recessed part 7. A plurality of semiconductor chips 4 are bonded on the first circuit pattern 5. A wire 8 connects an upper surface electrode of the plurality of semiconductor chips 4 to the second circuit pattern 6. Width of the second circuit pattern 6 increases from upstream to downstream of a current path in which current flows in the second circuit pattern 6. The first circuit pattern 5 has a step 9 at a side of the recessed part 7 in a plan view, and a width of the recessed part 7 increases in a tiered way to match an increase in a width of the second circuit pattern 6.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In order to prevent heat concentration, it has been proposed to arrange the semiconductor chips and bonding wires on the upper and lower arms so as to be point symmetrical with respect to the center point of the semiconductor device (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 170553 Summary of the Invention [Problem to be solved by the invention]

[0004] When arranging a plurality of semiconductor chips side by side, it is difficult to specify the chip mounting positions, which causes a problem of poor manufacturability.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to obtain a semiconductor device that can improve manufacturability. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a first circuit pattern having a recess in a plan view, a second circuit pattern disposed in the recess, a plurality of semiconductor chips bonded onto the first circuit pattern, and wires connecting upper surface electrodes of the plurality of semiconductor chips to the second circuit pattern, the width of the second circuit pattern increasing from upstream to downstream of a current path through which a current flows in the second circuit pattern, the first circuit pattern having a step in a plan view on a side of the recess, and the width of the recess increasing in a stepped manner in accordance with the increase in width of the second circuit pattern. the second circuit pattern has a first portion, a second portion wider than the first portion, and a third portion wider than the second portion, and the plurality of semiconductor chips have a first semiconductor chip pair sandwiching the first portion and having upper surface electrodes wire-connected to the first portion, a second semiconductor chip pair sandwiching the second portion and having upper surface electrodes wire-connected to the second portion, and a third semiconductor chip pair sandwiching the third portion and having upper surface electrodes wire-connected to the third portion.It is characterized by: Effect of the Invention

[0007] In the present disclosure, the first circuit pattern has a step on the side of the recess in a plan view, and the width of the recess increases in a stepped manner in accordance with the increase in the width of the second circuit pattern. When bonding a semiconductor chip onto the first circuit pattern, the chip mounting position can be specified using the step as a guide, thereby improving manufacturability. [Brief description of the drawings]

[0008] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Diagram 2] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Diagram 3] 1 is an enlarged plan view of a portion of a semiconductor device according to a first embodiment. [Figure 4] FIG. 11 is a plan view showing a semiconductor device according to a second embodiment. [Diagram 5] FIG. 11 is a plan view showing a semiconductor device according to a third embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line I-II of FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0010] Embodiment 1 Fig. 1 is a plan view showing a semiconductor device according to a first embodiment. Fig. 2 is a circuit diagram of the semiconductor device according to the first embodiment. An insulating substrate 2 is provided inside a case 1. A plurality of semiconductor chips 3 and a plurality of semiconductor chips 4 are provided on the insulating substrate 2. The collector of the semiconductor chip 3 is connected to an electrode C1 of the case 1. The emitter of the semiconductor chip 3 and the collector of the semiconductor chip 4 are connected to electrodes C2E1. The emitter of the semiconductor chip 4 is connected to an electrode E2. Although not shown in the figure, the inside of the case 1 is sealed with a sealant, and a lid is provided above the case 1.

[0011] The semiconductor chip 3 is a single element consisting of a switching element Tr1 and a free wheel element Di1 connected in anti-parallel. The semiconductor chip 4 is a single element consisting of a switching element Tr2 and a free wheel element Di2 connected in anti-parallel. Combining two elements into a single element in this way contributes to miniaturization. The switching elements Tr1 and Tr2 are, for example, IGBTs, but may also be MOSFETs or the like.

[0012] 3 is an enlarged plan view of a portion of the semiconductor device according to embodiment 1. A first circuit pattern 5 and a second circuit pattern 6 are provided on the upper surface of insulating substrate 2. First circuit pattern 5 has a recess 7 in plan view. Second circuit pattern 6 is disposed in recess 7.

[0013] A plurality of semiconductor chips 4 are arranged side by side along the side of the recess 7 and bonded onto the first circuit pattern 5. Two pairs of semiconductor chips 4 face each other with the recess 7 in between. The upper surface electrode of the semiconductor chip 4 is an emitter electrode, which is connected to the second circuit pattern 6 by a wire 8. The lower surface electrode of the semiconductor chip 4 is a collector electrode, which is connected to the second circuit pattern 6 by solder or the like. Thus, the plurality of semiconductor chips 4 are connected in parallel with each other.

[0014] The current output from the emitters of the multiple semiconductor chips 4 flows from the right side to the left side of the second circuit pattern 6 in FIG. 3, and then flows to the electrode E2 in FIG. 1. The width of the second circuit pattern 6 increases from the upstream to the downstream of the current path through which the current flows in this second circuit pattern 6. Therefore, the voltage drop due to the large current flowing in the second circuit pattern 6 increases from the upstream to the downstream of the path. This makes it possible to equalize the parasitic inductance, thereby making it possible to balance the electrical characteristics between the chips. Furthermore, the device can be made smaller because the upstream pattern width is small.

[0015] Moreover, the first circuit pattern 5 has steps 9 in a plan view on the sides of the recess 7, and the width of the recess 7 increases in a stepped manner in accordance with the increase in the width of the second circuit pattern 6. When bonding the semiconductor chip 4 onto the first circuit pattern 5, the chip mounting position can be specified using the steps 9 as a guide, thereby improving manufacturability. Note that the steps 9 are not essential between all of the semiconductor chips 4. The steps 9 are not essential on both sides of the recess 7, and the step 9 may be provided on only one side.

[0016] Moreover, the wires 8 connected to the pair of semiconductor chips 4 sandwiching the recess 7 are wire-bonded in a straight line. This minimizes the wire length, making it possible to suppress a temperature rise in the wires 8.

[0017] Moreover, the pair of semiconductor chips 4 sandwiching the recess 7 are arranged symmetrically with respect to the second circuit pattern 6. This makes it possible to maintain a balance between the wiring inductances of the two chips, thereby reducing noise in the semiconductor device.

[0018] Embodiment 2 4 is a plan view showing a semiconductor device according to a second embodiment. If adjacent semiconductor chips 4 are joined at an angle to each other, this affects heat dissipation and reliability. In contrast, in this embodiment, a step 9 is disposed between each of the adjacent semiconductor chips 4. Therefore, by using the step 9 as a guide when joining the semiconductor chips 4, it is possible to prevent adjacent semiconductor chips 4 from being joined at an angle.

[0019] Third embodiment Fig. 5 is a plan view showing a semiconductor device according to a third embodiment. Fig. 6 is a cross-sectional view taken along line I-II in Fig. 5. One wire 8 is connected to a pair of semiconductor chips 4 on either side of a recess 7 at the most upstream of the current path, and is stitch-connected to only one location of the second circuit pattern 6. As a result, there is only one wire bond location on the second circuit pattern 6, and therefore the pattern width of the second circuit pattern 6 can be narrowed compared to the case where there are two wire bonds.

[0020] The semiconductor chips 3 and 4 are not limited to those made of silicon, but may be made of wide band gap semiconductors having a larger band gap than silicon. Wide band gap semiconductors are, for example, silicon carbide, gallium nitride-based materials, or diamond. A semiconductor chip made of such a wide band gap semiconductor has high voltage resistance and allowable current density, and can be miniaturized. By using this miniaturized semiconductor chip, a semiconductor device incorporating this semiconductor chip can also be miniaturized and highly integrated. In addition, since the semiconductor chip has high heat resistance, the heat dissipation fins of the heat sink can be miniaturized, and the water-cooled part can be air-cooled, so the semiconductor device can be further miniaturized. In addition, since the power loss of the semiconductor chip is low and highly efficient, the efficiency of the semiconductor device can be increased.

[0021] Although the preferred embodiments have been described above in detail, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. Various aspects of the present disclosure are described below as appendices. (Appendix 1) A first circuit pattern having a recess in a plan view; A second circuit pattern disposed in the recess; a plurality of semiconductor chips bonded onto the first circuit pattern; and wires connecting the upper surface electrodes of the plurality of semiconductor chips to the second circuit pattern; a width of the second circuit pattern increases from an upstream side to a downstream side of a current path through which a current flows in the second circuit pattern; A semiconductor device characterized in that the first circuit pattern has a step in a planar view on the side of the recess, and the width of the recess increases in a stepped manner in accordance with an increase in the width of the second circuit pattern. (Appendix 2) The semiconductor chips are arranged side by side along the side of the recess, 2. The semiconductor device according to claim 1, wherein the step is disposed between adjacent semiconductor chips. (Appendix 3) The semiconductor device described in appendix 1 or 2, characterized in that the wires are connected to the pair of semiconductor chips on either side of the recess at the most upstream of the current path, and are stitch-connected to the second circuit pattern. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the wires connected to the pair of semiconductor chips sandwiching the recess are wire-bonded in a straight line. (Appendix 5) 5. The semiconductor device according to claim 1, wherein the semiconductor chips that are paired with each other across the recess are arranged symmetrically with respect to the second circuit pattern. (Appendix 6) 6. The semiconductor device according to claim 1, wherein the semiconductor chip is a single element that includes a switching element and a free wheel element. (Appendix 7) 7. The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are formed of a wide band gap semiconductor. [Explanation of symbols]

[0022] 4 semiconductor chip, 5 first circuit pattern, 6 second circuit pattern, 7 recess, 8 wire, 9 step

Claims

1. a first circuit pattern having a recess in a plan view; A second circuit pattern disposed in the recess; a plurality of semiconductor chips bonded onto the first circuit pattern; wires connecting the upper surface electrodes of the plurality of semiconductor chips to the second circuit pattern; a width of the second circuit pattern increases from an upstream side to a downstream side of a current path through which a current flows in the second circuit pattern; the first circuit pattern has a step on a side of the recess in a plan view, and a width of the recess increases stepwise in accordance with an increase in a width of the second circuit pattern; the second circuit pattern has a first portion, a second portion wider than the first portion, and a third portion wider than the second portion; The semiconductor device is characterized in that the plurality of semiconductor chips include a first semiconductor chip pair that sandwiches the first portion and has top surface electrodes wire-connected to the first portion, a second semiconductor chip pair that sandwiches the second portion and has top surface electrodes wire-connected to the second portion, and a third semiconductor chip pair that sandwiches the third portion and has top surface electrodes wire-connected to the third portion.

2. The semiconductor chips are arranged side by side along the side of the recess, 2. The semiconductor device according to claim 1, wherein the step is disposed between adjacent ones of the semiconductor chips.

3. The semiconductor device according to claim 1 or 2, characterized in that one of the wires is connected to the pair of semiconductor chips on either side of the recess at the most upstream side of the current path, and is stitch-connected to only one point of the second circuit pattern.

4. 3. The semiconductor device according to claim 1, wherein the wires connected to the pair of semiconductor chips sandwiching the recess are wire-bonded in a straight line.

5. 3. The semiconductor device according to claim 1, wherein the pair of semiconductor chips sandwiching the recess are arranged symmetrically with respect to the second circuit pattern.

6. 3. The semiconductor device according to claim 1, wherein the semiconductor chip is a single element that includes a switching element and a free wheel element.

7. 3. The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are formed of a wide band gap semiconductor.

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