Low-Density Parity-Check (LDPC) Data Decoding Using Iterative Variable Accuracy

Abstract

To provide a low-density parity-check (LDPC) data decoding method using iterative variable accuracy.SOLUTION: A method includes: segmenting an LDPC encoded data block of probability values representing likelihood between binary values by dividing the LDPC encoded data block into a plurality of data probability value segments and a plurality of parity probability value segments; decoding the LDPC encoded data block by adjusting the probability values of the LDPC encoded data block on the basis of a parity-check matrix according to an iteration-variable accuracy parameter representing a trade-off between accuracy and computational efficiency; defining correspondence between the data probability value segments and the parity probability value segments on the basis of the parity-check matrix; and concatenating the likely binary values that satisfy the parity-check matrix associated with the probability values of each data probability value segment to form a decoded data block.SELECTED DRAWING: Figure 4

Description

[Background technology]

[0001] Wireless data communication has become ubiquitous in modern society. As digital data transmission became more prevalent, the usefulness of reliable, error-free communication over noisy wireless channels became apparent. This led to the creation of Forward Error Correction (FEC) codes. FEC codes are mathematical algorithms used to add redundant information to transmitted data, allowing the receiver to correct errors that may have occurred during transmission. FEC codes have become essential as wireless communication systems have expanded, especially with the advent of mobile telephony and data-intensive applications. Without FEC, wireless data transmissions would suffer from higher error rates, leading to data corruption and costly retransmissions. FEC codes, such as Low-Density Parity-Check (LDPC) codes, are an essential component of modern wireless technology, making wireless communication reliable and efficient by improving data integrity and mitigating the effects of channel impairments. [Brief description of the drawings]

[0002] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, according to standard industry practice, various features have not been drawn to scale. In fact, dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0003] [Figure 1] 1 is a schematic diagram of a system for low-density parity-check (LDPC) data transmission in accordance with at least one embodiment of the present invention.

[0004] [Diagram 2] FIG. 1 is a schematic diagram of an integrated circuit encoder for LDPC data encoding in accordance with at least one embodiment of the present invention.

[0005] [Diagram 3]FIG. 1 is a schematic diagram of an integrated circuit decoder for LDPC data decoding in accordance with at least one embodiment of the present invention.

[0006] [Figure 4] 1 is an operational flow for LDPC data decoding with iterative variable accuracy in accordance with at least one embodiment of the present invention.

[0007] [Diagram 5] 1 is an operational flow for data probability value segment decoding in accordance with at least one embodiment of the present invention.

[0008] [Figure 6] 1 is an operational flow for adjustment basis quantity determination in accordance with at least one embodiment of the present invention.

[0009] [Figure 7] 1 is an operational flow for subset probability value adjustment in accordance with at least one embodiment of the present invention.

[0010] [Figure 8] FIG. 1 is a block diagram of a hardware configuration for LDPC data decoding with iterative variable accuracy, in accordance with at least some embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, or arrangements, etc. are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, or arrangements, etc. are contemplated. In addition, the disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purposes of brevity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0012] Efficient decoding of data encoded with FEC codes plays a key role in the proliferation of wireless communications to a vast array and variety of connected devices, such as Internet of Things (IoT) devices, many of which have limited power and processing capabilities.

[0013] FIG. 1 is a schematic diagram of a system for low-density parity check (LDPC) data transmission, in accordance with at least one embodiment of the present invention. The system includes an encoder 101, a transmitter 103, a receiver 106, and a decoder 108. In at least some embodiments, the encoder 101 and the transmitter 103 are part of a single device, such as a transmission tower of a wireless access network. In at least some embodiments, the receiver 106 and the decoder 108 are part of a single device, such as a smartphone, that communicates with the wireless access network. In at least some embodiments, such a single device has the encoder, the transmitter, the receiver, and the decoder, allowing two-way communication. In FIG. 1, the encoder 101 and the transmitter 103 are not part of the same device as the receiver 106 and the decoder 108, since the transmitter 103 is in direct communication with the receiver 106.

[0014] The encoder 101 is configured to receive original data 100 and transmit encoded data 102 to a transmitter 103. In at least some embodiments, the encoder 101 is configured to receive the original data 100 in one or more blocks of a predetermined length. In at least some embodiments, the encoder 101 is configured to apply FEC coding to the original data 100 to generate encoded data 102. In at least some embodiments, the encoder 101 is configured to apply LDPC coding to the original data 100 to generate encoded data 102. In at least some embodiments, the encoder 101 is an integrated circuit, such as a Field-Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or the like. In at least some embodiments, the encoder 101 is a computer having a processor and a memory that stores instructions for execution by the processor.

[0015] The transmitter 103 is configured to receive the encoded data 102 from the encoder 101 over wireless communication and transmit binary values ​​104 of the encoded data 102 to the receiver 106. In at least some embodiments, the transmitter 103 is configured to transmit the encoded data 102 in one or more blocks of a predetermined length. In at least some embodiments, the transmitter 103 is configured to transmit the binary values ​​104 according to a standard wireless protocol, such as 5G, BLUETOOTH, BLE, WiFi, 3G GPRS, 3G EVDO, 3G HSPA, 4G WiMAX, 4G E-UTRAN (LTE), etc. Although not all of the aforementioned standards, such as 3G and 4G, currently utilize LDPC, in at least some embodiments, the transmitter 103 includes configurations for multiple standard wireless protocols. In at least some embodiments, the transmitter 103 is configured to transmit in a frequency and timing scheme according to the standard wireless protocol. In at least some embodiments, the transmitter 103 is configured to transmit the binary value 104 over a data channel and other information for decoding the encoded data 102, such as information representing a parity check matrix, over a control channel.

[0016] The receiver 106 is configured to receive probability values ​​105 through wireless reception and transmit encoded probability values ​​107 to the decoder 108. In at least some embodiments, the receiver 106 is configured to record the probability values ​​105 when attempting to receive the binary value 104, the probability values ​​105 representing one or more probabilities that the binary value received from the transmission of the binary value 104 as transmitted by the transmitter 103 represents a 1 or a 0. In at least some embodiments, the receiver 106 records probability values ​​during reception having a reliability proportional to the signal-to-noise ratio. In at least some embodiments, the receiver 106 is configured to record more reliable probability values ​​during instances of a higher signal-to-noise ratio and record less reliable probability values ​​during instances of a lower signal-to-noise ratio. In at least some embodiments, the received values ​​are represented as follows: z i =y i +n i formula 1 Here, z i represents the received value, and y i represents the transmitted value, and n i Let x denote Additive White Gaussian Noise (AWGN), i from 1 to N, where N is the number of received coded probability values. In at least some embodiments, receiver 106 converts the received values ​​to the Log-Likelihood Ratio (LLR) domain as follows:

number

[0017] In at least some embodiments, the receiver 106 is configured to use multiple bits of data to record one or more of the probability values ​​105 corresponding to one of the binary values ​​104. In at least some embodiments, the number of bits of data used to record each one of the probability values ​​105 depends on the hardware capabilities of the receiver 106 or the decoder 108. In at least some embodiments, the receiver 106 is configured to use 6 bits of data to record one or more of the probability values ​​105 corresponding to one of the binary values ​​104. In at least some embodiments, the receiver 106 is configured to receive the probability values ​​105 in one or more blocks of predetermined length. In at least some embodiments, the receiver 106 is configured to assemble the probability values ​​105 into the coded probability values ​​107 using a format that defines a correspondence between the probability values ​​of the coded probability values ​​107 and the binary values ​​of the coded data 102. In at least some embodiments, the receiver 106 is configured to receive the probability values ​​105 over a data channel and other information for decoding the encoded data 102, such as information representing a parity check matrix, over a control channel.

[0018] The decoder 108 is configured to receive the coded probability values ​​107 from the receiver 106 and output decoded data 109. In at least some embodiments, the decoder 108 is configured to decode the coded probability values ​​107 into decoded data 109. In at least some embodiments, the decoder 108 is configured to apply FEC decoding to the coded probability values ​​107 to generate the decoded data 109. In at least some embodiments, the decoder 108 is configured to apply LDPC decoding to the coded probability values ​​107 to generate the decoded data 109. In at least some embodiments, the decoder 108 is an integrated circuit such as an FPGA, an ASIC, or the like. In at least some embodiments, the decoder 108 is a computer having a processor and a memory that stores instructions for execution by the processor.

[0019] 2 is a schematic diagram of an integrated circuit encoder 201 for LDPC data encoding in accordance with at least one embodiment of the present invention. The integrated circuit encoder 201 includes a segmentation processor 210, an encoding processor 213, a concatenation processor 216, and a parameter processor 219.

[0020] The segmentation processor 210 is configured to receive the original data block 200 and transmit data segments 211 to the encoding processor 213 and the concatenation processor 216. In at least some embodiments, the segmentation processor 210 is configured to divide the original data block 200 into a plurality of data segments. In at least some embodiments, the segmentation processor 210 is configured to divide the original data block 200 into one or more segments of a predetermined length. In at least some embodiments, the segmentation processor 210 is configured to divide the original data block 200 into segments having a length according to the length of the original data block 200. In at least some embodiments, the segmentation processor 210 is configured to divide the original data block into a plurality of data segments according to the columns of the LDPC-based graph. In at least some embodiments, the original data block 200 corresponds to an "information block" in the 5G standard, which is the result of a previous segmentation of a transport block that is not performed by the segmentation processor 210.

[0021] The encoding processor 213 is configured to receive the data segments 211 and transmit the parity segments 214 to the concatenation processor 216. In at least some embodiments, the encoding processor 213 is configured to apply a parity check matrix to the data segments 211 to generate the parity segments 214. In at least some embodiments, the encoding processor 213 is configured to apply an LDPC parity check matrix to the data segments 211 to generate the parity segments 214. In at least some embodiments, the encoding processor 213 is configured to apply one or more cyclic shifts to each data segment 211 according to the parity check matrix to generate the parity segments 214. In at least some embodiments, the encoding processor 213 is configured to apply one or more cyclic shifts to some of the parity segments, such as the "core" parity segments of the parity segments 214 according to the parity check matrix to generate other parity segments among the parity segments 214. In at least some embodiments, the encoding processor 213 is configured to input a value to each bit of each parity segment such that the sum of the bit values ​​and binary values ​​in a subset of values ​​of one or more data segments and other parity segments corresponding to that bit is an even number.

[0022] The concatenation processor 216 is configured to receive the data segments 211 and the parity segments 214 and output the encoded data block 202. In at least some embodiments, the concatenation processor 216 is configured to concatenate the data segments 211 with the parity segments 214 to generate the encoded data block 202. In at least some embodiments, the concatenation processor 216 is configured to concatenate the data segments 211 with the parity segments 214 into a format that defines a correspondence between a subset of values ​​in the data segments 211 and the parity segments 214.

[0023] The parameter processor 219 is configured to receive the parameter stream 218 and send information to the segmentation processor 210, the encoding processor 213, and the concatenation processor 216. In at least some embodiments, the parameter processor 219 is configured to receive the parameter stream 218 over a control channel. In at least some embodiments, the parameter processor 219 is configured to receive information indicative of a parity check matrix corresponding to the original data block 200 in the parameter stream 218. In at least some embodiments, the parameter processor 219 is configured to send associated parameters to each of the segmentation processor 210, the encoding processor 213, and the concatenation processor 216. In at least some embodiments, the parameter processor 219 is configured to send information indicative of the segment size to the segmentation processor 210. In at least some embodiments, the parameter processor 219 is configured to send information indicative of the parity check matrix corresponding to the original data block 200 to the encoding processor 213. In at least some embodiments, the parameter processor 219 is configured to send information indicative of the parity check matrix corresponding to the original data block 200 to the concatenation processor 216.

[0024] 3 is a schematic diagram of an integrated circuit decoder 308 for LDPC data decoding in accordance with at least one embodiment of the invention. The integrated circuit decoder 308 includes a segmentation processor 320, one or more decoding processors 323, a concatenation processor 326, and a parameter processor 329.

[0025] The segmentation processor 320 is configured to receive the data block of coded probability values ​​307 and transmit probability value segments 321 to the decoding processor 323. In at least some embodiments, the probability value segments 321 include a data probability value segment and a parity probability value segment. In at least some embodiments, the segmentation processor 320 is configured to divide the data block of coded probability values ​​307 into a plurality of data probability value segments and a plurality of parity probability value segments, each probability value of the coded data block representing a likelihood between binary values. In at least some embodiments, the segmentation processor 320 is configured to divide the data block of coded probability values ​​307 into segments having a length according to the length of the data block of coded probability values ​​307.

[0026] The decode processors 323 are each configured to receive the probability value segments 321 and transmit decoded binary value segments 324 to the concatenation processor 326. In at least some embodiments, each decode processor 323 performs iterations variable The method is configured to adjust the probability value of the encoded data block according to the accuracy parameter based on a parity check matrix, the parity check matrix defining the correspondence between the data probability value segment and the parity probability value segment, where: variableThe accuracy parameter represents a trade-off between accuracy and computational efficiency. In at least some embodiments, each of the decode processors 323 is configured to apply a parity check matrix to the probability value segments 321 to generate a decoded binary value segment 324. In at least some embodiments, each of the decode processors 323 is configured to apply an LDPC parity check matrix to the probability value segments 321 to generate a decoded binary value segment 324. In at least some embodiments, each of the decode processors 323 is configured to apply one or more cyclic shifts to each data probability value segment and each parity probability value segment of the probability value segments 321 according to the parity check matrix to generate a decoded binary value segment 324. In at least some embodiments, each of the decode processors 323 is configured to compare binary values ​​in a subset of values ​​of corresponding data probability value segments and parity probability value segments to ensure that the sum of the values ​​is even. In at least some embodiments, each of the decode processors 323 includes a sorter for sorting the probability values ​​into segments to find a minimum, a calculator for calculating an update value from the minimum, a function selector for selecting the correct function for determining the amount of adjustment based on the minimum, and an iterative variable An accuracy parameter selector for selecting an accuracy parameter.

[0027] The concatenation processor 326 is configured to receive the decoded binary value segments 324 and output a decoded data block 309. In at least some embodiments, the concatenation processor 326 is configured to concatenate likely binary values ​​that satisfy a parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block. In at least some embodiments, the concatenation processor 326 is configured to concatenate the decoded binary value segments 324 to generate the decoded data block 309. In at least some embodiments, the concatenation processor 326 is configured to concatenate the decoded binary value segments 324 to form the same format as the original data block.

[0028] The parameter processor 329 is configured to receive the parameter stream 328 and send information to the segmentation processor 320, the decoding processor 323, and the concatenation processor 326. In at least some embodiments, the parameter processor 329 is configured to send a plurality of parameters to each of the segmentation processor, the decoding processor, and the concatenation processor, where the plurality of parameters correspond to the encoded data block. In at least some embodiments, the parameter processor 329 is configured to receive the parameter stream 328 over a control channel. In at least some embodiments, the parameter processor 329 is configured to receive information indicative of a parity check matrix corresponding to the data block 307 of the encoded probability values ​​in the parameter stream 328. In at least some embodiments, the parameter processor 329 is configured to send associated parameters to each of the segmentation processor 320, the decoding processor 323, and the concatenation processor 326. In at least some embodiments, the parameter processor 329 is configured to send information indicative of a segment size to the segmentation processor 320. In at least some embodiments, the parameter processor 329 is configured to send information representing a parity check matrix corresponding to the data block 307 of coded probability values ​​to the decoding processor 323. In at least some embodiments, the parameter processor 329 is configured to send information representing a parity check matrix corresponding to the data block 307 of coded probability values ​​to the concatenation processor 326.

[0029] 4 is an operational flow for LDPC data decoding with iterative variable accuracy according to at least one embodiment of the present invention. The operational flow provides a method for LDPC data decoding with iterative variable accuracy. In at least some embodiments, the method is performed by one or more decode processors of an integrated circuit, such as the decode processor 323 shown in FIG. 3, or a decoder controller that includes sections for performing certain operations, such as the controller and decoder shown in FIG. 8, which are described below.

[0030] At S430, the segmentation section of the controller segments the LDPC encoded data block. In at least some embodiments, the segmentation section segments the low density parity check (LDPC) encoded data block of probability values ​​by dividing the encoded data block into a plurality of data probability value segments and a plurality of parity probability value segments, each probability value of the encoded data block representing a likelihood between binary values. In at least some embodiments, the segmentation section divides the encoded data block into one or more segments of a predetermined length. In at least some embodiments, the segmentation section divides the encoded data block into segments having a length according to the length of the encoded data block.

[0031] At S433, the decoding section of the controller decodes the data probability value segment. In at least some embodiments, the decoding section applies a parity check matrix to the data probability value segment and the parity probability value segment to generate a decoded binary value segment. In at least some embodiments, the decoding section applies an LDPC parity check matrix to the data probability value segment and the parity probability value segment to generate a decoded binary value segment. In at least some embodiments, the decoding section applies one or more cyclic shifts to the data probability value segment and the parity probability value segment according to the parity check matrix to generate a decoded binary value segment. In at least some embodiments, the decoding section compares the binary values ​​in a subset of values ​​of corresponding data probability value segments and parity probability value segments to ensure that the sum of the values ​​is even. In at least some embodiments, the decoding section iteratively variable Decode the encoded data block by adjusting the probability value of the encoded data block according to the accuracy parameter and based on a parity check matrix, the parity check matrix defining the correspondence between the data probability value segment and the parity probability value segment, where: variable The accuracy parameter represents a trade-off between accuracy and computational efficiency.In at least some embodiments, the decoding section performs the operational flow shown in Figure 5, which is described below.

[0032] At S439, the concatenation section concatenates the likely binary values. In at least some embodiments, the concatenation section concatenates the likely binary values ​​that satisfy a parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block. In at least some embodiments, the concatenation section concatenates the likely binary value segments to generate a decoded data block. In at least some embodiments, the concatenation section concatenates the likely binary value segments into the same format as the original data block.

[0033] 5 is an operational flow for decoding data probability value segments in accordance with at least one embodiment of the present invention. The operational flow provides a method for decoding data probability value segments. In at least some embodiments, the method is performed by one or more decode processors of an integrated circuit, such as the decode processor 323 shown in FIG. 3, a decode section of a decoder, such as the decode section shown in FIG. 8, which is described below.

[0034] At S540, the decode section or a subsection thereof compares the probability values ​​in the subsets. In at least some embodiments, the decode section compares subsets of probability values ​​from one or more data probability value segments and corresponding parity probability value segments. In at least some embodiments, as the iterations proceed, the decode section compares subsets of probability values, each subset having an associated probability value according to a parity check matrix, and each subset's associated probability value is from a corresponding data probability value segment and parity probability value segment. In at least some embodiments, the decode section references the parity check matrix to determine which values ​​of the data probability value segment and the parity probability value segment belong to each subset. In at least some embodiments, each row of the parity check matrix defines a subset of values ​​of the data probability value segment and the parity probability value segment. In at least some embodiments, the probability values ​​of each subset correspond to an original binary value and sum to an even number. In at least some embodiments, each probability value is included in more than one subset.

[0035] At S542, the decoding section or a subsection thereof determines an adjustment basis quantity. In at least some embodiments, the decoding section determines an adjustment basis quantity that represents a quantity of the least reliable probability values ​​among the other probability values ​​in the subset on which the adjustment is based. In at least some embodiments, as the iterations proceed, the decoding section determines an adjustment basis quantity for each subset, the adjustment basis quantity representing a quantity of the least reliable probability values ​​among the other probability values ​​in the subset on which the adjustment is based. In at least some embodiments, the quantity of the one or more least reliable probability values ​​is the adjustment basis quantity. In at least some embodiments, the adjustment basis quantity is less than or equal to the quantity of the other probability values ​​in the subset. In at least some embodiments, the decoding section determines a fixed adjustment basis quantity for the first iteration of each subset. In at least some embodiments, the decoding section performs the operational flow shown in FIG. 6 for each subsequent iteration of each subset, which is described below.

[0036] At S544, the decode section or a subsection thereof adjusts the probability values ​​of the subsets. In at least some embodiments, the decode section adjusts each probability value in the subset based on one or more least reliable probability values ​​among the other probability values ​​in the subset. In at least some embodiments, the decode section performs iterations of adjusting each probability value in each subset. In at least some embodiments, as the iterations progress, the decode section adjusts each probability value in each subset based on one or more least reliable probability values ​​among the other probability values ​​in the subset. In at least some embodiments, the decode section performs the operational flow shown in FIG. 7, which is described below.

[0037] At S546, the decoding section or a subsection thereof determines whether a termination condition has been met. In at least some embodiments, the decoding section determines that the termination condition has been met in response to the parity check matrix being filled or in response to performing a predetermined number of iterations. In at least some embodiments, the iterations of adjustment are performed until the likely binary values ​​associated with the probability values ​​fill the parity check matrix or until a predetermined number of iterations have been performed. In at least some embodiments, the decoding section determines that the parity check matrix has been filled in response to determining that the sum of the likely binary values ​​in each subset is even. In at least some embodiments, the decoding section determines that the parity check matrix has been filled in response to determining that the sum of the likely binary values ​​in each subset is even in successive iterations. In response to the decoding section determining that the termination condition has not yet been met, the operational flow returns to the probability value comparison at S540 after selecting (S547) a next subset. In response to the decoding section determining that the termination condition has been met, the operational flow proceeds to outputting the decoded binary value segment at S549.

[0038] At S549, the decoding section or a subsection thereof outputs the decoded binary value segment. In at least some embodiments, the decoded binary value segment includes a likely binary value according to the final adjusted probability value of the data probability value segment. In at least some embodiments, the decoding section sends the decoded binary value segment to a concatenation section for concatenation of the decoded binary value segment. In at least some embodiments, if there is no interdependence between the subsets, the subsets may be processed in parallel. In at least some embodiments, the corresponding data probability value segment and the parity probability value segment according to the parity check matrix are processed in parallel.

[0039] 6 is an operational flow for determining adjusted base quantities in accordance with at least one embodiment of the present invention. The operational flow provides a method for determining adjusted base quantities. In at least some embodiments, the method is performed by one or more decode processors of an integrated circuit, such as the decode processor 323 shown in FIG. 3, a decode section of a decoder, such as the decode section shown in FIG. 8, which is described below.

[0040] At S650, the decoding section or a subsection thereof repeats variable In at least some embodiments, the decoding section determines the accuracy parameter of the iteration based on the iteration value and an error rate of the previous iteration. variable In at least some embodiments, the decoding section determines, for each subsequent iteration of the adjustment, an accuracy parameter based on at least the iteration value and an error rate of a previous iteration. variable In at least some embodiments, the accuracy parameter is determined. variable The accuracy parameter is expressed as: J'k=f(k,Ek-1) Equation 3 where J'k is the iteration of the current iteration variable represents an accuracy parameter, k represents an iteration, and E represents the error rate of the previous iteration. In at least some embodiments, the decoding section increases the number of iterations as the number of iterations increases and in response to a high error rate. variable Repeat to increase the accuracy parameter variable and determining an accuracy parameter. In at least some embodiments, the error rate is the proportion of subsets where the sum of the likely binary values ​​in the subset is even for all of the subsets. In at least some embodiments, the error rate is the proportion of probability values ​​in the subset where the sum of the likely binary values ​​in the subset is not even for all of the probability values. In at least some embodiments, the decoding section performs an iteration based on other decoder parameters only or based on other decoder parameters in addition to at least the iteration values ​​and error rate of the previous iteration. variableIn at least some embodiments, the decoding section determines an accuracy parameter for each iteration further based on the signal to noise ratio alone or further based on the signal to noise ratio in addition to at least the iteration value, the error rate, or both of the previous iteration. variable In at least some embodiments, the decoding section or the decoding processor performs iterative variable A Look-Up Table (LUT) is included in which accuracy parameter values ​​are associated with corresponding iteration and error rate values.

[0041] At S653, the decoding section repeats variable Determine whether the accuracy parameter is less than the number of probability values ​​in the subset. variable In response to the decoding section determining that the accuracy parameter is less than the quantity of probability values ​​in the subset, the operational flow proceeds to applying the accuracy parameter at S656. variable In response to the decoding section determining that the accuracy parameter is not less than the quantity of probability values ​​in the subset, the operational flow proceeds to applying an adjustment quantity at S658 that is equal to one less than the subset quantity.

[0042] At S656, the decoding section or a subsection thereof applies the accuracy parameter as an adjustment quantity. At S658, the decoding section or a subsection thereof applies as an adjustment quantity a quantity that is one less than the quantity of probability values ​​in the subset. In other words, the decoding section applies the iterations variable Apply the lesser of the adjusted base quantities between the accuracy parameter and one less than the quantity of probability values ​​in the subset. In at least some embodiments, the operations of S653, S656, and S658 are expressed as follows: J = min(J',(I-1)) Equation 4 where J represents the adjusted base quantity and I represents the quantity of probability values ​​in the subset.

[0043] 7 is an operational flow for subset probability value adjustment in accordance with at least one embodiment of the present invention. The operational flow provides a method for adjusting subset probability values. In at least some embodiments, the method is performed by one or more decode processors of an integrated circuit, such as the decode processor 323 shown in FIG. 3, a decode section of a decoder, such as the decode section shown in FIG. 8, which is described below.

[0044] At S760, the decoding section or a subsection thereof determines one or more minimum confidence values. In at least some embodiments, the decoding section determines one or more minimum confidence values ​​in the subset other than the selected value. In at least some embodiments, the decoding section determines which other probability value in the subset has the lowest confidence value. In at least some embodiments, each probability value is represented by an LLR. In at least some embodiments, the LLR value is positive if the probability of 0 is higher than the probability of 1 and negative if the probability of 1 is higher than the probability of 0, consistent with Equation 2. In at least some embodiments, the absolute value of the LLR value indicates the confidence level. In at least some embodiments, the decoding section determines which probability value in the subset has the lowest confidence value based on the absolute value of the LLR value. In at least some embodiments, the decoding section determines which probability value in the subset has the lowest confidence value based on the absolute value of the beta value for each LLR value, where the decoding section determines the beta value as follows: β mn =LLR n -α mn formula 5 Here, LLR n represents the LLR value in column n of the parity check matrix, and α mn LLR from the immediately preceding iteration of probability value adjustment for a subset of row m n represents the adjustment value of β mn LLR for a subset of row m nrepresents the β value of . In at least some embodiments, the decoding section determines which probability value in the subset has the lowest confidence value as follows:

number

[0045] At S762, the decode section, or a subsection thereof, determines an adjustment amount. In at least some embodiments, the decode section determines an adjustment amount based on the number of minimum confidence values ​​that are equal to the adjusted base quantity. In at least some embodiments, the decode section determines an adjustment amount equal to the minimum confidence value in response to the adjusted base quantity being one. In at least some embodiments, the decode section determines an adjustment amount equal to the average of the minimum confidence values ​​in response to the adjusted base quantity being greater than one. In at least some embodiments, the decode section determines an adjustment amount as follows:

number

[0046] At S764, the decode section determines whether the sum of the binary values ​​in the subset is even. In response to determining that the sum of the corresponding binary values ​​is not even, the operational flow proceeds to decreasing the confidence at S765. In response to determining that the sum of the corresponding binary values ​​is even, the operational flow proceeds to increasing the confidence at S766.

[0047] At S765, the decoding section or a subsection thereof decreases a confidence value of the selected probability value by an adjustment amount. In at least some embodiments, the probability value is adjusted to decrease the confidence in the likely binary value in response to determining that the sum of the likely binary values ​​in the subset is not even. In at least some embodiments, the decoding section decreases the absolute value of the LLR value of the selected probability value. In at least some embodiments, the absolute value of the LLR value becomes negative due to the decrease, causing the LLR value to represent the opposite binary value as the likely value.

[0048] At S766, the decoding section or a subsection thereof increases a confidence value of the selected probability value by an adjustment amount. In at least some embodiments, the probability value is adjusted to increase the confidence in the likely binary value in response to determining that the sum of the likely binary values ​​in the subset is even. In at least some embodiments, the decoding section increases the absolute value of the LLR value of the selected probability value.

[0049] In at least some embodiments, the decryption section performs the operations of S764, S765, and S766 as follows:

number

number

number

[0050] At S768, the decode section determines whether all of the probability values ​​in the subset have been adjusted. In response to the decode section determining that unadjusted probability values ​​remain, the operational flow returns to the minimum confidence value determination at S760 after selecting the next probability value (S769). In response to the decode section determining that all of the probability values ​​in the subset have been adjusted, the operational flow ends. In at least some embodiments, adjustments to the probability values ​​are not made until the amount of adjustment for all of the probability values ​​in the subset has been determined, and then adjustments are made to all of the probability values ​​in the subset at once.

[0051] FIG. 8 is a block diagram of a hardware configuration for LDPC data decoding with iterative variable accuracy in accordance with at least some embodiments of the invention.

[0052] An exemplary hardware configuration includes a decoder 808 that interacts with an input device 878 directly or through a network 877. In at least some embodiments, the decoder 808 is a computer or other computing device that receives input or commands from the input device 878. In at least some embodiments, the decoder 808 is integrated with the input device 878. In at least some embodiments, the decoder 808 is a computer system that executes computer-readable instructions to perform operations for LDPC data decoding with iterative variable accuracy.

[0053] The decoder 808 includes a controller 872, a storage unit 874, an input / output interface 876, and a communication interface 879. In at least some embodiments, the controller 872 includes a processor or programmable circuitry that executes instructions that cause the processor or programmable circuitry to perform operations according to the instructions. In at least some embodiments, the controller 872 includes analog or digital programmable circuitry, or any combination thereof. In at least some embodiments, the controller 872 includes physically separate storage or circuitry that interacts through communication. In at least some embodiments, the storage unit 874 includes a non-volatile computer readable medium that can store executable and non-executable data for access by the controller 872 during execution of instructions. The communication interface 879 transmits and receives data from a network 877. The input / output interface 876 connects to various input and output units, such as input devices 878, via parallel ports, serial ports, keyboard ports, mouse ports, monitor ports, etc., to accept commands and present information. In some embodiments, the storage unit 874 is external to the decoder 808.

[0054] The controller 872 includes a segmentation section 880, a decoding section 882, and a concatenation section 884. The storage unit 874 includes an LDPC encoded data block 890, a parity check matrix 892, and an accuracy parameter 894.

[0055] The segmentation section 880 is a circuit or instruction of the controller 872 configured to divide the coded data block of probability values ​​into segments. In at least some embodiments, the segmentation section 880 is configured to divide the coded data block of probability values ​​into a plurality of data probability value segments and a plurality of parity probability value segments, where each probability value in the coded data block represents a likelihood between binary values. In at least some embodiments, the segmentation section 880 utilizes information in the storage unit 874, such as the LDPC coded data block 890 and the parity check matrix 892. In at least some embodiments, the segmentation section 880 includes subsections for performing additional functions, as described in the flow charts above. In at least some embodiments, such subsections are referred to by names associated with the corresponding functions.

[0056] The decode section 882 is a circuit or instruction of the controller 872 configured to decode the probability value segments. In at least some embodiments, the decode section 882 performs iterative decoding. variable The method is configured to adjust the probability value of the encoded data block according to the accuracy parameter based on a parity check matrix, the parity check matrix defining the correspondence between the data probability value segment and the parity probability value segment, where: variable The accuracy parameter represents a tradeoff between accuracy and computational efficiency. In at least some embodiments, the decode section 882 utilizes information in the storage unit 874, such as a parity check matrix 892 and an accuracy parameter 894. In at least some embodiments, the decode section 882 includes subsections for performing additional functions, as described in the preceding flow charts. In at least some embodiments, such subsections are referred to by names associated with the corresponding functions.

[0057] The concatenation section 884 is circuitry or instructions of the controller 872 configured to concatenate the decoded binary value segments. In at least some embodiments, the concatenation section 884 is configured to concatenate likely binary values ​​that satisfy a parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block. In at least some embodiments, the concatenation section 884 includes subsections for performing additional functions as described in the preceding flow charts. In at least some embodiments, such subsections are referred to by names associated with the corresponding functions.

[0058] In at least some embodiments, the apparatus is a separate device capable of processing logical functions to perform the operations herein. In at least some embodiments, the controller and storage unit need not be entirely separate devices, and in some embodiments share circuitry or one or more computer-readable media. In at least some embodiments, the storage unit includes a hard drive that stores both computer-executable instructions and data accessed by the controller, and the controller includes a combination of a central processing unit (CPU) and RAM into which the computer-executable instructions can be copied in whole or in part for execution by the CPU during performance of the operations herein.

[0059] In at least some embodiments where the apparatus is a computer, programs installed within the computer can cause the computer to function as the apparatus of the embodiments described herein or to perform operations associated with the apparatus of the embodiments described herein, and in at least some embodiments, such programs are executable by a processor to cause the computer to perform specific operations associated with some or all of the blocks of the flowcharts and block diagrams described herein.

[0060] At least some embodiments are described with reference to flow charts and block diagrams, whose blocks represent (1) steps of a process in which an operation is performed, or (2) sections of a controller responsible for performing an operation. In at least some embodiments, certain steps and sections are implemented by dedicated circuitry, programmable circuitry provided with computer readable instructions stored on a computer readable medium, and / or a processor provided with computer readable instructions stored on a computer readable medium. In at least some embodiments, the dedicated circuitry includes digital and / or analog hardware circuitry, including integrated circuits (ICs) and / or discrete circuits. In at least some embodiments, the programmable circuitry includes reconfigurable hardware circuitry, such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), etc., including logical AND, OR, XOR, NAND, NOR and other logic operations, flip-flops, registers, memory elements, etc.

[0061] In at least some embodiments, a computer readable storage medium includes a tangible device capable of maintaining and storing instructions for use by an instruction execution device. In some embodiments, a computer readable storage medium includes, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves on which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as being a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted through a wire.

[0062] In at least some embodiments, the computer readable program instructions described herein can be downloaded from a computer readable storage medium to the respective computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. In at least some embodiments, the network includes copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. In at least some embodiments, a network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing / processing device.

[0063] In at least some embodiments, the computer readable program instructions that perform the operations described above are either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including object oriented programming languages, such as Smalltalk, or C++, and traditional procedural programming languages, such as the "C" programming language or similar programming languages. In at least some embodiments, the computer readable program instructions are executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In at least some embodiments, in the latter scenario, the remote computer is connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or a connection is made to an external computer (e.g., through the Internet using an Internet Service Provider). In at least some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), executes computer readable program instructions by utilizing state information of the computer readable program instructions to individualize the electronic circuitry to perform aspects of the invention.

[0064] Although the embodiments of the present invention have been described, the scope of any subject matter described in the claims is not limited to the above-described embodiments. Those skilled in the art will understand that various modifications and improvements to the above-described embodiments are possible. Those skilled in the art will also understand that the scope of the claims includes embodiments to which such modifications or improvements have been made.

[0065] The operations, procedures, steps, and stages of each process performed by the apparatus, system, program, and method shown in the claims, embodiments, or figures can be performed in any order, unless the order is indicated by "prior to" or "before" or the like, and unless output from a previous process is used in a later process. Even if a process flow is described in the claims, embodiments, or figures using phrases such as "first" or "next," such description does not necessarily mean that the processes must be performed in the order described.

[0066] In at least some embodiments, low density parity check (LDPC) data decoding using iterative variable accuracy includes segmenting an LDPC encoded data block of probability values ​​by dividing the LDPC encoded data block into a plurality of data probability value segments and a plurality of parity probability value segments, each probability value of the LDPC encoded data block representing a likelihood between binary values, and iteratively variable Decoding the LDPC coded data block by adjusting the probability values ​​of the LDPC coded data block based on a parity check matrix according to the accuracy parameter, the parity check matrix defining a correspondence between the data probability value segments and the parity probability value segments, and concatenating the most likely binary values ​​that satisfy the parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block. variable The accuracy parameter represents a tradeoff between accuracy and computational efficiency.

[0067] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations of the present disclosure are possible without departing from the spirit and scope of the present disclosure.

Claims

1. segmenting a low density parity check (LDPC) encoded data block of probability values ​​by dividing the LDPC encoded data block into a plurality of data probability value segments and a plurality of parity probability value segments, each probability value of the LDPC encoded data block representing a likelihood between binary values; decoding the LDPC coded data block by adjusting the probability values ​​of the LDPC coded data block based on a parity check matrix according to an iteratively variable accuracy parameter, the parity check matrix defining a correspondence between data probability value segments and parity probability value segments; and concatenating likely binary values ​​filling the parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block; where the iteratively variable accuracy parameter represents a tradeoff between accuracy and computational efficiency. A method for providing the above.

2. The step of decoding comprises: comparing subsets of probability values, each subset having an associated probability value according to the parity check matrix, the associated probability values ​​of each subset being from corresponding data probability value segments and parity probability value segments; where the probability values ​​of each subset correspond to original binary values, the sum of which is even, where each probability value is included in more than one subset; and adjusting each probability value in each subset based on one or more minimum confidence probability values ​​of the other probability values ​​in the subset; wherein each probability value is adjusted to increase confidence in the likely binary value in response to determining that a sum of the likely binary values ​​in the subset is even; wherein each probability value is adjusted to decrease confidence in the likely binary value in response to determining that the sum of the likely binary values ​​in the subset is not even.

2. The method of claim 1, comprising:

3. The step of decoding comprises: determining, for each subset, an adjustment basis quantity, said adjustment basis quantity representing the quantity of the least confident probability value among said other probability values ​​in said subset on which said adjustment is based; wherein the quantity of the one or more minimum confidence probability values ​​is the adjusted basis quantity; wherein the adjusted base quantity is less than or equal to the quantity of the other probability values ​​in the subset. The method of claim 2 further comprising:

4. The step of decoding comprises: performing iterations of adjustment of each probability value in each subset; for each subsequent iteration of adjustment, determining the iteration-variable accuracy parameter based on at least the iteration value and an error rate of a previous iteration; and applying, for each subset, the lesser of the adjusted basis quantity between the iteratively variable accuracy parameter and a quantity one less than the quantity of probability values ​​in the subset. The method of claim 3 further comprising:

5. The error rate is the proportion of subsets for which the sum of the most likely binary values ​​in the subset is even for all of the subsets. The method according to claim 4.

6. The error rate is the proportion of probability values ​​in the subset for which the sum of the most likely binary values ​​in the subset is even for all of the probability values. The method according to claim 4.

7. The step of determining the iteratively variable accuracy parameter comprises: determining said iteratively variable accuracy parameter further based on a signal to noise ratio. The method of claim 4 further comprising:

8. The iterations of adjustment are performed until likely binary values ​​associated with the probability values ​​fill the parity check matrix or until a predetermined number of iterations have been performed. The method according to claim 4.

9. To the processor: segmenting a low density parity check (LDPC) encoded data block of probability values ​​by dividing the LDPC encoded data block into a plurality of data probability value segments and a plurality of parity probability value segments, each probability value of the LDPC encoded data block representing a likelihood between binary values; decoding the LDPC coded data block by adjusting the probability values ​​of the LDPC coded data block based on a parity check matrix according to an iteratively variable accuracy parameter, the parity check matrix defining a correspondence between data probability value segments and parity probability value segments; and concatenating likely binary values ​​filling the parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block; Run the command, where the iteratively variable accuracy parameter represents a tradeoff between accuracy and computational efficiency. Computer program.

10. The step of decrypting includes: comparing subsets of probability values, each subset having an associated probability value according to said parity check matrix, said associated probability values ​​of each subset being from corresponding data probability value segments and parity probability value segments; where the probability values ​​of each subset correspond to original binary values, the sum of which is even, where each probability value is included in more than one subset; and adjusting each probability value in each subset based on one or more minimum confidence probability values ​​of the other probability values ​​in said subset; wherein each probability value is adjusted to increase confidence in the likely binary value in response to determining that a sum of the likely binary values ​​in the subset is even; wherein each probability value is adjusted to decrease confidence in the likely binary value in response to determining that the sum of the likely binary values ​​in the subset is not even.

10. The computer program of claim 9, comprising:

11. The step of decrypting includes: determining, for each subset, an adjustment basis quantity, said adjustment basis quantity representing the quantity of the least confident probability value among said other probability values ​​in said subset on which said adjustment is based; wherein the quantity of the one or more minimum confidence probability values ​​is the adjusted basis quantity; wherein the adjusted base quantity is less than or equal to the quantity of the other probability values ​​in the subset. The computer program product of claim 10 further comprising:

12. The step of decrypting includes: performing an iteration of adjusting each probability value in each subset; determining, for each subsequent iteration of adjustment, the iteration-variable accuracy parameter based on at least the iteration value and an error rate of a previous iteration; and applying, for each subset, the lesser of the adjusted basis quantity between the iteratively variable accuracy parameter and a quantity one less than the quantity of probability values ​​in the subset. The computer program product of claim 11 , further comprising:

13. The error rate is the proportion of subsets for which the sum of the most likely binary values ​​in the subset is even for all of the subsets.

13. A computer program product as claimed in claim 12.

14. The error rate is the proportion of probability values ​​in the subset for which the sum of the most likely binary values ​​in the subset is even for all of the probability values.

13. A computer program product as claimed in claim 12.

15. The step of determining the iteratively variable accuracy parameter comprises: determining said iteratively variable accuracy parameter further based on a signal-to-noise ratio; The computer program product of claim 12 further comprising:

16. The iterations of adjustment are performed until likely binary values ​​associated with the probability values ​​fill the parity check matrix or until a predetermined number of iterations have been performed.

13. A computer program product as claimed in claim 12.

17. a segmentation processor configured to partition a data block of LDPC encoded probability values ​​into a plurality of data probability value segments and a plurality of parity probability value segments, each probability value of the LDPC encoded data block representing a likelihood between binary values; a decoding processor configured to adjust the probability values ​​of the LDPC encoded data block according to an iteratively variable accuracy parameter and based on a parity check matrix, the parity check matrix defining a correspondence between data probability value segments and parity probability value segments; and a concatenation processor configured to concatenate likely binary values ​​filling the parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block; where the iteratively variable accuracy parameter represents a tradeoff between accuracy and computational efficiency.

16. A device comprising:

18. The decode processor includes: comparing subsets of probability values, each subset having an associated probability value according to the parity check matrix, the associated probability values ​​of each subset being from corresponding data probability value segments and parity probability value segments; where the probability values ​​of each subset correspond to original binary values, the sum of which is even, where each probability value is included in more than one subset; and adjusting each probability value in each subset based on one or more minimum confidence probability values ​​of the other probability values ​​in the subset; wherein each probability value is adjusted to increase confidence in the likely binary value in response to determining that a sum of the likely binary values ​​in the subset is even; wherein each probability value is adjusted to decrease confidence in the likely binary value in response to determining that the sum of the likely binary values ​​in the subset is not even.

20. The device of claim 17, further configured to:

19. The decode processor includes: determining an adjustment basis quantity for each subset, said adjustment basis quantity representing the quantity of the least confident probability value among the other probability values ​​in said subset on which said adjustment is based; wherein the quantity of the one or more minimum confidence probability values ​​is the adjusted basis quantity; wherein the adjusted base quantity is less than or equal to the quantity of the other probability values ​​in the subset.

20. The device of claim 18, further configured to:

20. The device is a circuit comprising: a parameter processor configured to transmit a plurality of parameters to each of the segmentation processor, the decoding processor, and the concatenation processor; wherein the plurality of parameters corresponds to the encoded data block. The device of claim 17 further comprising:

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