Tray

Abstract

To provide a technique that can place a semiconductor substrate in the correct position with respect to an edge ring.SOLUTION: A tray according to the present disclosure on which a semiconductor substrate is placed includes a substrate placement portion on which a semiconductor substrate is placed, and an edge ring placement portion that is provided around the substrate placement portion and on which an edge ring is placed. The substrate placement portion and the edge ring placement portion include a conductive tray body, and a dielectric film formed on at least the top surface of the tray body.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a tray. [Background technology]

[0002] In plasma processing of semiconductor substrates, an edge ring (also called a focus ring) may be placed along the outer periphery of the semiconductor substrate placed in a chamber (processing vessel) that is kept at a predetermined vacuum level. Placing the edge ring controls the plasma at the outer periphery of the semiconductor substrate, so that the outer periphery and center of the semiconductor substrate can be processed uniformly. In this case, the positional relationship between the semiconductor substrate and the edge ring is important. Therefore, it is required to transport the semiconductor substrate accurately relative to the edge ring.

[0003] In addition, the edge ring is consumed by the plasma processing, and therefore needs to be replaced periodically. The edge ring is usually replaced by opening the chamber in which the edge ring is placed to the atmosphere. As a method for replacing the edge ring without opening the chamber to the atmosphere, it has been proposed to provide an edge ring storage chamber connected to a vacuum transfer chamber and to transfer the edge ring to the chamber using a transfer mechanism of the vacuum transfer chamber.

[0004] It is also known to place the semiconductor substrates on a tray and transport the tray into the chamber. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2017-084872 A [Patent Document 2] JP 2006-196691 A [Patent Document 3] JP 2011-114178 A Summary of the Invention [Problem to be solved by the invention]

[0006] Usually, the semiconductor substrate is transferred into the chamber via an atmospheric transfer chamber, a load lock chamber, and a vacuum transfer chamber. Therefore, even if the transfer mechanism is controlled to transfer the semiconductor substrate accurately to the edge ring arranged in the chamber, the semiconductor substrate may shift from the transfer mechanism before being transferred into the chamber, and the transfer may not be accurate. Furthermore, when the edge ring is transferred into the chamber using the transfer mechanism of the vacuum transfer chamber, it is necessary to transfer the edge ring accurately to the mounting table on which the edge ring is placed.

[0007] The present disclosure provides techniques that allow for proper positioning of a semiconductor substrate relative to an edge ring. [Means for solving the problem]

[0008] According to one aspect of the present disclosure, there is provided a tray on which a semiconductor substrate is placed, the tray having a substrate placement portion on which the semiconductor substrate is placed, and an edge ring placement portion provided around the substrate placement portion and on which an edge ring is placed. The substrate placement portion and the edge ring placement portion each have a conductive tray body and a dielectric film formed on at least an upper surface of the tray body. Effect of the Invention

[0009] According to the technique of the present disclosure, the semiconductor substrate can be positioned at the correct position relative to the edge ring. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a substrate processing system. [Diagram 2] FIG. 2 is a diagram illustrating an example of the configuration of a process module. [Diagram 3] FIG. 3 is a diagram showing an example of the shape of a tray. [Figure 4] FIG. 4 is a diagram showing an example of the shape of an edge ring placed on a tray. [Diagram 5]FIG. 5 is a diagram showing an example of the shapes of an edge ring and a wafer placed on a tray. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of the mounting device. [Figure 7] FIG. 7 is a flowchart showing an example of a processing procedure of the conveying method. [Figure 8] FIG. 8 is a diagram showing an example of a conveying method. [Figure 9] FIG. 9 is a diagram showing an example of a conveying method. [Figure 10] FIG. 10 is a diagram showing an example of a conveying method. [Figure 11] FIG. 11 is a diagram showing an example of a conveying method. [Figure 12] FIG. 12 is a graph showing the relationship between the electrostatic capacitance per unit area and the attractive force per unit area in the electrostatic chuck of the process module. [Figure 13] FIG. 13 is a diagram showing the positional relationship between the rotation angle sensor and the horizontal position sensor. [Figure 14] FIG. 14 is a diagram showing the correct positional relationship between the edge ring and the wafer. [Figure 15] FIG. 15 is a diagram showing an example of adjusting the position of the wafer. [Figure 16] FIG. 16 is a diagram showing an example of adjusting the position of the wafer. [Figure 17] FIG. 17 is a diagram showing an example of adjusting the position of the wafer. [Figure 18] FIG. 18 is a diagram showing an example of adjusting the position of the wafer. [Figure 19] FIG. 19 is a diagram showing an example of the configuration of a substrate processing system in which a tray stocker 5 is connected to a vacuum transfer chamber. [Figure 20] FIG. 20 is a diagram showing an example of a tray in which the edge ring mounting portion and the substrate mounting portion are formed at the same height. [Figure 21] FIG. 21 is a diagram showing an example in which a DC voltage is applied to a tray body without using lift pins. [Figure 22]FIG. 22 is a diagram showing another example in which a DC voltage is applied to a tray body without using lift pins. [Figure 23] FIG. 23 is a diagram showing another example in which a DC voltage is applied to a tray body without using lift pins. [Figure 24] FIG. 24 is a diagram showing an example of de-electrifying the wafer W without using lift pins. [Diagram 25] FIG. 25 is a diagram showing another example of de-electrifying the wafer W without using lift pins. [Figure 26] FIG. 26 is a diagram showing an example of a tray that functions as a bipolar electrostatic chuck. [Figure 27] FIG. 27 is a diagram showing an example of a placement device for placing the tray TR8. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the technology of the present disclosure will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0012] <Configuration of the substrate processing system> FIG. 1 is a diagram showing an example of the configuration of a substrate processing system.

[0013] In FIG. 1, the substrate processing system 100 has a FOUP 14, an atmospheric transfer chamber 11, an edge ring stocker 2, a tray stocker 5, an aligner 3, a load lock chamber 12, a vacuum transfer chamber 13, a process module 4, a first transfer mechanism 15, and a second transfer mechanism 16.

[0014] The FOUP 14 is a container capable of housing semiconductor substrates (hereinafter sometimes referred to as "wafers") and has an openable and closable lid. When the FOUP 14 housing wafers is attached to the atmospheric transfer chamber 11, the lid of the FOUP 14 engages with the gate door GT of the atmospheric transfer chamber 11, disengaging the latch of the lid of the FOUP 14 and allowing the lid of the FOUP 14 to be opened. When the gate door GT is opened in this state, the lid of the FOUP 14 moves together with the gate door GT, opening the lid of the FOUP 14 and connecting the inside of the FOUP 14 to the inside of the atmospheric transfer chamber 11.

[0015] The atmosphere inside the atmospheric transfer chamber 11 is kept at atmospheric atmosphere, and the edge ring stocker 2 and the tray stocker 5 are connected to the atmospheric transfer chamber 11 via an openable / closable shutter 23. The edge ring stocker 2 accommodates a plurality of edge rings. The tray stocker 5 accommodates a plurality of trays. The aligner 3 is connected to the atmospheric transfer chamber 11 via an opening 22. A first transfer mechanism 15 is provided inside the atmospheric transfer chamber 11, and the first transfer mechanism 15 transfers the wafer, the edge ring, and the tray between the FOUP 14, the edge ring stocker 2, the tray stocker 5, the aligner 3, and the load lock chamber 12. The first transfer mechanism 15 has a base 15a, a multi-joint arm 15b, and a pick 15c. The base end side of the arm 15b is connected to the base 15a, and the tip side of the arm 15b is connected to the pick 15c. Base 15a is movable in the atmospheric transfer chamber 11 in the direction of the arrow (the longitudinal direction of atmospheric transfer chamber 11). Pick 15c is formed in a U-shape and supports a wafer, an edge ring, and a tray. When pick 15c removes an edge ring from edge ring stocker 2, shutter 23 between edge ring stocker 2 and atmospheric transfer chamber 11 is opened, and when pick 15c removes a tray from tray stocker 5, shutter 23 between tray stocker 5 and atmospheric transfer chamber 11 is opened.

[0016] The atmospheric transfer chamber 11 and the vacuum transfer chamber 13 are connected via a load lock chamber 12. A vacuum atmosphere is maintained inside the vacuum transfer chamber 13. A gate valve G separates the atmospheric transfer chamber 11 from the load lock chamber 12 and the vacuum transfer chamber 13 from the load lock chamber 12. Normally, the gate valve G is closed, and when a wafer, an edge ring, or a tray is transferred from the atmospheric transfer chamber 11 to the load lock chamber 12 by a first transfer mechanism 15, the gate valve G provided between the atmospheric transfer chamber 11 and the load lock chamber 12 is opened. In addition, when a tray on which an edge ring and a wafer are placed is taken out of the load lock chamber 12 by a second transfer mechanism 16 and transferred into the vacuum transfer chamber 13, the gate valve G provided between the load lock chamber 12 and the vacuum transfer chamber 13 is opened.

[0017] The load lock chamber 12 is provided with a vacuum pump (not shown) as an exhaust mechanism and a leak valve (not shown) for returning the pressure to atmospheric pressure, and the inside of the load lock chamber 12 can be switched between an atmospheric atmosphere and a vacuum atmosphere. When a wafer, an edge ring, or a tray is transferred from the atmospheric transfer chamber 11 to the load lock chamber 12 by the first transfer mechanism 15, the inside of the load lock chamber 12 is switched to an atmospheric atmosphere, and when a tray on which the wafer and the edge ring are placed is taken out of the load lock chamber 12 by the second transfer mechanism 16 and transferred into the vacuum transfer chamber 13, the inside of the load lock chamber 12 is switched to a vacuum atmosphere.

[0018] A second transfer mechanism 16 is provided in the vacuum transfer chamber 13, and the second transfer mechanism 16 transfers a tray on which a wafer and an edge ring are placed between the load lock chamber 12 and the process module 4. The second transfer mechanism 16 has a base 16a, an articulated arm 16b, and a pick 16c. The base end of the arm 16b is connected to the base 16a, and the tip end of the arm 16b is connected to the pick 16c. The base 16a is movable in the vacuum transfer chamber 13 in the direction of the arrow (the longitudinal direction of the vacuum transfer chamber 13). The pick 16c is formed in a U-shape and supports the tray on which the wafer and the edge ring are placed.

[0019] The vacuum transfer chamber 13 and the process module 4 are separated by a gate valve G. Normally, the gate valve G is closed, and when a tray on which a wafer and an edge ring are placed is transferred from inside the vacuum transfer chamber 13 to inside the process module 4 by the second transfer mechanism 16, the gate valve G provided between the vacuum transfer chamber 13 and the process module 4 is opened.

[0020] The process module 4 performs processing on a wafer, which is an object to be processed, in a vacuum atmosphere. The process module 4 performs processing, such as etching and film formation, on the wafer placed on a tray.

[0021] <Process module configuration> Fig. 2 is a diagram showing an example of the configuration of a process module 4. The process module 4 shown in Fig. 2 is configured as a capacitively coupled parallel plate substrate processing apparatus.

[0022] 2, the process module 4 has a chamber 10 which is a processing vessel made of metal such as aluminum or stainless steel. The chamber 10 is safety grounded.

[0023] A disk-shaped susceptor 12 is arranged horizontally in the chamber 10. A tray TR1 on which a wafer W and an edge ring ER are placed is placed on the susceptor 12. The susceptor 12 also functions as a lower electrode. A gate valve G for opening and closing an entrance for the wafer W is attached to a side wall of the chamber 10. The susceptor 12 is made of a metal such as aluminum, and is supported by an insulating cylindrical support 14 extending vertically upward from the bottom of the chamber 10.

[0024] An annular exhaust path 18 is formed between a conductive cylindrical support part (inner wall part) 16 that extends vertically upward from the bottom of the chamber 10 along the outer periphery of the cylindrical support part 14 and the side wall of the chamber 10. An exhaust port 22 is provided at the bottom of the exhaust path 18.

[0025] An exhaust device 26 is connected to the exhaust port 22 via an exhaust pipe 24. The exhaust device 26 has a vacuum pump such as a turbo molecular pump, and reduces the pressure of the processing space PS in the chamber 10 to a desired vacuum level. The pressure inside the chamber 10 is preferably kept constant, for example, in the range of 10 mTorr to 3500 mTorr.

[0026] A wafer W to be subjected to substrate processing is placed on the susceptor 12 via a tray TR1, and an edge ring ER is disposed so as to surround the wafer W. The edge ring ER is made of a conductive material such as Si or SiC or an insulating material such as SiO2, and is placed on the upper surface of the tray TR1.

[0027] An electrostatic chuck 40 for attracting a wafer is provided on the upper surface of the susceptor 12. The electrostatic chuck 40 is formed by sandwiching a sheet-like or mesh-like conductor between film-like or plate-like dielectrics. A DC power supply 42 disposed outside the chamber 10 is electrically connected to the conductor in the electrostatic chuck 40 via a switch 44 and a power supply line 46. When the switch 44 is turned on, a DC voltage is applied to the electrostatic chuck 40 from the DC power supply 42, and the DC voltage generates a Coulomb force in the electrostatic chuck 40, causing the wafer W to be electrostatically attracted to the electrostatic chuck 40 via the tray TR1.

[0028] An annular coolant chamber 48 extending in the circumferential direction is provided inside the susceptor 12. A coolant (e.g., cooling water) at a predetermined temperature is circulated and supplied to the coolant chamber 48 from a chiller unit (not shown) via pipes 50 and 52. The temperature of the wafer W is controlled by controlling the temperature of the coolant. Furthermore, in order to improve the accuracy of the temperature of the wafer W, a heat transfer gas (e.g., He gas) from a heat transfer gas supply unit (not shown) is supplied between the tray TR1 and the wafer W via a gas supply pipe 51 and a gas passage 56 in the susceptor 12.

[0029] A disk-shaped upper electrode 60 is provided on the ceiling of the chamber 10 so as to face (i.e., oppose) the susceptor 12 in parallel. The upper electrode 60 is attached to the ceiling of the chamber 10 via a ring-shaped insulator 98 made of, for example, ceramic.

[0030] The upper electrode 60 has an electrode plate 64 directly facing the susceptor 12, and an electrode support 66 that detachably supports the electrode plate 64 from behind (above). The material of the electrode plate 64 is preferably a conductive material such as Si or Al. The electrode support 66 is made of, for example, anodized aluminum. Thus, in the process module 4, the disk-shaped susceptor 12 (i.e., the lower electrode) and the disk-shaped upper electrode 60 are arranged parallel to and facing each other.

[0031] The gas supply unit 76 supplies a processing gas to the chamber 10. The upper electrode 60 also serves as a shower head to supply the processing gas to the processing space PS defined between the upper electrode 60 and the susceptor 12. More specifically, a gas diffusion chamber 72 is provided inside the electrode support 66, and a large number of gas discharge holes 74 penetrating from the gas diffusion chamber 72 to the susceptor 12 side are formed in the electrode support 66 and the electrode plate 64. A gas supply pipe 78 extending from the gas supply unit 76 is connected to a gas inlet 72a provided in the upper part of the gas diffusion chamber 72.

[0032] A first RF (Radio Frequency) power supply 150 is connected to the upper electrode 60 via a first matching box 152. The first matching box 152 matches the impedance of the first RF power supply 150 side with the impedance of the load (mainly the electrode, plasma, and chamber) side. The first RF power supply 150 can apply a high-frequency voltage for plasma generation having a frequency in the range of 30 to 150 MHz to the upper electrode 60. By applying such a high-frequency voltage to the upper electrode 60, a high-density plasma in a preferable dissociated state can be generated in the processing space PS, and plasma processing can be performed under lower pressure conditions. The frequency of the output voltage of the first RF power supply 150 is preferably 50 to 80 MHz, and is typically adjusted to a frequency of 60 MHz or near 60 MHz.

[0033] A second RF power supply 160 is connected to the susceptor 12 serving as a lower electrode via a second matching box 162 and a connection rod 36. The second matching box 162 matches the impedance on the second RF power supply 160 side with the impedance on the load (mainly the electrode, plasma, and chamber) side. The second RF power supply 160 is capable of applying a high-frequency bias voltage having a frequency in the range of several hundred kHz to several tens of MHz to the susceptor 12. The frequency of the output voltage of the second RF power supply 160 is typically adjusted to 2 MHz, 13.56 MHz, or the like.

[0034] <Shapes of tray, edge ring and wafer> FIG. 3 is a diagram showing an example of the shape of a tray, FIG. 4 is a diagram showing an example of the shape of an edge ring placed on the tray, and FIG. 5 is a diagram showing an example of the shapes of an edge ring and a wafer placed on the tray.

[0035] As shown in FIG. 3, the tray TR1 has a disk-like shape and includes a conductive tray body 101, a dielectric film 102 formed to cover the periphery of the tray body 101, a lift pin contact portion 103, and through holes 104, 105, and 106. The through hole 104 is a through hole for supplying a heat transfer gas between the tray TR1 and the wafer W through the gas passage 56 (FIG. 2) in the process module 4. The through hole 105 is a through hole for a lift pin that lifts and lowers the wafer W. The through hole 106 is a through hole for a lift pin that lifts and lowers the edge ring ER. The lift pin contact portion 103 is a part of the back surface of the tray body 101 that contacts the lift pin that lifts the tray TR1, and the dielectric film 102 is not formed thereon. The lift pin contact portion 103 may be formed as a recess that matches the shape of the lift pin. In addition, a substrate mounting portion 108 on which the wafer W is mounted and an edge ring mounting portion 107 on which the edge ring ER is mounted are formed on the upper surface of the tray TR1. The edge ring mounting portion 107 is provided around the substrate mounting portion 108. That is, each of the substrate mounting portion 108 and the edge ring mounting portion 107 has a conductive tray body 101 and a dielectric film 102 formed so as to cover the periphery of the tray body 101. The edge ring mounting portion 107 is formed at a lower position than the substrate mounting portion 108. It is sufficient that the dielectric film 102 is formed on at least the upper surface of the tray body 101.

[0036] 4, the edge ring ER has an annular shape, and the outer periphery of the edge ring ER is circular, whereas a flat portion FL having a flat shape is formed on a part of the inner periphery of the edge ring ER. The edge ring ER is placed on the edge ring placement portion 107 on the upper surface of the tray TR1. The inner periphery of the edge ring ER is formed to be thinner than the outer periphery of the edge ring ER. That is, the inner periphery of the edge ring ER is formed so that when the edge ring ER is placed on the edge ring placement portion 107, the upper surface of the inner periphery of the edge ring ER is at substantially the same height as the upper surface of the substrate placement portion 108 or is lower than the upper surface of the substrate placement portion 108. The outer periphery of the edge ring ER is formed so that when the wafer W is placed on the substrate placement portion 108 on the upper surface of the tray TR1, the upper surface of the outer periphery of the edge ring ER is at substantially the same height as the upper surface of the wafer W or is higher than the upper surface of the wafer W.

[0037] 5, the wafer W has a disk-like shape, and a V-shaped notch NT is formed on a part of the outer periphery of the wafer W. The wafer W is placed on a substrate placement portion 108 on the upper surface of the tray TR1. When the wafer W is placed on the substrate placement portion 108, the wafer W is placed so that the notch NT overlaps with the flat portion FL of the edge ring ER. In this manner, the substrate placement portion 108 has a support surface that supports the back surface of the wafer W, and through holes 104 and 105 that penetrate the tray body 101 and the dielectric film 102. The area of ​​the substrate placement portion 108 is smaller than the area of ​​the wafer W. That is, when the wafer W is placed, the outer periphery of the wafer W on which the notch NT is formed is located outside the outer periphery of the substrate placement portion 108 and on the inner periphery of the edge ring ER.

[0038] As described above, the wafer W and the edge ring ER can be placed on the tray TR1.

[0039] <Configuration of the mounting device> Fig. 6 is a diagram showing a configuration example of a mounting device. In this embodiment, a mounting device 12A as shown in Fig. 6 is used as a load lock chamber 12. In Fig. 6, the mounting device 12A has a container 201, a rotation angle sensor 202, a horizontal position sensor 203, a mounting table 204, a first lift pin 205, a second lift pin 206, a third lift pin 207, a DC power supply 208, and a switch 209. The rotation angle sensor 202 is installed on the top wall of the container 201, and the horizontal position sensor 203 is installed on the side wall of the container 201. The mounting table 204 is accommodated in a conductive container 201. The mounting device 12A also has a first lifting mechanism (not shown) for raising and lowering the first lift pin 205, a second lifting mechanism (not shown) for raising and lowering the second lift pin 206 independently of the first lift pin 205, and a third lifting mechanism (not shown) for raising and lowering the third lift pin 207 independently of the first lift pin 205 and the second lift pin 206. The first lift pin 205, the second lift pin 206, and the third lift pin 207 are made of a conductive material (e.g., Ni, Al, etc.). A DC power supply 208 is connected to the first lift pin 205 via a switch 209. The second lift pin 206 and the third lift pin 207 are grounded. In addition, the mounting device 12A is provided with a vacuum pump (not shown) as an exhaust mechanism capable of lowering the pressure inside the container 201 below atmospheric pressure, and a leak valve (not shown) for returning the pressure inside the container 201 to atmospheric pressure.

[0040] <Transportation method in substrate processing system> Fig. 7 is a flowchart showing an example of a processing procedure of the transport method.Figs. 8 to 11 are diagrams showing an example of the transport method.

[0041] 7, first, in step S1, the tray TR1 is transported to the load lock chamber 12 by the first transport mechanism 15. The tray TR1 is accommodated in a tray stocker 5 connected to the atmospheric transport chamber 11. The first transport mechanism 15 takes the tray TR1 out of the tray stocker 5, and then the tray TR1 placed on a pick 15c is carried into the load lock chamber 12 (into the placement device 12A). At this time, the pressure inside the load lock chamber 12 is atmospheric pressure.

[0042] Next, in step S2, the tray TR1 is placed on the placement table 204 in the load lock chamber 12. As shown in Fig. 8, the first lift pins 205 are raised to separate the tray TR1 from the pick 15c (i.e., the tray TR1 is lifted up). At this time, the first lift pins 205 come into contact with the lift pin contact portions 103 on the rear surface of the tray body 101.

[0043] Next, the pick 15c is withdrawn from the load lock chamber 12 while the first lift pin 205 is kept in the position shown in FIG.

[0044] Next, the tray TR1 is placed on the placement table 204 by lowering the first lift pins 205 (that is, lifting down the tray TR1).

[0045] Next, in step S3, the edge ring ER is transported to the load lock chamber 12 by the first transport mechanism 15. The edge ring ER is accommodated in the edge ring stocker 2 connected to the atmospheric transport chamber 11. The first transport mechanism 15 takes the edge ring ER out of the edge ring stocker 2, and then transports the edge ring ER placed on a pick 15c into the load lock chamber 12.

[0046] Next, in step S4, the edge ring ER is placed on the tray TR1 placed on the placement table 204 in the load lock chamber 12. As shown in Fig. 9, the third lift pins 207 are raised to separate the edge ring ER from the pick 15c (i.e., the edge ring ER is lifted up). At this time, the third lift pins 207 come into contact with the rear surface of the edge ring ER through the through holes 106 of the tray TR1. Since the third lift pins 207 are grounded, the edge ring ER is neutralized by the tip of the third lift pins 207 coming into contact with the rear surface of the edge ring ER.

[0047] Next, the pick 15c is withdrawn from the load lock chamber 12 while the third lift pin 207 is kept in the position shown in FIG.

[0048] Next, the third lift pins 207 are lowered (that is, the edge ring ER is lifted down) to place the edge ring ER on the tray TR1.

[0049] Next, in step S5, the position of the edge ring ER placed on the tray TR1 is measured. As shown in FIG. 10, the position of the edge ring ER placed on the tray TR1 is measured using the rotation angle sensor 202 and the horizontal position sensor 203, and the position information of the edge ring ER is acquired. A signal indicating the acquired position information is transmitted to the aligner 3. The rotation angle sensor 202 is realized, for example, by using a CCD (Charge-Coupled Device). By photographing the flat part FL from above the edge ring ER, the rotation angle RA of the edge ring ER relative to a predetermined reference position RP is measured, and rotation angle information RAI indicating the rotation angle RA is acquired as the first position information of the edge ring ER. The horizontal position sensor 203 is realized, for example, by using a laser irradiated toward the edge ring ER from the side of the edge ring ER. By measuring the distance between the horizontal position sensor 203 and the outer periphery of the edge ring ER, the horizontal position deviation HP of the edge ring ER relative to the predetermined reference position RP is measured, and horizontal position information HPI indicating the position deviation HP is acquired as the second position information of the edge ring ER. Therefore, the position information transmitted from the load lock chamber 12 to the aligner 3 includes the rotation angle information RAI of the edge ring ER and the horizontal position information HPI of the edge ring ER.

[0050] Next, in step S6, the position of the wafer W is adjusted in the aligner 3. The wafer W is transferred from the FOUP 14 into the aligner 3 by the first transfer mechanism 15. Then, the aligner 3 adjusts the position of the wafer W based on the position information transmitted from the load lock chamber 12. That is, the aligner 3 rotates the wafer W based on rotation angle information RAI of the edge ring ER, while adjusting the horizontal position of the wafer W based on horizontal position information HPI of the edge ring ER. The adjustment of the position of the wafer W will be described in detail later.

[0051] Next, in step S7, the wafer W is transferred to the load lock chamber 12 by the first transfer mechanism 15. The wafer W after the position adjustment is placed on the pick 15c of the first transfer mechanism 15, removed from the aligner 3, and transferred to above the mounting table 204 in the load lock chamber 12.

[0052] Next, in step S8, the wafer W is placed on the tray TR1 placed on the mounting table 204 in the load lock chamber 12. As shown in Fig. 11, the second lift pins 206 are raised to separate the wafer W from the pick 15c (i.e., the wafer W is lifted up). At this time, the second lift pins 206 come into contact with the back surface of the wafer W through the through holes 105 of the tray TR1. Since the second lift pins 206 are grounded, the tip of the second lift pins 206 comes into contact with the back surface of the wafer W, thereby removing electricity from the wafer W.

[0053] Next, the pick 15c is withdrawn from the load lock chamber 12 while the second lift pin 206 is kept in the position shown in FIG.

[0054] Next, the second lift pins 206 are lowered (that is, the wafer W is lifted down) to place the wafer W on the tray TR1.

[0055] Next, in step S9, a DC voltage is applied to the tray body 101. The vacuum pump starts evacuation of the container 201, and the first lift pin 205 is brought into contact with the lift pin contact portion 103. The switch 209 is turned on to connect the first lift pin 205 to the DC power supply 208, and the DC power supply 208 applies a positive DC voltage to the first lift pin 205. By applying a positive DC voltage to the first lift pin 205, a positive DC voltage is applied from the DC power supply 208 to the tray body 101 via the first lift pin 205 and the lift pin contact portion 103. The wafer W is electrostatically attracted to the tray TR1 by the Coulomb force generated in the tray TR1 by the DC voltage applied to the tray body 101. In addition, for example, when the edge ring ER is made of a conductive material such as Si or SiC, the edge ring ER is also electrostatically attracted to the tray TR1. In this manner, the wafer W is attracted to the tray TR1 by contacting the first lift pins 205 with the rear surface of the tray body 101 and applying a DC voltage to the tray body 101 via the first lift pins 205.

[0056] Next, in step S10, the tray TR1 on which the edge ring ER and the wafer W are placed is carried into the process module 4. The switch 209 is turned off to stop the application of the DC voltage to the tray body 101, while the first lift pins 205 are raised while keeping their tips in contact with the rear surface of the tray TR1. Since the tray TR1 remains charged even after the application of the DC voltage to the tray body 101 is stopped, the wafer W is attracted and held on the tray TR1.

[0057] Next, the tray TR1 is carried out by the second transfer mechanism 16 in the vacuum transfer chamber 13. The pick 16c of the second transfer mechanism 16 is inserted into the load lock chamber 12, so that the pick 16c is positioned below the tray TR1 lifted by the first lift pins 205.

[0058] Next, the tray TR1 is placed on the pick 16c by lowering the first lift pins 205. Then, the pick 16c is removed from the load lock chamber 12, and the tray TR1 on which the wafer W and the edge ring ER are placed is transferred from the load lock chamber 12 to the process module 4 by the second transfer mechanism 16.

[0059] Since the tray TR1 remains charged even while the tray TR1 on which the wafer W and the edge ring ER are placed is being transported from the load lock chamber 12 to the process module 4, the wafer W after the position adjustment continues to be attracted to the tray TR1. Therefore, it is possible to prevent the position of the wafer W after the position adjustment from being shifted during the transport from the load lock chamber 12 to the process module 4.

[0060] In addition, the edge ring ER is generally heavier than the wafer W. Therefore, when the tray TR1 is transported from the load lock chamber 12 to the process module 4, the edge ring ER is less likely to shift than the wafer W. Therefore, even if the edge ring ER is made of an insulating material such as SiO2, transportation using the tray TR1 is effective. However, if the edge ring ER is made of a conductive material such as Si or SiC, it is more effective because not only the wafer W but also the edge ring ER can be adsorbed to the tray TR1.

[0061] The tray TR1 transported to the process module 4 is placed on the susceptor 12 (electrostatic chuck 40) in the process module 4. The susceptor 12 is provided with lift pins (not shown), and the tray TR1 is placed on the susceptor 12 (electrostatic chuck 40) in the same procedure as in step S2. After the tray TR1 is placed on the electrostatic chuck 40, a switch 44 is turned on, and a DC voltage is applied to the electrostatic chuck 40 from a DC power supply 42. As a result, the wafer W is attracted to the electrostatic chuck 40 via the tray TR1.

[0062] Next, in step S11, a plasma process such as etching is performed.

[0063] After the plasma processing is completed, in step S12, the tray TR1 on which the edge ring ER and the wafer W are placed is transferred out of the process module 4. The tray TR1 transferred out of the process module 4 is placed on the placement table 204 in the load lock chamber 12. After the pressure in the load lock chamber 12 is returned to atmospheric pressure using a leak valve (not shown), the wafer W is transferred out of the load lock chamber 12 by the first transfer mechanism 15. The transferred wafer W is accommodated in the FOUP 14.

[0064] The edge ring ER and the tray TR1 may or may not be stored in the edge ring stocker 2 and the tray stocker 5, respectively. The edge ring ER and the tray TR1 may be left on the mounting table 204 in the load lock chamber 12, and a new wafer W may be loaded. That is, the next process may start from step S5 or step S6. In addition, when replacing a worn edge ring ER, the worn edge ring ER may be stored in the edge ring stocker 2, and a new edge ring ER may be loaded. That is, the next process may start from step S3.

[0065] <Attraction force in electrostatic chuck> The tray TR1 carried into the process module 4 in step S10 is placed on the electrostatic chuck 40. Therefore, the wafer W is not placed directly on the electrostatic chuck 40, but is placed via the tray TR1. Fig. 12 is a graph showing the relationship between the capacitance per unit area and the attraction force per unit area in the electrostatic chuck of the process module. For example, if the thickness of the dielectric layer above the electrode built into the electrostatic chuck is 0.3 mm, the thicknesses of the dielectric film 102 on the upper surface of the tray body 101 and the dielectric film 102 on the lower surface of the tray body 101 are each 0.1 mm, and the relative dielectric constant of each dielectric is 8.5, the capacitance of the tray TR1 is 0.124 µF / m 2In this case, when a DC voltage of 5 kV is applied to the electrostatic chuck 40 from the DC power supply 42, a Coulomb force having an attractive force of about 170 Torr per unit area is obtained in the electrostatic chuck 40. Therefore, even if a heat transfer gas is supplied between the tray TR1 placed on the electrostatic chuck 40 in the process module 4 and the wafer W, an attractive force strong enough to prevent the wafer W from being separated due to the pressure of the heat transfer gas can be obtained.

[0066] <Adjusting the wafer position> Fig. 13 is a diagram showing the positional relationship between the rotation angle sensor and the horizontal position sensor. As shown in Fig. 13, in the mounting device 12A, the edge ring ER is placed on the tray TR1 so that the flat part FL is located below the rotation angle sensor 202. In addition, in the mounting device 12A, horizontal position sensors 203 are installed at three points around the edge ring ER placed on the tray TR1.

[0067] FIG. 14 is a diagram showing the correct positional relationship between the edge ring ER and the wafer. As shown in FIG. 14, in the correct positional relationship between the edge ring ER and the wafer W, the center of the edge ring ER and the center of the wafer W coincide, and the center of the flat portion FL of the edge ring ER coincides with the apex of the recess of the notch NT of the wafer W. Therefore, in order to set the correct positional relationship between the edge ring ER and the wafer W, a straight reference line L1 and a straight reference line L2 are set in advance. A reference position RP is defined by the reference line L1 in the horizontal direction and the reference line L2 in the vertical direction. The reference line L1 and the reference line L2 intersect each other perpendicularly. In the correct positional relationship between the edge ring ER and the wafer W, the center of the edge ring ER and the center of the wafer W coincide with the intersection point of the reference line L1 and the reference line L2, and the center of the flat portion FL and the apex of the recess of the notch NT coincide with the reference line L1.

[0068] Fig. 15 to Fig. 18 are diagrams showing an example of the position adjustment of the wafer. Fig. 15 and Fig. 17 show the position of the edge ring ER placed on the tray TR1, and Fig. 16 and Fig. 18 show the position of the wafer W after the position adjustment.

[0069] The horizontal position sensor 203 is used to measure the horizontal positional deviation HP relative to the reference position RP defined by the reference lines L1 and L2, as shown in FIG. 15, for the edge ring ER placed on the tray TR1. In measuring the positional deviation HP, as shown in FIG. 15, a straight line LA in the horizontal direction and a straight line LB in the vertical direction are set for the edge ring ER placed on the tray TR1. The straight lines LA and LB intersect perpendicularly with each other, and the center of the edge ring ER coincides with the intersection point of the straight lines LA and LB, and the center of the flat portion FL coincides with the straight line LA. The horizontal position sensor 203 measures the direction and amount of deviation of the intersection point of the straight lines LA and LB relative to the intersection point of the reference lines L1 and L2 as the positional deviation HP. In adjusting the horizontal position of the wafer W in the aligner 3, the center position of the wafer W is moved from the intersection point of the reference lines L1 and L2 by the positional deviation HP, as shown in FIG. 16. This allows the center of the edge ring ER, which is placed on the tray TR1 shifted by the position shift HP, to be aligned with the center of the wafer W, making it possible to make the gap between the inner circumference of the edge ring ER and the outer circumference of the wafer W placed within the edge ring ER constant around the entire circumference.

[0070] 17, a rotation angle RA is measured for the edge ring ER placed on the tray TR1 using a rotation angle sensor 202. The rotation angle RA is measured for the edge ring ER placed on the tray TR1, the rotation angle RA being determined by the reference line L1 and the reference line L2. In measuring the rotation angle RA, a straight line LC in the horizontal direction and a straight line LD in the vertical direction are set for the edge ring ER placed on the tray TR1, as shown in FIG. 17. The straight lines LC and LD intersect perpendicularly to each other, and the center of the edge ring ER and the intersection of the reference line L1 and the reference line L2 coincide with the intersection of the straight lines LC and LD, and the center of the flat portion FL coincides with the straight line LC. The rotation angle RA of the straight line LC with respect to the reference line L1 is measured by the rotation angle sensor 202. In the rotation of the wafer W in the aligner 3, the wafer W is rotated by the rotation angle RA from the reference position RP. This allows the wafer W to be placed so that the apex of the recess of the notch NT of the wafer W is aligned with the center of the flat portion FL of the edge ring ER placed on the tray TR1, with the flat portion FL being shifted by the rotation angle RA, as shown in FIG.

[0071] In this embodiment, the edge ring ER and the wafer W are placed on the tray TR1 in the load lock chamber 12 and transported to the process module 4. The placement position of the edge ring ER is measured in the load lock chamber 12, and the wafer W is adjusted based on the measurement result and placed on the tray TR1. Therefore, even if the placement position of the edge ring ER is misaligned, the wafer W can be transported to a correct position relative to the edge ring ER. In addition, since the tray TR1 can electrostatically adsorb the wafer W and the edge ring ER, the edge ring ER and the wafer W placed on the tray TR1 in the load lock chamber 12 can be transported to the process module 4 without being misaligned. Furthermore, when the wafer W is transported to the edge ring ER arranged in the process module 4, it is considered that the relative positions of the edge ring ER and the wafer W are misaligned due to an error that occurs when the wafer W is transported from the load lock chamber 12 to the process module 4. However, in this embodiment, the wafer W is transported to the edge ring ER in the load lock chamber 12, so that the relative positions of the edge ring ER and the wafer W are not misaligned due to a transport error from the load lock chamber 12 to the process module 4. That is, in this embodiment, the wafer W can be transferred to a correct position relative to the edge ring ER in the load lock chamber 12, and can be transferred from the load lock chamber 12 to the process module 4 while maintaining the relative position between the wafer W and the edge ring ER. Therefore, the wafer W can be subjected to uniform plasma processing in the process module 4.

[0072] The embodiments of the present disclosure should be considered to be illustrative and not restrictive in all respects. Indeed, the above-described embodiments may be embodied in various forms. Furthermore, the above-described embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the claims.

[0073] For example, in the above embodiment, an example has been described in which the tray stocker 5 is connected to the atmospheric transfer chamber 11, but the tray stocker 5 may be connected to the vacuum transfer chamber 13 as shown in FIG. 19. FIG. 19 is a diagram showing an example of the configuration of a substrate processing system in which the tray stocker 5 is connected to the vacuum transfer chamber. Also, the edge ring stocker 2 may be connected to the vacuum transfer chamber 13. In these cases, the edge ring and / or the tray are carried into the load lock chamber 12 by the second transfer mechanism 16.

[0074] In the above embodiment, the edge ring and the wafer are placed on a tray in the load lock chamber 12, but they may be placed outside the load lock chamber 12. For example, a placement device 12A separate from the load lock chamber 12 may be connected to the atmospheric transfer chamber 11, and the tray on which the edge ring and the wafer are placed may be carried into the load lock chamber 12 by the placement device 12A.

[0075] In the above embodiment, in step S2, the tray TR1 is placed on the placement table 204, but it does not have to be placed thereon. In step S3, the first lift pins 205 may be lowered to an extent that the edge ring ER can be carried in, and the processes from step S3 onward may be performed in a state in which the tray TR1 is supported by the first lift pins 205.

[0076] In the above embodiment, the trays are stored in the tray stocker 5, the edge rings are stored in the edge ring stocker 2, and then each is carried into the load lock chamber 12. However, a tray on which an edge ring is previously placed may be stored in the tray stocker 5. In this case, the processes of steps S3 and S4 can be omitted. Also, the edge ring stocker 2, the third lift pins 207 of the mounting device 12A that raises and lowers the edge ring, and the through holes 106 of the tray TR1 through which the third lift pins 207 pass can be omitted.

[0077] Furthermore, in the above embodiment, an example has been described in which an edge ring whose inner periphery is located below the outer periphery of the wafer W is used, but the inner periphery of the edge ring does not have to be located below the outer periphery of the wafer W. That is, in tray TR1, edge ring mounting portion 107 is formed at a position lower than substrate mounting portion 108, but the edge ring mounting portion may be formed at a position higher than the substrate mounting portion or at the same position as the substrate mounting portion.

[0078] FIG. 20 is a diagram showing an example of a tray in which an edge ring placement portion and a substrate placement portion are formed at the same height. In FIG. 20, the tray TR2 has a disk-like shape and includes a conductive tray body 251, a dielectric film 252 formed to cover the periphery of the tray body 251, an annular groove 253, an annular protective member 254 accommodated in the groove 253, a lift pin contact portion 255, and through holes 256 and 257. Note that the dielectric film 252 may be formed at least on the upper surface of the tray body 251. The through hole 256 is a through hole for supplying a heat transfer gas between the tray TR2 and the wafer W through the gas passage 56 (FIG. 2) in the process module 4. The through hole 257 is a through hole for a lift pin that lifts and lowers the wafer W. Note that the tray TR2 does not have a through hole for a lift pin that lifts and lowers the edge ring ER, but may have one. Further, on the upper surface of the tray TR2, a substrate mounting portion 259 on which a wafer W is mounted, and an edge ring mounting portion 258 on which an edge ring ER is mounted are formed. The edge ring mounting portion 258 is provided around the substrate mounting portion 259. The substrate mounting portion 259 and the edge ring mounting portion 258 are formed on the same plane.

[0079] In the tray TR2, the outer periphery of the wafer W does not overlap with the inner periphery of the edge ring ER, so that the dielectric film between the wafer W and the edge ring ER is exposed to plasma during plasma processing. For this reason, it is considered that the wafer W is contaminated by the dielectric film or the material constituting the tray body exposed due to the wear of the dielectric film. Therefore, in the tray TR2, a protective member 254 is provided between the substrate placement portion 259 and the edge ring placement portion 258. The protective member 254 is accommodated in a groove 253 provided between the substrate placement portion 259 and the edge ring placement portion 258. It is preferable that the material of the protective member 254 is the same as the material of the edge ring ER. In the tray TR2, the shapes of the edge ring ER and the tray TR2 can be simplified.

[0080] In the above embodiment, the DC voltage is applied to the tray body 101 by the first lift pins 205 connected to the DC power supply 208. However, the DC voltage may be applied to the tray body 101 without using the lift pins.

[0081] FIG. 21 is a diagram showing an example in which a DC voltage is applied to a tray body without using lift pins. A mounting device 12B as shown in FIG. 21 is used as a load lock chamber 12. The same parts as those of the mounting device 12A shown in FIG. 6 are not described and / or illustrated. In FIG. 21, the mounting device 12B has a conductive mounting table 352, an insulating support portion 351, a DC power source 353, and a conductive lift pin 501. The lift pin 501 is grounded. A tray TR3 is mounted on the mounting table 352. An edge ring ER and a wafer W are mounted on the tray TR3. The wafer W is mounted on the tray TR3 by lifting and lowering the lift pin 501. Thus, the wafer W is de-electrified when it is lifted and lowered by the lift pin 501.

[0082] The tray TR3 is formed by laminating a dielectric film 361 on a conductive tray body 362. The tray TR3 is different from the tray TR1 shown in FIG. 3 in that the dielectric film 361 is formed only on the upper surface of the tray body 362, and the lower surface of the tray body 362 is not covered with the dielectric film. That is, the conductive tray body 362 is exposed on the lower surface of the tray TR3. Therefore, when the tray TR3 on which the edge ring ER and the wafer W are placed is placed on the placement table 352, a DC voltage is applied to the placement table 352 by the DC power source 353, so that a DC voltage is applied to the tray body 362. As a result, a Coulomb force is generated in the tray TR3, and the wafer W is electrostatically attracted to the tray TR3.

[0083] FIG. 22 is a diagram showing another example in which a DC voltage is applied to a tray body without using lift pins. A mounting device 12C as shown in FIG. 22 is used as a load lock chamber 12. Description and / or illustration of parts that overlap with the mounting device 12B shown in FIG. 21 are omitted. The mounting device 12C is different from the mounting device 12B shown in FIG. 21 in that a conductive terminal 361 is provided on the upper surface of a conductive mounting table 352. The conductive terminal 361 may be formed by protruding a part of the conductive mounting table 352, or may be formed of a member different from the mounting table 352. For example, the conductive terminal 361 may be formed of a spring.

[0084] The tray TR4 is placed on the placement table 352. The tray TR4 has a conductive tray body 451, a dielectric film 452 formed to cover the periphery of the tray body 451, and a DC power supply connection part 453. The DC power supply connection part 453 is a part of the back surface of the tray body 451 with which the conductive terminal 361 contacts, and the dielectric film 452 is not formed. The DC power supply connection part 453 may be formed as a recessed part matching the shape of the conductive terminal 361. The tray TR4 is different from the tray TR1 shown in FIG. 3 in that the DC power supply connection part 453 is provided. When the tray TR4 on which the edge ring ER and the wafer W are placed is placed on the placement table 352, the conductive terminal 361 of the placement table 352 contacts the tray body 451 via the DC power supply connection part 453. Therefore, in a state where the tray TR4 on which the edge ring ER and the wafer W are placed is placed on the placement table 352, a DC voltage is applied to the placement table 352 by the DC power supply 353, whereby a DC voltage is applied to the tray body 451. As a result, a Coulomb force is generated in the tray TR4, and the wafer W is electrostatically attracted to the tray TR4.

[0085] FIG. 23 is a diagram showing another example of applying a DC voltage to a tray body without using lift pins. A mounting device 12D as shown in FIG. 23 is used as a load lock chamber 12. The same parts as those of the mounting device 12C shown in FIG. 22 will not be described and / or illustrated. The mounting device 12D is different from the mounting device 12C shown in FIG. 22 in that the mounting table 371 is made of an insulating material and the DC power supply 355 is not connected to the mounting table 371. A conductive conduction terminal 361 is provided on the upper surface of the mounting table 371, and the conduction terminal 361 is directly connected to the DC power supply 355. A tray TR5 is placed on the mounting table 371.

[0086] Like the tray TR4, the tray TR5 has a conductive tray body 471, a dielectric film 472 formed to cover the periphery of the tray body 471, and a DC power supply connection part 473. When the tray TR5 on which the edge ring ER and the wafer W are placed is placed on the placement table 371, the conductive terminal 361 of the placement table 371 comes into contact with the tray body 471 via the DC power supply connection part 473. Thus, in a state in which the tray TR5 on which the edge ring ER and the wafer W are placed is placed on the placement table 371, a DC voltage can be applied to the tray body 471 by the DC power supply 355. As a result, a Coulomb force is generated in the tray TR5 by the DC voltage applied to the tray body 471, and the wafer W is electrostatically attracted to the tray TR5.

[0087] In the above embodiment, the wafer W is neutralized by the grounded conductive lift pins. However, the wafer W may be neutralized without using the lift pins.

[0088] FIG. 24 is a diagram showing an example of discharging the wafer W without using lift pins. A mounting apparatus 12E as shown in FIG. 24 is used as the load lock chamber 12. The description and / or illustration of the same parts as those of the mounting apparatus 12B shown in FIG. 21 will be omitted. In FIG. 24, the mounting apparatus 12E has a ground member 354. The mounting apparatus 12E is different from the mounting apparatus 12B in that the mounting apparatus 12E uses the ground member 354, not the grounded lift pins 501, to discharging the wafer W. The ground member 354 is electrically connected to the grounded container 201. The ground member 354 is configured to be able to come into contact with the wafer W placed on the tray TR6. In addition, the ground member 354 may be configured to be able to come into contact with not only the wafer W but also the edge ring ER.

[0089] 24, the wafer W is grounded and neutralized by contacting a grounding member 354 with the wafer W. With the tray TR6 on which the edge ring ER and the wafer W are placed placed on the placement table 352, a DC voltage is applied to the placement table 352 by a DC power supply 353. As a result, a Coulomb force is generated on the tray TR6 by the DC voltage applied to the placement table 352, and the wafer W is electrostatically attracted to the tray TR6.

[0090] Fig. 25 is a diagram showing another example of de-electrifying a wafer W without using lift pins. A mounting device 12F as shown in Fig. 25 is used as a load lock chamber 12. Description and / or illustration of parts that overlap with the mounting device 12C shown in Fig. 22 will be omitted. In Fig. 25, the mounting device 12F has an RF power supply 392 connected to a conductive mounting table 382.

[0091] When the tray TR7 on which the edge ring ER and the wafer W are placed is placed on the placement table 382, ​​the DC power supply 391 is connected to the tray body 481 via the DC power supply connection part 483. With the DC power supply 391 connected to the tray body 481, the DC power supply 391 applies a DC voltage to the tray body 481. The RF power supply 392 applies a high frequency voltage for plasma generation having a frequency in the range of 30 to 150 MHz to the placement table 382. By applying such a high frequency voltage to the placement table 382, ​​the plasma PLS can be generated in the container 201. The edge ring ER and the wafer W are grounded via the plasma PLS generated in the container 201. As a result, a Coulomb force is generated on the tray TR7 by the DC voltage applied to the tray body 481, and the wafer W is electrostatically attracted to the tray TR7.

[0092] In the above embodiment, the tray is configured to function as a monopolar electrostatic chuck, but it may be configured to function as a bipolar electrostatic chuck.

[0093] FIG. 26 is a diagram showing an example of a tray that functions as a bipolar electrostatic chuck. In FIG. 26, the tray TR8 has a disk shape and includes a conductive first tray body 302, a conductive second tray body 301, a dielectric film 303 formed so as to cover the periphery of the first tray body 302 and the second tray body 301, an insulating layer 304, lift pin contact parts 305, 306, and through holes 307, 308. The tray TR8 is different from the tray TR1 in that the tray body is divided into two parts, the first tray body 302 and the second tray body 301, by the insulating layer 304, and that the lift pin contact parts are provided on the first tray body 302 and the second tray body 301, respectively. The insulating layer 304 electrically separates the first tray body 302 and the second tray body 301 in the horizontal direction. The through hole 307 is a through hole for supplying a heat transfer gas between the tray TR2 and the wafer W via the gas passage 56 (FIG. 2) in the process module 4. The through hole 308 is a through hole for a lift pin.

[0094] FIG. 27 is a diagram showing an example of a mounting device on which a tray TR8 is mounted. A mounting device 12G as shown in FIG. 27 is used as a load lock chamber 12. In FIG. 27, the mounting device 12G is different from the mounting device 12A as shown in FIG. 6 in that the mounting device 12G has a first lift pin 401, an insulating second lift pin 409, a first DC power supply 407, a second DC power supply 405, and switches 406 and 408. The first lift pin 401 has a conductive first pin 404, a conductive second pin 403, and an insulating support part 402 that connects the first pin 404 and the second pin 403. In addition, the mounting device 12G has a first lift mechanism (not shown) that lifts and lowers the first lift pin 401, and a second lift mechanism (not shown) that lifts and lowers the second lift pin 409 independently of the first lift pin 401. A first DC power supply 407 is connected to the first pin 404 via a switch 408 , and a second DC power supply 405 is connected to the second pin 403 via a switch 406 .

[0095] As shown in FIG. 27, the tray TR9 on which the wafer W and the edge ring ER are placed is placed on the placement table 204. The first pin 404 and the second pin 403 are in contact with the lift pin contact portions 305 and 306. The switch 408 is turned on to connect the first pin 404 to the first DC power supply 407, so that the first DC power supply 407 applies a positive DC voltage to the first pin 404. By applying a positive DC voltage to the first pin 404, the first DC power supply 407 applies a positive DC voltage to the first tray body 302 via the first pin 404 and the lift pin contact portion 306. In addition, the switch 406 is turned on to connect the second pin 403 to the second DC power supply 405, so that the second DC power supply 405 applies a negative DC voltage to the second pin 403. By applying a negative DC voltage to the second pin 403, a negative DC voltage is applied from the second DC power supply 405 to the second tray body 301 via the second pin 403 and the lift pin contact portion 305. The wafer W is electrostatically attracted to the tray TR2 by a Coulomb force generated in the tray TR2 by the DC voltage applied to the first tray body 302 and the second tray body 301. Furthermore, for example, when the edge ring ER is made of a conductive material such as Si or SiC, the edge ring ER is also electrostatically attracted to the tray TR2.

[0096] In the above embodiment, in step S6, the aligner 3 rotates the wafer W and adjusts the horizontal position of the wafer W. However, the adjustment of the horizontal position of the wafer W may be performed by controlling the first transfer mechanism 15 based on the horizontal position information HPI of the edge ring ER. In other words, the horizontal position of the wafer W may be adjusted by transferring the wafer W to above the mounting table 204 by the first transfer mechanism 15 based on the horizontal position information HPI of the edge ring ER so that the center of the wafer W coincides with the center of the edge ring ER.

[0097] A control unit (not shown) controls the individual operations of the components of the substrate processing systems 100 and 200, and the overall operation (sequence) of the substrate processing systems 100 and 200. One example of the control unit is a microcomputer.

[0098] It should be noted that the embodiments of the present disclosure are illustrative in all respects and should not be considered as limiting. Indeed, the above-mentioned embodiments can be embodied in various forms. Furthermore, the above-mentioned embodiments may be omitted, replaced, or modified in various forms without departing from the scope of the claims and the spirit thereof. For example, in the above description, etching is given as an example of substrate processing, but the substrate processing to which the technology of the present disclosure can be applied is not limited to etching. For example, by changing the degree of vacuum in the processing space PS and the processing gas to those suitable for film formation, it is also possible to apply the technology of the present disclosure to film formation, which is one type of substrate processing.

[0099] Regarding the above embodiment, the following supplementary notes are further disclosed.

[0100] (Appendix 1) A tray on which a semiconductor substrate is placed, a substrate placement portion on which the semiconductor substrate is placed; an edge ring placement portion provided around the substrate placement portion and on which an edge ring is placed, The substrate placement portion and the edge ring placement portion are A conductive tray body; and a dielectric film formed on at least the upper surface of the tray body. Tray.

[0101] (Appendix 2) The edge ring mounting portion is formed at a position lower than the substrate mounting portion. 2. A tray as described in Appendix 1.

[0102] (Appendix 3) The area of ​​the substrate placement portion is smaller than the area of ​​the semiconductor substrate. 2. A tray as described in Appendix 2.

[0103] (Appendix 4) the substrate placement portion and the edge ring placement portion are formed on the same plane; 2. A tray as described in Appendix 1.

[0104] (Appendix 5) a protective member is provided between the substrate placement portion and the edge ring placement portion; 1. A tray as described in Appendix 4.

[0105] (Appendix 6) the protective member is accommodated in a groove provided between the substrate placement portion and the edge ring placement portion; 13. A tray as described in Appendix 5.

[0106] (Appendix 7) The substrate placement unit includes: a support surface for supporting a rear surface of the semiconductor substrate; a through hole penetrating the tray body and the dielectric film; 2. A tray as described in Appendix 1.

[0107] (Appendix 8) Further comprising an insulating layer that electrically isolates the tray body in the horizontal direction. 2. A tray as described in Appendix 1.

[0108] (Appendix 9) A mounting table; A first lift pin that raises and lowers a tray placed on the placement table; second lift pins for lifting and lowering the semiconductor substrate placed on the tray; a first lift mechanism that raises and lowers the first lift pin; a second lift mechanism that lifts and lowers the second lift pins independently of the first lift pins; A voltage application unit that applies a voltage to the tray; A mounting device having the above structure.

[0109] (Appendix 10) The voltage application unit is a DC power supply connected to the mounting table. 10. The mounting device of claim 9.

[0110] (Appendix 11) The mounting table has a conductive terminal for electrically connecting the tray and the mounting table. 10. The mounting device of claim 9.

[0111] (Appendix 12) The voltage application unit is a first DC power supply connected to the first lift pin. 10. The mounting device of claim 9.

[0112] (Appendix 13) the second lift pin is grounded; 10. The mounting device of claim 9.

[0113] (Appendix 14) The first lift pin comprises: The first pin, The second pin, an insulating support portion connecting the first pin and the second pin; the first DC power source is connected to the first pin; a second DC power source connected to the second pin; 13. The mounting device of claim 12.

[0114] (Appendix 15) Further, a third lift pin is provided to raise and lower the edge ring placed on the tray. 10. The mounting device of claim 9.

[0115] (Appendix 16) the third lift pin is grounded; 16. The mounting device of claim 15.

[0116] (Appendix 17) A container that houses the mounting table; and an exhaust mechanism capable of lowering the pressure inside the container to a pressure lower than atmospheric pressure. 10. The mounting device of claim 9.

[0117] (Appendix 18) Further comprising an RF power source connected to the mounting table. 10. The mounting device of claim 9. [Explanation of symbols]

[0118] 100,200 Substrate Processing System 2 Edge Ring Stocker 3 Aligners 4 Process Module 5 Tray Stocker 11 Atmospheric transport chamber 12 Load lock chamber 13 Vacuum transfer chamber 14 FOUP 15 First conveying mechanism 16 Second transport mechanism

Claims

1. A tray on which a semiconductor substrate is placed, a substrate placement portion on which the semiconductor substrate is placed; an edge ring placement portion provided around the substrate placement portion and on which an edge ring is placed, The substrate placement portion and the edge ring placement portion are A conductive tray body; and a dielectric film formed on at least the upper surface of the tray body. Tray.

2. The edge ring mounting portion is formed at a position lower than the substrate mounting portion.

2. The tray of claim 1.

3. The area of ​​the substrate placement portion is smaller than the area of ​​the semiconductor substrate.

3. The tray of claim 2.

4. the substrate placement portion and the edge ring placement portion are formed on the same plane; 2. The tray of claim 1.

5. a protective member is provided between the substrate placement portion and the edge ring placement portion; 5. The tray of claim 4.

6. the protective member is accommodated in a groove provided between the substrate placement portion and the edge ring placement portion; 6. The tray of claim 5.

7. The substrate placement unit includes: a support surface for supporting a rear surface of the semiconductor substrate; a through hole penetrating the tray body and the dielectric film; A tray according to any one of claims 1 to 6.

8. Further comprising an insulating layer that electrically isolates the tray body in the horizontal direction. A tray according to any one of claims 1 to 7.

9. The dielectric film has a thickness of 0.3 mm or less. A tray according to any one of claims 1 to 8.

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