Semiconductor device, its manufacturing method, and module

Abstract

To provide a semiconductor device capable of sufficiently securing adhesion between a resin and a lead frame without causing voids or solder cracks, a method of manufacturing the same, and a module including the semiconductor device.SOLUTION: A semiconductor device includes: a lead frame including a first opening; a resin filled in the first opening; and a semiconductor element electrically connected to the lead frame. A sidewall surface of the lead frame in the first opening is formed so as to have average surface roughness larger than that of the lead frame.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device, a manufacturing method thereof, and a module. [Background technology]

[0002] In recent years, as design rules for semiconductor devices have been tightened and wafer processes have been significantly changed, semiconductor packages are being required to be smaller, thinner, and less expensive. Methods for mounting chips in semiconductor packages to substrates are broadly divided into wire bonding and flip chip bonding. In particular, flip chip bonding has attracted attention because it is suitable for high density and high integration of chips. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-212290 A [Patent Document 2] JP 2019-47064 A

[0004] [overview] Flip chip bonding is a method for electrically connecting the chip surface to the substrate using protruding terminals arranged in an array, rather than using wires as in wire bonding. Compared to wire bonding, flip chip bonding does not require wiring space for wires, so the package itself can be made smaller.

[0005] Chips mounted on a substrate using flip chip bonding are vulnerable to external stress, etc., so they are protected by sealing with resin. However, there is a problem that voids and solder cracks occur around the interface between the resin and the lead frame or the protruding terminals due to insufficient adhesion between the resin and the lead frame. The voids and solder cracks increase the resistance of the joint, and there is a risk that the semiconductor device will not operate normally due to heat generated by the resistance.

[0006] The present embodiment provides a semiconductor device in which sufficient adhesion between the resin and the lead frame is ensured without causing voids or solder cracks, a manufacturing method thereof, and a module including the semiconductor device.

[0007] One aspect of this embodiment is a semiconductor device comprising a lead frame having a first opening, resin filled in the first opening, and a semiconductor element electrically connected to the lead frame, wherein a sidewall surface of the lead frame at the first opening has an average surface roughness greater than that of a top surface of the lead frame.

[0008] Another aspect of this embodiment is a module including the above-described semiconductor device.

[0009] Another aspect of the present embodiment is a method for manufacturing a semiconductor device, comprising the steps of performing a roughening treatment on a lead frame having a first opening, forming a pillar on a semiconductor substrate, joining the pillar to the lead frame, and filling the first opening with resin.

[0010] According to this embodiment, it is possible to provide a semiconductor device in which sufficient adhesion between the resin and the lead frame is ensured without causing voids or solder cracks, a manufacturing method thereof, and a module including the semiconductor device. [Brief description of the drawings]

[0011] [Figure 1]FIG. 1 is a schematic cross-sectional view of a semiconductor device according to one aspect of the present embodiment. [Diagram 2] FIG. 2 is (a) a schematic cross-sectional view of the periphery of a lead frame in a semiconductor device according to one aspect of the present embodiment, and (b) an enlarged schematic cross-sectional view of the periphery of the lead frame. [Diagram 3] FIG. 3 is (a) a schematic cross-sectional view of the periphery of a lead frame in a semiconductor device according to one aspect of the present embodiment, and (b) an enlarged schematic cross-sectional view of the periphery of the lead frame. [Figure 4] FIG. 4 is (a) a schematic cross-sectional view of the periphery of a lead frame in a semiconductor device of a comparative example, and (b) an enlarged schematic cross-sectional view of the periphery of the lead frame. [Diagram 5] FIG. 5 is (a) a schematic cross-sectional view of the periphery of a lead frame in a semiconductor device of a comparative example, and (b) an enlarged schematic cross-sectional view of the periphery of the lead frame. [Figure 6] FIG. 6 is a diagram illustrating a method for manufacturing a lead frame, showing (a) a step of patterning a resist mask on the top and bottom of a metal plate, (b) a step of forming an opening in the metal plate, (c) a step of providing a protective seal, (d) a step of performing a roughening treatment, and (e) a step of removing protective seal 17. [Figure 7] FIG. 7 is a diagram illustrating a method for manufacturing a lead frame, showing (a) a step of performing a roughening treatment, and (b) a step of performing a treatment to form a flat surface. [Figure 8] FIG. 8 is a schematic cross-sectional view of a semiconductor device according to one aspect of the present embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view of a semiconductor device according to one aspect of the present embodiment. [Figure 10] FIG. 10 is a diagram illustrating one aspect of a method for manufacturing a semiconductor device according to the present embodiment, and shows (a) a step of roughening the sidewall surface of the lead frame, (b) a step of forming pillars 55 on the semiconductor substrate 10, (c) a step of stacking the semiconductor substrate 10 and pillars 55 on the lead frame, and (d) a step of sealing with resin. [Figure 11]FIG. 11 is a layout diagram of a module including a semiconductor device according to one aspect of the present embodiment. [Figure 12] FIG. 12 is a layout diagram of a module including a semiconductor device according to one aspect of the present embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view of an outer end portion of a lead frame in a semiconductor device according to one aspect of the present embodiment. [Figure 14] FIG. 14 is (a) a perspective view and (b) a bottom view of a package including a semiconductor device according to one aspect of the present embodiment.

[0012] [Detailed Description] Next, the present embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and planar dimensions of each component is different from the actual relationship. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0013] The following embodiments are merely examples of devices and methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of the components. Various modifications can be made to the embodiments within the scope of the claims.

[0014] A schematic cross-sectional view of a semiconductor device according to this embodiment is shown in Fig. 1. The semiconductor device shown in Fig. 1 includes a region 12 including a lead frame 20, a region 11 including pillars 55, and a semiconductor substrate 10. The lead frame 20 includes an opening, and the sidewall surface of the lead frame 20 at the opening has a larger average surface roughness than the upper surface of the lead frame 20 (the interface between regions 11 and 12 in the figure). The lead frame 20 is electrically connected to a semiconductor element included in the semiconductor substrate 10 via the pillars 55. Furthermore, the lead frame 20, the pillars 55, and the semiconductor substrate 10 are covered and sealed with resin 22.

[0015] Here, a region 14 including the sidewall surface of the lead frame 20 and a region 16 including the upper surface of the lead frame 20 in the opening of the lead frame 20 shown in FIG. 1 will be described with reference to FIGS.

[0016] Fig. 2(a) is a schematic cross-sectional view of the lead frame 20 in region 14 and its surroundings, and Fig. 2(b) is an enlarged view of region 24 shown in Fig. 2(a). As shown in Fig. 2(a), resin 22 is filled into an opening provided in the lead frame 20. Solder 19 for joining to pillar 55 is provided on the lead frame 20. Although a detailed description will be given later, the opening has a first region having a first opening width and a second region having a second opening width narrower than the first opening width.

[0017] 2(b), the sidewall surface of the leadframe 20 in the region 26 is roughly scraped off by roughening treatment, and the fine parts of the roughened sidewall surface are filled with the resin 22. The resin 22 penetrates into the fine irregularities of the sidewall surface of the leadframe 20 and hardens, improving adhesion (also called the anchor effect).

[0018] Examples of the roughening treatment include sandblasting, applying a roughening liquid, or immersing in a roughening liquid. The average surface roughness of the roughened sidewall surface is preferably, for example, 2 to 5 μm. The average surface roughness can be determined, for example, in accordance with JIS B 0601:2013 or ISO 25178.

[0019] 3(a) is a schematic cross-sectional view of the lead frame 20 in the region 16 after the thermal cycle test, and FIG. 3(b) is an enlarged view of the region 28 shown in FIG. 3(a). Solder 19 for joining to the pillar 55 is provided on the lead frame 20. The heat treatment process tends to cause the resin 22 to peel off from the lead frame 20 or to cause solder cracks to progress, but in one aspect of the present embodiment, the adhesion between the lead frame 20 and the resin 22 is sufficiently ensured by the anchor effect described above, so that the occurrence of voids and solder cracks can be suppressed even on the upper surface of the lead frame 20 as shown in FIG. 3(b).

[0020] As a comparative example of the semiconductor device according to this embodiment, a schematic cross-sectional view of the periphery of a lead frame in which the side wall surface of the opening is not subjected to roughening treatment is shown in FIG. 4 and FIG.

[0021] Fig. 4(a) is a schematic cross-sectional view of the periphery of lead frame 20 in region 14 when the sidewall surface of the opening is not roughened, and Fig. 4(b) is an enlarged view of region 21 shown in Fig. 4(a). As shown in Fig. 4(b), the adhesion between lead frame 20 and resin 22 is insufficient, so voids 23 are generated between lead frame 20 and resin 22.

[0022] Fig. 5(a) is a schematic cross-sectional view of the periphery of lead frame 20 in region 16 when the sidewall surface of the opening portion after the thermal cycle test is not roughened, and Fig. 5(b) is an enlarged view of region 27 shown in Fig. 5(a). As shown in Fig. 5(b), the adhesion between lead frame 20 and resin 22 is insufficient, so that voids occur between lead frame 20 and resin 22 in region 29, and solder cracks occur around solder 19 that joins lead frame 20 and pillar 55.

[0023] Therefore, by providing a lead frame 20 having a roughened sidewall surface, the anchor effect ensures sufficient adhesion between the lead frame 20 and the resin 22, and the occurrence of voids and solder cracks can be suppressed, thereby reducing defects in the semiconductor device.

[0024] The lead frame 20 can be made of, for example, copper, copper-tin alloy, copper-zirconium alloy, copper-iron alloy, and copper-chromium-tin-zinc alloy, or other copper alloy, iron-nickel alloy, or stainless steel. Iron-nickel alloys are preferable because their thermal expansion coefficient is close to that of silicon, and they cause less damage to the die bonding agent that bonds the chip and die pad made of silicon, etc., even in a heat treatment process, etc., and are advantageous when mounting a large chip. Copper or copper alloys have smaller electrical resistance and thermal resistance than iron-nickel alloys, and are suitable for products that require high-speed operation. The thermal expansion coefficient of copper or copper alloys is close to that of the resin 22, and therefore are advantageous in mounting large packages and small chips, and are suitable for microcomputers, system LSIs, etc.

[0025] [Lead frame manufacturing method] An example of a method for manufacturing a lead frame in a semiconductor device according to the present embodiment will be described. First, as shown in FIG. 6(a), a metal plate 13 is prepared. A resist mask 17a is patterned on the top and bottom of the metal plate 13, and openings are formed in the metal plate 13 by etching or the like using the resist mask 17a as a mask. Thereafter, as shown in FIG. 6(b), the resist mask 17a is removed, and the metal plate with the openings formed therein becomes the lead frame 20. The material of the metal plate 13 may be, for example, the material of the lead frame shown above. The thickness of the metal plate 13 may be, for example, about 100 to 200 μm.

[0026] 6(c), a protective seal 17b is provided on the lead frame 20. The protective seal 17b may be made of, for example, polysilicon or silicon oxide.

[0027] Next, as shown in FIG. 6(d), the lead frame 20 is roughened, and then, as shown in FIG. 6(e), the protective seal 17b is removed to manufacture the lead frame 20. When the roughening process is performed, the upper surface of the lead frame 20 is not roughened by the roughening process because the protective seal 17b is disposed on the lead frame 20. It is preferable that the upper surface of the lead frame 20 is not roughened in order to ensure the bonding strength with the solder. By roughening only the side wall surface of the lead frame at the opening, the bonding strength between the lead frame and the solder can be ensured by suppressing the diffusion of the solder while ensuring the adhesion between the lead frame and the resin.

[0028] Furthermore, when roughening the lead frame 20, the sidewall surface and the top surface of the opening may be roughened without using the protective seal 17b as shown in Fig. 7(a) after removing the resist mask, and then the top surface that does not need roughening may be polished or tapped to make it flat as shown in Fig. 7(b). Furthermore, if the roughening of the top surface of the lead frame is to an extent that does not significantly contribute to the bonding strength between the lead frame and the solder, the process of making the roughened surface flat may not be performed.

[0029] Alternatively, after the roughening treatment, the metal plate may be punched out to produce a lead frame.

[0030] The region 11 including the pillar 55 in FIG. 1 will be described with reference to FIG. 8. An insulating layer 32 and an insulating layer 34 are provided on the metal layer 30, and a metal layer 38, a metal layer 40, and a metal layer 42 are provided on the insulating layer 34. The metal layer 38 is electrically connected to the metal layer 30 via a plug 36 provided in the insulating layer 32 and the insulating layer 34. Furthermore, a resin 44 is provided to cover the insulating layer 34 and the metal layer 42. The pillar 55 is made of a laminate of a metal layer 46, a metal layer 48, a metal layer 50, and a metal layer 52, and is electrically connected to the metal layer 42 via an opening provided in the resin 44. In addition, the thin metal layer 46 constituting the pillar 55 functions as a seed layer.

[0031] Here, the pillar 55 will be described with reference to FIG.

[0032] The overlap W1 between the end of the resin 44 and the pillar 55 is, for example, 5 to 20 μm. The overlap W2 between the resin 44 and the metal layer 38 (or the metal layer 40 or 42) is, for example, 15 to 35 μm.

[0033] In addition, two or more pillars 55 may be provided, and the pillar arrangement can be designed in various ways, such as a 3 row x 4 column arrangement (12 pillars), a 3 row x 5 column arrangement (15 pillars), a 5 row x 5 column arrangement (25 pillars), a 3 row x 5 column arrangement with pillars only on the periphery (12 pillars), or a 5 row x 5 column arrangement with pillars only on the periphery and center (e.g., 19 or 21 pillars).

[0034] Furthermore, it is preferable that the pitch distance P between one pillar 55 and another pillar 55 closest thereto is, for example, 150 to 250 μm, since this increases the bonding area with the lead frame 20 and increases the bonding strength.

[0035] Similarly to the pillars 55, there may be two or more metal layers 38 (and metal layers 40 and 42) above which the pillars 55 are arranged, and the number of metal layers 38 and the number of pillars 55 may be the same or different. For example, a configuration may be used in which two pillars 55 are arranged on one metal layer 38. The distance PE between one metal layer 38 and another closest metal layer 38 is, for example, 10 to 100 μm.

[0036] Pillar 55 may include at least one selected from the group consisting of copper, nickel, tin, and silver. For example, metal layer 46 and metal layer 48 may be made of copper, metal layer 50 may be made of nickel, and metal layer 52 may be made of a tin-silver alloy.

[0037] The width of the pillar 55 is, for example, 50 to 200 μm, the total thickness of the metal layers 46 and 48 constituting the pillar 55 is, for example, 35 to 45 μm, the thickness of the metal layer 50 constituting the pillar 55 is, for example, 2 to 5 μm, and the thickness of the metal layer 52 constituting the pillar 55 is, for example, 15 to 30 μm. The height H of the pillar 55 is, for example, 55 to 75 μm.

[0038] The metal layer 38, the metal layer 40, and the metal layer 42 may each independently include at least one selected from the group consisting of copper, silver, gold, nickel, and palladium, and may have a single-layer structure or a multi-layer structure. For example, the metal layer 38 may be made of copper, the metal layer 40 may be made of nickel, and the metal layer 42 may be made of palladium. The thicknesses of the metal layers 38 and 40 may each independently be, for example, about 1 to 10 μm, and the thickness of the metal layer 40 may be, for example, about 0.05 to 2 μm. The thickness of the metal layer 42 may be thinner than the metal layers 38 and 40 in terms of adhesion to the upper layer.

[0039] A thermosetting resin can be used for the resin 44. For example, a polyimide resin may be used as the thermosetting resin. In addition, by forming the end of the resin 44 to be rounded, it is preferable that the coverage of the metal layer 46 at the end of the resin 44 can be improved when the metal layer 46 is formed.

[0040] The semiconductor substrate 10 is disposed below the pillar 55 and the metal layer 38. The semiconductor substrate 10 includes a semiconductor element layer 60 including a semiconductor element, an interlayer insulating layer 62, a wiring layer 63, an insulating layer 64, a wiring layer 65, an insulating layer 66, a metal layer 30, an insulating layer 68, an insulating layer 70, and a plug 36. The pillar 55 is electrically connected to the semiconductor element in the semiconductor element layer 60 via the metal layer 42, the metal layer 40, the metal layer 38, the plug 36, the metal layer 30 functioning as a wiring layer, the wiring layer 65, the wiring layer 63, and the like. The insulating layer 68, the insulating layer 70, and the metal layer 30 may have a configuration as shown in FIG. 8 (insulating layer 32, insulating layer 34, metal layer 30).

[0041] The interlayer insulating layer 62, the insulating layer 64, the insulating layer 66, the insulating layer 68, and the insulating layer 70 may each independently be made of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, tantalum oxide, or the like, and may have a single-layer structure or a multilayer structure. Note that the insulating layer 70 is preferably made of silicon nitride or aluminum oxide, which has a function of blocking the diffusion of impurities.

[0042] The wiring layer 63, the wiring layer 65, the metal layer 30, and the plug 36 may each independently be made of at least one type selected from the group consisting of tungsten, titanium, aluminum, copper, an aluminum alloy, and a copper alloy, and may have a single layer structure or a multilayer structure.

[0043] [Method of manufacturing semiconductor device] A method for manufacturing a semiconductor device in which a structure including a semiconductor substrate 10, pillars 55, etc. is provided on a lead frame 20 will be described.

[0044] First, as shown in Fig. 10(a), an opening is formed in each lead frame 20, and a roughening process is performed on the sidewall surface of the opening to make it rough. Next, as shown in Fig. 10(b), pillars 55 are formed on the semiconductor substrate 10. Next, as shown in Fig. 10(c), a structure including the semiconductor substrate 10 and the pillars 55 is stacked on each lead frame 20 in a face-down state by inverting the structure upside down. Specifically, the electrode terminals of the semiconductor element included in the semiconductor substrate 10 are joined and electrically connected to each lead frame 20 via the pillars 55 and solder.

[0045] Next, as shown in FIG. 10(d), the lead frames 20, the semiconductor substrate 10, and the pillars 55 are sealed with a resin 22. The resin 22 is filled into the roughened openings. For example, a molding resin containing a filler in an epoxy resin can be used as the resin 22. The resin 22 can be formed by, for example, a transfer molding method or a compression molding method. The resin 22 may be formed so as to expose the entire back surface of the semiconductor substrate 10, or may be formed so as to cover a part or all of the back surface of the semiconductor substrate 10.

[0046] Furthermore, resin 22 penetrates into the minute irregularities on the side wall surface of lead frame 20 and hardens to seal it, thereby ensuring sufficient adhesion between lead frame 20 and resin 22 and suppressing the occurrence of voids and solder cracks, thereby reducing defects in the semiconductor device.

[0047] Next, the lead frames 20, the semiconductor substrate 10, the pillars 55, and the like sealed with the resin 22 are cut into individual pieces, thereby completing a plurality of semiconductor devices. The cutting can be performed by using a slicer or the like, for example.

[0048] Through the above steps, a semiconductor device including a lead frame having a roughened sidewall surface can be obtained.

[0049] [Module Layout] 11 is a layout diagram of a module including a semiconductor device according to one aspect of the present embodiment. The semiconductor device (semiconductor chip 74) in the module includes a lead frame 20 and pillars 55.

[0050] 12 is a layout diagram of the module with some of the configuration in FIG. 11 omitted. The outer end of the module is surrounded by openings 25 (25E, 25M1, 25M2, 25M3, 25M4, etc.) provided in lead frame 20. Openings 25 are designed to hold resin 22, and providing openings 25 makes it possible to prevent resin from overflowing and to apply and form the resin uniformly. The shape of openings 25 is not particularly limited, but is preferably rounded so that resin 22 can be filled into the fine details of the opening.

[0051] 13, the sidewall surface of the opening 15 is roughened by roughening treatment. The opening 15 has a first region 71 having a first opening width WH1 and a second region 72 having a second opening width WH2 narrower than the first opening width WH1. The first region 71 is located above the second region 72. The depth of the opening 25 is shallower than the opening 15, for example, 80 to 100 μm. Furthermore, the opening 25 is located closer to the outer end of the lead frame 20 than the opening 15, which contributes to suppressing the above-mentioned overflow of the resin and making the resin evenly applied and formed.

[0052] Furthermore, since opening 25 and second region 72 of opening 15 can be formed simultaneously, the depth of opening 25 is the same as the depth of second region 72. Note that in this specification and the like, "same" includes values ​​within a range of ±5%.

[0053] [package] A package including a semiconductor device according to one embodiment of the present invention will be described with reference to Fig. 14. Fig. 14(a) is a perspective view of a package including a semiconductor device according to one embodiment of the present invention, and Fig. 14(b) is a bottom view of the package.

[0054] This package is an example of a QFN (Quad Flat No Lead Package) suitable for miniaturization and high integration, and can be used in portable electronic devices such as smartphones. The outer lead part of the lead frame is also sealed with resin, and the terminal electrodes to be soldered to the mounting board are formed on the back side of the package as shown in Figure 14(b). In addition, since the terminal electrodes are fixed with resin, they do not deform during handling, and the pitch can be made narrower. The package is not limited to QFN, and may be QFP (Quad Flat Package), SOP (Small Outline Package), TSSOP (Thin Shrink Small Outline Package), SOJ (Small Outline J-leaded), etc.

[0055] [application] A module or package including the semiconductor device according to one aspect of the embodiment can be used in various applications, such as, for example, smartphones, tablet terminals, personal computers, wearable terminals, data terminals, barcode scanners, battery chargers, surveillance cameras, gas alarms, medical equipment, healthcare equipment, industrial equipment such as robots, car navigation systems, engine control units, electric power steering, in-vehicle equipment such as in-vehicle camera modules, AV equipment such as TVs, home theaters, audio equipment, home appliances such as air conditioners, refrigerators, rice cookers, hair dryers, etc. By including the semiconductor device according to one aspect of the embodiment, it is possible to provide the above-mentioned equipment and products that have reduced defects and ensure high reliability.

[0056] [Other embodiments] As described above, several embodiments have been described, but the descriptions and drawings forming a part of the disclosure are illustrative and should not be understood as limiting. From this disclosure, various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art. Thus, the present embodiment includes various embodiments not described herein. [Industrial Applicability]

[0057] The semiconductor device of the present embodiment and the manufacturing method thereof can also be used in various semiconductor module technologies such as IGBT modules, diode modules, and MOS modules (Si, SiC, GaN, AlN, gallium oxide), and can be applied to a wide range of application fields such as inverter circuit modules that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and inverter circuit modules that convert power generated by solar cells, wind power generators, and other power generation devices (especially private power generation devices) into power from a commercial power source.

[0058] Furthermore, the semiconductor device of the present embodiment can reduce defects due to heat and has excellent heat resistance, and therefore can be used in an on-vehicle module that ensures on-vehicle reliability. [Explanation of symbols]

[0059] Reference Signs List 10...semiconductor substrate, 11...region, 12...region, 13...metal plate, 14...region, 15...opening, 16...region, 17a...resist mask, 17b...protective seal, 18...region, 19...solder, 20...lead frame, 21...region, 22...resin, 23...void, 24...region, 25...opening, 26...region, 27...region, 28...region, 29...region, 30...metal layer, 32...insulating layer , 34...insulating layer, 36...plug, 38...metal layer, 40...metal layer, 42...metal layer, 44...resin, 46...metal layer, 48...metal layer, 50...metal layer, 52...metal layer, 55...pillar, 60...semiconductor element layer, 62...interlayer insulating layer, 63...wiring layer, 64...insulating layer, 65...wiring layer, 66...insulating layer, 68...insulating layer, 70...insulating layer, 71...first region, 72...second region, 74...semiconductor chip

Claims

1. a lead frame including a first opening and a second opening, the first opening and the second opening having a first opening width portion and a second opening width portion having a width smaller than that of the first opening width portion; A resin filled in the first opening; A semiconductor element; a pillar electrically connecting the lead frame and the semiconductor element and having a plurality of metal layers; Each of the first opening width portion and the second opening width portion has a side wall surface that forms a rounded concave surface, One end of the pillar faces the lead frame and the other end of the pillar faces the semiconductor element, in a cross-sectional view, both side ends of one of the plurality of metal layers provided on the semiconductor element side protrude toward the lead frame side beyond a central portion of the one metal layer on the lead frame side and have a rounded shape; a bottom surface of a central portion of the first metal layer on the lead frame side is formed between both side ends of the first metal layer; A semiconductor device, wherein the surfaces of both side ends of the first metal layer are formed so as to become steeper in cross section as they approach the bottom surface.

2. The second opening width portion and the second opening are provided on a first surface side facing the pillar of the lead frame, The semiconductor device according to claim 1 , wherein the first opening width portion is provided on a second surface side of the lead frame opposite to the first surface.

3. The semiconductor device according to claim 1 , wherein the second opening is shallower than the first opening.

4. The semiconductor device according to claim 3 , wherein the second opening is closer to an outer end of the lead frame than the first opening.

5. 5. The semiconductor device according to claim 1, wherein an outer end of said semiconductor device is surrounded by said second opening.

6. 6. The semiconductor device according to claim 1, wherein the pillar includes at least one type selected from the group consisting of copper, nickel, tin, and silver.

7. A module comprising a semiconductor device according to any one of claims 1 to 6.

8. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, comprising the steps of: performing a roughening treatment on the lead frame; forming the pillar on a semiconductor substrate comprising the semiconductor element; bonding the pillar to the lead frame; and filling the first opening with the resin.

9. The method for manufacturing a semiconductor device according to claim 8 , wherein the roughening treatment is performed on a side wall surface of the first opening and a side wall surface of the second opening.

10. The method for manufacturing a semiconductor device according to claim 8 , wherein the roughening treatment is performed by applying a roughening liquid or by immersing the substrate in the roughening liquid.

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