Bus transceiver with ring suppression

Abstract

The transceiver (100) includes a driver stage (140) and a transition-triggered ring suppression circuit (120). The driver stage (140) has a first transistor (M1) coupled between a supply voltage terminal and a first bus terminal and a second transistor (M4) coupled between ground and a second bus terminal. The transition-triggered ring suppression circuit (120) is coupled to the first and second transistors (M1, M4). The transition-triggered ring suppression circuit (120) is configured to be enabled when the transceiver (100) transitions from a dominant state to a recessive state. Furthermore, while the transceiver (100) is in the recessive state, the transition-triggered ring suppression circuit (120) is configured to damp ringing at at least one of the first or second bus terminals.

Description

[Technical field]

[0001] Controller Area Network (CAN) is a bus standard designed to allow microcontrollers and devices to communicate with each other in applications without a host computer. The CAN bus protocol is a message-based protocol that is particularly suited to the multiplexed electrical wiring in automobiles, but is also useful in other applications. Summary of the Invention

[0002] In one example, a transceiver includes a driver stage and a transient triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between ground and a second bus terminal. The transient triggered ring suppression circuit is coupled to the first and second transistors. The transient triggered ring suppression circuit is configured to be enabled when the transceiver transitions from a dominant state to a recessive state. The transient triggered ring suppression circuit is also configured to dampen ringing on at least one of the first or second bus terminals while the transceiver is in the recessive state.

[0003] For a detailed description of various examples, reference will now be made to the accompanying drawings. [Brief description of the drawings]

[0004] [Figure 1] 1 illustrates an example of a CAN bus transceiver that includes a transient triggered ring suppression circuit.

[0005] [Diagram 2] 4 shows an example signal waveform of ringing on a CAN bus without a transient triggered ring suppression circuit in the transceiver.

[0006] [Diagram 3]2 shows example signal waveforms illustrating damped ringing on the CAN bus for the transceiver of FIG. 1 having a transient-triggered ring suppression circuit; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] As CAN bus speeds increase, so does ringing on the bus due to improper electrical termination. When a CAN bus transceiver transitions from a "dominant" to a "recessive" state, reflections from improperly terminated stubs can cause ringing on the transceiver. If the magnitude of the ringing is high enough, the transceiver misinterprets the ringing as a dominant bit. Thus, the ringing can cause bit errors. Examples described herein include a CAN bus transceiver that includes a transient-triggered ring suppression circuit that is enabled when the transceiver transitions to a recessive state. Any ringing on the bus is attenuated via the transient-triggered ring suppression circuit, resulting in a ringing signal of smaller amplitude and shorter duration, which results in fewer bit errors. The transient-triggered ring suppression circuit described herein is also applicable to other bus protocols besides CAN.

[0008] FIG. 1 illustrates an example of at least a portion of a CAN bus transceiver 100. The CAN bus transceiver 100 includes a transmitter 101 and a receiver 150. CAN BUS terminals are denoted CANH and CANL. The receiver 150 is coupled to CANH and CANL to receive a signal transmitted by another transceiver on the bus and outputs a received signal RxD to other logic (not shown). The receiver 150 includes a differential resistor Rid between CANH and CANL. The transmitter 101 includes a pulse generator 110, a voltage buffer 115, a transient triggered ring suppression circuit 120, a nulling circuit 130, and a driver stage 140. The voltage buffer 115 generates a voltage equal to one-half the supply voltage on a common voltage terminal (VCM) in one example.

[0009] The driver stage 140 includes transistors M1-M5 and a driver 142. M1, M3, and M6 are p-type metal oxide semiconductor field effect transistors (PMOS), and M2, M4, and M5 are n-type metal oxide semiconductor field effect transistors (NMOS). As PMOS or NMOS devices, each such transistor includes a control input (gate) and current terminals (source and drain). Other types of transistors may also be used, such as bipolar junction transistors that also have a control input (base) and current terminals (collector and emitter).

[0010] M1-M3 are connected in series between a supply voltage terminal (VCC) and CANH, with the source of M1 coupled to VCC, the drain of M1 connected to the source of M2 at node N1, the drain of M2 connected to the source of M3 at node N2, and CANH taken from the drain of M3. Similarly, M4-M6 are connected in series between ground and CANL, with the source of M4 coupled to ground, the drain of M4 connected to the source of M5 at node N3, the drain of M5 connected to the source of M6 at node N4, and CANL taken from the drain of M6. A termination resistor Rterm (e.g., 120 ohms) is connected between CANH and CANL, although the transceiver could be terminated in other ways (e.g., with a 60 ohm resistor connected in series between CANH and CANL and a capacitor connected between the node between the resistor and ground).

[0011] The gates of PMOS transistors M3 and M6 are connected to ground, so that M3 and M4 remain on continuously. The sources of M3 and M6 remain fixed at the transistor threshold voltages above ground (e.g., 0.7V). M3 and M6 act to block large negative voltages from the respective bus terminals CANH or CANL from damaging the transceiver. The gates of M2 and M5 are connected to VCC, which blocks large positive voltages from the respective bus terminals CANH or CANL from damaging the transceiver.

[0012] Driver 142 receives a transmit signal TxD on its input and drives complementary outputs 143 and 144, which are connected to the gates of M1 and M4, respectively. CANH and CANL are either driven to a dominant state with the CANH voltage higher than the CANL voltage, or are not driven and pulled to a recessive state by a passive resistor with the CANH voltage equal to or lower than the CANL voltage. A "0" data bit encodes a dominant state, and a "1" data bit encodes a recessive state. In a dominant state, TxD is set equal to 0, and in a recessive state, TxD is set equal to 1. When TxD is 0 (dominant state), output 143 of driver 142 is 0 (low) and output 144 is 1 (high). When output 143 is 0 and output 144 is 0, both PMOS transistor M1 and NMOS transistor M4 are turned on, which pulls CANH up towards VCC and CANL down towards ground. According to the CAN bus protocol, in the dominant state, the CAN bus differential voltage is nominally 2V. In the recessive state, TxD is 1, so the output 143 of the driver 142 is 1 and the output 144 is 0, and both M1 and M4 are turned off. With M1 and M4 off, the voltage on CANH and CANL is passively approximately equal to VCM through resistors Rterm and Rid. In the above example, VCM is equal to VCC / 2. In an application where VCC is 5V, VCM is 2.5V, and in the recessive state, CANH and CANL are both approximately equal to 2.5V (approximately zero differential voltage).

[0013] The recessive nullification circuit includes NMOS transistors M7-M12. The gates of M7 and M8 are both connected to the pulse generator 110. The drain of M7 is connected to the drain of M1 and the source of M2 (node ​​N1). M9 is connected between the drain of M8, the drain of M2, and the source of M3 (node ​​N2). M9 may be biased on and operative to prevent a large positive voltage on N2 from damaging the transceiver. The sources of M7 and M8 are both connected to the sources of M10 and M11. The gates of M10 and M11 are both connected to the pulse generator 110. The drain of M10 is connected to the drain of M4 and the source of M5 (node ​​N3). M12 is connected between the drain of M11, the drain of M5, and the source of M6 (node ​​N4). M12 is biased on and operative to prevent a large positive voltage on N4 from damaging the transceiver.

[0014] Pulse generator 110 generates pulses 114 and 116 on outputs 111 and 112, respectively, in response to a 0 to 1 transition of TxD. The width of the pulse may be fixed or programmable. In one example, the width is 200 nanoseconds. During the pulse, M7, M8, M10, and M11 are on. Recessive disable circuit 130 functions to force each of nodes N1-N4 to equal VCM for a short period of time (e.g., 200 ns) upon the recessive node transition to help force the voltages on CANH and CANL to equal each other and VCM. When pulses 114 and 116 end, CAN and CANL remain at VCM.

[0015] The transition triggered ring suppression circuit 120 helps suppress ringing on the CAN bus during a transition from a dominant state to a recessive state. The transition triggered ring suppression circuit 120 includes switches SW1 and SW2, resistors R1 and R2, capacitors C1 and C2, and NMOS transistors M21 and M22. SW1 is coupled between VCC and the gate of M21. In one example, SW1 may be a PMOS transistor. R1 is also coupled between VCC and the gate of M21. C1 is coupled between the source and gate of M21. SW2 is coupled between ground and the gate of M22. In one example, SW may be an NMOS transistor. R2 is also coupled between ground and the gate of M22. C2 is coupled between the gate and drain of M21.

[0016] During the dominant state (TxD is 0), M1 is on. When M1 is on, node N1 is pulled up to VCC, so the source of M21 is VCC. The source of M22 is coupled to VCM. During the dominant state, control signals 121 and 122 cause switches SW1 and SW2 to close. In this example, control signals 121 and 122 are generated by pulse generator 110. If SW1 is implemented as a PMOS transistor, control signal 121 may be asserted by pulse generator 110 to track the logic state of TXD (i.e., when TXD is high, control signal 121 is forced high and vice versa). If SW2 is implemented as an NMOS transistor, control signal 122 may be asserted by pulse generator 110 to track the logic inverse of the logic state of TXD (i.e., when TXD is high, control signal 122 is forced low and vice versa). In one example, pulse generator 110 includes a buffer (with positive and negative outputs) for generating control signals 121 and 122. When SW1 is closed, the gate of M21 is pulled up to VCC. Thus, the gate-source voltage across M21 is insufficient to turn M21 on, so M21 is turned off. When SW2 is closed, the gate of M22 is pulled, keeping M22 in the off state.

[0017] Upon entering the recessive state, the control signals 121 and 122 change logic states, opening the switches SW1 and SW2, thereby enabling the transition-triggered ring suppression circuit. R1 pulls the gate of M21 high, thereby keeping M21 in the off state. However, if there is a ringing signal on CANH, it propagates through M3 and M2 to the capacitor C1. The ringing signal causes C1 to charge, and if the magnitude of the ringing signal is large enough, C1 may be charged to a voltage large enough to turn on M21 (at least a threshold voltage above VCM). The resistor R1, connected between VCC and the gate of M21, discharges the gate of M21, thereby eventually causing M21 to turn on. As such, the ringing signal on CANH is dissipated through the portion of the transition-triggered ring suppression circuit 120 coupled to CANH (i.e., R1, C1, and M21).

[0018] In the recessive state and on the CANL side of the bus, R2 pulls the gate of M22 low, thereby keeping M22 off. Any ringing signal on CANL propagates through M6 and M5 to capacitor C2. C2 charges due to the ringing signal, and if the magnitude of the ringing signal is large enough, C2 charges to a voltage large enough to turn on M22 (at least a threshold voltage above the source of M22, which is connected to VCM). Resistor R2, connected between ground and the gate of M22, discharges the gate of M22, thereby eventually causing M22 to turn on. As such, the ringing signal on CANL is dissipated through the portion of the transition-triggered ring suppression circuit 120 coupled to CANL (i.e., R2, C2, and M22).

[0019] FIG. 2 illustrates the potential levels of CANH and CANL during a dominant state and upon transition to a recessive state for a CAN bus transceiver that does not have a transition-triggered ring suppression circuit 120. The top curve shows the CANH and CANL signals, and the bottom curve is the differential voltage (i.e., CANH-CANL). During the dominant state, CANH is 3.5V and CANL is 1.5V, so the differential voltage is 2V. Upon entering the recessive state, the CANH and CANL voltage levels approach each other at approximately VCM, which in this example is 2.5V. However, in the example of FIG. 1, upon entering the recessive state, ringing 210 occurs. The magnitude of the ringing signal decreases over time. The initial ringing peak, shown at 220, is high enough to cause bit errors in the transceiver, which misinterprets the ringing as a new dominant state.

[0020] 3 illustrates CANH and CANL during a dominant state and upon transition to a recessive state for a CAN bus transceiver having the transition-triggered ring suppression circuit 120 described above. As can be seen, the magnitude of the ringing 310 is attenuated compared to the ringing 210 in FIG. 2, and the peak ringing level 320 is not large enough to cause bit errors. Additionally, the ringing 310 dissipates much more quickly than the ringing 210.

[0021] The term "couple" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with the description of this disclosure. For example, in a first example, device A is coupled to device B if device A generates a signal to control device B to perform an action, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A where intervening component C does not substantially change the functional relationship between devices A and B.

[0022] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. A transceiver comprising: A driver stage, a first transistor coupled between a supply voltage terminal and a first bus terminal, the first transistor having a current terminal coupled to the first bus terminal; a second transistor coupled between ground and a second bus terminal, the second transistor having a current terminal coupled to the second bus terminal; the driver stage including a third transistor coupled between the common voltage terminal and the terminal of the first transistor, the third transistor having a control input and first and second current terminals; a first capacitor coupled between a first current terminal of the third transistor and a control input of the third transistor; a first resistor coupled between the supply voltage terminal and a control input of the third transistor; a first switch coupled between the supply voltage terminal and a control input of the third transistor; Including a transceiver.

2. 2. The transceiver of claim 1, A transceiver configured such that the first switch is on during a first state of the transceiver and is off during a second state of the transceiver.

3. 3. The transceiver of claim 2, The transceiver is a controller area network (CAN) bus transceiver, the first state being a dominant state and the second state being a recessive state.

4. 2. The transceiver of claim 1, The transceiver further includes a voltage buffer having an output coupled to the common voltage terminal.

5. 2. The transceiver of claim 1, a fourth transistor coupled between the current terminal of the second transistor and the common voltage terminal, the fourth transistor having a control input and first and second current terminals; a second capacitor coupled between the first current terminal of the fourth transistor and a control input of the fourth transistor; a second resistor coupled between said ground and a control input of said fourth transistor; a second switch coupled between said ground and a control input of said fourth transistor; The transceiver further comprises:

6. 6. The transceiver of claim 5, the transceiver further comprising a transmitter driver having a driver input configured to receive a transmit signal, a first output coupled to a control input of the first transistor, and a second output coupled to the control input of the second transistor.

7. 6. The transceiver of claim 5, the first switch is configured to be on during a first state of the transceiver and off during a second state of the transceiver; The transceiver, wherein the second switch is configured to be on during a first state of the transceiver and off during a second state of the transceiver.

8. 8. The transceiver of claim 7, the transceiver is a controller area network (CAN) bus transceiver, the first state is a dominant state and the second state is a recessive state; The transceiver further includes a voltage buffer having an output for providing a common voltage to the common voltage terminal.

9. 2. The transceiver of claim 1, the transceiver further comprising a recessive nulling circuit coupled to the common voltage terminal, the current terminal of the first transistor, and the current terminal of the second transistor, the recessive nulling circuit configured to drive the current terminals of the first and second transistors to the voltage on the common voltage terminal for a period of time upon a transition of the transceiver from a dominant state to a recessive state.

10. A transceiver comprising: a driver stage including a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between ground and a second bus terminal; a transition-triggered ring suppression circuit coupled to the first and second transistors and configured to be enabled when the transceiver transitions from a dominant state to a recessive state and to dampen ringing on at least one of the first or second bus terminals while the transceiver is in the recessive state; a third transistor coupled between a terminal of the second transistor and a common voltage terminal, the third transistor having a control input and first and second current terminals; a first capacitor coupled between a second current terminal of the third transistor and a control input of the third transistor; a first resistor coupled between said ground and a control input of said third transistor; a first switch coupled between said ground and a control input of said third transistor; a transition-triggered ring suppression circuit, Including a transceiver.

11. 11. The transceiver of claim 10, the transition triggered ring suppression circuit comprising: a fourth transistor coupled between the common voltage terminal and a terminal of the first transistor, the fourth transistor having a control input and first and second current terminals; a second capacitor coupled between the first current terminal of the fourth transistor and a control input of the fourth transistor; a second resistor coupled between the supply voltage terminal and a control input of the fourth transistor; a second switch coupled between the supply voltage terminal and a control input of the fourth transistor; The transceiver further comprises:

12. 11. The transceiver of claim 10, The transceiver is configured such that the first switch is on during the dominant state and is off during the recessive state.

13. 11. The transceiver of claim 10, The transceiver further includes a voltage buffer having an output coupled to the common voltage terminal.

14. A transceiver comprising: a driver stage including a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between ground and a second bus terminal; a transition-triggered ring suppression circuit coupled to the first and second transistors and configured to be enabled upon a transition of the transceiver from a dominant state to a recessive state and to suppress ringing on at least one of the first and second bus terminals while the transceiver is in the recessive state; a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the third transistor having a control input and first and second current terminals; a first capacitor coupled between a first current terminal of the third transistor and a control input of the third transistor; a first resistor coupled between the supply voltage terminal and a control input of the third transistor; a first switch coupled between the supply voltage terminal and a control input of the third transistor; the transition triggered ring suppression circuit comprising: Including a transceiver.

15. A transceiver comprising: A driver stage, a first transistor coupled between a supply voltage terminal and a first bus terminal, the first transistor having a current terminal coupled to the first bus terminal; a second transistor coupled between ground and a second bus terminal, the second transistor having a current terminal coupled to the second bus terminal; the driver stage including a third transistor coupled between a common voltage terminal and a current terminal of the first transistor, the third transistor having a control input and first and second current terminals; a first capacitor coupled between a first current terminal of the third transistor and a control input of the third transistor; a first resistor coupled between the supply voltage terminal and a control input of the third transistor; a first switch coupled between the supply voltage terminal and a control input of the third transistor; a fourth transistor coupled between a terminal of the second transistor and the common voltage terminal, the fourth transistor having a control input and first and second current terminals; a second capacitor coupled between the first current terminal of the fourth transistor and a control input of the fourth transistor; a second resistor coupled between said ground and a control input of said fourth transistor; a second switch coupled between said ground and a control input of said fourth transistor; Including a transceiver.

16. 16. The transceiver of claim 15, The transceiver further comprising a voltage buffer having an output coupled to second current terminals of the third and fourth transistors, the voltage buffer configured to generate a common voltage on the common voltage terminal.

17. 17. The transceiver of claim 16, a recessive nulling circuit coupled to the common voltage terminal, the current terminal of the first transistor, and the current terminal of the second transistor, the recessive nulling circuit configured to cause a voltage on the current terminals of the first and second transistors to become the voltage on the common voltage terminal for a period of time during a transition of the transceiver from a first state to a second state.

18. 16. The transceiver of claim 15, The transceiver, wherein the transceiver is a Controller Area Network (CAN) bus transceiver.

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