High voltage isolation barrier with electrical overstress integrity

Abstract

The electronic device (100) includes a multi-level metallization structure (103) on a semiconductor layer (101) including a first region (196), a second region (198), a pre-metal level (110) on the semiconductor layer, and N metallization structure levels (120, 130, 140, 150, 160, 170, 180) greater than three on the pre-metal level. The electronic device also includes an insulating component (104) in the first region, the insulating component including first terminals (106) and second terminals (108) of different respective metallization structure levels (130, 180) and a conductive shield (105) between the first region and the second region in the multi-level metallization structure, the conductive shield including respective interconnected metal lines (126, 136, 146, 156, 166, 176, 186) and trench vias (118, 128, 138, 148, 158, 168, 178) in the metallization structure levels surrounding the first region.

Description

[Background technology]

[0001] Many circuits contain circuit elements in multiple voltage domains, such as low-voltage logic circuit elements in a low-voltage domain and communication driver circuitry in a second high-voltage domain. In normal operation, a high-voltage digital isolator provides a communication channel between different voltage domains while protecting the low-voltage circuitry against device degradation due to harmful currents or voltages to the high-voltage domain. An electrical overstress (EOS) event in a circuit element near a high-voltage isolation barrier component can potentially damage the high-voltage barrier, such that the high-voltage barrier is no longer able to isolate the low-voltage circuit elements from the high-voltage domain. Summary of the Invention

[0002] In one embodiment, an electronic device includes a multi-level metallization structure over a semiconductor layer, and an insulating component in a first region and a conductive shield between the first region and a second region of the metallization structure. The metallization structure includes a pre-metal level over the semiconductor layer and a metallization structure level over the pre-metal level. The insulating component includes first and second terminals in different metallization structure levels. The conductive shield includes interconnected metal lines and trench vias surrounding the first region in each metallization structure level. In one example, the insulating component is a capacitor. In another example, the insulating component is a transformer. In one example, the second terminal of the insulating component is at the top or final metallization structure level and includes an exposed side. In one example, the first region includes a plurality of insulating components. In one example, one of the metallization structure levels includes a metal line with a gap and a metal routing feature that extends through the gap and connects to the first terminal of the insulating component. The conductive shield in one example has a step shape in side view.

[0003] In another aspect of the disclosure, a packaged electronic device is provided. The packaged electronic device includes a first and a second semiconductor die within the device. The die and electrical connections are encapsulated in a package structure with partially exposed leads. The first semiconductor die includes a semiconductor layer, a multilevel metallization structure with first and second regions on the semiconductor layer, an insulating component in the first region of the metallization structure, and a conductive shield with metal lines and trench vias interconnected between the first and second regions. In one example, the conductive shield has a step shape. In one example, the insulating component is a capacitor. In another example, the insulating component is a transformer. In one example, the second die also includes a second semiconductor layer, a second multilevel metallization structure with first and second regions on the second semiconductor layer, and a second insulating component in the first region of the second metallization structure.

[0004] Another aspect provides a method, the method including forming a multi-level metallization structure over a semiconductor layer including first and second regions, the conductive shield including metal lines and trench vias interconnected between the first and second regions. The method also includes separating a first semiconductor die including the semiconductor layer and the multi-level metallization structure from a wafer, forming an electrical connection between a second terminal of the insulating component and a conductive feature of the second semiconductor die, and encapsulating the first semiconductor die, the second semiconductor die, and the electrical connection within a package structure including exposed conductive leads along one or more sides of the package structure. [Brief description of the drawings]

[0005] [Figure 1] 1 is a partial cross-sectional side view of an electronic device comprising an isolation capacitor in a first region surrounded by a conductive shield in a multilevel metallization structure over a semiconductor layer.

[0006] [Diagram 2] FIG. 2 is a partial top plan view of the electronic device of FIG. 1 taken along line 2-2.

[0007] [Diagram 3] FIG. 3 is a partial top plan view of the electronic device of FIG. 1 taken along line 3-3.

[0008] [Figure 4] FIG. 4 is a schematic diagram of a packaged electronic device including the device of FIGS. 1-3.

[0009] [Diagram 5] 1 is a flow chart of a method of fabricating a packaged electronic device.

[0010] [Figure 6] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 7] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 8] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 9] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 10] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 11] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 12] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 13] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 14] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 15] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 16] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 17] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 18] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 20] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 21] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 22] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 23] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Figure 24] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5. [Diagram 25] 6 is a partial cross-sectional side view of the device of FIGS. 1-3 undergoing metallization structure fabrication processing in accordance with the method of FIG. 5.

[0011] [Figure 26] FIG. 2 is a partial top plan view showing a portion of a leadframe having a semiconductor die attached thereto that receives wire bonds.

[0012] [Figure 27] FIG. 1 is a perspective view of a packaged electronic device.

[0013] [Figure 28]1 is a partial cross-sectional side view of another electronic device including an isolation transformer in a first region surrounded by a conductive shield in a multilevel metallization structure over a semiconductor layer.

[0014] [Figure 29] FIG. 29 is a partial top plan view of the electronic device of FIG. 28 taken along line 29-29.

[0015] [Diagram 30] FIG. 30 is a partial top plan view of the electronic device of FIG. 28 taken along line 30-30. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] In the drawings, like reference numerals refer to like elements throughout, and various features are not necessarily drawn to scale. Additionally, the term "couple" includes an indirect or direct electrical or mechanical connection, or a combination thereof. For example, when a first device couples or is coupled to a second device, the connection may be by a direct electrical connection, or an indirect electrical connection through one or more intervening devices and connections. One or more operational characteristics of the various circuits, systems, and / or components are described below in the context of the functionality that results from the configuration and / or interconnection of the various structures when the circuit elements are powered and operating.

[0017] Referring initially to FIGS. 1-3, FIG. 1 illustrates a partial cross-sectional side view of an electronic device 100, and FIGS. 2 and 3 illustrate top cross-sectional views of a portion of the electronic device 100 taken along lines 2-2 and 3-3, respectively, of FIG. 1. The electronic device 100 includes a semiconductor layer 101. In one example, the semiconductor layer 101 is or includes a p-type semiconductor material having an insulating structure 102 (e.g., a shallow trench isolation or STI structure) formed on or within the top side of the semiconductor layer 101. The semiconductor layer 101 in one example is a silicon layer, a silicon-germanium layer, a silicon-on-insulator (SOI) structure, or another layer having a semiconductor material. The electronic device 100 further includes a multilevel metallization structure 103 disposed on the top side of the semiconductor layer 101. The electronic device 100 also includes an insulating component 104 and a conductive shield 105 in the multilevel metallization structure 103.

[0018] As also described further below, insulating component 104 is in a first region of multilevel metallization structure 103, and conductive shield 105 is formed by interconnected metal lines and trench vias of the multilevel metallization structure to provide a Faraday cage around insulating component 104. Conductive shield 105 separates the first region from a second region outside multilevel metallization structure 103. In one implementation, electronic device 100 also includes additional circuit elements (e.g., low voltage logic circuitry, not shown) formed on and / or within semiconductor layer 101 below the second region outside multilevel metallization structure 103.

[0019] 1, insulating component 104 is a capacitor that includes a first (e.g., lower or bottom) terminal 106 (e.g., a first capacitor plate) that is spaced apart from semiconductor layer 101 by a distance 107 (e.g., 2.8 μm). And as further described below, conductive shield 105 in one example includes a gap in one of the constituent metal layers, and a conductive routing feature connects low voltage logic circuitry in a second region to first terminal 106 of insulating component 104. Capacitor 104 also includes a second (e.g., upper or top) terminal 108 (e.g., a second capacitor plate). While not a strict requirement of all possible implementations, in this example, first terminal 106 and second terminal 108 are generally parallel to one another. Additionally, the first terminal 106 and the second terminal 108 are separated from each other by a distance 109 (e.g., 12.7 μm), with a layer of dielectric material between the terminals 106 and 108 forming the capacitor 104. In the illustrated example, the second terminal 108 of the capacitor insulating component 104 includes an exposed top side such that the second terminal 108 can be a high voltage domain terminal (e.g., a bond wire) of a second semiconductor die (e.g., FIGS. 4 and 26 below).

[0020] The multilevel metallization structure 103 includes a premetal level 110 and an integer number N of metallization structure levels, where N is greater than 3. The example of FIGS. 1-3 includes N=7 metallization structure levels. The premetal level 110 includes a premetal dielectric (PMD) layer 111 on the semiconductor layer 101. In one example, the PMD layer 111 is or includes silicon dioxide (SiO2) and has a thickness of about 1.2 μm. The premetal level 110 includes a cylindrical contact 114 and a premetal trench contact 118 on the semiconductor layer 101. The contacts 114 and 118 extend through the PMD layer 111 along a vertical (e.g., Z) direction in FIG. 1. The trench contact 118 tightly surrounds a central first portion of the PMD layer 111 in the premetal level 110. In one example, the premetal level contact 114 and the trench contact 118 are or include tungsten. 1, a pre-metal trench contact 118 is connected to the semiconductor layer 101 to form a ground connection between the STI portions 102 and provides a bottom portion of the conductive shield 105 that acts as a grounded Faraday cage around the insulating component 104. Although not a strict requirement of all possible implementations, the pre-metal level 110 further includes trench contacts 118 in a region 119 about the periphery of the illustrated portion of the electronic device 100, for example to provide protection against cracking and mechanical stress of the device 100.

[0021] As shown in Figures 1 and 3, the multilevel metallization structure 103 also includes a first metallization structure level 120 (e.g., labeled M1 in Figure 1) on the premetal level 110. The first metallization structure level 120 includes a first interlevel dielectric (ILD) layer 121, a conductive metal line 122 and a cylindrical tungsten via 124 in a second portion of the multilevel metallization structure 103. The first metallization structure level 120 further includes a metal routing feature 125, a first metal line 126, and a routing via 127 on the metal routing feature 125 in a first portion of the multilevel metallization structure 103. In one example, the first metal line 126 is or includes aluminum metal with a thickness along the Z direction in Figure 1 of about 0.61 μm. The first metallization structure level 120 also includes a first trench via 128 on the first metal line 126. The first ILD layer 121 extends over the PMD layer 111, the metal routing feature 125, and the first metal line 126. The first metal line 126 extends at least partially over the pre-metal trench contact 118, and the first trench via 128 extends over the first metal line 126. The first trench via 128 and the first metal line 126 surround another portion of the first region of the multilevel metallization structure 103 at the first metallization structure level 120. The first ILD layer 121 in one example is or includes silicon dioxide (SiO2) and has a thickness (e.g., along the Z direction in FIG. 1) of about 1.2 μm.

[0022] As shown in FIG. 3, the metal routing feature 125 extends from the first region, through a gap G in the first metal line 126, to a second region of the first metallization level 120. Although not a strict requirement of all possible implementations, the first metallization structure 120 also includes trench vias 128 in a region 119 near the periphery of the illustrated portion of the electronic device 100, for example, to reduce cracking and mechanical stress in the device 100. Although not a strict requirement of all possible implementations, the first metallization structure level 120, and the other metallization structure levels in the examples of FIGS. 1-3, include vias 114 and trench contacts 118 that are or include tungsten. Also, although not a requirement of all possible implementations, the first metallization structure level 120 and the other metallization structure levels of the multilevel metallization structure 103 include metal lines that are or include aluminum or copper.

[0023] A second metallization level 130 (labeled M2 in FIG. 1) extends over the first metallization level 120 in the multilevel metallization structure 103. The second metallization level 130 includes a second ILD layer 131, a conductive metal line 132 in a second portion of the multilevel metallization structure 103, and a cylindrical tungsten via 134. In one example, the second ILD layer 131 is or includes silicon dioxide and has a thickness along the Z direction of about 1.2 μm. The second metallization level 130 further includes a second metal line 136 at least partially over the first trench via 128 and a second trench via 138 over the second metal line 136. In one example, the second metal line 136 is or includes aluminum metal and has a thickness along the Z direction in FIG. 1 of about 0.61 μm. The second metallization structure level 130 also includes a first terminal 106 of the insulating component 104 spaced apart from the second metal line 136 and extending at least partially over a routing via 127 on the metal routing feature 125 in a central first portion of the second metallization structure level 130. The second ILD layer 131 in this example extends over the first ILD layer 121, the second metal line 136, and the first terminal 106. A second trench via 138 extends over the second metal line 136. The second trench via 138 and the second metal line 136 surround a second portion of the first region of the second metallization structure level 130. 1, second terminal 108 of insulating component 104 includes lateral edges (left and right sides in FIG. 1), and each first metal line 126 and second metal line 136 includes opposing lateral edges that are spaced apart from the respective lateral edges of second terminal 108 along a first direction (e.g., the X-direction in FIGS. 1-3) by a respective non-zero separation distance 137. Although not a strict requirement of all possible implementations, second metallization structure 130 also includes trench vias 138 in region 119 near the periphery of the depicted portion of electronic device 100.

[0024] The multilevel metallization structure 103 also includes a third metallization level 140 (labeled M3 in FIG. 1 ). The third metallization level 140 extends over the second metallization level 130 in the multilevel metallization structure 103. The third metallization level 140 includes a third ILD layer 141, a conductive metal line 142 in a second portion of the multilevel metallization structure 103, and a cylindrical tungsten via 144. In one example, the third ILD layer 141 is or includes silicon dioxide and has a thickness of about 2.5 μm along the Z direction. The third metallization level 140 further includes a third metal line 146 at least partially over the second trench via 138, and a third trench via 148 over the third metal line 146. The third metal line 146 in one example is or includes aluminum metal and has a thickness along the Z direction in FIG. 1 of about 0.61 μm. The third ILD layer 141 in this example extends over the second ILD layer 131 and the third metal line 146. A third trench via 148 extends through the third ILD layer 141 over the third metal line 146. The third trench via 148 and the third metal line 146 surround a portion of the first region of the third metallization level 140. As shown in FIG. 1, the third metal line 146 includes lateral edges that are spaced apart along the X direction from respective lateral edges of the second terminals 108 by a non-zero separation distance 147. 1-3 has the stepped shape shown in FIG 1 with a non-zero separation distance 147 (e.g., about 30 μm) that is greater than the separation distance 137 of the preceding (e.g., underlying) second metallization structure level 130. Although not a strict requirement of all possible implementations, the third metallization structure 140 also includes trench vias 148 in the region 119 near the periphery of the depicted portion of the electronic device 100.

[0025] A fourth metallization level 150 (labeled M4 in FIG. 1 ) extends over the third metallization level 140 in the multilevel metallization structure 103. The fourth metallization level 150 includes a fourth ILD layer 151, a conductive metal line 152 in a second portion of the multilevel metallization structure 103, and a cylindrical tungsten via 154. The fourth ILD layer 151 in one example is or includes silicon dioxide and has a thickness of about 3.2 μm along the Z direction. The fourth metallization level 150 further includes a fourth metal line 156 at least partially over the third trench via 148 and a fourth trench via 158 over the fourth metal line 156. The fourth metal line 146 in one example is or includes aluminum metal and has a thickness of about 1.3 μm along the Z direction in FIG. 1 . The fourth ILD layer 151 in this example extends over the third ILD layer 141 and the fourth metal line 156. A fourth trench via 158 extends through the fourth ILD layer 151 over the fourth metal line 156. The fourth trench via 158 and the fourth metal line 156 surround a portion of a first region of the fourth metallization structure level 150. As shown in FIG. 1, the fourth metal line 156 includes lateral edges that are spaced apart along the X-direction from respective lateral edges of the second terminals 108 by a non-zero separation distance 157 (e.g., about 40 μm) that is greater than the separation distance 147 of the preceding (e.g., underlying) third metallization structure level 140. Although not a strict requirement of all possible implementations, the fourth metallization structure 150 also includes trench vias 158 in a region 119 near the periphery of the illustrated portion of the electronic device 100.

[0026] The multilevel metallization structure 103 also includes a fifth metallization level 160 (labeled M5 in FIG. 1 ) that extends above the fourth metallization level 150 in the multilevel metallization structure 103. The fifth metallization level 160 includes a fifth ILD layer 161, a conductive metal line 162 in a second portion of the multilevel metallization structure 103, and a cylindrical tungsten via 164. The fifth ILD layer 161 in one example is or includes silicon dioxide and has a thickness along the Z direction of about 3.2 μm. The fifth metallization level 160 further includes a fifth metal line 166 that is at least partially on the fourth trench via 158, and a fifth trench via 168 on the fifth metal line 166. The fifth metal line 166 in one example is or includes aluminum metal and has a thickness along the Z direction in FIG. 1 of about 1.3 μm. The fifth ILD layer 161 in this example extends over the fourth ILD layer 151 and the fifth metal line 166. A fifth trench via 168 extends through the fifth ILD layer 161 over the fifth metal line 166. The fifth trench via 168 and the fifth metal line 166 surround a portion of a first region of the fifth metallization structure level 160. As shown in FIG. 1, the fifth metal line 166 includes lateral edges that are spaced apart along the X-direction from respective lateral edges of the second terminals 108 by a non-zero separation distance 167 (e.g., about 50 μm) that is greater than the separation distance 157 of the preceding (e.g., underlying) fourth metallization structure level 150. Although not a strict requirement of all possible implementations, the fifth metallization structure 160 also includes trench vias 168 in a region 119 near the periphery of the illustrated portion of the electronic device 100.

[0027] A sixth metallization level 170 (labeled M6 in FIG. 1 ) extends above the fifth metallization level 160 in the multilevel metallization structure 103. The sixth metallization level 170 includes a sixth ILD layer 171, a conductive metal line 172 in a second portion of the multilevel metallization structure 103, and a cylindrical tungsten via 174. The sixth ILD layer 171 in one example is or includes silicon dioxide and has a thickness of about 3.2 μm along the Z direction. The sixth metallization level 170 further includes a sixth metal line 176 at least partially over the fifth trench via 168 and a sixth trench via 178 over the sixth metal line 176. The sixth metal line 176 in one example is or includes aluminum metal and has a thickness of about 1.3 μm along the Z direction in FIG. 1 . The sixth ILD layer 171 in this example extends over the fifth ILD layer 161 and the sixth metal line 176. A sixth trench via 178 extends through the sixth ILD layer 171 over the sixth metal line 176. The sixth trench via 178 and the sixth metal line 176 surround a portion of a first region of the sixth metallization structure level 170. As shown in FIG. 1, the sixth metal line 176 includes lateral edges that are spaced apart along the X-direction from respective lateral edges of the second terminals 108 by a non-zero separation distance 177 (e.g., about 70 μm) that is greater than the separation distance 167 of the preceding (e.g., underlying) fifth metallization structure level 160. Although not a strict requirement of all possible implementations, the sixth metallization structure 170 also includes trench vias 178 in a region 119 near the periphery of the illustrated portion of the electronic device 100.

[0028] The exemplary multilevel metallization structure 103 in FIGS. 1-3 has N metallization levels, where N=7. A top or top (e.g., Nth or seventh) metallization level 180 (labeled M7 in FIG. 1) extends above the sixth metallization level 170 in the multilevel metallization structure 103. The seventh metallization level 180 has a bilayer structure including a layer 181 that is or includes silicon oxynitride (SiON) and has a thickness of 0.3 μm, and a layer 182 that is or includes silicon nitride (SiN) and has a thickness of 0.55 μm. The seventh metallization level 180 further includes a protective overcoat (PO) layer 183 (e.g., SiO2) and conductive metal lines 184 in a second portion of the multilevel metallization structure 103, a portion of which connects to a conductive die pad that provides electrical conductivity to an external component (e.g., another die or conductive features of a lead frame, not shown). A silicon oxynitride layer 185 extends over a portion of layer 183 and has a thickness of 2.8 μm in one example. Layers 183 and 184 together form a protective overcoat (PO) layer.

[0029] The seventh (e.g., Nth) metallization level 180 also includes the second terminal 108 of the insulating component 104 and a seventh (e.g., Nth) metal line 186. The second terminal 108 is spaced from the Nth metal line 186 by a non-zero separation distance 187 (e.g., about 90 μm) that is greater than the separation distance 177 of the preceding (e.g., underlying) sixth metallization level 170, as shown in FIGS. 1 and 2. The layer 183 in one example is or includes silicon dioxide and has a thickness of about 4.5 μm along the Z direction. The seventh metal line 186 extends at least partially over the sixth trench via 178. The seventh metal line 186 in one example is or includes aluminum metal and has a thickness of about 3.0 μm along the Z direction in FIG. 1. Layer 183 in this example extends over bilayer structures 181, 182 and over sixth ILD layer 171 in the gap between bilayer structures 181, 182. Layer 183 also extends over a portion of second terminal 108 and over seventh metal line 186. Seventh metal line 186 surrounds the top of the first region of seventh metallization level 180 to complete conductive shield 105.

[0030] The exemplary electronic device 100 in FIGS. 1-3 includes a capacitor isolation component 104 with a first terminal 106 at a second metallization level 130 and a second terminal 108 at a seventh metallization level 180. In other implementations, each of the first terminal 106 and second terminal 108 may be present at different ones of the metallization levels 120, 130, 140, 150, 160, 170, 180. Although not a strict requirement of all possible implementations, the illustrated example further includes a stepped shape of the conductive shield 105 with increasing separation distances 137, 147, 157, 167, 177, and 187. Also, different implementations include a conductive shield with a non-stepped shape. The illustrated stepped shape advantageously provides a generally consistent spacing between the second terminal 108 of the isolation component 104 and the shield structure 105. The conductive shield 105 provides a generally continuous conductive metal (e.g., copper, tantalum nitride, titanium, titanium nitride, aluminum, tungsten) Faraday cage or shield structure that is connected to the semiconductor layer 101 by trench contacts 118 to provide a ground shield that completely surrounds the first region of the multi-level metallization structure 103. In one example, copper doped aluminum lines are sandwiched by titanium nitride and copper lines are sealed on three sides by tantalum nitride. The trench vias in some implementations are copper for a tungsten or copper damascene process or contain tungsten or copper to form the conductive shield structure 105.

[0031] In one implementation, the second terminal 108 of the isolation component 104 is electrically connected to a high voltage signal from a circuit (and, e.g., the circuit and a second semiconductor die) in a different voltage domain than the circuit elements in the second portion of the multilevel metallization structure 103. In one example, the electronic device 100 includes a low voltage logic circuit (not shown) with connection and routing structures in the second portion of the multilevel metallization structure 103, and the conductive shield 105 provides a substantially continuous isolation barrier between the second portion and the first portion of the multilevel metallization structure 103. In the illustrated implementation, the conductive shield 105 is created by interconnected metal lines 126, 136, 146, 156, 166, 176, 186 and trench contacts / vias 118, 128, 138, 148, 158, 168, 178 in each metallization structure level 120, 130, 140, 150, 160, 170, 180 surrounding the first region 196 of the multilevel metallization structure 103, with only one or more small gaps G (e.g., FIG. 3) for electrical connection of the first terminal 106 to a low-voltage circuit element or connection of a second portion of the multilevel metallization structure 103.

[0032] The electronic device 100 in one example includes two or more insulating components 104 (e.g., capacitors with top plates or second terminals 108 as seen in FIG. 2). In one implementation, one or more pairs of capacitor insulating components 104 are provided in a first portion of the multilevel metallization structure 103, and a conductive shield 105 provides a single grounded Faraday cage structure surrounding all of the insulating components 104. In a further alternative implementation, multiple conductive shields 105 are fabricated within the multilevel metallization structure 103 to provide multiple grounded Faraday cage structures that individually surround one or more associated insulating components. In the example of FIGS. 1-3, the individual capacitor insulating components 104 are laterally spaced apart from one another in a first region of the multilevel metallization structure 103, and each include a first terminal 106 and a second terminal 108 that are at different ones of the metallization structure levels (e.g., levels 130 and 180 in the illustrated example). Also, in the example of FIGS. 1-3, each of the capacitor isolation components 104 includes an associated conductive routing feature 125 that extends through a corresponding gap G in the metal line 126 .

[0033] As shown in FIG. 1, the exemplary upper capacitor plate or second terminal 108 may be soldered or otherwise electrically connected to another circuit (e.g., in the high voltage domain). FIG. 1 shows an example in which a bond wire 188 has a first end soldered to an exposed top side 192 of the second terminal 108 to facilitate electrical connection to a conductive feature of another die (e.g., as illustrated in connection with FIG. 4 and FIG. 26 and further described below). The exemplary electronic device 100 also includes a polyimide layer 190 that extends over some portions of the protective overcoat layers 183 and 185 and has a thickness of 10 μm. The polyimide layer 190 in one example provides a stress barrier to relieve mechanical stress on the semiconductor layer 101 and the multi-level metallization structure 103 following encapsulation in a molded packaging structure, for example, to relieve mechanical stress between an overlying mold compound and the surface of layer 185 that may potentially delaminate after several temperature cycling events.

[0034] Polyimide layer 190, protective oxide layer 185, and layer 183 in this example include a gap exposing top side 192 of second terminal 108. Layers 181 and 182 in this example include a gap having a lateral gap distance 191 that completely surrounds second terminal 108. Layers 183 and 185 also include a recess or gap that is laterally spaced a distance 194 (e.g., 273 μm) along the X direction from the bond wire opening. This recess or gap is located between outermost conductive lines 184 in one example so that cracks caused by dicing do not propagate into the die. Distance 194 varies in different implementations depending on what external circuitry is present around the insulating component, and in one example, the recess or gap completely surrounds the die. As shown in dashed form in FIG. 1, the conductive shield 105 surrounds the capacitor isolation component 104 and provides a grounded Faraday cage with a retractable stepped structure that separates a first region 196 (e.g., associated with a high voltage domain) from a second region 198 (e.g., associated with a lower or different voltage domain).

[0035] FIG. 4 illustrates a schematic diagram of an exemplary packaged electronic device 400 that includes the electronic device 100 described above. In this example, the packaged electronic device 400 includes a first die 100 that represents a singulated or separated semiconductor die as previously illustrated and described in connection with FIGS. 1-3. The first die device 100 includes a multi-level metallization structure 103 with a conductive shield 105 between isolated first and second regions 196 and 198, and a capacitor isolation component 104, as described above. The first semiconductor die or electronic device 100 is packaged with one or more additional semiconductor dies to create a packaged electronic component that includes conductive leads or terminals 401, 402, 403, 404, 405, 406, 408 associated with a first (e.g., low voltage) voltage domain, and conductive leads or terminals 409, 410, 411, 414, 415, and 416 associated with one or more additional (e.g., higher voltage) voltage domains.

[0036] As shown generally in Figure 4, an electronic device 100 (e.g., a first semiconductor die) includes a pair of capacitors 104, each having a first terminal 106 and a second terminal 108 connected (e.g., wire bonded) to a corresponding bond wire 188. In a corresponding user application (e.g., a communication system printed circuit board), terminals 401-406, 408-411, and 414-416 are soldered to corresponding circuit board traces 421-426, 428-431, and 434-436 to provide electrical interconnection and operation with associated signal lines or signals INA, INB, VCCI, GND, DIS, DT, VCCI, VSSB, OUTB, VDDB, VSSA, OUTA, and VDDA, respectively. The first die or electronic device 100 in this example includes logic circuitry 440 that provides low voltage first and second communication channel signals to the first terminals 106 of the respective capacitors 104.

[0037] The conductive shield 105 of the first semiconductor die electronic device 100 in Figures 1 and 4 insulates the first portion 196 of the multilevel metallization structure 103 from the high voltage associated with the second terminal 108. The capacitor 104 in Figure 4 provides an isolation barrier between the logic circuitry 440 and the capacitively coupled circuitry of the first additional semiconductor die 451 and the second additional semiconductor die 452 of the packaged electronic device 400. In one example, the semiconductor dies 451 and 452 also include a multilevel metallization structure 103 with the conductive shield 105 between the isolated first and second regions 196 and 198, and the capacitor 104 with the plate terminals 106 and 108 mentioned above. As shown in Figure 4, the respective bond wires 188 are wire bonded to the exposed top side 192 of the second terminal 108 to provide a series connected capacitor coupling between the logic circuitry 440 and the respective drivers 453 and 454 of the semiconductor dies 451 and 452. In another example, the second semiconductor die 451 and the third semiconductor die 452 do not include internal isolation capacitors, and the bond wires 188 are soldered to conductive features of the respective semiconductor dies 451 and 452, such as to the inputs of the respective drivers 453 and 454 (see example in FIG. 26 below). In one example, the semiconductor dies 451 and 452 are receivers for the packaged electronic device 400, where the outputs from the respective drivers 453 and 454 are connected to external circuitry that controls the voltage VSSA at the switching node 434.

[0038] A first receiver output channel (e.g., channel "A") of FIG. 4 provides a first channel driver output biased to a supply voltage VDD received at a supply node 460. The supply node 460 is connected through a boot resistor 462 and a diode 463 to provide a first supply voltage signal VDDA at a circuit board trace 436. A first driver 453 receives the first supply voltage VDDA as an upper rail supply, and a lower rail of the driver 453 is connected to a circuit board trace 434 to operate at a reference voltage VSSA. The external circuitry includes a boot capacitor 464 connected between terminals 414 and 416, and an output of the driver 453 is connected to a terminal for 15 to provide a first gate drive output. A second receiver output channel (e.g., channel "B") includes a second driver 454 on a second semiconductor die 452 and is biased according to a supply voltage VDD and a ground reference voltage VSSB at terminals 411 and 409, respectively. The external circuitry also includes a supply voltage capacitor 466 connected between the supply voltage VDD and the ground reference voltage VSSB at the ground reference node 429. In operation, the drivers 453 and 454 operate according to signals received from the logic circuit 440 via isolated capacitive coupling channels to provide respective gate drive signals OUTA and OUTB that are connected to the gates of respective high-side and low-side transistors 471 and 472. The high-side transistor 471 has a drain terminal 470 that is connected to the high-voltage supply voltage HV, and a capacitor 474 is connected between the drain terminal 470 and the ground reference node 429. The source terminal of the high-side transistor 471 and the drain terminal of the low-side transistor 472 are connected to the switching node 434.

[0039] Referring also to FIGS. 5-25, FIG. 5 illustrates a method 500 for fabricating a packaged electronic device including a first die with an insulating component (e.g., capacitor, transformer, etc.) and a multi-level insulating structure in a multi-level metallization structure. FIGS. 6-25 are partial views of the first die 100 of FIGS. 1-4 undergoing fabrication processing according to method 500. Method 500 illustrates steps such as acts and / or events associated with building a multi-level metallization structure incorporating capacitor 104 and conductive shield 105. The described steps may be used simultaneously to fabricate and interconnect other electronic circuits and / or components (e.g., transistor circuits to form logic circuit 440 of FIG. 4, etc.) in a single semiconductor die 100. The multi-level metallization structure 103 in one example includes metal lines, cylindrical vias, and trench vias that electrically couple terminals of insulating component 104 to one or more internal components (not shown).

[0040] Method 500 includes front-end processing at 502, such as fabricating one or more circuit components (e.g., transistors, etc.) on and / or within a starting wafer. In electronic device 100 of FIG. 1 , front-end processing at 502 includes processing of a starting semiconductor wafer, such as a p-type silicon wafer, an SOI structure comprising a silicon layer, a silicon-germanium layer, or other layer having semiconductor material. Processing at 501 in one example also includes fabricating transistors on and / or within semiconductor layer 101, and forming isolation structures, such as the illustrated STI structure 102, on and / or within a top side of semiconductor layer 101.

[0041] 9-18 show a metallization structure 103 formed at 504, 506, 510, 520, 530, and 540 on a semiconductor layer 101. An example method 500 includes forming a pre-metal dielectric layer at 504 and forming associated contacts (e.g., tungsten contacts) at 506 to create a PMD level 110. The N metallization levels of the multi-level metallization structure 103 are then fabricated level by level. FIG. 6 shows an example of processing at 504 where a deposition process 600 is performed to deposit a pre-metal dielectric PMD layer 111 (e.g., SIO2) on the semiconductor layer 101. In one example, the process 600 deposits silicon dioxide to form a PMD layer 111 having a thickness of about 1.2 μm.

[0042] The method 500 continues at 506 with forming contacts (e.g., contacts 114 and 118) through the PMD layer 111. Figure 7 illustrates an example in which a contact formation process 700 is performed to form cylindrical contacts 114 and pre-metal trench contacts 118 on the semiconductor layer 101 through the PMD layer 111. In one example, the process 700 includes a patterned etch (not shown) to form cylindrical holes and trenches for the cylindrical contacts and trench contacts, respectively, one or more deposition steps to deposit a suitable metal (e.g., tungsten or including tungsten) in the openings, followed by a planarization step (e.g., chemical mechanical polishing or CMP) to provide a flat top side of the PMD layer 111 and the formed respective cylindrical contacts 114 and trench contacts 118. In one example, the trench formation creates a continuous trench for a pre-metal trench contact 118 that surrounds a portion of the first region 196 (FIG. 1 above) of the PMD layer 111, with the corresponding trench and resulting contact 118 extending up onto the semiconductor layer 101 where the grounded conductive shield 105 described above begins. In an example implementation, the cylindrical pre-metal level contact 114 is electrically coupled to one or more electronic circuit components of the electronic device 100 (e.g., for signal routing in the logic circuit 440 of FIG. 4). Also, while not a strict requirement of all possible implementations, a further trench contact 118 is formed in a region 119 (FIG. 1) near the periphery of the illustrated portion of the electronic device 100, at 506 in the example of FIG. 7, for example to provide protection from cracking and mechanical stress to the device 100.

[0043] The method 500 continues at 510 of Figure 5 with forming a first metallization level 120 on the PMD layer 111. Figures 8 and 9 show an example implementation in which the first metallization level 120 is formed at 512 and 514 of Figure 5. The first metallization level 120 includes a first metal line 126 on the pre-metal trench contact 118 and a metal routing feature 125. The metallization level 120 also includes a first ILD layer 121 on the PMD layer 111, the first metal line 126, the metal routing feature 125, and a routing via 127 and a first trench via 128 on the first metal line 126. As described above, the first trench via 128 and the first metal line 126 surround the first region 196 of the first metallization structure level 120 in the second region 198 of the first metallization structure level 120 (except for the gap region where 125 passes through 126 as shown in FIG. 3), and the metal routing feature 125 extends through the gap G in the first metal line 126 (e.g., FIG. 3 above).

[0044] At 512 in FIG. 5, a first metal layer feature (M1) is deposited and patterned. FIG. 8 shows an example where a process 800 is performed to deposit a metal layer (e.g., aluminum to a thickness of 0.61 μm) on the PMD layer 111 and etch exposed portions of the deposited metal using a patterned etch mask (not shown) to form metal routing feature 122 in the second region (region 198 in FIG. 1 above) and metal routing feature 125 and first metal line 126 in the first region (196 in FIG. 1). At 514, a first ILD layer 121 is deposited on the PMD layer 111. FIG. 9 shows an example where a deposition process 900 is performed to deposit an ILD layer 121 (e.g., silicon dioxide to a thickness of 1.2 μm) on the PMD layer 111. At 516, trenches and cylindrical holes are etched in the deposited ILD layer 121. FIG. 10 illustrates an example in which an etching process 1000 is performed using a patterned etching mask 1002. In the etching process 1000, cylindrical holes for expected vias and trenches for expected trench vias are formed. Processing at 516 also includes filling the etched cylindrical holes and trenches with a conductive metal (e.g., tungsten) to form cylindrical routing vias 124 and trench vias 128. FIG. 11 illustrates an example in which a deposition process 1100 is performed to deposit tungsten into the etched via holes and trenches to form cylindrical routing vias 124 and first trench vias 128 on the first metal line 126 to continue the conductive shield 105 at the first metallization level 120. In one example, although not a strict requirement of all possible implementations, processing at 510 of FIG. 5 further forms additional trench contacts 128 in the region 119 near the periphery of the depicted portion of the electronic device 100. In one example, processing at 510 also includes planarizing the via trenches after they have been filled.

[0045] 5 with forming a second metallization level 130 on the first metallization level 120. One example includes forming and patterning a second metal layer (M2) at 522 to form a second metal line 136 over the first trench via 128 and a first terminal 106 of the insulating component 104 laterally spaced from the second metal line 136 and extending over at least a portion of the routing via 127 in the first portion of the multilevel metallization structure 103. FIG. 12 illustrates the example electronic device 100 after formation of the second metallization level 130 and respective third and fourth metallization levels 140 and 150. 5, a second ILD layer 131 is deposited (e.g., silicon dioxide to a thickness of about 1.2 μm) over the first ILD layer 121, the second metal line 136, and the first terminal 106. At 526, trenches and cylindrical via holes are etched in the second ILD layer 131 and filled with tungsten to form second trench vias 138 over the second metal line 136, and the interconnect vias 134 and second portion 198 of the multilevel metallization structure 103. While not a strict requirement of all possible implementations, in the illustrated example, the second metallization structure level processing at 520 also forms additional trench vias 138 in the region 119 near the periphery of the illustrated portion of the electronic device 100.

[0046] In one example, a further metallization level is formed at 530 in Figure 5. Figure 12 further illustrates a process 1200 for forming a third metallization level 140 and a fourth metallization level 150 on the second metallization level 130 described above. Any number of intermediate metallization levels may be formed at 530 with respective metal lines and trench vias surrounding the first portion 196 of the multilevel metallization structure 103. In the illustrated example, each metallization level is created by first depositing and patterning a metal line layer, depositing an ILD layer, chemically mechanically polishing the ILD layer to remove topography, etching cylindrical via holes and trenches in the ILD layer, filling the via holes and trenches with tungsten, and then removing unwanted tungsten from the ILD surface by chemically mechanical polishing (e.g., CMP). FIG. 13 illustrates a process 1300 for forming an example fifth metallization level 160 in the electronic device 100 (eg, the process at 530 in FIG. 5).

[0047] Fabrication of the sixth metallization level 170 and seventh metallization level 180 (at 530 and 540 in FIG. 5) is shown in FIGs. 14-24, including the process 1400 of FIG. 14 of depositing and patterning the sixth metal line 176, the sixth level portion of the scribe seal stack 172, and other sixth metal tracks (not shown) therebetween. FIG. 15 shows further processing 1500 of depositing the sixth ILD layer 171 over the preceding fifth ILD layer 161, the seventh metal line 176, and the seventh level portion of the scribe seal stack 172.

[0048] The method 500 further includes forming a final metallization level (e.g., Nth metallization level 180) at 540 of FIG. 5. The Nth metallization level 180 includes an Nth metal line 186 on the trench via 178 of the underlying metallization level 170, a second terminal 108 of the insulating component 104, and a layer 183 on the Nth metal line 186. FIGS. 16 and 17 show deposition processes 1600 and 1700, respectively, for depositing the dielectric layers 181 and 182. In one example, the deposition process 1600 deposits silicon oxynitride 181 to a thickness of about 0.3 μm, and the deposition process 1700 deposits silicon nitride 182 to a thickness of about 0.65 μm. Operation 1800 of Figure 18 etches the trenches and cylindrical via holes and fills the via holes and trenches with tungsten to form a sixth trench via 178 and a sixth cylindrical tungsten via 174 in the second portion of the multilevel metallization structure 103. Figure 19 illustrates an etch process 1900 that etches exposed portions of the top metallization layer to form structures 108, 184, and 186 using an etch mask 1902 after deposition of the top metallization layer.

[0049] The formation of level 180 continues with an etching process 2000 in FIG. 20, which etches layers 182 and 181 using a mask 2002 to expose a portion of the top of the sixth ILD layer 171. A portion of the protective overcoat layer 183 is deposited on the Nth metal line 186 by a sequence of deposition processes 2100 in FIG. 21 (e.g., 1.5 μm thick silicon dioxide deposited by high density plasma (HDP), followed by 3.6 μm thick silicon dioxide deposited by plasma enhanced chemical vapor deposition (PECVD)). The bilayer 183 deposited by process sequence 2100 is chemically mechanically polished to remove topography so that layer 180 is within 1.5 μm. In FIG. 22, a deposition process 2200 is performed to deposit a final layer 185, which together with layer 183 forms a protective overcoat (PO) stack for device 100. In one example, this process deposits silicon oxynitride 185 to a thickness of about 2.8 μm. In FIG. 23, an etching process 2300 is performed using an etching mask 2302. The etching process 2300 etches openings in the protective overcoat stack, including an opening that exposes the top side 192 of the second terminal 108 of the capacitor insulating component 104. In FIG. 24, a dispensing or screening process 2400 is performed in which a polyimide layer 190 (e.g., to a thickness of about 10 μm) is formed over a portion of the protective overcoat stack 187 to create a stress barrier to relieve mechanical stress on the semiconductor layer 101 and the multilevel metallization structure 103. As shown in FIG. 24, the polyimide layer 190 has a gap that exposes the top side 192 of the second terminal 108.

[0050] 25-27, the method 500 continues at 550 with separating a first semiconductor die (e.g., die 100 of FIG. 4 above) including semiconductor layer 101 and multi-level metallization structure 103 from the wafer. The die is also attached to a leadframe and a wirebonding process is performed at 550 to provide an electrical connection to second capacitor terminal 108. FIG. 26 shows a packaged electronic device during processing at 550, where semiconductor die 100 is attached to first die attach pad 2601 of leadframe structure 2600 having leads or terminals 401-406, 408-411, and 414-416 as previously described. The die attach process at 550 in this example also includes attaching dies 451 and 452 (e.g., FIG. 4 above) to respective die attach pads 2602 and 2603 of the leadframe. Bonding wires are connected (e.g., welded, ultrasonically soldered, etc.) between the conductive features of the die 100, 451, 452 and / or to certain of the leads 401-406, 408-411, and 414-416. As shown in FIGS. 4, 25, and 26, the wire bonds also couple the wires 188 described above to the exposed top sides 192 of the second terminals 108 of the capacitor isolation components 104. In this example, the second ends of the bonding wires 188 are coupled to the corresponding second capacitor plates 108 of the die 451 and 452, respectively, to create a series connected capacitor coupling between the driver output of the first die 100 and the circuit elements of the die 451 and 452. Other electrical connection techniques, such as ball grid array or solder ball connections to the conductive features of the substrate, may be used to form electrical connections between the second terminals 108 of the isolation components 104 and the conductive features of the second semiconductor die at 550. The method 500 also includes molding and device separation at 560 in FIG.27 illustrates a molded singulated packaged electronic device 400 including a molded package structure 2700 (e.g., molding compound) that encloses the die 100, 451, and 452, electrical connections 188, and exposes portions of the conductive leads or terminals 401, 402, 403, 404, 405, 406, 408 along one or more sides of the package structure 2700. The example of FIG. 27 is a QFN (Quad Flat No Lead) packaged device 400. In other examples, different package types and configurations are possible, and the method 500 in one example also includes lead trimming and forming to provide a completed packaged electronic device with gull wing leads, J-type leads, etc.

[0051] The packaged electronic device 2700 and electronic device 100 described above provide an enhanced high voltage isolation barrier between the first portion 196 and the second portion 198 using a conductive shield 105 formed in the multilevel metallization structure 103 and the top metal layer during metallization processing. The conductive shield 105 robustly protects the encapsulated isolation barrier capacitor component 104 against nearby EOS events by an enhanced circumferential ground ring formed by the combination of the trench contacts / vias 118, 128, 138, 148, 158, 168, and 178 and the connected metal lines 126, 136, 146, 156, 166, 176, 178, and 186. While not a strict requirement of all possible implementations, in the illustrated example, trench contacts / vias 118, 128, 138, 148, 158, 168, and 178 are provided at all levels of the multilevel metallization structure 103. In one example, the trench contact and via levels 118, 128 are not present. Also, although not a requirement of all possible implementations, the example conductive shield 105 is grounded by connecting to the semiconductor layer 101 through the bottom trench via 118. The disclosed example mitigates the risk of losing the dielectric integrity of the device during an EOS event by creating a metal wall that substantially, completely, or at least partially surrounds the high voltage isolation component 104 to mitigate cracking from an EOS event, for example, surrounding at least 90% of the perimeter area with a tapered or vertical wall of metal surrounding a component. In one example, the trench via surrounding the HV region includes cuts in places to partially surround the high voltage component or device. For example, the cuts are provided where the structures of vias 1 and 2 coincide with the cuts in the first metal level to allow connection to the bottom plate. Also, the described EOS protection does not require the addition of additional circuit components, such as fuses or other one-time use devices, in the fabrication of the packaged electronic device.

[0052] 28-30, FIG. 28 is a cross-sectional side view of another electronic device 2800 with an isolation transformer insulating component 2804 in a first region 2896 surrounded by a conductive shield 2805 in a multilevel metallization structure 103 on a semiconductor layer 101. FIG. 29 is a partial top plan view taken along line 29-29 of the electronic device 2800 of FIG. 28, and FIG. 30 is a partial top plan view taken along line 30-30 of the electronic device 2800 of FIG. 28. The electronic device 2800 has similar numbered features and dimensions as described above in connection with FIGS. 1-3. In this example, the isolation component 2804 is a transformer with a first terminal 2806 formed as a transformer winding or a first transformer coil in a second metallization structure level 130. The second terminal 2808 in this example is a second transformer coil or second transformer winding as shown in FIG. 29, and the first coil (first terminal) 2806 has a similar shape in one example. The conductive shield 2805 separates the high voltage first region 2896 from the low voltage domain second region 2898 using conductive metal lines and trench vias as described above. As further shown in FIG. 30, two gaps are formed in the first metal line 126 to provide first and second routing structures 125 respectively connecting to the first and second ends of the primary transformer coil 2806, and the seventh metallization structure level 180 in this example provides exposed portions of the first and second ends of the second transformer coil 2808 for electrical connection to an external device (e.g., to another die of a packaged electronic device, not shown).

[0053] The foregoing examples are merely illustrative of some possible implementations of the various aspects of the disclosure, and equivalent modifications and / or alterations will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Modifications in the described examples are possible, and other implementations are possible, within the scope of the claims.

Claims

1. 1. An electronic device comprising: A semiconductor layer; a multilevel metallization structure above the semiconductor layer, the multilevel metallization structure including a first region, a second region, a premetal level above the semiconductor layer, and an integer number N of metallization structure levels above the premetal level, where N is greater than 3; an insulating component in the first region of the multilevel metallization structure, the insulating component including a first terminal and a second terminal, the first and second terminals being on different respective metallization levels of the multilevel metallization structure; a conductive shield between the first region and the second region of the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias at each of the metallization levels at least partially surrounding the first region of the multilevel metallization structure; the conductive shield has a stepped shape; the second terminal of the insulating component includes opposed lateral edges spaced apart from one another along a first direction; the metal lines of the respective metallization levels include lateral edges spaced apart from respective lateral edges of the second terminals along the first direction by respective separation distances; The respective separation distances are different from each other.

2. 2. The electronic device of claim 1, wherein a given one of the metallization levels of the multi-level metallization structure comprises: a respective one of the metal lines surrounding a portion of the first region of the multilevel metallization structure and including a gap; a metal routing feature spaced from the conductive shield and connected to the first terminal of the insulating component in the first region of the multilevel metallization structure, the metal routing feature extending from the first region of the multilevel metallization structure to the second region of the multilevel metallization structure through the gap of the respective one of the metal lines; The electronic device comprising:

3. 3. The electronic device of claim 2, the insulating component is a capacitor; the first terminal of the insulating component is a first capacitor plate connected to the metal routing feature; the second terminal of the insulating component is a second capacitor plate; The electronic device.

4. 3. The electronic device of claim 2, the isolation component is a transformer; the first terminal of the insulating component is a first transformer coil connected to the metal routing feature; the second terminal of the insulating component is a second transformer coil; Electronic devices.

5. 3. The electronic device of claim 2 further comprising a second insulating component spaced apart from an insulating component in the first region of the multi-level metallization structure, the second insulating component including a first terminal and a second terminal, the first and second terminals of the second insulating component being on different respective metallization levels of the multi-level metallization structure; the respective one of the metal lines of the given one of the metallization levels includes a second gap; the given one of the metallization levels includes a second metal routing feature spaced from the conductive shield, the second metal routing feature being connected to the first terminal of the second insulating component in the first region of the multilevel metallization structure, the second metal routing feature extending from the first region of the multilevel metallization structure to the second region of the multilevel metallization structure through the second gap of the respective one of the metal lines. Electronic devices.

6. 2. The electronic device of claim 1, wherein the multi-level metallization structure comprises: a pre-metal level including a pre-metal dielectric (PMD) layer on the semiconductor layer and a pre-metal trench contact on the semiconductor layer, the pre-metal level surrounding a portion of the first region of the PMD layer; a first metallization level above the pre-metal level, the first metallization level comprising: a first metal line on the pre-metal trench contact; Metal routing features; a first interlevel dielectric (ILD) layer over the PMD layer, the first metal line, and the metal routing feature; a first trench via on the first metal line, the first trench via and the first metal line surrounding another portion of the first region of the first metallization structure level; and a routing via on the metal routing feature, the routing via extending through a gap in the first metal line between the portion of the first region and a portion of the second region of the first metallization structure level. the first metallization level comprising: a second metallization level on the first metallization level, the second metallization level comprising: a second metal line on the first trench via; and the first terminal of the insulating component spaced apart from the second metal line; a second ILD layer over the first ILD layer, the second metal line, and the first terminal of the insulating component; a second trench via on the second metal line; a second metallization level, the second trench via and the second metal line surrounding a second portion of the first region of the second metallization level; 2. An electronic device comprising:

7. 7. The electronic device of claim 6, wherein the multi-level metallization structure further comprises: an Nth metallization level of the N metallization levels above the second metallization level, an Nth metal line on a trench via of an underlying metallization level; the second terminal of the insulating component spaced apart from the Nth metal line; an Nth ILD layer on the Nth metal line; the Nth metallization level, the Nth metal line surrounding an Nth portion of the first region of the Nth metallization level; one or more intermediate metallization levels between the second metallization level and the Nth metallization level; Including, each of the intermediate metallization levels includes a respective one of the interconnected metal lines and a respective one of the trench vias of the conductive shield, the respective one of the interconnected metal lines and the respective one of the trench vias surrounding the first region of the respective intermediate metallization level of the metallization levels; Electronic devices.

8. An electronic device, comprising: A semiconductor layer; a multilevel metallization structure above the semiconductor layer, the multilevel metallization structure including a first region, a second region, a premetal level above the semiconductor layer, and an integer number N of metallization structure levels above the premetal level, where N is greater than 3; an insulating component in the first region of the multilevel metallization structure, the insulating component including a first terminal and a second terminal, the first and second terminals being on different respective metallization levels of the multilevel metallization structure; a conductive shield between the first region and the second region of the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias at each of the metallization levels at least partially surrounding the first region of the multilevel metallization structure; The multi-level metallization structure comprises: a pre-metal level including a pre-metal dielectric (PMD) layer on the semiconductor layer and a pre-metal trench contact on the semiconductor layer, the pre-metal level surrounding a portion of the first region of the PMD layer; a first metallization level above the pre-metal level, the first metallization level comprising: a first metal line on the pre-metal trench contact; Metal routing features; a first interlevel dielectric (ILD) layer over the PMD layer, the first metal line, and the metal routing feature; a first trench via on the first metal line, the first trench via and the first metal line surrounding another portion of the first region of the first metallization structure level; and a routing via on the metal routing feature, the routing via extending through a gap in the first metal line between the portion of the first region and a portion of the second region of the first metallization structure level. the first metallization level comprising: a second metallization level on the first metallization level, the second metallization level comprising: a second metal line on the first trench via; and the first terminal of the insulating component spaced apart from the second metal line; a second ILD layer over the first ILD layer, the second metal line, and the first terminal of the insulating component; a second trench via on the second metal line; a second metallization level, wherein the second trench via and the second metal line surround a second portion of the first region of the second metallization level; the multi-level metallization structure further comprising: an Nth metallization level of the N metallization levels above the second metallization level, an Nth metal line on a trench via of an underlying metallization level; the second terminal of the insulating component spaced apart from the Nth metal line; an Nth ILD layer on the Nth metal line; the Nth metallization level, the Nth metal line surrounding an Nth portion of the first region of the Nth metallization level; one or more intermediate metallization levels between the second metallization level and the Nth metallization level; Including, each of the intermediate metallization levels includes a respective one of the interconnected metal lines and a respective one of the trench vias of the conductive shield, the respective one of the interconnected metal lines and the respective one of the trench vias surrounding the first region of the respective intermediate metallization level of the metallization levels; Electronic devices.

9. 2. The electronic device of claim 1, wherein the second terminal of the insulating component is at an Nth one of the metallization levels and includes an exposed side.

10. 2. The electronic device of claim 1, further comprising a second insulating component spaced apart from the insulating component in the first region of the multilevel metallization structure, the second insulating component including a first terminal and a second terminal, the first and second terminals of the second insulating component being at different respective metallization levels of the multilevel metallization structure.

11. 1. A packaged electronic device comprising: A first semiconductor die, A semiconductor layer; a multilevel metallization structure above the semiconductor layer, the multilevel metallization structure including a first region, a second region, a premetal level above the semiconductor layer, and an integer number N of metallization structure levels above the premetal level, where N is greater than 3; an insulating component in the first region of the multilevel metallization structure, the insulating component including a first terminal and a second terminal, the first and second terminals being in different respective metallization levels of the multilevel metallization structure, the second terminal including an exposed side; a conductive shield between the first region and the second region of the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias of the respective metallization levels at least partially surrounding the first region of the multilevel metallization structure; the first semiconductor die comprising: a second semiconductor die including conductive features; an electrical connection including a first end soldered to the exposed side of the second terminal and a second end soldered to the conductive feature of the second semiconductor die; a package structure enclosing the first semiconductor die, the second semiconductor die, and the electrical connections; conductive leads exposed along one or more sides of the package structure; Including, the insulating component is a capacitor; the first terminal of the insulating component is a first capacitor plate; a packaged electronic device, the second terminal of the insulating component being a second capacitor plate.

12. A packaged electronic device comprising: A first semiconductor die, A semiconductor layer; a multilevel metallization structure above the semiconductor layer, the multilevel metallization structure including a first region, a second region, a premetal level above the semiconductor layer, and an integer number N of metallization structure levels above the premetal level, where N is greater than 3; an insulating component in the first region of the multilevel metallization structure, the insulating component including a first terminal and a second terminal, the first and second terminals being in different respective metallization levels of the multilevel metallization structure, the second terminal including an exposed side; a conductive shield between the first region and the second region of the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias of the respective metallization levels at least partially surrounding the first region of the multilevel metallization structure; the first semiconductor die comprising: a second semiconductor die including conductive features; an electrical connection including a first end soldered to the exposed side of the second terminal and a second end soldered to the conductive feature of the second semiconductor die; a package structure enclosing the first semiconductor die, the second semiconductor die, and the electrical connections; conductive leads exposed along one or more sides of the package structure; Including, the second semiconductor die comprising: A second semiconductor layer; a second multilevel metallization structure on the second semiconductor layer, the second multilevel metallization structure including a first region, a second region, a premetal level on the second semiconductor layer, and an integer number M of metallization structure levels above the premetal level, where M is greater than 3; a second insulating component in the first region of the second multilevel metallization structure, the second insulating component including a first terminal and a second terminal, the first and second terminals being in different respective metallization levels of the second multilevel metallization structure, the second terminal including an exposed side; a second conductive shield between the first region and the second region of the second multilevel metallization structure, the second conductive shield including interconnected metal lines and trench vias at the respective metallization levels surrounding the first region of the second multilevel metallization structure; 1. A packaged electronic device comprising:

13. 13. The packaged electronic device of claim 12, the isolation component is a transformer; the first terminal of the insulating component is a first transformer coil; the second terminal of the insulating component is a second transformer coil; The packaged electronic device.

14. A packaged electronic device comprising: A first semiconductor die, A semiconductor layer; a multilevel metallization structure above the semiconductor layer, the multilevel metallization structure including a first region, a second region, a premetal level above the semiconductor layer, and an integer number N of metallization structure levels above the premetal level, where N is greater than 3; an insulating component in the first region of the multilevel metallization structure, the insulating component including a first terminal and a second terminal, the first and second terminals being in different respective metallization levels of the multilevel metallization structure, the second terminal including an exposed side; a conductive shield between the first region and the second region of the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias of the respective metallization levels at least partially surrounding the first region of the multilevel metallization structure; the first semiconductor die comprising: a second semiconductor die including conductive features; an electrical connection including a first end soldered to the exposed side of the second terminal and a second end soldered to the conductive feature of the second semiconductor die; a package structure enclosing the first semiconductor die, the second semiconductor die, and the electrical connections; conductive leads exposed along one or more sides of the package structure; Including, the conductive shield has a stepped shape; the second terminal of the insulating component includes opposed lateral edges spaced apart from one another along a first direction; the metal lines of the respective metallization levels include lateral edges spaced apart from respective lateral edges of the second terminals along the first direction by respective separation distances; The respective separation distances are different from each other. Packaged electronic devices.

15. 1. A method comprising: forming a multi-level metallization structure over a semiconductor layer, the multi-level metallization structure comprising: a first region, a second region, a pre-metal level on the semiconductor layer, and an integer number N of metallization levels above the pre-metal level, N being greater than 3; an insulating component including a first terminal and a second terminal in the first region of the multi-level metallization structure; forming the multilevel metallization structure including a conductive shield between the first region and the second region of the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias at each of the metallization levels at least partially surrounding the first region of the multilevel metallization structure, the conductive shield having a step shape, the second terminals of the insulating component including opposed lateral edges spaced apart from one another along a first direction, the metal lines at each of the metallization levels including lateral edges spaced apart from one another along the first direction by respective separation distances, the respective separation distances being different from one another; separating a first semiconductor die including the semiconductor layer and the multi-level metallization structure from a wafer; forming an electrical connection between the second terminal of the insulating component and a conductive feature of a second semiconductor die; enclosing the first semiconductor die, the second semiconductor die, and the electrical connections within a package structure and exposing conductive leads along one or more sides of the package structure; A method comprising:

16. 16. The method of claim 15, wherein forming the multi-level metallization structure further comprises: forming a pre-metal dielectric (PMD) layer over the semiconductor layer; forming a pre-metal trench contact on the semiconductor layer surrounding a portion of the first region of the PMD layer; forming a first metallization level on the PMD layer, the first metallization level comprising: a first metal line on the pre-metal trench contact; Metal routing features; a first interlevel dielectric (ILD) layer over the PMD layer, the first metal line, and the metal routing feature; a first trench via on the first metal line; forming a first metallization level, the first trench via and the first metal line surrounding the first region of the first metallization level in the second region of the first metallization level, the metal routing feature extending through a gap in the first metal line; forming a second metallization level on the first metallization level, the second metallization level comprising: a second metal line on the first trench via; and the first terminal of the insulating component, the first terminal being spaced apart from the second metal line; a second ILD layer over the first ILD layer, the second metal line, and the first terminal; a second trench via on the second metal line; forming a second metallization level, the second trench via and the second metal line surrounding the first region of the second metallization level; A method comprising:

17. 17. The method of claim 16, wherein forming the multi-level metallization structure further comprises: forming an Nth metallization level of the N metallization levels on the second metallization level, the Nth metallization level comprising: an Nth metal line on a trench via of an underlying metallization level; the second terminal of the insulating component spaced apart from the Nth metal line; an ILD layer on the Nth metal line; the Nth metal line surrounding the first region of the Nth metallization level; method.

18. 20. The method of claim 17, wherein forming the multi-level metallization structure further comprises: forming one or more intermediate metallization levels of the metallization levels between the second metallization level and the Nth metallization level, each intermediate metallization level of the metallization levels including a respective one of the interconnected metal lines and a respective one of the trench vias of the conductive shield, each one of the interconnected metal lines and each one of the trench vias surrounding the first region of the respective intermediate metallization level of the metallization levels.

19. A method comprising: forming a multi-level metallization structure over a semiconductor layer, the multi-level metallization structure comprising: a metallization structure level including a first region, a second region, a pre-metal level on the semiconductor layer, and an integer number N of metallization structure levels above the pre-metal level, N being greater than 3; an insulating component in the first region of the multilevel metallization structure, the insulating component including a first terminal and a second terminal, the first and second terminals being on different respective metallization levels of the multilevel metallization structure; a conductive shield between the first region and the second region of the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias at each of the metallization levels at least partially surrounding the first region of the multilevel metallization structure; The multi-level metallization structure comprises: a pre-metal level including a pre-metal dielectric (PMD) layer on the semiconductor layer and a pre-metal trench contact on the semiconductor layer, the pre-metal level surrounding a portion of the first region of the PMD layer; a first metallization level above the pre-metal level, the first metallization level comprising: a first metal line on the pre-metal trench contact; Metal routing features; a first interlevel dielectric (ILD) layer over the PMD layer, the first metal line, and the metal routing feature; a first trench via on the first metal line, the first trench via and the first metal line surrounding another portion of the first region of the first metallization structure level; and a routing via on the metal routing feature, the routing via extending through a gap in the first metal line between the portion of the first region and a portion of the second region of the first metallization structure level. the first metallization level comprising: a second metallization level on the first metallization level, the second metallization level comprising: a second metal line on the first trench via; and the first terminal of the insulating component spaced apart from the second metal line; a second ILD layer over the first ILD layer, the second metal line, and the first terminal of the insulating component; a second trench via on the second metal line; a second metallization level, wherein the second trench via and the second metal line surround a second portion of the first region of the second metallization level; the multi-level metallization structure further comprising: an Nth metallization level of the N metallization levels above the second metallization level, an Nth metal line on a trench via of an underlying metallization level; the second terminal of the insulating component spaced apart from the Nth metal line; an Nth ILD layer on the Nth metal line; the Nth metallization level, the Nth metal line surrounding an Nth portion of the first region of the Nth metallization level; one or more intermediate metallization levels between the second metallization level and the Nth metallization level; Including, each of the intermediate metallization levels includes a respective one of the interconnected metal lines and a respective one of the trench vias of the conductive shield, the respective one of the interconnected metal lines and the respective one of the trench vias surrounding the first region of the respective intermediate metallization level of the metallization levels; Electronic devices.

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