Encoder, decoder, transmitter and receiver, and chip

Abstract

To provide an encoder, a decoder, a transmitter, a receiver, and a chip with improved resistance to white noise while achieving lower delay for data transmission of a low-delay transmission channel (LLch) in terrestrial digital broadcasting.SOLUTION: An encoder 10 according to the present invention includes a first LDPC coding unit 11 that performs a first LDPC coding process on data in a first segment area allocated to LLch using a check matrix of a first LDPC coding rate, and a second LDPC coding unit 12 that performs a second LDPC coding process with the same code length using a check matrix of a second LDPC coding rate for data in a second segment area that is a non-partial reception band. A decoder according to the present invention decodes transmission data of LLch encoded by the encoder 10 in LDPC. A transmitter 1 according to the present invention includes the encoder 10, and a receiver 2 includes the decoder.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to the technical fields of satellite broadcasting, terrestrial broadcasting, fixed communication, and mobile communication, and in particular to an encoder, decoder, transmitter, receiver, and chip for digital data of a low latency transmission channel (LLch: Low Latency Channel) in next-generation terrestrial broadcasting. [Background technology]

[0002] The current terrestrial digital broadcasting system, ISDB-T, allows data transmission using AC (Auxiliary Channel), and ARIB-STD B31 specifies a transmission method for emergency earthquake alerts, which require low-latency transmission using AC. ISDB-T terrestrial digital broadcasting allows data transmission by dividing the frequency bandwidth of one channel (approximately 6 MHz) into 13 segments, but AC transmission achieves low-latency transmission by using the central segment (8 carriers) of the 13 segments, and uses a difference set cyclic code (273,191) as the error-correcting code.

[0003] 12(a) and 12(b) are block diagrams showing schematic configurations of a transmitter 100 and a receiver 200 for AC transmission data in the conventional terrestrial digital broadcasting system ISDB-T, respectively.

[0004] The transmitting device 100 includes a difference set cyclic encoding unit 101 , a DBPSK modulation unit 102 , and an OFDM modulation unit 103 .

[0005] The difference set cyclic encoding unit 101 performs error correction processing on the input AC transmission data using a difference set cyclic code (273, 191), generates AC transmission data with error correction parity added, and outputs the AC transmission data to the DBPSK modulation unit 102.

[0006] The DBPSK modulation unit 102 performs symbol mapping by DBPSK (Differential Phase Shift Keying) modulation on the AC transmission data to which the error correction parity has been added by the difference set cyclic encoding unit 101 to generate an AC carrier, and outputs the AC carrier to the OFDM modulation unit 103.

[0007] The OFDM modulation unit 103 orthogonally frequency-division multiplexes the AC carrier, three-layer data carriers, and a TMCC (Transmission and Multiplexing Configuration Control) carrier, which is a transmission control signal, to generate an OFDM (Orthogonal Frequency Division Multiplexing) modulated signal, and outputs the signal to the outside. Note that the OFDM modulation unit 103 uses the central segment (8 carriers) of the 13 segments to transmit AC carriers with the same content using the 8 carriers.

[0008] The receiving device 200 includes an OFDM demodulation unit 201 , an AC carrier extraction unit 202 , a DBPSK demodulation unit 203 , and a difference set cyclic code decoding unit 204 .

[0009] OFDM demodulation section 201 receives the OFDM modulated signal transmitted from transmitting apparatus 100 , performs OFDM demodulation processing on it, and outputs the OFDM demodulated signal to AC carrier extraction section 202 .

[0010] Based on an external AC specification, AC carrier extraction section 202 extracts an AC carrier from the OFDM demodulated signal and outputs it to DBPSK demodulation section 203 .

[0011] The DBPSK demodulation unit 203 performs DBPSK demodulation on the AC carrier obtained through the AC carrier extraction unit 202 through symbol demapping based on DBPSK, extracts AC symbols, and outputs them to the difference set cyclic code decoding unit 204.

[0012] The difference set cyclic code decoding unit 204 reconstructs the AC transmission data to which error correction parity has been added based on the likelihood judgment from the extracted AC symbols, performs decoding processing based on the difference set cyclic code (273, 191), restores an output bit string corresponding to the AC transmission data on the transmitting side, and outputs it to the outside.

[0013] In this way, AC transmission in the current terrestrial digital broadcasting standard ISDB-T achieves low-latency transmission by using the central segment (8 carriers) of 13 segments, and uses a difference set cyclic code (273,191) as the error correcting code.

[0014] Incidentally, the theoretical upper limit of the spectral efficiency relative to the signal-to-noise ratio is called the Shannon limit. In this specification, the communication capacity that a modulated signal can achieve is conveniently taken as the Shannon limit. ARIB STD-B44, which specifies the transmission method for 4K / 8K Super Hi-Vision satellite broadcasting, employs LDPC codes as error correcting codes for digital transmission (see, for example, Non-Patent Document 1). LDPC codes are linear codes defined by a very sparse parity check matrix H (the elements of the parity check matrix consist of 0 and 1, and the number of 1s is very small).

[0015] LDPC codes are powerful error-correcting codes that, by using an appropriate check matrix, can generally obtain transmission characteristics approaching the Shannon limit as the code length is increased. The use of LDPC codes as error-correcting codes for digital transmission is also being considered for the next-generation terrestrial digital broadcasting system (for example, see Non-Patent Document 2).

[0016] In the next-generation terrestrial digital broadcasting system, the frequency bandwidth of one channel (approximately 6 MHz) will be divided into 35 segments to enable data transmission, and three FFT point numbers are expected: 8K, 16K, and 32K. For the data carrier that forms the main signal, it is being considered to use an LDPC code as the inner code and BCH as the outer code.

[0017] However, in the next generation of terrestrial digital broadcasting, it is being considered to set up LLch for the purpose of low-latency transmission of digital data instead of AC, and to allocate it as one layer to be multiplexed onto OFDM signals. The specific configuration of the error correction method for LLch is still under consideration. [Prior art documents] [Non-patent literature]

[0018] [Non-Patent Document 1] "Transmission method standard for advanced wideband digital satellite broadcasting ARIB STD-B44 2.1 edition, revised March 25, 2016, Association of Radio Industries and Businesses (ARIB) [Non-Patent Document 2] Madoka Nakamura, "Research and Development for the Realization of Next-Generation Terrestrial Broadcasting," NHK Giken R&D No. 158, August 35, 2016, [online], [Retrieved November 11, 2019], Internet: https: / / www.nhk.or.jp / strl / publica / rd / rd158 / PDF / P28-35.pdf Summary of the Invention [Problem to be solved by the invention]

[0019] As mentioned above, the current terrestrial digital broadcasting system ISDB-T allows data transmission using AC for applications that require low-latency transmission, such as emergency earthquake alerts, but the transmitting device that performs the AC transmission transmits the same data in the central segment (8 carriers) to strengthen resistance to white noise, and therefore a diversity effect is obtained on the receiving device that receives the AC-transmitted data. However, even though AC transmission is a low-latency transmission, it still has a transmission delay of one frame (231.336 ms, mode=3, GI=1 / 8), and there is a demand for transmission with even lower latency.

[0020] In addition, the AC transmission in the current terrestrial digital broadcasting system ISDB-T, like TMCC transmission, uses a difference set cyclic code (273,191) as an error correcting code. This difference set cyclic code has excellent performance with a relatively short code, but it is desirable to further improve the resistance to white noise.

[0021] Therefore, in the next generation of terrestrial digital broadcasting, it is expected that LDPC codes will be adopted as an error correction method for LLch, instead of AC, for the purpose of low-latency transmission of digital data. LDPC codes not only have excellent transmission performance, but also enable variably setting the coding rate, which makes it possible to increase resistance to white noise. On the other hand, LDPC codes have the property that the longer the code length is, the closer the transmission characteristics approaching the Shannon limit can be obtained, but the problem is that the longer the code length is, the greater the transmission delay becomes.

[0022] For this reason, even if LDPC codes are adopted as the error correction method for LLch, it is necessary to achieve lower latency than conventional AC transmission and at the same time improve resistance to white noise.

[0023] In view of the above-mentioned problems, the object of the present invention is to provide an encoder, decoder, transmitting device, receiving device, and chip that achieves lower latency while improving resistance to white noise for data transmission on a low-latency transmission channel (LLch) in a terrestrial digital broadcasting system. [Means for solving the problem]

[0024] The encoder according to the present invention is an encoder that performs error correction coding processing on transmission data of a low-delay transmission channel in a terrestrial digital broadcasting system, and includes a first LDPC encoding means that performs a first LDPC coding processing using a check matrix of a first LDPC coding rate on data to be transmitted using a first segment area that is a central partial reception band among a predetermined number of segments assigned to the low-delay transmission channel, and a second LDPC encoding means that performs a second LDPC coding processing using a check matrix of a second LDPC coding rate on data to be transmitted using a second segment area that is a non-partial reception band other than the partial reception band among the predetermined number of segments assigned to the low-delay transmission channel, and 2 The LDPC coding process is characterized in that the respective code lengths are the same.

[0025] In the encoder according to the present invention, the first LDPC coding rate is set to a lower coding rate than the second LDPC coding rate.

[0026] In the encoder according to the present invention, the code length is 1224 bits.

[0027] In the encoder according to the present invention, the first LDPC coding rate is greater than or equal to 0.1 and less than 0.2, and the second LDPC coding rate is greater than or equal to 0.8 and less than 1.0.

[0028] In the encoder according to the present invention, the first LDPC coding rate is configured as 144 / 1224, and the second LDPC coding rate is configured as 1016 / 1224.

[0029] Moreover, in the encoder according to the present invention, the first LDPC encoding means is configured to perform the first LDPC encoding process using a parity check matrix having a code length of 1224 bits and an initial value set to a parity check matrix initial value table predetermined according to the first LDPC coding rate, and the parity check matrix includes a first submatrix in which elements of a submatrix corresponding to an information length according to the first LDPC coding rate are periodically arranged in the column direction with a first cycle number, a second submatrix in which elements of a submatrix of a submatrix of a code length corresponding to the first LDPC coding rate are periodically arranged in the column direction with a second cycle number different from the first cycle number, and a third submatrix obtained by shifting in the row direction for each of the first cycle number and periodically arranging elements of a submatrix ...

[0030] Moreover, in the encoder of the present invention, the second LDPC encoding means is configured to perform the second LDPC encoding process using a parity check matrix having a code length of 1224 bits and an initial value set to a parity check matrix initial value table predetermined according to the second LDPC coding rate, and the parity check matrix includes a submatrix in which one element of a submatrix corresponding to an information length according to the second LDPC coding rate is arranged in a column direction periodically with a third cycle number.

[0031] In addition, in the encoder according to the present invention, the check matrix initial value table (Table 1) for the coding rate of 144 / 1224, indicating initial values ​​when the first submatrix is ​​submatrix A, the second submatrix is ​​submatrix C, and the third submatrix is ​​submatrix D, is characterized in that it comprises the following table:

[0032] [Table 1]

[0033] In the encoder according to the present invention, the check matrix initial value table (Table 2) for the coding rate of 1016 / 1224 indicating the initial values ​​of the submatrices is characterized in that it comprises the following table:

[0034] [Table 2-1]

[0035] [Table 2-2]

[0036] [Table 2-3]

[0037] Furthermore, a decoder according to the present invention is characterized in comprising: means for LDPC decoding, using a check matrix of the first LDPC coding rate, data encoded by the encoder of the present invention through the first LDPC coding process; and means for LDPC decoding, using a check matrix of the second LDPC coding rate, data encoded by the encoder through the second LDPC coding process.

[0038] A transmitting device according to the present invention is also characterized in that it comprises an encoder according to the present invention.

[0039] A receiving device according to the invention is also characterized in that it comprises a decoder according to the invention.

[0040] Also, a chip according to the present invention is characterized by including any one of the encoder, decoder, transmitter, and receiver according to the present invention. Effect of the Invention

[0041] According to the present invention, the amount of delay in transmission of a low-latency transmission channel (LLch) in next-generation terrestrial digital broadcasting can be significantly reduced compared to AC transmission in the current terrestrial digital broadcasting system ISDB-T, and noise resistance can also be improved by using an LDPC code as an error correcting code. [Brief description of the drawings]

[0042] [Figure 1]1 is a block diagram illustrating only the main components of a low-latency transmission channel (LLch) transmission data transmission device according to an embodiment of the present invention. [Diagram 2] 1 is a block diagram illustrating only the main components of a receiving device for low-latency transmission channel (LLch) data in one embodiment according to the present invention. [Diagram 3] 13(a) and 13(b) are diagrams showing the configuration of an error correction block with an LDPC coding rate of 144 / 1224 according to one embodiment of an LDPC code with a code length of 1224 bits formed for data (L0ch transmission data) transmitted using a first segment area that is a central partial reception band among a predetermined number of segments assigned to a low-latency transmission channel according to the present invention, and the configuration of an error correction block with an LDPC coding rate of 1016 / 1224 according to one embodiment of an LDPC code with a code length of 1224 bits formed for data (L1ch transmission data) transmitted using a second segment area that is a non-partial reception band other than the partial reception band among a predetermined number of segments assigned to a low-latency transmission channel. [Figure 4] 13A and 13B are diagrams showing a parity check matrix H of an LDPC coding rate of 144 / 1224 for an LDPC code of a code length of 1224 bits formed for L0ch transmission data according to the present invention, and a parity check matrix H of an LDPC coding rate of 1016 / 1224 for an LDPC code of a code length of 1224 bits formed for L1ch transmission data according to the present invention. [Diagram 5] 1 is a diagram showing a submatrix B on a check matrix H relating to an LDPC code having a code length of 1224 bits formed for L0ch transmission data and L1ch transmission data according to the present invention. FIG. [Figure 6] 1 is a diagram showing a submatrix I on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L0 ch transmission data according to the present invention. FIG. [Figure 7] 1 is a diagram showing a submatrix A on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L0 ch transmission data according to the present invention. FIG. [Figure 8]1 is a diagram showing a submatrix C on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L0 ch transmission data according to the present invention. FIG. [Figure 9] 1 is a diagram showing a submatrix D on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L0 ch transmission data according to the present invention. FIG. [Figure 10] 1 is a diagram showing a submatrix A on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L1ch transmission data according to the present invention. FIG. [Figure 11] 13A and 13B are diagrams showing BER and FER characteristics versus C / N when DBPSK modulation is applied to L0ch transmission data and L1ch transmission data according to the present invention, respectively. [Figure 12] 1(a) and 1(b) are block diagrams showing schematic configurations of a transmitter and a receiver for AC transmission data in the conventional ISDB-T terrestrial digital broadcasting system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] Hereinafter, a transmitter 1 and a receiver 2 for low-delay transmission channel (LLch) data according to an embodiment of the present invention will be described with reference to the drawings. The transmission system according to an embodiment of the present invention is composed of a transmitter 1 shown in Fig. 1 and a receiver 2 shown in Fig. 2, which are based on the next-generation terrestrial broadcast transmission system, and employs an LDPC code as an error correction method for low-delay transmission channel (LLch) data used in the next-generation terrestrial broadcast transmission system, and is divided into two types of segment areas, each of which is optimized as a forward error correction code.

[0044] First, with reference to FIG. 1, a transmitting device 1 according to an embodiment of the present invention will be described.

[0045] [Transmitting device] FIG. 1 is a block diagram showing only the main components of a transmitter 1 for low-delay transmission channel (LLch) data according to an embodiment of the present invention. The transmitter 1 includes an encoder 10 (a first LDPC encoding unit 11 and a second LDPC encoding unit 12), a DBPSK modulation unit 13, and an OFDM modulation unit 16. The transmitter 1 is configured to transmit LLch transmission data divided into two types of segment areas, and performs a series of processes from generating an error correction block signal shown in FIG. 3 described later to generating an OFDM modulated signal. The transmitter 1 can transmit parameters related to transmission, such as the modulation method and coding rate of the LLch transmission data, by including them in the TMCC signal. In this example, the modulation method and coding rate of the LLch transmission data are predetermined between the transmitter 1 shown in FIG. 1 and the receiver 2 shown in FIG. 2, and an example will be described in which the receiver 2 demodulates and decodes the LLch transmission data without demodulating and decoding the TMCC signal.

[0046] In the next generation of terrestrial digital broadcasting, it is assumed that LLch will be set instead of AC for the purpose of low-latency transmission of digital data, and assigned as one layer to be multiplexed onto an OFDM signal. For this reason, the transmitting device 1 shown in Fig. 1 generates an OFDM modulated signal by orthogonal frequency division multiplexing the LLch carrier that is the carrier of the LLch transmission data, independent of the data carrier that is the main signal and the TMCC carrier that is the transmission control signal. Therefore, the LLch carrier can be transmitted to the receiving device 2, independent of the data carrier that is the main signal, like the TMCC carrier.

[0047] The transmitting device 1 illustrated in Fig. 1 has an encoder 10 including a first LDPC encoder 11 that performs a first LDPC encoding process on data (L0ch transmission data) to be transmitted using a first segment area (9 segments) that is a partial reception band in the center among a predetermined number of segments (35 segments) assigned to LLch, using a check matrix H with a first LDPC coding rate of 144 / 1224, and a second LDPC encoder 12 that performs a second LDPC encoding process on data (L1ch transmission data) to be transmitted using a second segment area (26 segments) that is a non-partial reception band other than the partial reception band, using a check matrix with a second LDPC coding rate of 1016 / 1224. Hereinafter, each component of the transmitting device 1 illustrated in Fig. 1 will be described.

[0048] The first LDPC encoding unit 11 inputs a bit string (144 information bits) of L0ch transmission data to be transmitted using a first segment area (9 segments) which is a partial reception band in the center of LLch, performs a first LDPC encoding process using a check matrix H with a first LDPC coding rate of 144 / 1224, constructs an error correction block having L0ch transmission data with LDPC parity added, and outputs the error correction block to the DBPSK modulation unit 13.

[0049] Incidentally, the first LDPC encoding unit 11 has a parity interleaving unit 11a that interchanges bits of the LDPC parity in an order specified in advance by a submatrix of the parity check matrix H, the details of which will be described later.

[0050] The second LDPC encoding unit 12 inputs a bit string (1016 information bits) of L1ch transmission data to be transmitted using a second segment area (26 segments) serving as a non-partial reception band of LLch, performs a second LDPC encoding process using a parity check matrix H with a second LDPC coding rate of 1016 / 1224, configures an error correction block having L1ch transmission data with LDPC parity added, and outputs the block to the DBPSK modulation unit 13. Note that, although an example will be described in which the second LDPC encoding unit 12 in this example does not have a parity interleaving function for replacing bits of LDPC parity, it is also possible to configure the second LDPC encoding unit 12 to have a parity interleaving unit similar to the first LDPC encoding unit 11.

[0051] Fig. 3(a) is a diagram showing the configuration of an error correction block with an LDPC coding rate of 144 / 1224 according to an embodiment of an LDPC code with a code length of 1224 bits formed for data (L0ch transmission data) transmitted using a first segment area (9 segments) that is a partial reception band in the center among a predetermined number of segments (35 segments) assigned to a low-delay transmission channel according to the present invention. Also, Fig. 3(b) is a diagram showing the configuration of an error correction block with an LDPC coding rate of 1016 / 1224 according to an embodiment of an LDPC code with a code length of 1224 bits formed for data (L1ch transmission data) transmitted using a second segment area (26 segments) that is a non-partial reception band other than the partial reception band among a predetermined number of segments (35 segments) assigned to a low-delay transmission channel according to the present invention.

[0052] As shown in Fig. 3(a) and (b), the error correction block of the L0ch transmission data with the first LDPC coding rate of 144 / 1224 in the first LDPC encoding unit 11 and the error correction block of the L1ch transmission data with the second LDPC coding rate of 1016 / 1224 in the second LDPC encoding unit 12 are configured by dividing the input bit string into predetermined lengths according to the respective LDPC coding rates. For example, for the error correction block with the LDPC coding rate of 144 / 1224 shown in Fig. 3(a), the input bit string of the L0ch transmission data is divided into 144-bit pieces as the information bit length, and each time it is output to the subsequent functional block.

[0053] In addition, the code length of each error correction block is 1224 bits based on the LDPC code, and the code length unit of the error correction block is common to reduce unnecessary processing load. Furthermore, it is generally known that the performance of the LDPC code is improved compared to the turbo code when the code length is 1000 bits or more, and on the other hand, in order to achieve low-delay transmission, it is preferable to use a code length as short as possible, so the code length is set to 1224 bits. In addition, since L0ch has 9 segments, and there are 8 carriers per segment, the code length is set to a multiple of 72. As a code length that satisfies this condition, other than 1224 bits, there are options such as 1008 bits, 1080 bits, and 1152 bits for lower-delay transmission, but 1224 bits is selected as a configuration that not only improves performance compared to difference set cyclic code or Reed-Solomon code, but also definitely improves performance compared to turbo code.

[0054] Moreover, the first LDPC coding rate of the L0ch transmission data is required to be receivable even at a very low C / N ratio in consideration of the transmission of an emergency earthquake warning, so it is set to 0.1 or more and less than 0.2, and therefore, as shown in Fig. 3(a), it is configured with 144 information bits. Moreover, the second LDPC coding rate of the L1ch transmission data is required to be 48 kbps in consideration of the transmission of voice, so it is set to 0.8 or more and less than 1.0, and therefore, as shown in Fig. 3(b), it is configured with 1016 information bits. In this way, the transmitting device 1 according to the present invention is divided into two types of segment areas so that the LDPC coding rate according to the purpose can be applied, and an appropriate coding rate is selected according to the purpose.

[0055] The DBPSK modulation unit 13 generates LLch carriers through symbol mapping by DBPSK modulation for the error correction blocks of the L0ch transmission data and the L1ch transmission data, each of which has an LDPC parity added, and outputs the LLch carriers to the OFDM modulation unit 16. Note that, in order to bring about a diversity effect on the receiving device 2 side, the LLch carriers may be allocated in the symbol direction in any number of 1, 2, 4, or 8 for the error correction blocks of the same content within the first segment area (9 segments) for the L0 carrier and within the second segment area (26 segments) for the L1 carrier.

[0056] The OFDM modulation unit 16 performs orthogonal frequency division multiplexing on the LLch carrier, the three-layer data carrier, and the TMCC carrier, which is a transmission control signal, to generate an OFDM modulated signal, and outputs it to the outside.

[0057] Next, a receiving device 2 according to an embodiment of the present invention will be described with reference to FIG.

[0058] [Receiving device] FIG. 2 is a block diagram showing only the main components of a receiver 2 for low-delay transmission channel (LLch) data according to an embodiment of the present invention. The receiver 2 shown in FIG. 2 includes an OFDM demodulator 21, an LLch carrier extractor 22, a DBPSK demodulator 23, and an LDPC decoder 24. In this example, the modulation method and coding rate of the LLch transmission data are determined in advance between the transmitter 1 shown in FIG. 1 and the receiver 2 shown in FIG. 2, and the receiver 2 demodulates and decodes the LLch transmission data without demodulating and decoding the TMCC signal. However, a configuration may also be adopted in which transmission-related parameters such as the modulation method and coding rate of the LLch transmission data are included in the TMCC signal and transmitted, and the receiver 2 demodulates and decodes the LLch transmission data after demodulating and decoding the TMCC signal.

[0059] The OFDM demodulation unit 21 receives the OFDM modulated signal transmitted from the transmission device 1 , performs OFDM demodulation processing, and outputs the OFDM demodulated signal to the LLch carrier extraction unit 22 .

[0060] The LLch carrier extraction unit 22 extracts at least one of the LLch carriers of L0ch and L1ch from the OFDM demodulated signal based on an external specification of L0ch or L1ch (or both L0ch and L1ch), and outputs it to the DBPSK demodulation unit 23.

[0061] The DBPSK demodulation unit 23 performs DBPSK demodulation on the LLch carrier obtained through the LLch carrier extraction unit 22 through symbol demapping based on DBPSK, extracts the LLch symbol of L0ch or L1ch, and outputs it to the LDPC decoding unit 24.

[0062] The LDPC decoding unit 24 reconstructs the LLch transmission data with error correction parity added for the extracted LLch symbols of L0ch or L1ch (or both L0ch and L1ch) based on a likelihood judgment using a corresponding check matrix, performs decoding processing based on the LDPC code to restore a bit string corresponding to the LLch transmission data of L0ch or L1ch (or both L0ch and L1ch) on the transmitting side, and outputs the bit string to the outside as an output bit string.

[0063] That is, the LDPC decoding unit 24 is configured as a decoder including: means for LDPC decoding, using a check matrix with a first LDPC coding rate of 144 / 1224, data encoded by a first LDPC encoding process performed by a first LDPC encoding unit 11 in the encoder 10; and means for LDPC decoding, using a check matrix with a second LDPC coding rate of 1016 / 1224, data encoded by a second LDPC encoding process performed by a second LDPC encoding unit 12 in the encoder 10.

[0064] [LDPC code with a code length of 1224 bits] First, with reference to the above-mentioned Fig. 3 and Fig. 4 to Fig. 10, the encoder 10 and the decoder (LDPC decoding unit 24) for each of the coding rates of 144 / 1224 and 1016 / 1224 in the LDPC code with a code length of 1224 bits will be described. Fig. 4(a) and (b) are diagrams showing the check matrix H with the LDPC coding rate of 144 / 1224 for the LDPC code with a code length of 1224 bits formed for the L0ch transmission data according to the present invention, and the check matrix H with the LDPC coding rate of 1016 / 1224 for the LDPC code with a code length of 1224 bits formed for the L1ch transmission data according to the present invention. Fig. 5 is a diagram showing a submatrix B on the check matrix H for the L0ch transmission data according to the present invention and the LDPC code with a code length of 1224 bits formed for the L1ch transmission data. Figs. 6 to 9 are diagrams showing the submatrices I, A, C, and D on the check matrix H for the LDPC code of the L0ch transmission data, respectively. FIG. 10 is a diagram showing a submatrix A on a parity check matrix H related to an LDPC code with a code length of 1224 bits formed for L1ch transmission data according to the present invention.

[0065] (Error correction block configuration with coding rates of 144 / 1224 and 1016 / 1224) As shown in Fig. 3(a), the error correction block of the L0ch transmission data is composed of 144 information bits and a code length of 1224 bits consisting of 1080 LDPC parity bits, and the coding rate is 144 / 1224. Also, as shown in Fig. 3(b), the error correction block of the L1ch transmission data is composed of 1016 information bits and a code length of 1224 bits consisting of 208 LDPC parity bits, and the coding rate is 1016 / 1224.

[0066] In the above-mentioned FIGS. 1 to 3, only the LDPC code is used as the error correction code. However, for example, the information bits in FIGS. 3(a) and 3(b) may include the parity of the BCH code, or may be appropriately subjected to power dispersal processing.

[0067] (Encoder processing process at LDPC coding rate 144 / 1224) As shown in Fig. 4(a), the first LDPC encoding unit 11 in the encoder 10 of this embodiment generates a check matrix H with an LDPC coding rate of 144 / 1224, which is divided into six regions by submatrices A, B, C, D, I, and O, and generates LDPC code parity using this check matrix H. The row length of the check matrix H corresponds to the LDPC code length, and the LDPC code length N is set to 1224. Since the coding rate of this check matrix is ​​144 / 1224, the column length of the check matrix H corresponds to the LDPC parity length, and the LDPC parity length P is 1080 bits.

[0068] In FIG. 4(a), submatrices A, C, and D are submatrices constructed using the parity check matrix initial value table shown in Table 1 above, and the LDGM structure (FIG. 5) is applied to submatrix B. The LDGM structure is a step matrix in which the row weight (the number of 1s in the row direction of the parity check matrix) is 1 in the first row, all the remaining row weights are 2, and the column weight is 2 for all columns. In the case of an error correction block of L0ch transmission data, the size of submatrix B is 72 bits in both the row and column directions. In addition, a diagonal matrix (FIG. 6) is applied to submatrix I. All row weights of the diagonal matrix are 1. The size of submatrix I is 1008 bits in both the row and column directions. Submatrix O corresponds to a zero matrix.

[0069] In the case of an error correction block of L0ch transmission data, the size of the submatrix A is composed of 72 bits (rows)×144 bits (columns) as shown in FIG.

[0070] Moreover, the size of the submatrix C is, as shown in FIG. 8, 1008 bits (rows)×144 bits (columns).

[0071] Moreover, the size of the submatrix D is, as shown in FIG. 9, composed of 1008 bits (rows)×72 bits (columns).

[0072] Since the size of any of the submatrices A, C, and D is finite, the positions of 1 in the parity check matrix are calculated based on the following equation (1). H q-j = mod{(h i-j + mod((q-1),8)) × Q),P} (1) Here, h i-j i is the row number of the check matrix initial value table, and h i-j j is the column number of the check matrix initial value table. q-j indicates the row number of the 1 in the qth column of the check matrix H. q-jIn the above, j indicates the order of the number of elements of the column weight. Therefore, when the column weight is 9, j = 1 to 9. q = 1 means that the first row of the check matrix initial value table is used. Also, mod(x, y) means the remainder when x is divided by y. Q in formula (1) is the number of cycles, whose value is determined for each coding rate, and Q is calculated using formula (2).

[0073] Q = row size of each submatrix / 8 (2)

[0074] Therefore, in the LDPC coding rate of this embodiment, Q=9 (first cycle number Q1) for submatrix A, and Q=126 (second cycle number Q2) for submatrix C and submatrix D.

[0075] A more specific method of generating check matrix H divided into six regions by submatrices A, B, C, D, I, and O at an LDPC coding rate of 144 / 1224 will be described below.

[0076] First, the submatrix A (FIG. 7) will be described. In order to form the submatrix A, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads out numerical values ​​from a part of the parity check matrix initial value table shown in Table 1 above, and periodically arranges the positions of 1 in the area of ​​the submatrix A in the parity check matrix H. The parity check matrix initial value table shown in Table 1 lists 27 numerical values ​​in the column direction and a maximum of 15 numerical values ​​in the row direction. These numerical values ​​correspond to the initial positions (initial values) of 1 in the parity check matrix used in the submatrices A, C, and D. That is, the numerical coordinates hi-j (numerical values) of the i-th row and j-th column in Table 1 specify the initial positions of 1 in the submatrices A, C, and D in the parity check matrix H shown in FIG. 4(a). As an example, in FIG. 7, h1-1(6) corresponds to arranging the 1 in the first column of the submatrix A in the sixth row of the parity check matrix H, and h1-2(50) corresponds to arranging the 1 in the first column of the submatrix A in the 50th row of the parity check matrix H. In addition, h2-1(28) corresponds to placing the 1 in the 9th column of submatrix A in the 28th row of parity check matrix H, and h2-2(43) corresponds to placing the 1 in the 9th column of submatrix A in the 43rd row of parity check matrix H.

[0077] Based on the above relationship, as shown in FIG. 7 , the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads out all of the numerical coordinates hi-j (numerical values) of 18 rows and j columns (3 columns) for specifying row positions at which 1 is to be placed for every 8 columns of submatrix A from the parity check matrix initial value table in Table 1, and initially assigns 1 to the specified positions in submatrix A, shifts 1 bit to the right in the row direction based on the position of this initially assigned 1, and then assigns 1 to positions shifted downward in the column direction by a first cycle number Q1=9 (9 bits), thereby repeating this process to configure submatrix A in parity check matrix H.

[0078] <Numeric coordinates hi-j (numeric values) for submatrix A of the check matrix initial value table in Table 1> Line 1: h1-1(6) to h1-3(67) 2nd line: h2-1(28) to h2-3(56) 3rd line: h3-1(0) to h3-3(21) ... Line 18: h18-1(51) to h18-3(68)

[0079] In this way, by reading out the numerical values ​​of 18 rows (each of these 18 rows corresponds to the first column of every 8 columns of submatrix A) in the numerical coordinates hi-j (numerical values) for submatrix A in Table 1 column by column (the numerical value of each column corresponds to the first row position of every 8 columns of submatrix A), and repeating the first cycle number Q1=9 shifts as shown in Fig. 7, it becomes possible to specify the position of 1 in submatrix A in the parity check matrix H equivalent to 8×18=144 bits (columns). Also, the number of rows in submatrix A is 8×Q1=72, and the size of submatrix A is 144 bits in the row direction and 72 bits in the column direction.

[0080] Next, the submatrix C (FIG. 8) will be described. In order to form the submatrix C, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads out values ​​from a part of the parity check matrix initial value table shown in Table 1 above, and periodically arranges the positions of 1 within the area of ​​the submatrix C in the parity check matrix H. The parity check matrix initial value table shown in Table 1 lists 27 values ​​in the column direction and a maximum of 15 values ​​in the row direction. The submatrix C differs from the submatrix A in the read out positions in the parity check matrix initial value table and the number of cycles.

[0081] As shown in FIG. 8, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads out all of the numerical coordinates hi-j (numerical values) of 18 rows and j columns (maximum 12 columns) for specifying row positions at which 1 is to be placed every 8 columns of the submatrix C from the parity check matrix initial value table in Table 1, and initially assigns 1 to the specified positions in the submatrix C, shifts 1 bit to the right in the row direction based on the position of the initially assigned 1, and then assigns 1 to positions shifted downward in the column direction by the second cycle number Q2=126 (126 bits), thereby repeating this process to configure the submatrix C in the parity check matrix H in FIG. 4(a).

[0082] <Numeric coordinates hi-j (numeric values) for submatrix C of the parity check matrix initial value table in Table 1> 1st line: h1-4(259) to h1-15(990) 2nd line: h2-4(140) to h2-15(1037) 3rd line: h3-4(105) to h3-15(998) 4th line: h4-4(99) to h4-15(920) 5th line: h5-4(101) to h5-13(762) ... Line 18: h18-4(142) to h18-13(961)

[0083] In this way, by reading out the values ​​of 18 rows (each of these 18 rows corresponds to the first column of every 8 columns of submatrix C) in the numerical coordinates hi-j (numerical value) for submatrix C in Table 1 for each column (the numerical value of each column corresponds to the first row position of every 8 columns of submatrix C), and repeating the second cycle number Q2=126 shifts as shown in Fig. 8, it becomes possible to specify the position of 1 in submatrix C in the parity check matrix H equivalent to 8×18=144 bits (columns). Also, the number of rows of submatrix C is 8×Q2=1008, and the size of submatrix C is 144 bits in the row direction and 1008 bits in the column direction.

[0084] Next, the submatrix D (FIG. 9) will be described. In order to form the submatrix D, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads out numerical values ​​from a part of the parity check matrix initial value table shown in Table 1 above (rows 19 to 27 in Table 1) and periodically arranges the positions of 1 in the area of ​​the submatrix D in the parity check matrix H. However, the submatrix D applies the second cycle number Q2=126, which is the same as the submatrix C, but differs from the submatrix C in that the parity bit replacement is applied as the parity interleaving unit 11a by using a row-direction bit shift equivalent to the first cycle number Q1=9 in the read cycle in the parity check matrix initial value table.

[0085] As shown in FIG. 9, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads out all of the numerical coordinates hi-j (numerical values) of 9 rows×j columns (8 columns) for specifying row positions at which 1's are to be placed every 8 columns of the submatrix D from the parity check matrix initial value table in Table 1, and initially assigns 1's to the specified positions in the submatrix D. Using the position of 1 initially assigned as a reference, the first LDPC encoding unit 11 shifts rightward in the row direction by a first cycle number Q1=9 bits, and then assigns 1's to positions shifted downward in the column direction by a second cycle number Q2=126 (126 bits), thereby configuring the submatrix D in the parity check matrix H in FIG. 4(a).

[0086] <Numeric coordinates hi-j (numeric values) for submatrix D in the parity check matrix initial value table in Table 1> Line 19: h19-1(217) to h19-8(1050) Line 20: h20-1(86) to h20-8(1059) Line 21: h21-1(481) to h21-8(1075) Line 22: h22-1(561) to h22-8(1012) Line 23: h23-1(213) to h23-8(1043) ... Line 27: h27-1(90) to h27-8(1052)

[0087] In this way, the read method of the parity check matrix initial value table to which parity interleaving is applied is a read method different from the submatrices A and C, and the numerical values ​​of 9 rows (each of these 9 rows corresponds to the first 9 columns of the submatrix D) in the numerical coordinate hi-j (numerical value) for the submatrix D in Table 1 are read column by column (the numerical value for each column corresponds to the row position of each of the first 9 columns of the submatrix D), and the read of one row of the numerical coordinate hi-j (numerical value) for the submatrix D in Table 1 is regarded as one set. Then, as shown in FIG. 9, by repeating a right shift of Q1=9 bits corresponding to the first cycle number and a downward shift of Q2=126 corresponding to the second cycle number eight times, it is possible to specify the position of 1 of the submatrix D in the parity check matrix H corresponding to 8×9=72 bits (columns). The number of rows of the submatrix D is 8×Q2=1008, and the size of the submatrix D is 72 bits in the row direction and 1008 bits in the column direction.

[0088] That is, the relationship between the check matrix initial value table in submatrix D shown in Table 1 and the column numbers in check matrix H is as follows: The value in the 19th row of the parity check matrix initial value table indicates the first position of 1 in the 145th column of parity check matrix H (i.e., the first column of submatrix D) (the row position in the first parity check matrix H repeated with cycle numbers Q1 and Q2). The value in the 20th row of the parity check matrix initial value table describes the first position of 1 in the 146th column (i.e., the second column of submatrix D) of parity check matrix H (the row position in the first parity check matrix H repeated with cycle numbers Q1 and Q2). The value in the 21st row of the parity check matrix initial value table is the first position of a 1 in the 147th column of the parity check matrix H (i.e., the third column of submatrix D) (the row position in the first parity check matrix H to be repeated with cycle numbers Q1 and Q2). The value in the 22nd row of the parity check matrix initial value table indicates the first position of a 1 in the 148th column of parity check matrix H (i.e., the 4th column of submatrix D) (the row position in the first parity check matrix H to be repeated with cycle numbers Q1 and Q2). The value in the 23rd row of the parity check matrix initial value table indicates the first position of a 1 in the 149th column of parity check matrix H (i.e., the 5th column of submatrix D) (the row position in the first parity check matrix H repeated with cycle numbers Q1 and Q2). The same applies below.

[0089] In FIG. 9, the value read from the 19th row of the parity check matrix initial value table is shifted by Q2=126 for every Q1=9 bits. By repeating this operation 8 times, the position of 1 in the submatrix D is determined for a total of 8 columns. Similarly, the value read from the 20th row of the parity check matrix initial value table is also shifted by Q2=126 for every Q1=9 bits, and the position of 1 in the submatrix D is determined for a total of 8 columns. After that, by repeating the same process for the 21st to 27th rows, the position of 1 in the submatrix D equivalent to 8 columns×9 sets=72 bits is determined. Therefore, the size of the submatrix D is 72 bits in the row direction and 1008 bits in the column direction. In this way, by including the submatrix D to which the parity interleaving that shifts by Q2 for every Q1 is applied in the parity check matrix H, it is possible to avoid the occurrence of cycle 4 that occurs between this submatrix D and the submatrix B that is connected to the higher order, and improve the decoding performance of the LDPC code. In other words, one of the factors that deteriorates the transmission characteristics of an LDPC code is the occurrence of an error floor, and it is known that the possibility of this error floor occurring increases when the arrangement of 1s contained in the check matrix H has many shape arrangements of cycle 4, for example. Therefore, as a means of solving this problem, the check matrix H is made to include a submatrix D.

[0090] Using the check matrix H, which is a set matrix of submatrices A, B, C, D, I, and O at the LDPC coding rate of 144 / 1224 obtained by the above process, the LDPC parity is calculated by the parity check equation (3). Note that, in the case of the coding rate of 144 / 1224, since the information bit length is 144 bits, in the parity check equation, the parity calculation based on the LDGM structure is applied to the 1st row to the 72nd row of the check matrix H, and the parity calculation based on the diagonal structure is applied to the 73rd row to the 1080th row.

[0091] H.C. T =0 (3)

[0092] (Encoder processing process at LDPC coding rate 1016 / 1224) On the other hand, the second LDPC encoding unit 12 in the encoder 10 of this embodiment generates a check matrix H with an LDPC coding rate of 1016 / 1224, which is divided into two regions by submatrices A and B, as shown in Fig. 4(b), and generates LDPC code parity using this check matrix H. The row length of the check matrix H corresponds to the LDPC code length, and the LDPC code length N is set to 1224. Since the coding rate of this check matrix is ​​1016 / 1224, the column length of the check matrix H corresponds to the LDPC parity length, and the LDPC parity length P is 280 bits.

[0093] In Fig. 4(b), submatrix A is a submatrix configured using the parity check matrix initial value table shown in Table 2 above, and the LDGM structure (Fig. 5) is applied to submatrix B. The LDGM structure is a step matrix in which the row weight (the number of 1s in the row direction of the parity check matrix) is 1 for the first row, all the remaining row weights are 2, and the column weight is 2 for all columns. The size of submatrix B is 208 bits in both the row and column directions in the case of the error correction block of L1ch transmission data.

[0094] In the case of an error correction block of L1ch transmission data, the size of submatrix A is composed of 208 bits (rows)×1016 bits (columns), as shown in FIG.

[0095] Since the size of the submatrix A is finite, the positions of 1 in the parity check matrix are calculated based on the above-mentioned formula (1). Furthermore, Q in formula (1) is calculated by the above-mentioned formula (2), and as shown in FIG. 10, Q=208 / 8=26.

[0096] Therefore, in the LDPC coding rate of this embodiment, 1016 / 1224, Q of the submatrix A is 26.

[0097] A method of generating a check matrix H from a submatrix A with an LDPC coding rate of 1016 / 1224 will be described more specifically below.

[0098] In order to form submatrix A, the second LDPC encoding section 12 in the encoder 10 of this embodiment reads out values ​​from a portion of the parity check matrix initial value table shown in Table 2 above, and periodically arranges the positions of 1 within the area of ​​submatrix A in parity check matrix H. The parity check matrix initial value table shown in Table 2 lists 127 values ​​in the column direction and a maximum of 5 values ​​in the row direction. This value corresponds to the first position (initial value) of 1 in the parity check matrix used in submatrix A. That is, the numerical coordinate h i-j (Numerical value) specifies the first position of 1 in submatrix A in parity check matrix H shown in Fig. 4(b). As an example, in Fig. 10, h1-1(7) corresponds to arranging the 1 in the first column of submatrix A in the seventh row of parity check matrix H, and h1-2(62) corresponds to arranging the 1 in the first column of submatrix A in the 62nd row of parity check matrix H. Also, h2-1(58) corresponds to arranging the 1 in the 9th column of submatrix A in the 58th row of parity check matrix H, and h2-2(91) corresponds to arranging the 1 in the 9th column of submatrix A in the 91st row of parity check matrix H.

[0099] Based on the above relationship, as shown in FIG. 10 , the second LDPC encoding unit 12 in the encoder 10 of this embodiment reads out all of the numerical coordinates hi-j (numerical values) of 127 rows and j columns (maximum of 5 columns) for specifying row positions at which 1 is to be placed every 8 columns of submatrix A from the parity check matrix initial value table in Table 2, and initially assigns 1 to the specified positions in submatrix A, shifts 1 bit to the right in the row direction based on the position of this initially assigned 1, and assigns 1 to positions shifted downward in the column direction by the number of cycles Q=26 (26 bits), thereby repeating this process to configure submatrix A in parity check matrix H.

[0100] <Numeric coordinates hi-j (numeric values) for submatrix A in the check matrix initial value table in Table 2> Line 1: h1-1(7) to h1-5(193) 2nd line: h2-1(58) to h2-5(153) 3rd line: h3-1(2) to h3-5(200) ... 8th line: h8-1(15) to h8-5(203) 9th line: h9-1(61) to h9-3(176) ... Line 127: h127-1(2) to h127-3(198)

[0101] In this way, the numerical values ​​of 127 rows (each of these 127 rows corresponds to the first column of every 8 columns of submatrix A) in the numerical coordinates hi-j (numerical value) for submatrix A in Table 2 are read out column by column (the numerical value of each column corresponds to the first row position of every 8 columns of submatrix A), and the cycle number Q=26 shifts are repeated as shown in Fig. 10, thereby making it possible to specify the position of 1 of submatrix A in the parity check matrix H equivalent to 8 x 127 = 1016 bits (columns). The number of rows of submatrix A is 8 x Q1 = 208, and the size of submatrix A is 1016 bits in the row direction and 208 bits in the column direction.

[0102] Using the check matrix H, which is the aggregate matrix of submatrices A and B at the LDPC coding rate of 1016 / 1224 obtained by the above process, the LDPC parity is calculated by the above-mentioned parity check equation (3). Note that, in the case of the coding rate of 1016 / 1224, since the information bit length is 1016 bits, the parity calculation based on the LDGM structure is applied in the parity check equation.

[0103] In addition, the check matrix initial value table for the check matrix used in the LDPC coding can be transmitted as auxiliary information from the transmitting device 1 to the receiving device 2, or can be held in advance by the receiving device 2. Alternatively, the check matrix itself can be transmitted from the transmitting device 1 to the receiving device 2, or can be held in advance by the receiving device 2.

[0104] Next, the process of the decoder (LDPC decoding unit 24) of this embodiment will be described.

[0105] (Decoder processing for LDPC coding rates of 144 / 1224 and 1016 / 1224) The decoder (LDPC decoding unit 24) of this embodiment performs LDPC code decoding processing by using the check matrix H shown in Fig. 4(a) for decoding the coded data (L0ch transmission data) with an LDPC coding rate of 144 / 1224, and by using the check matrix H shown in Fig. 4(b) for decoding the coded data (L1ch transmission data) with an LDPC coding rate of 1016 / 1224. The modulation method of each carrier of L0ch and L1ch of these coded data is transmitted by DBPSK.

[0106] The decoder (LDPC decoder 24) of this embodiment first receives the transmitted symbol x n and the received symbol y n Based on the log-likelihood ratio λ n (n=1~1224) is calculated. n is the natural logarithm of the ratio of the likelihood of sending bits 0 and 1, and is the ratio of the likelihood of sending symbols x n and the received symbol y n It is expressed by equation (4) using

[0107] λ n = ln{P(y n |x n =0) / P(y n |x n =1)} (4)

[0108] Using the log-likelihood ratio obtained by equation (4) and the check matrix H (corresponding to Figs. 4(a) and (b)) corresponding to each of the above-mentioned coding rates, LDPC decoding is performed using sum-product decoding or the like. The number of iterative decoding operations may be any value. In addition to sum-product decoding, various other methods such as min-sum decoding have been proposed for LDPC decoding, and various methods for maximizing the likelihood ratio using a check matrix can be applied to the LDPC decoding according to the present invention.

[0109] 11(a) and (b) show the C / N vs. BER (Bit Error Rate) and FER (Frame Error Rate) characteristics (computer simulation) when DBPSK modulation is applied to L0ch transmission data and L1ch transmission data according to the present invention, respectively. BER indicates the bit error rate, and FER indicates the frame error rate with one error correction block as a frame. For the L0ch transmission data shown in FIG. 11(a), the required C / N to satisfy BER=1.0E-7 is about -1.6 dB, and for the L1ch transmission data shown in FIG. 11(b), the required C / N to satisfy BER=1.0E-7 is about 5.7 dB. On the other hand, for the AC transmission data in the conventional terrestrial digital broadcasting system ISDB-T, the required C / N to satisfy BER=1.0E-7 is a value too large to be shown in FIG. 11, and is about 10 dB or more. Therefore, it was confirmed that the transmission performance of the L0ch transmission data and the L1ch transmission data according to the present invention has enhanced resistance to noise in both cases.

[0110] In the next generation terrestrial digital broadcasting system, the code length of the LDPC code used for the data carrier forming the main signal is considered to be 69120 bits (high quality transmission) or 17280 bits (simple transmission), but since the code length of the L0ch transmission data and the L1ch transmission data according to the present invention is 1224 bits, it is understood that extremely low delay transmission for the main signal is realized. Also, a significantly lower delay is realized compared to the current terrestrial digital broadcasting system ISDB-T. For example, the current terrestrial digital broadcasting system ISDB-T has a transmission delay of about 230 ms, but it has been confirmed that the transmission delay time of the L0ch transmission data according to the present invention at BER=1.0E-7 is about 25 ms after improving the SNR compared to ISDB-T, and even if 4 carriers are combined to further improve the SNR, it will be about 100 ms, so a significantly lower delay and lower noise is realized.

[0111] Regarding the above-described embodiment, each of the encoder 10 and the decoder (LDPC decoding unit 24), the transmitter 1 and the receiver 2 can be configured with one or more chips.

[0112] Furthermore, with respect to the above-mentioned embodiment, a computer that functions as the encoder 10 and the decoder (LDPC decoding unit 24), as well as the transmitting device 1 and the receiving device 2, can be configured, and a program for making each of the means of the encoder 10 and the decoder (LDPC decoding unit 24), as well as the transmitting device 1 and the receiving device 2 function can be suitably used. Specifically, a control unit for controlling each of the means can be configured with a central processing unit (CPU) in a computer, and a storage unit for appropriately storing a program required for operating each of the means can be configured with at least one memory. That is, the function of each of the above-mentioned means can be realized by having the CPU execute the program in such a computer. Furthermore, a program for making each of the means function can be stored in a predetermined area of ​​the above-mentioned storage unit (memory). Such a storage unit can be configured with a RAM or ROM inside the device, or can be configured with an external storage device (for example, a hard disk). Moreover, such a program can be configured with a part of the software on the OS (stored in a ROM or an external storage device) used by the computer. Furthermore, a program for making such a computer function as each of the means can be recorded on a computer-readable recording medium. Furthermore, each of the above-mentioned means can be configured as part of hardware or software, and can be realized by combining each of them.

[0113] Although the above-mentioned embodiment is described as a representative example, it is obvious to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present invention. For example, as other error correction coding when combined with LDPC coding, in addition to BCH coding, not only block coding such as Reed-Solomon coding, but also convolutional coding may be used, or other LDPC coding may be combined. Therefore, the present invention should not be construed as being limited by the above-mentioned embodiment, but is limited only by the claims. [Industrial Applicability]

[0114] An encoder and decoder, as well as a transmitter and a receiver according to the present invention, are useful in OFDM transmission systems requiring low-delay transmission. [Explanation of symbols]

[0115] 1. Transmitting device 10 encoder 11 First LDPC Encoding Unit 11a Parity interleave section 12 Second LDPC Encoding Section 13 DBPSK Modulation Section 16 OFDM Modulation Section 21 OFDM demodulation section 22 LLch carrier extraction section 23 DBPSK demodulation section 24 LDPC Decoding Section (Decoder) 100 Conventional transmitting device 101 Difference set cyclic coding unit 102 DBPSK Modulation Section 103 OFDM Modulation Section 200 Conventional receiving device 201 OFDM demodulation section 202 AC carrier extraction unit 203 DBPSK demodulation section 204 Difference Set Cyclic Code Decoding Unit

Claims

1. An encoder that performs error correction coding processing on transmission data of a low-delay transmission channel in a terrestrial digital broadcasting system, a first LDPC encoding means for performing a first LDPC encoding process on data to be transmitted using a first segment area, which is a central partial reception band, among a predetermined number of segments assigned to the low latency transmission channel, using a parity check matrix of a first LDPC coding rate; and a second LDPC encoding means for performing a second LDPC encoding process on data to be transmitted using a second segment area that is a non-partial reception band other than the partial reception band among a predetermined number of segments assigned to the low-latency transmission channel, using a parity check matrix of a second LDPC coding rate, The encoder according to claim 1, wherein the first LDPC encoding process and the second LDPC encoding process have the same code length.

2. 2. The encoder according to claim 1, wherein the first LDPC coding rate is set to a lower coding rate than the second LDPC coding rate.

3. 3. The encoder according to claim 1, wherein the code length is 1224 bits.

4. 4. The encoder according to claim 1, wherein the first LDPC coding rate is greater than or equal to 0.1 and less than 0.2, and the second LDPC coding rate is greater than or equal to 0.8 and less than 1.

0.

5. 5. The encoder of claim 1, wherein the first LDPC coding rate is 144 / 1224 and the second LDPC coding rate is 1016 / 1224.

6. the first LDPC encoding means is configured to perform the first LDPC encoding process using a check matrix having a code length of 1224 bits and an initial value set to a check matrix initial value table that is predetermined according to the first LDPC coding rate; 6. The encoder according to claim 1, wherein the check matrix includes a first submatrix in which one element of a submatrix corresponding to an information length according to the first LDPC coding rate is arranged in the column direction periodically at a first cycle number, a second submatrix in which one element is arranged in the column direction periodically at a second cycle number different from the first cycle number, and a third submatrix obtained by performing parity interleaving by shifting in the row direction for each of the first cycle number and arranging one element in the column direction periodically at the second cycle number.

7. the second LDPC encoding means is configured to perform the second LDPC encoding process using a check matrix having a code length of 1224 bits and an initial value set to a check matrix initial value table that is predetermined according to the second LDPC coding rate; 7. The encoder according to claim 1, wherein the check matrix includes a submatrix in which one element of a submatrix corresponding to an information length according to the second LDPC coding rate is arranged in a column direction periodically at a third cycle number.

8. The check matrix initial value table for the coding rate of 144 / 1224 indicating initial values ​​when the first submatrix is ​​submatrix A, the second submatrix is ​​submatrix C, and the third submatrix is ​​submatrix D is given as follows: 【Table 1】 7. An encoder as claimed in claim 6, comprising:

9. The parity check matrix initial value table for the coding rate of 1016 / 1224 indicating the initial values ​​of the submatrices is 【Table 2-1】 【Table 2-2】 【Table 2-3】 8. An encoder as claimed in claim 7, characterized in that it comprises:

10. 10. A decoder comprising: means for LDPC decoding data encoded by the encoder according to claim 1 using a check matrix of the first LDPC coding rate; and means for LDPC decoding data encoded by the encoder using the second LDPC coding rate using a check matrix of the second LDPC coding rate.

11. A transmitting device comprising an encoder according to any one of claims 1 to 9.

12. A receiving device comprising a decoder according to claim 10.

13. A chip comprising any one of the encoder according to claim 1 to 9, the decoder according to claim 10, the transmitter according to claim 11, and the receiver according to claim 12.

Images