Semiconductor Module

Abstract

To provide a structure of a semiconductor module suitable for a semiconductor element of gallium oxide.SOLUTION: A semiconductor module includes a semiconductor element 10, a first conductor plate 22, and a second conductor plate 26. The semiconductor element 10 includes a gallium oxide substrate 12, a lower surface electrode 14, and an upper surface electrode 16. The first conductor plate has a first joint surface 22a jointed to the lower surface electrode of the semiconductor element, and the second conductor plate has a second joint surface 26a jointed to the upper surface electrode of the semiconductor element. The gallium oxide substrate includes an active area (12X) and a non-active area 12Y that surrounds the active area. In a direction perpendicular to the gallium oxide substrate, the entire active area opposes the first joint surface of the first conductor plate and also opposes the second joint surface of the second conductor plate.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor module.

[0002] Patent Document 1 discloses a semiconductor module. This semiconductor module includes a semiconductor element, a first conductive plate joined to a lower electrode of the semiconductor element, and a second conductive plate joined to an upper electrode of the semiconductor element. With this configuration, heat generated in the semiconductor element is diffused through the first conductive plate and the second conductive plate, suppressing a temperature rise of the semiconductor element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-079957 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, the use of gallium oxide (Ga2O3) as a semiconductor material for semiconductor elements has been considered. While gallium oxide has many advantages, it is characterized by its low thermal conductivity. For example, the thermal conductivity of silicon carbide (SiC) is 490 W / mK, while that of gallium oxide is 14.1 W / mK. For this reason, in semiconductor elements that use gallium oxide, heat diffusion is difficult to occur inside the semiconductor element, and uneven temperature distribution is likely to occur. For such semiconductor elements, the structure of conventional semiconductor modules may not be able to suppress local temperature rises in the semiconductor element.

[0005] In view of the above, the present specification provides a structure of a semiconductor module suitable for a semiconductor element that employs gallium oxide. [Means for solving the problem]

[0006] A semiconductor module (2, 102, 202, 302) disclosed in this specification includes a semiconductor element (10), a first conductive plate (22), and a second conductive plate (26, 126, 226, 326). The semiconductor element (10) includes a gallium oxide substrate (12), a bottom electrode (14) located on the bottom surface of the gallium oxide substrate, and a top electrode (16) located on the top surface of the gallium oxide substrate. The first conductive plate has a first bonding surface (22a) bonded to the bottom electrode of the semiconductor element. The second conductive plate has a second bonding surface (26a) bonded to the top electrode of the semiconductor element.

[0007] The gallium oxide substrate has an active area (12X) through which a current flows between the lower electrode and the upper electrode, and a non-active area (12Y) that is provided along the periphery (12e) of the gallium oxide substrate and surrounds the active area. In a direction perpendicular to the gallium oxide substrate, the entire active area faces the first bonding surface of the first conductor plate and faces the second bonding surface of the second conductor plate. In other words, in a plan view perpendicular to the gallium oxide substrate, the entire active area overlaps the first bonding surface of the first conductor plate and also overlaps the second bonding surface of the second conductor plate.

[0008] In the above-mentioned semiconductor module, the active area of ​​the gallium oxide substrate generates heat when a current flows through the semiconductor element. The entire active area faces the first bonding surface of the first conductor plate and also faces the second bonding surface of the second conductor plate. With this configuration, heat generated in the active area is directly diffused from the gallium oxide substrate to the first conductor plate and the second conductor plate. As a result, even in a gallium oxide substrate with low thermal conductivity, uneven temperature distribution is unlikely to occur, and local temperature rise can be suppressed. [Brief description of the drawings]

[0009] [Figure 1]1 is a cross-sectional view showing a schematic configuration of a semiconductor module 2 of Example 1. In all the drawings, the up-down direction in the drawings coincides with the direction perpendicular to the semiconductor substrate 12. In addition, for clarity of illustration, hatching of the sealing body 20 is omitted. [Diagram 2] FIG. 2 is an enlarged view showing a part II in FIG. [Diagram 3] 10 is an enlarged view showing a main part of a semiconductor module 102 according to a second embodiment, which corresponds to part II of the first embodiment shown in FIG. 2. [Figure 4] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor module 202 according to a third embodiment. [Diagram 5] FIG. 5 is an enlarged view of a portion V in FIG. 4. [Figure 6] 7 is an enlarged view showing a main part of a semiconductor module 302 according to a fourth embodiment, which corresponds to part V of the third embodiment shown in FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In one embodiment of the present technology, the semiconductor element may further include a protective film (18) that is provided along the periphery of the upper electrode and defines an opening (18a) through which the upper electrode is exposed. In this case, the entire active area may face the opening of the protective film in a direction perpendicular to the gallium oxide substrate. In other words, the entire active area may be included within the opening of the protective film in a plan view perpendicular to the gallium oxide substrate. With this configuration, even if the semiconductor element includes the protective film, the thermal diffusion from the active area to the second conductor plate is not hindered by the protective film.

[0011] In the above embodiment, the second bonding surface of the second conductor plate may be a part of the lower surface of the second conductor plate facing the semiconductor element. In this case, another part (126b, 326b) of the lower surface of the second conductor plate may face the protective film in a direction perpendicular to the gallium oxide substrate. That is, the lower surface of the second conductor plate may be larger than the opening of the protective film, and only a part of the lower surface may be bonded to the upper electrode of the semiconductor element as the second bonding surface.

[0012] In one embodiment of the present technology, the second bonding surface of the second conductor plate may be bonded to the upper electrode of the semiconductor element via a solder layer (34). In this case, the entire active area may face the solder layer in a direction perpendicular to the gallium oxide substrate. In other words, the entire active area may overlap the solder layer in a plan view perpendicular to the gallium oxide substrate. However, in another embodiment, the second bonding surface of the second conductor plate is not limited to a solder layer, and may be bonded to the upper electrode of the semiconductor element via another material layer or directly.

[0013] In an embodiment of the present technology, the semiconductor module (2, 102) may further include a third conductor plate (24). In this case, the third conductor plate (24) may face the first conductor plate via the semiconductor element and the second conductor plate, and may be joined to the second conductor plate. With this configuration, by designing the second conductor plate as a spacer, a desired distance can be provided between the first conductor plate and the second conductor plate.

[0014] In the above embodiment, the semiconductor module may further include a sealing body (20) that seals the semiconductor element. In this case, the first conductive plate may be exposed at a lower surface (20a) of the sealing body, the second conductive plate may be located inside the sealing body, and the third conductive plate may be exposed at an upper surface (20b) of the sealing body. With this configuration, heat generated in the semiconductor element can be dissipated from the first conductive plate and the third conductive plate to the outside of the sealing body.

[0015] In one embodiment of the present technology, the second conductor plate (224, 324) may have a plate-shaped portion (225, 325) extending parallel to the first conductor plate, and a protruding portion (226, 326) protruding from the plate-shaped portion toward the semiconductor element and having the second bonding surface. With this configuration, by designing the protruding portion of the second conductor plate as a spacer, a desired gap can be provided between the first conductor plate and the second conductor plate.

[0016] In the above-described embodiment, the protrusion may have a frustum shape. In this case, the frustum shape may be a truncated pyramid shape or a truncated cone shape. With this configuration, the heat generated in the semiconductor element can be diffused widely in a radial manner.

[0017] In the above-described embodiment, the semiconductor module may further include a sealing body (20) that seals the semiconductor element and the first conductive plate. In this case, the first conductive plate may be exposed on a lower surface (20a) of the sealing body, and the plate-shaped portion of the second conductive plate may be exposed on an upper surface (20b) of the sealing body. With this configuration, heat generated in the semiconductor element can be dissipated from the first conductive plate and the third conductive plate to the outside of the sealing body.

[0018] In this specification, the expressions "upper", "lower", "upper surface", and "lower surface" are used for convenience to indicate the positional relationship of opposite directions, and do not limit the posture in use or manufacture of the semiconductor module. For example, the upper surface of a gallium oxide substrate merely refers to one main surface of the gallium oxide substrate, and the lower surface of a semiconductor element merely refers to the other main surface of the gallium oxide substrate located opposite the upper surface. EXAMPLES

[0019] (Example 1) A semiconductor module 2 of Example 1 will be described with reference to the drawings. The semiconductor module 2 of this example is not particularly limited, but can be used in a power conversion device such as a converter or inverter in an electric device such as an electric vehicle. Here, an electric vehicle broadly means a vehicle that runs on a road surface and has a driving motor that drives wheels. Examples of such electric vehicles include hybrid cars, fuel cell cars, rechargeable electric cars, and solar cars.

[0020] As shown in FIG. 1 and FIG. 2, the semiconductor module 2 includes a semiconductor element 10 and a sealing body 20 sealing the semiconductor element 10. The sealing body 20 is made of an insulating material. Although not particularly limited, the insulating material constituting the sealing body 20 may be a thermosetting resin material such as an epoxy resin. The semiconductor element 10 is a power semiconductor element, and may be, for example, a diode element, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) element, or an IGBT (Insulated Gate Bipolar Transistor) element. The semiconductor module 2 may include a plurality of semiconductor elements 10. In this case, the plurality of semiconductor elements 10 may be connected in parallel with each other or in series with each other.

[0021] The semiconductor element 10 has a semiconductor substrate 12, a lower electrode 14, an upper electrode 16, and a protective film 18. The semiconductor substrate 12 is a gallium oxide substrate mainly made of gallium oxide. The lower electrode 14 is provided on the lower surface of the semiconductor substrate 12 and is in ohmic contact with the lower surface of the semiconductor substrate 12. The upper electrode 16 is provided on the upper surface of the semiconductor substrate 12 and is in ohmic contact with the upper surface of the semiconductor substrate 12. Note that a part or the whole of the upper electrode 16 may be in Schottky contact with the semiconductor substrate 12. The same applies to the lower electrode 14. The material constituting the lower electrode 14 and the upper electrode 16 is not particularly limited, and may be a metal such as aluminum (Al) or nickel (Ni). The protective film 18 is made of an insulating material such as polyimide resin. The protective film 18 is provided along the periphery of the upper electrode 16 and defines an opening 18a through which the upper electrode 16 is exposed.

[0022] The semiconductor substrate 12 has an active area 12X and a non-active area 12Y. The active area 12X is provided in the center of the semiconductor substrate 12 in a plan view perpendicular to the semiconductor substrate 12. On the other hand, the non-active area 12Y is provided along the periphery 12e of the semiconductor substrate 12 and surrounds the active area 12X. The active area 12X is provided with an element structure such as a diode, a MOSFET, or an IGBT. The lower electrode 14 and the upper electrode 16 are electrically connected to each other via the element structure in the semiconductor substrate 12. That is, the active area 12X is a region where a current flows between the lower electrode 14 and the upper electrode 16, and is a region in the semiconductor substrate 12 that generates heat due to the passage of electricity.

[0023] The semiconductor module 2 further includes a lower conductor plate 22, an upper conductor plate 24, and a conductor spacer 26. The lower conductor plate 22 is joined to the lower electrode 14 of the semiconductor element 10. More specifically, a part 22a of the upper surface of the lower conductor plate 22 is joined to the lower electrode 14 of the semiconductor element 10 via a solder layer 32. The lower conductor plate 22 is made of a metal such as copper. As a result, the lower conductor plate 22 is electrically connected to the semiconductor element 10 and constitutes a part of the electric circuit in the semiconductor module 2. In addition, the lower conductor plate 22 is exposed to the lower surface 20a of the sealing body 20, and also functions as a heat sink that dissipates heat generated by the semiconductor element 10 to the outside of the sealing body 20.

[0024] The upper conductor plate 24 is joined to the upper electrode 16 of the semiconductor element 10 via the conductive spacer 26. More specifically, the lower surface of the upper conductor plate 24 and the upper surface of the conductive spacer 26 are joined via a solder layer 36. Also, the lower surface 26a of the conductive spacer 26 and the upper electrode 16 of the semiconductor element 10 are joined via a solder layer 34. The upper conductor plate 24 and the conductive spacer 26 are made of a metal such as copper. As a result, the upper conductor plate 24 is electrically connected to the semiconductor element 10 via the conductive spacer 26, and constitutes a part of the electric circuit in the semiconductor module 2. Also, the upper conductor plate 24 is exposed on the upper surface 20b of the sealing body 20, and also functions as a heat sink that releases heat from the semiconductor element 10 to the outside. That is, the semiconductor module 2 of this embodiment has a double-sided cooling structure in which a heat sink is exposed on both sides 20a and 20b of the sealing body 20.

[0025] Here, the lower conductor plate 22 in this embodiment is an example of a first conductor plate in the present technology. A part 22a of the upper surface of the lower conductor plate 22 is an example of a first bonding surface in the present technology, and may be referred to as the first bonding surface 22a below. The conductive spacer 26 in this embodiment is an example of a second conductor plate in the present technology. A lower surface 26a of the conductive spacer 26 is an example of a second bonding surface in the present technology, and may be referred to as the second bonding surface 26a below. The upper conductor plate 24 in this embodiment is an example of a third conductor plate in the present technology.

[0026] In the semiconductor module 2 of this embodiment, the entire active area 12X faces the first bonding surface 22a of the lower conductor plate 22 in a direction perpendicular to the semiconductor substrate 12. Furthermore, the entire active area 12X faces the second bonding surface 26a of the conductor spacer 26. That is, each of the first bonding surface 22a and the second bonding surface 26a is larger than the active area 12X of the semiconductor substrate 12, and the entire active area 12X overlaps with each of the first bonding surface 22a and the second bonding surface 26a in a plan view perpendicular to the semiconductor substrate 12. The size of the active area 12X may be the same as one or both of the first bonding surface 22a and the second bonding surface 26a.

[0027] As described above, when a current flows through the semiconductor element 10, the active area 12X of the semiconductor substrate 12 generates heat. The semiconductor substrate 12 is a gallium oxide substrate, and gallium oxide has a low thermal conductivity compared to other semiconductor materials. Therefore, heat diffusion is difficult to occur inside the semiconductor substrate 12, and uneven temperature distribution is likely to occur. For this reason, if the second bonding surface 26a of the conductor spacer 26 is small relative to the active area 12X and a part of the active area 12X does not face the second bonding surface 26a of the conductor spacer 26, the temperature of the semiconductor substrate 12 may locally increase at that position.

[0028] In contrast, in the semiconductor module 2 of this embodiment, the entire active area 12X faces the first bonding surface 22a of the lower conductor plate 22 and also faces the second bonding surface 26a of the conductor spacer 26. With this configuration, heat generated in the active area 12X is directly diffused from the semiconductor substrate 12 to the lower conductor plate 22 and the conductor spacer 26. As a result, even in a semiconductor substrate 12 with low thermal conductivity, non-uniform temperature distribution is unlikely to occur, and localized temperature rises can be suppressed.

[0029] In the semiconductor module 2 of this embodiment, the upper electrode 16 of the semiconductor element 10 is bonded to the second bonding surface 26a of the conductive spacer 26 through the opening 18a of the protective film 18. The opening 18a of the protective film 18 may be larger than the active area 12X of the semiconductor substrate 12, and the entire active area 12X may face the opening 18a of the protective film 18. In other words, in a plan view perpendicular to the semiconductor substrate 12, the entire active area 12X is contained within the opening 18a of the protective film 18. With this configuration, even if the semiconductor element 10 has the protective film 18, the thermal diffusion from the active area 12X to the conductive spacer 26 is not hindered by the protective film 18.

[0030] In the semiconductor module 2 of this embodiment, as described above, the second bonding surface 26a of the conductive spacer 26 is bonded to the upper electrode 16 of the semiconductor element 10 via the solder layer 34. However, in another embodiment, the second bonding surface 26a of the conductive spacer 26 is not limited to the solder layer 34, and may be bonded to the upper electrode 16 of the semiconductor element 10 via another material layer or directly. The solder layer 34 is larger than the active area 12X of the semiconductor substrate 12, and the entire active area 12X faces the solder layer 34. As a result, heat generated in the active area 12X is directly diffused to the conductive spacer 26 via the solder layer 34.

[0031] (Example 2) A semiconductor module 102 of Example 2 will be described with reference to Fig. 3. In the semiconductor module 102 of this example, the size of the conductor spacer 126 is changed compared to the semiconductor module 2 of Example 1. In the following, differences from Example 1 will be mainly described, and the same reference numerals will be used to omit redundant description of configurations common to Example 1. The conductor spacer 126 in this example is an example of a second conductor plate in the present technology.

[0032] In this embodiment, the lower surface of the conductive spacer 126 is also bonded to the upper electrode 16 of the semiconductor element 10. However, the lower surface of the conductive spacer 126 is larger than the opening 18a of the protective film 18, and only a part of the lower surface serves as a second bonding surface 126a bonded to the upper electrode 16. Therefore, the other part 126b of the lower surface of the conductive spacer 126 located on the periphery faces the protective film 18 in the direction perpendicular to the semiconductor substrate 12. In this way, by enlarging the size of the conductive spacer 126, the heat capacity of the conductive spacer 126 can be increased, and thus the temperature rise of the semiconductor element 10 can be further suppressed.

[0033] (Example 3) A semiconductor module 202 of Example 3 will be described with reference to Figs. 4 and 5. In the semiconductor module 202 of this example, the shape of the upper conductor plate 224 is changed compared to the semiconductor module 2 of Example 1. In the following, differences from Example 1 will be mainly described, and the same reference numerals will be used to omit redundant description of configurations common to Example 1. The upper conductor plate 224 in this example is an example of a second conductor plate in the present technology.

[0034] As shown in FIG. 4 and FIG. 5, in the semiconductor module 202 of this embodiment, the shape of the upper conductor plate 224 is changed and the conductive spacer 26 is omitted. The upper conductor plate 224 in this embodiment has a plate-shaped portion 225 extending parallel to the lower conductor plate 22 and a protruding portion 226 protruding from the plate-shaped portion 225 toward the semiconductor element 10. The plate-shaped portion 225 is exposed on the upper surface 20b of the sealing body 20, and the protruding portion 226 is joined to the upper electrode 16 of the semiconductor element 10. That is, in the semiconductor module 202 of this embodiment, the surface located at the lower end of the protruding portion 226 is a second joint surface 226a joined to the upper electrode 16. In this way, the upper conductor plate 224 in this embodiment has a shape that is generally integrated with the upper conductor plate 24 and the conductive spacer 26 in the first embodiment.

[0035] Although not particularly limited, the protruding portion 226 has a frustum shape, and the cross-sectional area increases toward the plate-shaped portion 225. With such a configuration, the heat generated in the semiconductor element 10 can be diffused widely in a radial manner. In this case, the shape of the protruding portion 226 may be a frustum pyramid shape or a frustum cone shape. In addition, the specific shape of the protruding portion 226 is not limited to a frustum shape and is not particularly limited.

[0036] (Example 4) A semiconductor module 302 of Example 4 will be described with reference to Fig. 6. In the semiconductor module 302 of this example, the shape of the upper conductor plate 324 is changed compared to the semiconductor module 202 of Example 3. In the following, differences from Example 3 will be mainly described, and the same reference numerals will be used to denote configurations common to Example 3, and redundant description will be omitted. The upper conductor plate 324 in this example is an example of a second conductor plate in the present technology.

[0037] In this embodiment, the upper conductive plate 324 also has a plate-shaped portion 325 extending parallel to the lower conductive plate 22 and a protruding portion 326 protruding from the plate-shaped portion 325 toward the semiconductor element 10. The plate-shaped portion 325 is exposed to the upper surface 20b of the sealing body 20, and the protruding portion 326 is bonded to the upper electrode 16 of the semiconductor element 10. However, the lower end surface of the protruding portion 326 is larger than the opening 18a of the protective film 18, and only a part of the lower end surface is a second bonding surface 326a bonded to the upper electrode 16. Therefore, the other part 326b of the lower end surface of the protruding portion 326 located on the periphery faces the protective film 18 in a direction perpendicular to the semiconductor substrate 12. In this way, by enlarging the size of the protruding portion 326, the heat capacity of the protruding portion 326 can be increased, and the temperature rise of the semiconductor element 10 can be further suppressed.

[0038] Specific examples of the technology disclosed in this specification have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology exemplified in this specification or the drawings can achieve multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0039] 2, 102, 202, 302: semiconductor module; 10: semiconductor element; 12: semiconductor substrate; 14: lower electrode; 16: upper electrode; 18: protective film; 20: sealing body; 22: lower conductor plate; 22a: first bonding surface; 24, 224, 324: upper conductor plate; 26, 126: conductor spacer; 26a, 126a, 226a, 326a: second bonding surface; 32, 34, 36: solder layer

Claims

1. A semiconductor element (10) having a gallium oxide substrate (12), a lower electrode (14) located on the lower surface of the gallium oxide substrate, and an upper electrode (16) located on the upper surface of the gallium oxide substrate; a first conductive plate (22) having a first bonding surface (22a) bonded to the lower electrode of the semiconductor element; a second conductive plate (324) having a second bonding surface (326a) bonded to the upper electrode of the semiconductor element; Equipped with The gallium oxide substrate has an active area (12X) in which a current flows between the lower electrode and the upper electrode, and a non-active area (12Y) provided along the periphery (12e) of the gallium oxide substrate and surrounding the active area; In a direction perpendicular to the gallium oxide substrate, the entire active area faces the first bonding surface of the first conductor plate and faces the second bonding surface of the second conductor plate; The semiconductor element further includes a protective film (18) provided along a periphery of the upper electrode and defining an opening (18a) through which the upper electrode is exposed; the entire active area faces the opening in the protective film in a direction perpendicular to the gallium oxide substrate; The second conductive plate is A plate-like portion (325) extending parallel to the first conductive plate; A protrusion (326) protruding from the plate-like portion toward the semiconductor element and having a frustum shape; having The second bonding surface of the second conductor plate is a part of a flat lower end surface (326a+326b) of the protruding portion facing the semiconductor element, In a direction perpendicular to the gallium oxide substrate, another part (326b) of the flat lower end surface of the protrusion faces the protective film; A semiconductor module (302).

2. the second bonding surface of the second conductor plate is bonded to the upper electrode of the semiconductor element via a solder layer (34); The semiconductor module according to claim 1 , wherein the entire active area faces the solder layer in a direction perpendicular to the gallium oxide substrate.

3. The semiconductor device further includes a sealing body (20) that seals the semiconductor element and the first conductive plate, The first conductive plate is exposed on a lower surface (20a) of the sealing body, The semiconductor module according to claim 1 , wherein the plate-like portion of the second conductor plate is exposed on an upper surface of the sealing body.

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