Printed wiring board and method for manufacturing printed wiring board

Abstract

A printed wiring board of the present disclosure is provided with a multilayer substrate including: a core substrate having a first surface and a second surface; a first build-up layer positioned on the first surface of the core substrate; and a second build-up layer positioned on the second surface of the core substrate. The multilayer substrate includes a cavity, a first conductor layer, and a second conductor layer. The cavity penetrates through the first build-up layer and the core substrate, and has a bottom surface which is a surface of the second build-up layer. The first conductor layer is positioned at the bottom surface of the cavity. The second conductor layer is positioned in the second build-up layer, and is positioned to overlap at least a part of a peripheral portion of the bottom surface of the cavity in a plan perspective.

Description

[Technical field]

[0001] The present disclosure relates to printed wiring boards having cavities and methods for making printed wiring boards. [Background technology]

[0002] In recent years, with the trend toward higher integration and higher density of substrates and wiring, there are cases where a large-volume cavity is provided in a multi-layer substrate and electronic components are mounted therein. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-122728 A Summary of the Invention

[0004] The printed wiring board of the present disclosure has a multilayer substrate. The multilayer substrate has a core substrate having a first surface and a second surface, a first buildup layer located on the first surface of the core substrate, and a second buildup layer located on the second surface of the core substrate. The multilayer substrate also has a cavity, a first conductor layer, and a second conductor layer. The cavity penetrates the first buildup layer and the core substrate, and the bottom surface is the surface of the second buildup layer, the first conductor layer is located on the bottom surface of the cavity, and the second conductor layer is located within the second buildup layer and overlaps at least a portion of the periphery of the bottom surface of the cavity in a planar perspective view.

[0005] The method for manufacturing a printed wiring board of the present disclosure includes a first step of preparing a core substrate having a first surface and a second surface, the second surface being provided with a seed layer; a second step of performing pattern plating on the seed layer provided on the core substrate to form a first conductor layer; a third step of removing a portion of the seed layer from a surface of the seed layer including the first conductor layer of the core substrate such that the seed layer remains in a central portion of the core substrate in which a cavity is to be formed; and a third step of forming a first buildup layer having a first insulating resin layer on the first surface of the core substrate. a fourth step of forming a second buildup layer having a second insulating resin layer on the second surface of the core substrate; a fifth step of pattern plating the surface of the second buildup layer to form a second conductor layer at a position overlapping at least a portion of the periphery of the bottom surface of the cavity formed in a plan view; and a sixth step of processing the core substrate from the side of the first buildup layer to penetrate the first buildup layer and the core substrate and form the cavity whose bottom surface is the surface of the second buildup layer. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view illustrating a configuration of a printed wiring board according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Diagram 3] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 4] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Diagram 5] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 6] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 7] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 8] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 9]4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 10] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 11] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 12] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 13] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 14] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 15] 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 16] 1 is a cross-sectional view illustrating an effect of a printed wiring board according to an embodiment. [Figure 17] 1 is a cross-sectional view illustrating an effect of a printed wiring board according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. Fig. 1 is a diagram showing a configuration of a printed wiring board according to one disclosed embodiment. The printed wiring board shown in Fig. 1 is an example.

[0008] The printed wiring board shown as an embodiment has a multilayer substrate 54 as shown below. The multilayer substrate 54 has a core substrate 51, a first buildup layer 61, and a second buildup layer 62. The core substrate 51 has a first surface 51a and a second surface 51b. The first buildup layer 61 and the second buildup layer 62 are laminated on the core substrate 51. The first buildup layer 61 has an insulating resin layer 61a and an insulating resin layer 61b. The second buildup layer 62 has an insulating resin layer 62a and an insulating resin layer 62b.

[0009] The first buildup layer 61 is disposed so as to face the first surface 51a of the core substrate 51. The second buildup layer 62 is disposed so as to face the second surface 51b of the core substrate 51. The multilayer substrate 54 also has a cavity 20, a first conductor layer 17, and a second conductor layer 12a.

[0010] The cavity 20 is open in the multilayer substrate 54 from the first buildup layer 61 side to the core substrate 51. The cavity 20 is provided such that the surface 62aa of the second buildup layer 62 becomes the bottom surface 79.

[0011] The first conductor layer 17 is disposed so as to be exposed at the bottom surface 79 of the cavity 20. The second conductor layer 12a is provided on a surface 62ab opposite to the core substrate 51 of the insulating resin layer 62a.

[0012] The second conductor layer 12a is located within the second buildup layer 62. Also, when the multilayer substrate 54 is seen through in a plan view, the second conductor layer 12a is located so as to overlap at least a portion of the peripheral portion 79t of the bottom surface 79 of the cavity 20. In other words, when the multilayer substrate 54 is seen through in a plan view, the second conductor layer 12a is provided at a position corresponding to the peripheral portion 79t of the bottom surface 79 of the cavity 20. With this configuration, even if a cavity 20 with a large volume is provided in the printed wiring board, the printed wiring board can be made less likely to bend.

[0013] When a cavity 20 having a large volume and a thin bottom side is formed in the multilayer substrate 54, it is prone to bending at the bottom side 79. The mechanical strength can be increased by inserting a metal member into the peripheral portion 79t of the bottom side 79 of the cavity 20, which is prone to bending. This is due to the high elastic modulus of the metal member. In this case, the second conductor layer 12a is located in a lower layer, separated from the first conductor layer 17 and seed layer 12 exposed at the bottom side 79 of the cavity 20 by a distance equivalent to the thickness of the insulating resin layer 62a.

[0014] When multilayer substrate 54 is viewed in plan, first conductor layer 17 is located at the center of bottom surface 79 of cavity 20, and second conductor layer 12a is located at peripheral portion 79t of bottom surface 79 of cavity 20. In addition, first conductor layer 17 and second conductor layer 12a are arranged so as to be separated by about one insulating resin layer in the thickness (stacking) direction of multilayer substrate 54.

[0015] This makes it possible to make the multilayer substrate 54 less likely to bend even when the volume of the cavity 20 is large and the insulating resin layers (62a, 62b) below the cavity 20 are thin. If the second conductor layer 12a were arranged so as to be exposed on the bottom surface 79 of the cavity 20, there is a concern that the multilayer substrate 54 would be more likely to bend and that it would be difficult to ensure electrical insulation between the second conductor layer 12a and the first conductor layer 17 originally arranged in the cavity 20.

[0016] The multilayer substrate 54 will be described in detail below. As shown in Fig. 1, the printed wiring board of this embodiment has a multilayer substrate 54. The multilayer substrate 54 has a core substrate 51, a first buildup layer 61, and a second buildup layer 62.

[0017] Core substrate 51 is, for example, a substrate having seed layers 12 on both sides of base material 11. Base material 11 is a so-called sheet-shaped molded body made of insulating resin. On one surface (upper surface) of core substrate 51, a conductor layer 16 forming an electric circuit is formed.

[0018] A conductor layer 17 forming an electric circuit is formed on the other surface (lower surface) of core substrate 51. Core substrate 51 has conductor layer 16 and via 15 connecting conductor layer 17 to each other.

[0019] That is, the multilayer substrate 54 has a conductor layer 16, a conductor layer 17, and a via 15. The via 15 penetrates the insulating resin layer 11 in the thickness direction. The via 15 is disposed between the conductor layer 16 and the conductor layer 17. The conductor layer 16 is disposed so as to partially overlap the seed layer 12 formed on one surface (upper surface) of the base material 11. The conductor layer 17 is disposed so as to partially overlap the seed layer 12 formed on the other surface (lower surface) of the base material 11.

[0020] The first buildup layer 61 is disposed on the upper surface of the core substrate 51, and has an insulating resin layer 61a and a conductor layer, which will be described below. In the example shown in Fig. 1, the first buildup layer 61 has an insulating resin layer 61a, one surface (lower surface) of which contacts the core substrate 51, and an insulating resin layer 61b, one surface (lower surface) of which contacts the other surface (upper surface) of the insulating resin layer 61a.

[0021] A conductive layer forming an electric circuit is formed on the upper surface of the insulating resin layer 61a. The insulating resin layer 61a has a via 15 that connects the conductor layer formed on the upper surface thereof to the conductor layer 16 formed on the upper surface of the core substrate 51. The via 15 is formed so as to penetrate the insulating resin layer 61a in the thickness direction.

[0022] A conductor layer 63 is formed on the other surface (top surface) of the insulating resin layer 61b. The insulating resin layer 61b has a via 15 that connects the conductor layer 63 formed on its top surface to the conductor layer formed on the top surface of the insulating resin layer 61a. The via 15 is formed so as to penetrate the insulating resin layer 61b in the thickness direction.

[0023] That is, the vias 15 are provided in each of the two first buildup layers 61 arranged on the upper surface side of the core substrate 15.

[0024] The second buildup layer 62 is disposed on the other surface (lower surface) of the core substrate 51, and has an insulating resin layer 62a and a conductor layer, which will be described below. In the example shown in FIG. 1, the second buildup layer 62 has an insulating resin layer 62a, one surface (upper surface) of which is in contact with the core substrate 51, and an insulating resin layer 62b, one surface (upper surface) of which is in contact with the other surface (lower surface) of the insulating resin layer 62a. Hereinafter, the insulating resin layer 62a may be referred to as a first insulating resin layer 62a. Similarly, the insulating resin layer 62b may be referred to as a second insulating resin layer 62b.

[0025] A first conductor layer 17 forming an electric circuit is formed on the upper surface of the insulating resin layer 62a. A conductive layer forming an electric circuit is formed on the other surface (lower surface) of the insulating resin layer 62a. The insulating resin layer 62a has a via 15 that connects the first conductor layer 17 formed on the upper surface with the conductive layer formed on the lower surface. The via 15 is formed so as to penetrate the insulating resin layer 62a in the thickness direction. The via 15 is also formed in the insulating resin layer 62a so as to overlap the first conductor layer 17 in the direction parallel to the surface.

[0026] A conductor layer 64 is formed on the other surface (lower surface) of the insulating resin layer 62b. The insulating resin layer 62b has a via 15 that connects the conductor layer 64 formed on the lower surface and the conductive layer formed on the lower surface of the insulating resin layer 62a. That is, the insulating resin layer 62b located at the bottommost layer of the multilayer substrate 54 has the via 15. The via 15 is formed so as to penetrate the insulating resin layer 62b in the thickness direction.

[0027] 1, the via 15 provided in the insulating resin layer 62a and the via 15 provided in the insulating resin layer 62b are in an overlapping state. In the example shown in Fig. 1, the via 15 formed in the second buildup layer 62 is formed within the cavity forming region 65 and directly below the cavity 20. The insulating resin layer 62a and the insulating resin layer 62b are in an overlapping state.

[0028] To repeat, multilayer substrate 54 has cavity 20. Cavity 20 penetrates first buildup layer 61 and core substrate 51 from the conductor layer 63 side of multilayer substrate 54. That is, cavity 20 forms a space whose bottom surface is the upper surface of second buildup layer 62. Cavity 20 opens so as to occupy a partial region (cavity forming region 65) of the surface of multilayer substrate 54 on which conductor layer 63 is formed.

[0029] The cavity 20 has a concave cross section. In the cavity 20, the surface (bottom surface 79) of the insulating resin in a partial region of the second buildup layer 62 and the first conductor layer 17 formed on the upper surface of the second buildup layer 62 are exposed as bottom surfaces (in a flat state) of equal height. That is, the first conductor layer 17 in the cavity 20 is disposed so as to be exposed on the surface of the insulating resin layer 62a which is the bottom surface of the cavity 20.

[0030] Also, the first conductor layer 17 in the cavity 20 is partially embedded in the insulating resin layer 62a. At the bottom of the cavity 20, it is preferable that a surface 79 (bottom surface 79) on the insulating resin layer 62a and the first conductor layer 17 are disposed so as to be substantially flush with each other. The word "substantially" is used because the first conductor layer 17 is exposed by etching, and therefore some unevenness (steps) (2 μm to 3 μm) may occur. A part of the first conductor layer 17 formed at the bottom of the cavity 20 functions as a connection pad for connecting to an electronic component.

[0031] The multilayer substrate 54 has, around the cavity 20, in addition to the above-mentioned conductor layer 16, first conductor layer 17, and via 15, a seed layer 12a (hereinafter referred to as the second conductor layer 12a).

[0032] The second buildup layer 62 has a second conductor layer 12a at a position corresponding to the cavity forming region 65 at approximately the center in the thickness direction. The second conductor layer 12a is formed at a position corresponding to at least the side wall surface in the depth direction of the cavity 20. That is, the second conductor layer 12a is located at a portion where the side wall surface (20a in FIG. 1) of the cavity 20 is extended toward the first insulating resin layer 62a and the second insulating resin layer 62b. The position of the second conductor layer 12a when viewed in the thickness direction of the multilayer substrate 54 is a position where the side wall surface 20a of the cavity 20 is lowered toward the first insulating resin layer 62a in the second buildup layer 62 arranged on the lower layer side of the core substrate 51.

[0033] The position of the second conductor layer 12a in the planar direction on the multilayer substrate 54 is a central position directly below the wall surface 20a of the cavity 20. The position of the wall surface 20a of the cavity 20 and the position hanging down from the position of the wall surface 20a of the cavity 20 toward the first insulating resin layer 62a can also be referred to as the contour part of the cavity 20. The second conductor layer 12a is preferably disposed directly below the contour part of the cavity 20.

[0034] The second conductor layer 12a may be formed between the insulating resin layer 62a and the insulating resin layer 62b (on the bonding surface). The second conductor layer 12a may be in a state where it is not connected to other conductor layers and conductive layers. In other words, the second conductor layer 12a may be electrically isolated from other conductor layers and conductive layers.

[0035] The conductor layers 63 and 64 are connected to each other via through holes 10 penetrating the first buildup layer 61, the core substrate 51, and the second buildup layer 62 in an area other than the cavity forming area 65. Note that conductor layers 73 and 74 (see FIG. 14) and solder resists 71 and 72 (see FIG. 13) may be formed above and below the through holes 10 in a later process as necessary. The solder resists 71 and 72 are formed on the surfaces of the uppermost layer and / or the lowermost layer of the multilayer substrate 54. The conductor layers 73 and 74 are surrounded by an insulating coating of the solder resists 71 and 72 and function as connection pads.

[0036] Although conductor layer 16 and conductor layer 17 are electrically the same, the conductor layer formed integrally with via 15 is referred to as conductor layer 16, and the conductor layer laminated on seed layer 12 described later is referred to as first conductor layer 17.

[0037] In this way, the printed wiring board of the embodiment is provided with a cavity forming region 65 of a multilayer substrate 54 in which a first buildup layer 61 is laminated on the upper surface (first surface) of a core substrate 51 as a substrate having an insulating resin layer 11 and a second buildup layer 62 is laminated on the lower surface (second surface) of the core substrate 51, and is provided with a cavity 20 formed by countersinking from above the first buildup layer 61 to penetrate through the core substrate 51 with a surface 79 of the insulating resin layer 62a of the second buildup layer 62 as a bottom surface, and a conductor layer 17 having a surface at the same height as the surface 79 of the insulating resin layer 62a of the second buildup layer 62 and embedded in the insulating resin layer 62a of the second buildup layer 62 so that the surface forms part of the bottom surface of the cavity 20.

[0038] In the example shown in Figure 1, a seed layer 12 has been formed in advance on the underside of core substrate 51 in an area including cavity formation region 65, and the insulating resin layer 11 of core substrate 51 has been removed by the recess processing performed during cavity formation, leaving only conductor layer 17.

[0039] The printed wiring board of the embodiment has a second conductor layer 12a in a second buildup layer 62 arranged on the lower layer side of the cavity 20. In this printed wiring board (multilayer substrate 54), the cavity 20 is formed so as to penetrate from the first buildup layer 61 to the core substrate 51 and reach a range exceeding 1 / 2 of the thickness of the multilayer substrate 54, particularly a range exceeding 3 / 5. The cavity 20 is formed to a deep position in the thickness direction of the multilayer substrate 54. Since the cavity 20 is formed to a deep position in the thickness direction of the multilayer substrate 54, the multilayer substrate 54 is easily bent around the cavity 20. In other words, it is easily bent compared to a printed wiring board in which the cavity 20 is formed to a position equal to or less than 1 / 2 of the thickness direction of the multilayer substrate 54.

[0040] In the printed wiring board of the embodiment, even the portion of core substrate 51 located at the center in the thickness direction of multilayer substrate 54 is removed. That is, the member of core substrate 51, which normally has glass cloth, is not present where cavity 20 is formed. Since core substrate 51 is partially removed in this manner, there is a risk that the mechanical strength of this printed wiring board will be weakened.

[0041] When this printed wiring board is used as, for example, a connector portion for electrical connection, a socket or the like is inserted into the cavity 20. Normally, when a connector is inserted into the cavity 20, the printed wiring board is prone to deformation.

[0042] However, in the printed wiring board of the embodiment, the second conductor layer 12a is provided below the wall surface 20a of the cavity 20, so that the printed wiring board is less likely to bend even at the position where the cavity 20 exists. In this printed wiring board, even if the cavity 20 penetrating the core substrate 51 is formed, it is possible to increase the mechanical strength of the second buildup layer 62 located on the bottom side of the cavity 20.

[0043] In this case, the second conductor layer 12a may be formed so as to spread out from the contour portion of the cavity 20. The second conductor layer 12a is preferably disposed so as to straddle the cavity 20 side and the outside of the cavity 20 with the hanging position of the wall surface 20a of the cavity 20 as the center.

[0044] The second conductor layer 12a may have a strip shape. Here, strip shape refers to a long shape with a predetermined width. In the case of the second conductor layer 12a, the predetermined width refers to a region that spreads in both directions from the center when the position of the wall surface 20a of the cavity 20 is the center. The spread region is a range in which an insulating portion is provided between the other adjacent conductors (the conductor layer including the via 15 in FIG. 1). A specific predetermined width can be set to be 5 μm or more and 500 μm or less.

[0045] 2, the second conductor layer 12a may be arranged to go around the vicinity of the position where the bottom surface 79 and the wall surface 20a of the cavity 20 provided in the multilayer substrate 54 intersect. FIG. 2 is a diagram showing a plan view of the interface between the insulating resin layer 62a and the insulating resin layer 62b, and shows a state in which the second conductor layer 12a is arranged in a band shape to go around the peripheral portion 79t of the cavity 20. In other words, when the second conductor layer 12a is arranged in the second buildup layer 62 in a ring shape, the multilayer substrate 54 can be made even more difficult to bend.

[0046] Cavity 20 is a cross-sectional concave portion formed by countersinking a partial region of a predetermined layer of multilayer substrate 54 (cavity forming region 65 (see FIG. 7) including the range of seed layer 12 formed on core substrate 51 and the shielded conductor prohibited area at the boundary between the cavity portion where seed layer 12 is not formed and the non-cavity portion) by drilling and / or laser processing to a predetermined depth (a position near seed layer 12 obtained by removing the center of thickness or above inside core substrate 51), removing the remaining portion by laser processing to expose seed layer 12, and then removing seed layer 12 by flash etching. "Center of thickness or above" refers to a depth that is half or more of the thickness of core substrate 51 and does not reach seed layer 12.

[0047] That is, the cavity 20 has a cavity bottom (bottom surface) in which the seed layer 12 formed on the lower surface of the core substrate 51 is exposed by countersinking the cavity forming region 65 with an area capable of accommodating electronic components, and then the exposed seed layer 12 is removed by flash etching to expose the insulating resin layer 62a and the conductor layer 17 thereunder in a substantially flat manner. In addition, in the above-mentioned cavity forming region 65, directly below the boundary between the cavity portion and the non-cavity portion where the seed layer 12 is not formed, a second conductor layer 12a is formed in a layer lower than the bottom surface of the cavity 20 (between the insulating resin layer 62a and the insulating resin layer 62b). This second conductor layer 12a spreads from directly below the bottom surface of the cavity 20 to the periphery. In addition, in this embodiment, the second conductor layer 12a spreads in a strip shape around and inwardly of the cavity contour portion of the bottom surface of the cavity 20. The second conductor layer 12a is made of, for example, copper having a thickness of 12 μm or more, and is made up of a dummy pattern or a ground layer, a power supply layer, or the like.

[0048] The electronic component accommodated in cavity 20 is, for example, a bare chip (an unpackaged IC without terminals) and has an electrode on its bottom for connection to multilayer substrate 54. The electrode on the bottom of the electronic component may be connected to the surface of conductor layer 17 exposed flatly on the bottom of the cavity as a component mounting land, or may be connected via metal plating layer 80 (see FIG. 14) formed by plating conductor layer 17. In this case, metal plating layer 80 is formed by stacking plating layers such as nickel plating, gold plating, etc.

[0049] The conductor layers 63, 64 are formed on the surface of the multilayer substrate 54 (the core substrate 51 and the first and second buildup layers 61, 62 above and below it) and are formed as part of the circuit wiring (conductor layer 63a) by later etching. The conductor layers 63, 64 are copper solid patterns, and are formed, for example, by copper plating (thickness: about 15 μm) on copper foil (thickness: about 9 μm).

[0050] Vias 15 are connected to the ends (direction along the surface) of conductor layers 63 and 64. Vias 15 provide interlayer connection between conductors (conductor layers 16, 17, 63, 64, etc.) provided on any layer of multilayer substrate .

[0051] Core substrate 51 is formed by processing insulating resin layer 11 (see FIG. 3-7) having seed layers 12 formed on the top and bottom surfaces thereof, and forming vias 15 therein.

[0052] Examples of the insulating resin forming the insulating resin layer 11 include epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether (PPE) resin, phenol resin, polytetrafluoroethylene (PTFE) resin, silicon resin, polybutadiene resin, polyester resin, melamine resin, urea resin, polyphenylene sulfide (PPS) resin, polyphenylene oxide (PPO) resin, etc. Two or more of these resins may be mixed.

[0053] The vias 15 are formed by filling the via hole pilot holes 14 (see FIG. 4) with metal plating by a plating process. The vias 15 connect the conductors (conductor layers 63, 64, 16, 17, etc.) provided on each layer (including the inner layer and the outer layer) of the multilayer substrate 54 (see FIG. 8). In FIG. 8, it can be seen that the conductor layer 63 on the upper surface is connected to the conductor layer 17 through the via 15, and the conductor layer 64 on the lower surface is connected to the conductor layer 17 through the via 15.

[0054] The seed layer 12 is, for example, copper having a thickness of 1 μm to 10 μm (1 μm or more and 10 μm or less), and is disposed with a part of it remaining under the conductor layer 17. There are no particular limitations on the seed layer 12 as long as it is electrically connected and can shield the laser, but for example, a thin copper foil or electroless copper plating is used. A thin copper foil with a dense metal composition is more suitable.

[0055] Core substrate 51 is formed by forming the upper and lower surfaces of insulating resin layer 11 by a method such as modified semi-additive process (M-SAP) or semi-additive process (SAP), and exposing connection pads provided in a partial area of ​​seed layer 12 and conductor layer 17 (the central part of the lower surface of core substrate 51 in Figure 5) that will become circuit wiring while protecting them from flash etching with an etching resist.

[0056] The printed wiring board of the present disclosure can basically be obtained through the above-mentioned steps 1 to 6. Hereinafter, the method for producing the printed wiring board of the embodiment will be described with reference to Figs.

[0057] 3, the core substrate base 11A is formed by laminating a seed layer 12 (e.g., a conductive metal foil such as a thin copper foil) on the upper surface (first surface 11a) and the lower surface (second surface 11b) of a base 11 made of insulating resin. In this case, the thickness of the seed layer 12 is preferably, for example, about 1 μm to 10 μm. Alternatively, the core substrate base 11A may have the seed layer 12 on at least the lower surface of the base 11.

[0058] Subsequently, as shown in FIG. 4, the core board base material 11A is subjected to laser processing to form pilot holes 14 for via holes.

[0059] When the via hole pilot hole 14 is formed by laser processing, a thin resin film may remain at the bottom of the via hole pilot hole 14. In this case, a desmear process is performed. In the desmear process, the resin is swelled with a strong alkali, and then the resin is decomposed and removed using an oxidizing agent (e.g., chromic acid, a permanganate aqueous solution, etc.).

[0060] In addition, the resin film may be removed by, for example, wet blasting with an abrasive or plasma treatment. Furthermore, the inner wall surface of the via hole pilot hole 14 may be roughened for plating. Examples of the roughening treatment include a wet process using an oxidizing agent (e.g., chromic acid, a permanganate aqueous solution, etc.) and a dry process such as plasma treatment or ashing treatment.

[0061] (Pattern plating process) 5, this process is a process in which pattern plating is performed on partial regions of seed layer 12 provided on the upper and lower surfaces of insulating resin base material 11 and on via hole pilot holes 14 to form conductor layer 16, first conductor layer 17, and vias 15. Specifically, dry film 13 (plating resist) is attached onto seed layer 12 by lamination, and then exposed to light and developed to remove dry film 13 from areas where circuit parts such as conductor layer 16 and vias 15 on the upper surface and first conductor layer 17, which is a conductive circuit on the lower surface, are to be formed.

[0062] Next, a pattern plating process is performed on the via hole pilot holes 14 for forming a circuit portion of the insulating resin substrate 11 from which a portion of the dry film 13 has been removed, and on the seed layer 12 surrounding the via hole pilot holes 14, to form a conductor layer 16 on the upper surface of the insulating resin substrate 11, a via 15 inside the substrate 11, and a conductive layer (including the seed layer 12 and the first conductor layer 17) on the lower surface of the substrate 11.

[0063] Here, the pattern plating may be performed by copper plating alone or by combining copper plating with nickel plating. The reason for using a combination of copper plating and nickel plating is that there is a concern that the pattern plating portions other than the seed layer 12 may be slightly etched when the seed layer 12 is removed in a later process. The nickel plating functions as a barrier against the removal of the seed layer 12. The nickel plating and copper plating are performed continuously. In this case, the thickness of the nickel plating is preferably 2 μm or more.

[0064] This nickel plating process is sometimes called "barrier plating." If the plating film formed in this process also serves as a plating film for surface treatment of component mounting, continuous plating of nickel, gold, nickel, and copper may be performed. In this case, the thickness of the nickel plating should be 2 μm or more for the first coat and 3 μm or more for the second coat, and the gold plating should be 0.3 μm or more for wire bonding, depending on the component mounting method.

[0065] The correction of the circuit width is no different from that of the normal M-SAP or semi-additive methods, even though this technology is used; it is sufficient to correct the width to about 6 μm wider than the design value before exposure.

[0066] (Dry film peeling process) Next, after pattern plating, the remaining dry film 13 is peeled off to expose the seed layer 12.

[0067] (Processing process for cavity forming area) Next, as shown in FIG. 6, a dry film 18 (photosensitive etching resist) is attached by lamination to the seed layer 12 and the first conductor layer 17 on the lower surface (second surface 11b) of the substrate 11. After this, exposure and development are performed, and the dry film 18 is left in the cavity forming region 65 (excluding the no-shielding-conductor area at the boundary between the cavity portion and the non-cavity portion) and removed from other portions. Parts of the exposed seed layer 12 that are not covered by the dry film 18 and are not required as conductive circuits are removed by flash etching. After this, the dry film 18 is removed from the surfaces of the seed layer 12 and the first conductor layer 17.

[0068] That is, in this step, the dry film 18 is attached to the cavity formation region 65 within the area where the seed layer 12 is formed on the surface (second surface 11b in this case) of the substrate 11, and then the seed layer 12 outside the dry film 18 is removed by flash etching. After that, the dry film 18 on the seed layer 12 is peeled off. In this case, the seed layer 12 formed on the upper surface (first surface 11a) of the substrate 11 is also removed.

[0069] In this manner, a core substrate 51 as shown in Fig. 7 is completed. A conductor layer 16 is formed on the upper surface (first surface 11a) of the base material 11 of this core substrate 51 as part of a circuit electrically connected to the via 15. In addition, the seed layer 12 remains in a cavity forming region 65 (excluding a no-shielding-conductor area at the boundary between the cavity portion and the non-cavity portion) on the lower surface (second surface 11b) of the core substrate 51. The portion of the seed layer 12 within the cavity forming region 65 serves as a laser receiver (shielding member) during laser processing, which will be described later.

[0070] In addition, a first conductor layer 17 serving as a conductive circuit is formed on the lower surface of the base material 11. In this example, the circuit is formed using M-SAP as an example, but the circuit (in this case, the first conductor layer 17) can also be formed using SAP that uses electroless copper plating as a seed layer.

[0071] (Build-up layer formation process) In this step, build-up is performed an arbitrary number of times on at least the lower layer (lower surface) of the upper layer (upper surface) and lower layer (lower surface) of the core substrate base material 11A that will become the core substrate 51, to produce the laminated substrate 54A. That is, in this step, the first build-up layer 61 and the second build-up layer 62 are formed on the core substrate base material 11A that will become the core substrate 51, with the seed layer 12 partially remaining in the cavity formation region 65. This forms the laminated substrate 54A in which part of the seed layer 12 is embedded between the internal core substrate 51 (insulating resin substrate) and the second build-up layer 62 (lower structure).

[0072] Here, a conventional method may be used as the build-up process for forming the first build-up layer 61 and the second build-up layer 62. For example, a method may be used in which an insulating resin layer 61a is first attached to a core board base material 11A that will become the core board 51, and then via holes are formed using a laser. Thereafter, a plating process is performed on the surface of the insulating resin layer 61a including the via holes, to form the vias 15 and the conductor layer 17. When the first build-up layer 61 is to be multi-layered as shown in FIG. 7, the same process is repeated.

[0073] To form the circuits in the first buildup layer 61 and the second buildup layer 62, not only a subtractive method in which conductors unnecessary for the circuits are removed by etching, but also M-SAP, SAP, etc. can be applied as in the case of the core substrate 51. To laminate the first and second buildup layers 61, 62, techniques such as multi-stage pressing or resin lamination are used.

[0074] In this example, an insulating resin layer 61a, an insulating resin layer 61b, and a conductor layer 17 (first conductor layer 17) are formed in the upper first buildup layer 61. A conductor layer 63 connected to the via 15 is formed on the top surface of the first buildup layer 61, which is the uppermost layer (surface layer). When forming the conductor layer 63 on the top surface of the top layer (insulating resin layer 61b) of the multilayer substrate 54, the range of a cavity formation region 65 is removed in advance. This is to facilitate countersinking in the cavity formation step described below.

[0075] The second buildup layer 62 has an insulating resin layer 62a, an insulating resin layer 62b, and a conductor layer 17. In the insulating resin layer 62a directly below the core substrate base material 11A that becomes the core substrate 51, a via 15 is formed within a cavity forming region 65. This via 15 is connected to the first conductor layer 17 of the core substrate 51 at the upper part, and is connected to the via 15 of the insulating resin layer 62b of the lower layer at the lower part. The first conductor layer 17 is formed on the left and right lower surfaces of the insulating resin layer 62a and the insulating resin layer 62b. By forming a through hole 10 penetrating the first conductor layer 17, interlayer connection is made between the first conductor layer 17 of the other layers, the conductor layer 63 of the uppermost layer, and the conductor layer 64 of the lowermost layer.

[0076] Furthermore, in the cavity forming region 65, directly below the boundary between the cavity portion and the non-cavity portion (at a position corresponding to the cavity forming region 65 and its boundary), the above-mentioned second conductor layer 12a is formed one layer below the bottom surface of the cavity 20 (between the insulating resin layer 62a and the insulating resin layer 62b). This second conductor layer 12a serves as a laser receiver (shielding member) during laser processing to be described later, and prevents the laser from penetrating into the lower layer. Any method may be used to form this second conductor layer 12a, and may be a subtractive method, an M-SAP method, a semi-additive method, or the like.

[0077] (Cavity formation process) 9, in this step, a drill is directed from the side of first buildup layer 61 of laminated substrate 54A toward seed layer 12 left on core substrate 51. In other words, a cavity formation region 65 provided in advance in laminated substrate 54A is processed as if being gouged out with a drill.

[0078] In this case, there are two steps: a step (countersinking process 1) of penetrating the first buildup layer 61 by inserting a drill into the cavity formation region 65 in the stacking direction (thickness direction), and partially removing the insulating resin layer 61a and the insulating resin layer 61b while leaving a part of the base material 11 on the seed layer 12 inside the core substrate 51 to form the cavity 20; and a step (countersinking process 2) of using the seed layer 12 and the second conductor layer 12a, one layer below, as shielding members for the laser light, removing the insulating resin 68 remaining in the cavity 20 by laser processing, and exposing the seed layer 12 to the bottom of the cavity 20.

[0079] (Counterboring 1 (Drilling)) In this process, a recess is cut (cutting process using a combination of drilling and laser processing is also possible) from above the laminated substrate 54A through the first buildup layer 61 in the cavity formation region 65 to the substrate 11 in the core substrate substrate 11A, and most of the insulating resin is removed except for a part of the substrate 11 on the seed layer 12 on the underside of the core substrate substrate 11A to form a cavity 20.

[0080] Specifically, as shown in FIG. 9, a drill 66 having a sensor at the bit tip is placed at one end of the cavity formation region 65 (for example, the left end as viewed in the figure), and drilled down to a position just before the seed layer 12 on the surface of the core substrate base material 11A (a position just before the bottom of the cavity 20), and the drill 66 is moved from that position in the lateral direction A to remove the insulating resin layer 11 with the drill 66.

[0081] In this example, a part of the base material 11 is left on the bottom of the cavity 20, but if the drilling accuracy is high, it may be drilled down to the very edge of the surface of the seed layer 12.

[0082] The reason why the recessing process is performed in two stages, including drilling and not just laser processing, which will be described later, is that the seed layer 12, etc. is used as a receiving conductor (shielding member) for the laser processing, which will be described later, and the insulating resin 68, which is the remaining part of the base material 11, is removed.

[0083] (Counterboring 2 (Laser processing)) In this step, as shown in Fig. 10, laser light is irradiated from above the opening of cavity 20 in the direction of arrow B to remove insulating resin 68 left on the bottom of cavity 20 by the drilling process in Fig. 8. For the laser processing, a processing laser such as a carbon dioxide laser (CO2 laser) or a YAG laser can be used.

[0084] In conventional technologies, if the conditions for laser ablation are not appropriate, there is a problem that the laser may penetrate to the lower layer in the no-shielding-conductor area at the boundary between the cavity and non-cavity sections, potentially damaging the substrate.

[0085] In the method for manufacturing a printed wiring board of the present disclosure, the seed layer 12 and the second conductor layer 12a, which is one layer below, are used as shielding members for laser light, and the remaining portion of the upper layer portion left on the bottom of the cavity 20 is removed by laser processing, exposing the flat surface of the seed layer 12 on the bottom of the cavity 20, as shown in Fig. 11. At this time, by using the second conductor layer 12a as a shielding member for laser light, even when the conditions for laser irradiation are not appropriate, it is possible to prevent the laser from penetrating to the lower layer and damaging the base material (insulating resin layer 62a in this case) in the no-shielding-conductor area at the boundary between the cavity portion and the non-cavity portion.

[0086] When the insulating resin 68 at the bottom of the cavity 20 is processed by laser processing, a thin resin film (fine resin debris) may remain in that area. To remove such remaining fine resin debris, the area carbonized by the laser is cleaned. For this purpose, a water washing process such as high-pressure water washing or a desmear process using a plasma process or permanganate process is performed. These processes may be performed twice or three times.

[0087] The desmear treatment is a treatment in which the resin is swollen with a strong alkali and then decomposed and removed using an oxidizing agent (e.g., chromic acid, a permanganate aqueous solution, etc.). The resin film may also be removed by wet blasting with an abrasive or by plasma treatment. When performing plasma treatment, masking with a dry film may be performed to protect the surface substrate.

[0088] In addition, when performing the desmear treatment, in order to protect the outermost layer base material and the outermost layer circuit, the process may be reversed and the outermost layer circuit may be formed after forming the cavity 20. In that case, in order to protect the cavity 20, it is necessary to protect it with a dry film or the like. An electrodeposition resist (ED, etc.) can also be used.

[0089] The second conductor layer 12a used as a laser light receiving conductor (laser light shielding member) can improve the rigidity of the multilayer substrate 54, which is reduced due to the absence of an upper structure due to the cavity 20. In this case, the second conductor layer 12a is sufficient as a laser light shielding member only on the cavity outline, but the rigidity can be further enhanced by arranging it on the entire bottom surface of the cavity. Furthermore, the plate thickness of the cavity portion, which is prone to variation when wiring alone is used, can be stabilized. When the second conductor layer 12a is arranged only on the cavity outline, the laser can be sufficiently shielded by arranging the second conductor layer 12a 200 μm wide outward from the end of the seed layer 12, taking into account the laser irradiation diameter and interlayer positional deviation.

[0090] In addition, because the seed layer 12 penetrates into the substrate 11, if multiple circuits are to be extended from the first conductor layer 17 to the outside of the cavity, the multiple circuits will short-circuit each other at the seed layer 12. However, by forming the seed layer 12 to be slightly narrower than the cavity 20, the seed layer 12 will not penetrate into the substrate 11, and multiple circuits can be extended to the outside of the cavity.

[0091] The copper foil (barrier layer) of the seed layer 12 at the bottom of the cavity 20 can be of various types, such as a profile-free foil, a low-profile foil, or a standard foil.

[0092] Here, the effect of forming the second conductor layer 12a will be described with reference to Fig. 16 and Fig. 17. Fig. 16 is a diagram showing an outline of the cavity 20, and Fig. 17 is an enlarged view of the periphery of the contour of the cavity 20 shown by the dashed line A in Fig. 16. The second conductor layer 12a is disposed on the lower surface of the insulating resin layer 62a, and as described above, it functions as a shielding member for the laser light L. In this case, in this embodiment, the insulating resin layer 62a may be processed so that the vicinity of its surface is locally affected by the laser light.

[0093] When the second conductor layer 12a is provided on the insulating resin layer 62a below the contour of the cavity 20, the upper side of the second conductor layer 12a is slightly gouged out when the contour is processed with a laser beam, and the volume of this gouged out part is smaller than when the second conductor layer 12a is not provided.

[0094] The shape of the hollowed-out portion is stepped on the wall surface 20a side of the cavity 20 (62aL in the figure), but the opposite inner side of the cavity 20 (symbol 62aR) is perpendicular to the surface (bottom surface 79) of the insulating resin layer 62a.

[0095] When the solder resist R is formed on the bottom surface 79 side of the cavity 20, it is possible to prevent the solder resist R from creeping up the wall surface 20a, and at the same time, the solder resist can be formed with a uniform thickness on the bottom surface of the cavity 20. This is because the wall surface 20a side (62aL) of the cavity 20 is stepped, so the solder resist easily creeps up, but the inner side (62aR) is a vertical surface, so the solder resist does not easily creep up.

[0096] At the intersection X between the inner side 62aR of the hollowed portion and the bottom surface 79, the solder resist can be made to have the same thickness as the other parts of the bottom surface 79. That is, in FIG. 17, the thickness t C1 and the thickness t of the solder resist on the bottom surface 79 79 can be the same. Here, "the same" means that the relationship roughly satisfies the following formula: t C1 -t 79 ≦1μm

[0097] In this embodiment, the order is to form the outermost circuit and then the cavity 20, but when the cavity 20 is subjected to a desmear treatment such as a permanganate treatment after the laser treatment, the cavity 20 may be formed before the formation of the outermost circuit in order to protect the surface base material and prevent deterioration of the circuit peel strength. Also, when the outermost circuit is formed by pattern plating such as M-SAP, the process can be combined with the seed layer removal process described later to reduce the number of processes.

[0098] (Seed layer removal process) In this process, as shown in FIG. 12, the seed layer 12 exposed at the bottom of the cavity 20 is removed by flash etching to expose the surface 79 of the insulating resin layer 62a of the second build-up layer 62 and the surface of the conductor layer 17 embedded in the insulating resin.

[0099] More specifically, in this process, the seed layer 12 (copper foil) which is a barrier layer is removed by flash etching the bottom of the cavity forming region 65. In this way, the multilayer substrate 54 is obtained. The surface (bottom surface 79) of the insulating resin layer 62a below the core substrate 51 and the first conductor layer 17 embedded in the insulating resin layer 62a with its surface exposed at the same height (position) as the bottom surface 79 form a part of the bottom surface 79 of the cavity 20. The first conductor layer 17 exposed flat on the bottom surface of the cavity 20 in this way functions as a component mounting land, and makes it possible to connect the circuit wiring in this multilayer substrate 54 and the electronic components accommodated in the cavity 20.

[0100] If it is not desired to reduce the thickness of the conductor in the outermost layer by flash etching, it can be performed after the solder resist, or masking with a dry film can be performed after the solder resist, and the areas to be etched can be selected arbitrarily.

[0101] As mentioned above, there is a concern that the pattern plating portion may be slightly etched in addition to the seed layer. However, the amount of etching is about 2 μm, and since the flash etching solution has the property of etching uniformly in the vertical direction, there is no adverse effect on the conductor thickness.

[0102] If nickel plating is used as the barrier plating, the nickel must be etched further. Nickel remover NH-1860 series (manufactured by MEC Co., Ltd.) is suitable for etching nickel.

[0103] When gold plating is applied under nickel barrier plating for wire bonding applications, it is theoretically possible to use ferric chloride solution or cupric chloride solution, which are typical etching solutions for the subtractive method, since they do not dissolve gold. However, due to their strong penetrating power into the interface, they will penetrate into the interface between the gold plating and the insulating material, causing side etching that dissolves the nickel plating and copper plating underneath the gold plating, making them unsuitable.

[0104] (Outer layer circuit formation process) In this process, the conductor layer 64 of the second buildup layer 62 at the bottom of the multilayer substrate 54 formed as shown in FIG. 12 is etched to remove a portion of the conductor layer 64a as a circuit as shown in FIG. 13. Also, the conductor layer 63 of the first buildup layer 61 at the top of the substrate is etched to remove a portion of the conductor layer 63a as a circuit wiring or wiring pattern. The outer layer circuit may be formed by a subtractive method using an electrodeposited resist as an etching resist, which has excellent conformability to the wall surfaces of recesses and through holes. The electrodeposited resist is an etching resist that utilizes the properties of electrodeposition coating.

[0105] (Solder resist process) In this process, the first and second buildup layers 61, 62 shown in Fig. 13 are coated with an insulating film including parts of the conductor layers 63a, 64a, and solder resists 71, 72 are formed as shown in Fig. 14. Either a dry film type or a liquid type can be used as the solder resist.

[0106] (Electronic component mounting location formation process) The steps after this are performed when a step is required for the component mounting land. In this step, as shown in Fig. 15, plating is applied to the conductor layer 17 exposed at the bottom of the cavity 20 to form a metal plating layer 80, and a connection pad, which is a component mounting land with a step from the bottom surface, is formed.

[0107] A circuit pattern may also be formed by plating on the conductor layer 63a of the first buildup layer 61 on the upper part of the multilayer substrate 54. At this time, if the through-hole 10 is filled with resin or metal, the upper and lower parts of the through-hole 10 where there is no solder resist 71 are also plated, so that conductor layers 73, 74 are also formed there.

[0108] If necessary, a process for mounting electronic components may be added as follows. In this process, an electronic component is accommodated in cavity 20, and electrodes provided on the bottom of the electronic component are brought into contact with metal plating layer 80 (connection pads) to connect the circuits. Note that if electronic components are not mounted here but are instead mounted elsewhere, the processes following the electronic component mounting process are not necessary.

[0109] Thus, the core substrate base material 11A for forming the printed wiring board of this embodiment has a base material 11 made of insulating resin having a first surface (upper surface) 11a and a second surface (lower surface) 11b facing the first surface (upper surface) 11a. A seed layer 12 is formed on the second surface (lower surface) 11b of the base material 11 made of insulating resin. A first conductor layer 17 is formed on a partial region of the seed layer 12 by pattern plating. The core substrate 51 has a base material 11 made of insulating resin, a seed layer 12, and a first conductor layer 17. A second build-up layer 62 built up with insulating resin is formed on at least the lower surface of the core substrate 51, forming a multi-layer substrate (laminated substrate 54A). A cavity 20 is formed by processing the laminated substrate 54 such that a portion of the core substrate 51 (cavity forming region 65) is recessed from the side of the first buildup layer 61 so that the seed layer 12 of the second surface (lower surface) 51b of the core substrate 51 is exposed at the bottom. When the seed layer 12 exposed at the bottom of the cavity 20 is removed by flash etching, the surface (bottom surface 79) of the insulating resin layer 62a of the second buildup layer 62 located below the core substrate 51 remains. The first conductor layer 17 is embedded in the bottom surface 79 so that the top surface is aligned substantially flush with the bottom surface. With this configuration, the circuit connection between the electronic component accommodated in the cavity 20 and the substrate side can be made at the bottom of the electronic component.

[0110] In this way, by forming the first conductor layer 17, which is approximately flush with the bottom surface 79 of the cavity 20, as a connection pad (component mounting land) and connecting it to an electrode at the bottom of the electronic component, the peel strength of the component mounting land as a wiring pattern at the bottom of the cavity 20 can be improved.

[0111] The examples of the manufacturing procedures for printed wiring boards in each of the above embodiments are just examples, and it is possible to change the processing steps in various ways by interchanging the processing steps, adding new processing steps, and deleting some processing steps.

[0112] Although an embodiment of the present invention has been described, this embodiment is shown by way of example only, and the present invention can be embodied in various other forms, and components can be omitted, substituted, or modified without departing from the spirit of the invention. [Explanation of symbols]

[0113] 10...through hole, 11...insulating resin substrate, 12...seed layer, 12a...second conductor layer, 13, 18...dry film, 14...via hole pilot hole, 15...via, 16, 63, 64...conductor layer, 17...first conductor layer, 20...cavity, 51...core substrate, 54...multilayer substrate, 61, 62...build-up layer, 61a, 61b, 62a, 62b...insulating resin layer, 66...drill, 68...insulating resin, 71, 72...solder resist, 79...bottom surface, 80...metal plating layer.

Claims

1. A first step of preparing a core substrate having a first surface and a second surface, the second surface being provided with a seed layer; a second step of forming a first conductor layer by pattern plating the seed layer provided on the core substrate; a third step of removing a portion of the seed layer on a surface of the seed layer including the first conductor layer of the core substrate such that the seed layer remains in a central portion of the core substrate, which is a region in which a cavity is to be formed; a fourth step of forming a first buildup layer having a first insulating resin layer on the first surface of the core substrate and forming a second buildup layer having a second insulating resin layer on the second surface of the core substrate; a fifth step of pattern-plating the surface of the second buildup layer with nickel, gold, nickel, and copper in that order to form a second conductor layer at a position that overlaps at least a portion of a periphery of a bottom surface of the cavity to be formed in a plan view; a sixth step of forming the cavity, the bottom surface of which is a surface of the second buildup layer, by using the seed layer and the second conductor layer as a shielding member for a laser beam when penetrating the first buildup layer and the core substrate by laser processing from the first buildup layer side of the core substrate; A method for manufacturing a printed wiring board comprising the steps of:

2. The method for manufacturing a printed wiring board according to claim 1 , wherein the second conductor layer is formed so as to go around a peripheral portion of the bottom surface of the cavity.

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