Semiconductor device and electronic device

Abstract

To provide a technology advantageous for miniaturizing a semiconductor device while providing ESD resistance. [Solution] A semiconductor device has a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and a varistor. The interconnect structure includes a pad region including a pad, and a circuit region, each of the pad region and the circuit region including a plurality of interconnect layers, an interlayer insulating film disposed between the plurality of interconnect layers, and a via plug connecting the plurality of interconnect layers to each other, the varistor is electrically connected to the pad, and is disposed in the circuit region and above an upper surface of the semiconductor substrate.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices include an ESD protection circuit for protecting electronic circuits disposed therein from noise such as ESD (Electro-Static Discharge).

[0003] Patent Document 1 describes an ESD protection circuit disposed between two bonding pads. In the ESD protection circuit ESD described in Patent Document 1, a resistor R1 and a capacitor C1 are connected in series between a power supply voltage VCC and a reference potential VSS, and an input part of an inverter Iv1 is connected to a connection part between the resistor R1 and the capacitor C1. The inverter Iv1 is configured by connecting a P-channel MOS transistor T1 and an N-channel MOS transistor T2 in series between a power supply voltage VCC and a reference potential VSS. The output part of the inverter Iv1 is connected to a gate of a clamping transistor T3 made of an N-channel MOS. A power supply voltage VCC is connected to one end of the source / drain of the transistor T3, and a reference potential VSS is connected to the other end of the source / drain of the transistor T3. A reference potential VSS is connected to the gate of the transistor T3 via a resistor R2, and a parasitic diode DP is formed at a junction part between the well region and the source of the transistor T3. A diode D1 is connected between the power supply voltage VCC and the reference potential VSS. In general, an ESD protection circuit built into a semiconductor device has a complex configuration and can occupy a large area in the semiconductor device, which leads to an increase in the size of the semiconductor device.

[0004] Although it is less relevant to the present application, Patent Document 2 describes a nonvolatile memory device including a lower electrode layer formed on a substrate, a resistance change layer connected to the lower electrode layer, an upper electrode layer connected to the resistance change layer, and an insulating metal oxide thin film layer formed on the lower electrode layer. Patent Document 2 describes that the nonvolatile memory device may further include a non-ohmic element connected in series to the resistance change layer, and that the non-ohmic element is any one of an MIM diode, an MSM diode, and a varistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2015-88652 A [Patent Document 2] JP 2008-305889 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a technique that is advantageous for miniaturizing a semiconductor device while providing ESD resistance. [Means for solving the problem]

[0007] A first aspect of the present invention relates to a semiconductor device having a semiconductor substrate, a wiring structure arranged on the semiconductor substrate, and a varistor, wherein in the semiconductor device, the wiring structure includes a pad region including a pad, and a circuit region, each of the pad region and the circuit region includes a plurality of wiring layers, an interlayer insulating film arranged between the plurality of wiring layers, and a via plug connecting the plurality of wiring layers to each other, the varistor is electrically connected to the pad, and the varistor is arranged in the circuit region and above an upper surface of the semiconductor substrate.

[0008] A second aspect of the present invention relates to an electronic device, the electronic device including the semiconductor device according to the first aspect. Effect of the Invention

[0009] According to the present invention, a technique is provided that is advantageous for miniaturizing a semiconductor device while providing ESD resistance. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view illustrating a schematic configuration of a semiconductor device according to an embodiment; [Diagram 2] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to an embodiment; [Diagram 3] FIG. 2 is a diagram illustrating an equivalent circuit of a portion of a semiconductor device according to an embodiment; [Figure 4] FIG. 2A is a diagram showing a CAD layout of a conventional ESD protection circuit, and FIG. 2B is a diagram showing a schematic diagram of the CAD layout of the varistor of the present embodiment. [Diagram 5] 1 is a graph showing the results of an approximate calculation of the relationship between the area occupied by a protection element and HBM (Human Body Model) resistance. [Figure 6] 1 is a cross-sectional view of a semiconductor device incorporating a conventional ESD protection circuit ESDC. [Figure 7] FIG. 1 is a plan view of a semiconductor device incorporating a conventional ESD protection circuit ESDC. [Figure 8] FIG. 2 is a cross-sectional view of a semiconductor device of varistor V of the present embodiment. [Figure 9] FIG. 2 is a plan view of a semiconductor device of varistor V of the present embodiment. [Figure 10] FIG. 2A is a schematic plan view of the varistor of the first embodiment, FIG. 2B is a schematic cross-sectional view of the varistor of the first embodiment, and FIG. 2C is a schematic cross-sectional view of a modified example of the varistor of the first embodiment. [Figure 11] 5A is a schematic plan view of a varistor according to a second embodiment, FIG. 5B is a schematic cross-sectional view of the varistor according to the second embodiment, and FIG. 5C is a schematic cross-sectional view of a modified example of the varistor according to the second embodiment. [Figure 12] FIG. 11 is a schematic plan view of a varistor according to a third embodiment. [Figure 13]FIG. 13( a ) is a schematic cross-sectional view of a varistor according to a third embodiment, and FIG. 13( b ) is a schematic cross-sectional view of a varistor according to the third embodiment. [Figure 14] FIG. 13 is a schematic plan view of a varistor according to a fourth embodiment. [Figure 15] FIG. 13( a ) is a schematic cross-sectional view of a varistor according to a fourth embodiment, and FIG. 13( b ) is a schematic cross-sectional view of a varistor according to the fourth embodiment. [Figure 16] 13A is a schematic plan view of a varistor according to a fifth embodiment, FIG. 13B is a schematic cross-sectional view of the varistor according to the fifth embodiment, and FIG. 13C is a schematic cross-sectional view of a modified example of the varistor according to the fifth embodiment. [Figure 17] FIG. 13 is a schematic plan view of a varistor according to a sixth embodiment. [Figure 18] FIG. 13( a ) is a schematic cross-sectional view of a varistor according to a sixth embodiment, and FIG. 13( b ) is a schematic cross-sectional view of a varistor according to the sixth embodiment. [Figure 19] 11A to 11C are diagrams illustrating electronic devices according to application examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims, and not all combinations of features described in the embodiments are essential to the invention. Two or more features among the multiple features described in the embodiments may be arbitrarily combined. Also, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0012] 1 and 2 are a plan view and a cross-sectional view, respectively, that respectively show a schematic configuration of a semiconductor device 1 according to an embodiment. The semiconductor device 1 may include a semiconductor chip 12 having one or more varistors V and one or more pads 16. The semiconductor device 1 may also include one or more lead frames 14, and a package 10 that seals the semiconductor chip 12. Each pad 16 of the semiconductor chip 12 and the corresponding lead frame 14 may be electrically and physically connected by a bonding wire 18. When forming the bonding wire 18, a bonding ball 17 may be formed on the pad 16, and the pad 16 and the bonding wire 18 may be electrically and physically connected via the bonding ball 17. The semiconductor chip 12 may have a pad region including the pad 16, and a circuit region. In the circuit region, various circuit blocks, for example, a power supply circuit, an arithmetic circuit, an ADC (AD converter), a memory circuit, an audio processor, a DAC (DA converter), a video processor, a bus, a clock circuit, and the like, may be arranged.

[0013] 3 is a diagram illustrating an equivalent circuit of a part of the semiconductor device 1 of an embodiment. The semiconductor device 1 may include, for example, one or more power supply pads VDD, one or more ground pads GND, one or more input pads IN1, IN2, one or more output pads OUT1, OUT2, and one or more circuit blocks CB. Although not shown, the semiconductor device 1 may include one or more input / output pads. The power supply pads, ground pads, input pads, output pads, and input / output pads may be collectively referred to as pads. The power supply pad VDD may be electrically connected to the power supply line VDDL. The power supply line VDDL may be supplied with a voltage (a voltage converted by the power supply circuit) supplied from the power supply pad VDD via a power supply circuit.

[0014] Two or more pads may be electrically connected to each other by a path including the varistor V. Alternatively, two or more pads may be electrically connected to each other by a path including the varistor V and the resistor element R. In another aspect, the varistor V may be electrically connected to the pad by a wiring pattern WP. Alternatively, the varistor V may be electrically connected to the pad via the wiring pattern WP and the resistor element R. The varistor V may be, for example, a varistor having a molybdenum oxide film as a resistive film. A varistor having a molybdenum oxide film as a resistive film is excellent in that the varistor voltage can be adjusted over a wide range. The varistor V may be, for example, a varistor having a ceramic obtained by adding a metal oxide to ZnO (zinc oxide) and firing the resulting resistive film. Alternatively, the varistor V may have a resistive film made of another material.

[0015] Conventionally, semiconductor devices have protected their internal circuits from surge currents by an ESD protection circuit including a diode including a PN junction formed in a semiconductor substrate. The ESD protection circuit including a diode including a PN junction occupies a fairly large area, which causes the semiconductor device to become larger. In this embodiment, the semiconductor device 1 is made smaller by incorporating a varistor V as a protection element in the semiconductor device 1. The varistor V can have a structure selected from a variety of structures, as described below.

[0016] Fig. 4(a) shows a schematic CAD layout of a conventional ESD protection circuit ESDC incorporated in a semiconductor device. The ESD protection circuit ESDC can be electrically connected to a pad BP via a wiring pattern WP. Fig. 4(b) shows a schematic CAD layout of a varistor V of this embodiment incorporated in a semiconductor device. The varistor V can be electrically connected to a pad BP via a wiring pattern WP.

[0017] Fig. 5 is a graph showing the results of estimating the relationship between the area occupied by the protection element and HBM (Human Body Model) resistance, where the solid line indicates the case where the varistor of this embodiment is used as the protection element, and the dotted line indicates the case where the conventional ESD protection circuit ESDC shown diagrammatically in Fig. 4(a) is used as the protection element. According to this embodiment, it is possible to obtain excellent HBM resistance while reducing the area of ​​the protection element.

[0018] 6 and 7 respectively show a cross-sectional view and a plan view of a semiconductor device incorporating a conventional ESD protection circuit ESDC. In FIG. 6, a surge current path in the conventional semiconductor device is shown typically by a thick arrow. The semiconductor device has a wiring structure WS on a semiconductor substrate SS. The semiconductor device also has an ESD protection circuit ESDC arranged adjacent to a pad region PR including a pad BP to which a bonding wire BW is connected, and the pad BP and the ESD protection circuit ESDC are connected via a wiring pattern WP. The ESD protection circuit ESDC includes a PN junction formed in the semiconductor substrate SS.

[0019] 8 and 9 show a cross-sectional view and a plan view of the semiconductor device 1 of this embodiment in which the varistor V is incorporated, respectively. In FIG. 8, the path of the surge current in the semiconductor device 1 of this embodiment is shown typically by a thick arrow. The semiconductor device 1 has a wiring structure WS on a semiconductor substrate SS. The wiring structure WS includes a pad region PR including a pad BP and a circuit region CR, and each of the pad region PR and the circuit region CR may include a plurality of wiring layers WL, an interlayer insulating film ILIF disposed between the plurality of wiring layers WL, and a via plug VP connecting the plurality of wiring layers WL to each other. In this embodiment, the varistor V as a protection element is disposed in the circuit region CR and above the upper surface of the semiconductor substrate SS. On the other hand, a conventional protection element includes a PN junction formed on the semiconductor substrate SS. A bonding wire BW may be electrically and physically connected to the upper surface of the pad BP via a bonding ball BB.

[0020] The varistor V may be disposed in the circuit region CR at a position close to the pad region PR. The varistor V may be electrically connected to the pad BP by the wiring pattern WP. Alternatively, the varistor V may be electrically connected to the pad BP via a resistor element in addition to the wiring pattern WP. As shown in FIG. 1, the wiring structure WS of the semiconductor device 1 may have a plurality of pads 16 (including 16-1 and 16-2). The wiring structure WS may have, for example, a pad region PR-1 including a first pad 16-1 and a pad region PR-2 including a second pad 16-2, and the varistor V may be disposed between the first pad region PR-1 and the second pad region PR-2. The circuit region CR may include a transistor Tr disposed under the varistor V. This is advantageous for increasing the circuit size that can be incorporated in the semiconductor device 1.

[0021] 8, the varistor V may have an electrode including a conductive film arranged on the farthest wiring layer WLF among the multiple wiring layers WL that is farthest from the semiconductor substrate SS. In another respect, the varistor V may include an electrode including a conductive film arranged on each of at least two wiring layers WL among the multiple wiring layers WL, as illustrated in FIG.

[0022] Below, we will explain several embodiments of the varistor V that can be incorporated in the semiconductor device 1. However, these are merely examples, and the varistor V may have other structures.

[0023] FIG. 10(a) shows a schematic plan view of the varistor V of the first embodiment. FIG. 10(b) shows a schematic cross-sectional view of the varistor V of the first embodiment. The varistor V of the first embodiment may have a resistive film 110, a first electrode 121 arranged in a first region R1 of a main surface 111 (here, the upper surface) of the resistive film 110, and a second electrode 122 arranged in a second region R2 of the main surface 111 of the resistive film 110. The second region R2 is separated from the first region R1. The first electrode 121 and the second electrode 122 may be formed of a conductive film arranged in one of the wiring layers WL, for example, the farthest wiring layer WLF farthest from the semiconductor substrate SS. The first electrode 121 and the second electrode 122 may be formed of, for example, a metal (for example, aluminum) or an alloy (for example, aluminum to which tungsten or copper is added). The resistive film 110 may be a molybdenum oxide film, but may be a film made of other materials. The first electrode 121 and the second electrode 122 may have a circular, elliptical, or round shape. Alternatively, the first electrode 121 and the second electrode 122 may have a rectangular shape with rounded corners. Alternatively, the first electrode 121 and the second electrode 122 may have a square or polygonal shape with rounded corners, or may have another shape.

[0024] Fig. 10(c) shows a schematic cross-sectional view of a modified example of the varistor V of the first embodiment. The varistor V of the modified example of the first embodiment may have a resistive film 110, a first electrode 121 arranged in a first region R1 of the main surface 112 (here, the lower surface) of the resistive film 110, and a second electrode 122 arranged in a second region R2 of the main surface 112 of the resistive film 110. The second region R2 is separated from the first region R1. The first electrode 121 and the second electrode 122 may be formed of a conductive film arranged in one of the multiple wiring layers WL.

[0025] FIG. 11(a) shows a schematic plan view of the varistor V of the second embodiment. FIG. 11(b) shows a schematic cross-sectional view of the varistor V of the second embodiment. Items not mentioned regarding the varistor V of the second embodiment (including modified examples) may follow the above description. The varistor V of the second embodiment may have an intermediate film 130 disposed between the main surface 111 of the resistive film 110 and the first electrode 121, and between the main surface 111 of the resistive film 110 and the second electrode 122. The intermediate film 130 may be, for example, a silicon film containing impurities (for example, a polysilicon film or an amorphous silicon film). The intermediate film 130 is advantageous for providing ohmic contact between the resistive film 110, which may be composed of a molybdenum oxide film, and the first electrode 121 and the second electrode 122.

[0026] 11(c) is a schematic cross-sectional view of a modified example of the varistor V of the second embodiment. The varistor V of the modified example of the second embodiment may have an intermediate film 130 disposed between the main surface 112 of the resistive film 110 and the first electrode 121, and between the main surface 112 of the resistive film 110 and the second electrode 122. The intermediate film 130 may be, for example, a silicon film containing impurities (for example, a polysilicon film or an amorphous silicon film). The intermediate film 130 is advantageous for providing ohmic contact between the resistive film 110, which may be composed of a molybdenum oxide film, and the first electrode 121 and the second electrode 122.

[0027] FIG. 12 shows a schematic plan view of the varistor V of the third embodiment. FIG. 13(a) shows a schematic cross-sectional view of the varistor V of the third embodiment. Items not mentioned regarding the varistor V of the third embodiment (including modified examples) may follow the above explanation. The varistor V of the third embodiment may have a resistive film 110, a first electrode 121 arranged in a first region of the main surface 111 (here, the upper surface) of the resistive film 110, and a second electrode 122 arranged in a second region of the main surface 111 of the resistive film 110. In the varistor V of the third embodiment, each of the first electrode 121 and the second electrode 122 includes at least two conductive films 201, 202 arranged in at least two wiring layers WL of the multiple wiring layers WL. The varistor V of the third embodiment may further include a plug VP that electrically connects the at least two conductive films 201, 202. The at least two conductive films 201, 202 may include a first conductive film 201 including a first pattern P1 and a second conductive film 202 including a plurality of second conductive patterns P2 smaller than the first pattern P1. Such a configuration is advantageous for adjusting the varistor voltage of the varistor V. The varistor voltage may be adjusted, for example, by adjusting the area of ​​the second conductive pattern P2.

[0028] 13(b) shows a schematic cross-sectional view of a modified example of the varistor V of the third embodiment. The varistor V of the modified example of the third embodiment may have a resistive film 110, a first electrode 121 arranged in a first region of a main surface 112 (here, the lower surface) of the resistive film 110, and a second electrode 122 arranged in a second region of the main surface 112 of the resistive film 110.

[0029] Fig. 14 shows a schematic plan view of the varistor V of the fourth embodiment. Fig. 15(a) shows a schematic cross-sectional view of the varistor V of the fourth embodiment. Items not mentioned regarding the varistor V of the fourth embodiment (including modified examples) may follow the explanations given above. The varistor V of the fourth embodiment may have intermediate films 130 arranged between the main surface 111 (here, the upper surface) of the resistive film 110 and the first electrode 121, and between the main surface 111 of the resistive film 110 and the second electrode 122.

[0030] 15(b) shows a schematic cross-sectional view of a modified example of the varistor V of the fourth embodiment. The varistor V of the modified example of the second embodiment may have intermediate films 130 disposed between the main surface 112 (here, the lower surface) of the resistive film 110 and the first electrode 121, and between the resistive film 110 and the second electrode 122.

[0031] FIG. 16(a) shows a schematic plan view of the varistor V of the fifth embodiment. FIG. 16(b) shows a schematic cross-sectional view of the varistor V of the fifth embodiment. Items not mentioned regarding the varistor V of the fifth embodiment (including modified examples) may follow the above explanation. The varistor V of the fifth embodiment may have a first electrode 121, a resistive film 110 arranged on the first electrode 121, and a second electrode 122 arranged on the resistive film 110. In other words, the varistor V of the fifth embodiment may have a first electrode 121 arranged on one main surface 112 side of the resistive film 110, and a second electrode 122 arranged on the other main surface 111 side of the resistive film 110. In the first to fourth embodiments, a current path is formed so that a current flows in a direction along the main surface of the resistive film 110, whereas in the fifth embodiment, a current path is formed so that a current flows in the thickness direction of the resistive film 110. The second electrode 122 may be formed of a conductive film disposed in one of the wiring layers WL, for example, the farthest wiring layer WLF from the semiconductor substrate SS. The first electrode 121 may be formed of a conductive film disposed in one of the wiring layers WL. The first electrode 121 and the second electrode 122 may be formed of a metal (for example, aluminum) or an alloy (for example, aluminum with added tungsten or copper).

[0032] 16(c) shows a schematic cross-sectional view of a modified example of the varistor V of the fifth embodiment. The modified varistor V of the fifth embodiment may have intermediate films 130 disposed between the resistive film 110 and the first electrode 121, and between the resistive film 110 and the second electrode 122.

[0033] FIG. 17 is a schematic plan view of the varistor V of the sixth embodiment. FIG. 18(a) is a schematic cross-sectional view of the varistor V of the sixth embodiment. Items not mentioned regarding the varistor V of the sixth embodiment (including modified examples) may follow the above description. The varistor V of the sixth embodiment may have a first electrode 121, a resistive film 110 arranged on the first electrode 121, and a second electrode 122 arranged on the resistive film 110. In the varistor V of the sixth embodiment, the first electrode 121 includes at least two conductive films 201a, 202a arranged on at least two wiring layers WL of the multiple wiring layers WL. In addition, in the varistor V of the sixth embodiment, the second electrode 122 includes at least two conductive films 201b, 202b arranged on at least two wiring layers WL of the multiple wiring layers WL. Moreover, the varistor V of the sixth embodiment may further include a plug VP that electrically connects at least two conductive films 201a, 202a, and a plug VP that electrically connects at least two conductive films 201b, 202b.

[0034] The at least two conductive films 201a, 202a may include a first conductive film 201a including a first pattern P1a and a second conductive film 202a including a plurality of second conductive patterns P2a smaller than the first pattern P1a. The at least two conductive films 201b, 202b may include a first conductive film 201b including a first pattern P1b and a second conductive film 202b including a plurality of second conductive patterns P2b smaller than the first pattern P1b. Such a configuration is advantageous for adjusting the varistor voltage of the varistor V. The varistor voltage may be adjusted, for example, by adjusting the area of ​​the second conductive pattern P2.

[0035] 15(b) shows a schematic cross-sectional view of a modified example of the varistor V of the sixth embodiment. The varistor V of the modified example of the second embodiment may have intermediate films 130 disposed between one main surface 112 (here, the lower surface) of the resistive film 110 and the first electrode 121, and between the other main surface 112 (here, the upper surface) of the resistive film 110 and the second electrode 122.

[0036] FIG. 19 shows a configuration example of an electronic device 1100 as an application example of the semiconductor device 1 described above. The electronic device 1100 may be, for example, a computer, an information terminal, a communication terminal, a camera, a signal processing device, a vehicle control device, a flight control device, or the like, or a combination of at least two of these electronic devices. The electronic device 1100 includes a plurality of semiconductor devices 1101, 1102, and 1103, which may be arranged on one or more printed wiring boards (PCBs). At least one of the plurality of semiconductor devices 1101, 1102, and 1103 may incorporate a varistor V, as in the semiconductor device 1 described above. The electronic device 1100 may include one or more varistors Ve arranged outside the plurality of semiconductor devices 1101, 1102, and 1103. The varistor Ve may have the configuration described as any one of the first to sixth embodiments. The varistor Ve may be arranged between two or more signal lines 1112 in the electronic device 1100. Such two or more signal lines 1112 may be disposed next to each other or through other signal lines 1112. Varistor Ve may be disposed between the signal line 1112 and a power line. Varistor Ve may be disposed between the signal line 1112 and a ground line. Varistor Ve may be electrically connected to a pad or terminal 1111.

[0037] The invention is not limited to the above-described embodiment, and various modifications and variations are possible within the scope of the gist of the invention. [Explanation of symbols]

[0038]

Claims

1. A semiconductor device having a semiconductor substrate, a wiring structure disposed on the semiconductor substrate, and a varistor, the wiring structure includes a pad region including a pad, and a circuit region, each of the pad region and the circuit region including a plurality of wiring layers, an interlayer insulating film disposed between the plurality of wiring layers, and a via plug connecting the plurality of wiring layers to each other; The varistor is electrically connected to the pad; the varistor is disposed in the circuit region and above the upper surface of the semiconductor substrate; A semiconductor device comprising:

2. the varistor is disposed in a position in the circuit region adjacent to the pad region; 2. The semiconductor device according to claim 1,

3. The varistor is electrically connected to the pad by a wiring pattern.

2. The semiconductor device according to claim 1,

4. the varistor is electrically connected to the pad via a wiring pattern and a resistive element; 2. The semiconductor device according to claim 1,

5. the wiring structure further comprises a second pad region including a second pad; the varistor is disposed between the pad region and the second pad region; 2. The semiconductor device according to claim 1,

6. The varistor has a molybdenum oxide film as a resistive film.

2. The semiconductor device according to claim 1,

7. the varistor has an electrode including a conductive film disposed on a farthest wiring layer among the plurality of wiring layers, the farthest wiring layer from the semiconductor substrate; 2. The semiconductor device according to claim 1,

8. the varistor includes an electrode including a conductive film disposed on each of at least two of the plurality of wiring layers; 2. The semiconductor device according to claim 1,

9. the varistor has a resistive film, a first electrode disposed in a first region of a main surface of the resistive film, and a second electrode disposed in a second region of the main surface of the resistive film, the second region being spaced apart from the first region; 2. The semiconductor device according to claim 1,

10. each of the first electrode and the second electrode includes at least two conductive films arranged in at least two wiring layers among the plurality of wiring layers; 10. The semiconductor device according to claim 9.

11. The varistor further includes a plug electrically connecting the at least two conductive films.

11. The semiconductor device according to claim 10.

12. The at least two conductive films include a first conductive film including a first pattern and a second conductive film including a plurality of second conductive patterns smaller than the first pattern.

12. The semiconductor device according to claim 11.

13. the varistor further includes intermediate films disposed between the resistive film and the first electrode and between the resistive film and the second electrode, 10. The semiconductor device according to claim 9.

14. The varistor includes a first electrode, a resistive film disposed on the first electrode, and a second electrode disposed on the resistive film.

2. The semiconductor device according to claim 1,

15. each of the first electrode and the second electrode includes at least two conductive films arranged in at least two wiring layers among the plurality of wiring layers; 15. The semiconductor device according to claim 14.

16. The varistor further includes a plug electrically connecting the at least two conductive films.

16. The semiconductor device according to claim 15,

17. The at least two conductive films include a first conductive film including a first pattern and a second conductive film including a plurality of second conductive patterns smaller than the first pattern.

17. The semiconductor device according to claim 16.

18. the varistor further includes intermediate films disposed between the resistive film and the first electrode and between the resistive film and the second electrode, 15. The semiconductor device according to claim 14.

19. the circuit region includes a transistor disposed below the varistor; 19. The semiconductor device according to claim 1,

20. 19. An electronic device comprising the semiconductor device according to claim 1.

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