Image sensor integrated circuit with isolation structure and method - Patents.com

Abstract

To provide a method and a device, capable of reducing a loading effect at a crossroad region in an etching process.SOLUTION: A method includes: forming a masking layer on a backside of a substrate 140, the substrate including pixel regions 110a, 110b having photodetectors 82, and transistors 20 positioned on or in a front side of the substrate; forming a mask opening in the masking layer by exposing the masking layer to patterned light, the mask opening including mask pixel regions that mask the pixel regions, and mask protrusion regions that extend from the mask pixel regions toward a mask crossroad region; forming a substrate opening in the substrate by etching the substrate through the mask opening; and forming an isolation structure 165 in the substrate opening.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] The semiconductor integrated circuit (IC) industry is experiencing rapid growth. Technological advances in IC materials and designs have produced multiple generations of ICs, with each generation having smaller and more complex circuits than the previous generation. During the evolution of ICs, feature density (i.e., the number of interconnected devices per chip area) has generally increased while feature size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This miniaturization process generally provides advantages by improving production efficiency and reducing associated costs. Such miniaturization has also increased the complexity of IC processing and manufacturing. Summary of the Invention [Problem to be solved by the invention]

[0002] The etching process that forms the openings is subject to a loading effect in the crossover region, causing the depth of the BDTI structure at the crossover region to be deeper than the depth of the BDTI structure at the walls of the BDTI structure. [Means for solving the problem]

[0003] According to at least one embodiment, a method includes forming a masking layer on a backside of a substrate, the substrate including a pixel region having a light receiving element and a transistor disposed on / within a front side of the substrate; forming a mask opening in the masking layer by exposing the masking layer to patterned light, the mask opening including a mask pixel region masking the pixel region and a mask protrusion region extending from the mask pixel region toward a mask intersection region; forming a substrate opening in the substrate by etching the substrate through the mask opening; and forming an isolation structure in the substrate opening.

[0004] In accordance with at least one embodiment, a device includes a substrate, a photodetector in the substrate, a transistor on or in a first side of the substrate, and an isolation structure in the substrate laterally surrounding the photodetector, the isolation structure including a first wall extending in a first direction and having a first width, a second wall extending in a second direction transverse to the first direction, and a crossover region located in an overlap region of the first wall and the second wall and having a second width narrower than the first width.

[0005] According to at least one embodiment, a method includes forming a light receiving element in a substrate, forming a transistor on a first side of the substrate, and forming a pattern mask on a second side of the substrate, the second side facing away from the first side. The pattern mask includes a wall exposure region. The wall exposure region includes a first wall exposure region having a first width extending in a first direction and a second wall exposure region extending in a second direction transverse to the first direction. The pattern mask further includes a crossover region in an area where the first wall exposure region and the second wall exposure region overlap, the crossover region having a second width less than the first width. The method further includes forming an opening in the substrate by etching through the pattern mask and forming an isolation structure in the opening. Effect of the Invention

[0006] By reducing the dimensions of the cross-way region, the loading effect in the cross-way region is reduced. BDTI improvements, including increased depth uniformity, enable smaller pixel sizes for partial as well as full BDTI structures, which paves the way for image sensor ICs with increased pixel density. [Brief description of the drawings]

[0007] Aspects of the present invention are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, according to standard practice in the industry, various features have not been drawn to scale, and in fact the dimensions of various features illustrated in the accompanying drawings may be arbitrarily expanded or reduced for illustrative clarity. [Figure 1]1A to 1G are schematic side and top cross-sectional views of a portion of an image sensor IC according to an embodiment of the present invention. [Diagram 2] 2A to 2F are schematic side and top cross-sectional views of a cross-section of an image sensor IC according to an embodiment of the present invention. [Diagram 3] 3A-3Q are diagrams of an image sensor IC at various stages of manufacture according to various embodiments. [Figure 4] FIG. 4 is a flow diagram illustrating a method of manufacturing an image sensor IC according to various aspects of the present invention. [Diagram 5] FIG. 5 is an illustration of a lithographic exposure system in accordance with various embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The following embodiments provide many different embodiments or examples for implementing different features of the present invention. To simplify the present invention, specific examples of elements and arrangements are described below. Of course, these are illustrative and not intended to be limiting. For example, a configuration of a first feature above or on a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also be an embodiment in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. In addition, the present invention may repeat symbols in various embodiments. This repetition is for the purpose of simplicity and clarity, and does not itself dictate a relationship between the various embodiments and / or configurations mentioned.

[0009] Additionally, spatially relative terms such as "below," "lower," "upper," "top," and the like may be used to facilitate the description to explain the relationship of one element or feature depicted in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] Terms indicating relative degrees, such as "about," "substantially," and the like, should be interpreted as one of ordinary skill in the art would interpret them in light of current technical norms. Such terms may be process and / or equipment dependent, and should not be interpreted as being more or less restrictive than one of ordinary skill in the art would normally recognize for the technology being described.

[0011] The present invention relates generally to semiconductor devices, and more particularly to image sensor integrated circuits (ICs), such as backside illuminated (BSI) image sensor ICs, that include backside deep trench isolation (BDTI) structures. BDTI structures, which have very high aspect ratios and high uniformity, are useful for electrical isolation in complementary metal oxide semiconductor (CMOS) image sensors and photodetectors.

[0012] The BDTI structure overlaps the floating diffusion node, and the BDTI structure is formed subsequent to the formation of the floating diffusion node such that the floating diffusion node is below the opening in which the BDTI structure is formed. The etching process that forms the opening can suffer from a loading effect in the crossover region, causing the BDTI structure to have a deeper depth at the crossover region than at the walls of the BDTI structure. This effect is exacerbated when the opening is formed using a relatively low etching power. The exacerbated loading effect dramatically reduces isolation performance because the wall depth is reduced to prevent a deep crossover region depth resulting in contact (e.g., breakage) with the floating diffusion node.

[0013] Embodiments of the present invention include an improved optical proximity correction (OPC) process that achieves high aspect ratio and high uniformity BDTI structures. By reducing the dimensions of the crossover regions, loading effects in the crossover regions are reduced. BDTI improvements, including improved depth uniformity, enable smaller pixel sizes for partial as well as full BDTI structures, which paves the way for image sensor ICs with increased pixel density.

[0014] Figure 1A illustrates a side cross-sectional view of an image sensor integrated circuit (IC) 10A according to various embodiments. Figure 1B illustrates a top cross-sectional view of the image sensor IC 10A taken along line BB in Figure 1A.

[0015] Image sensor IC 10A includes a substrate 140 having a plurality of pixel regions 110a, 110b, 110c, 110d, which may be collectively referred to as pixel regions 110a-110d. In some embodiments, pixel regions 110a-110d are arranged in a matrix or grid, as shown in FIG. 1B.

[0016] The pixel regions 110a-110d include respective light receiving elements 82, such as one light receiving element 82 for each pixel region 110a-110d. In some embodiments, the light receiving elements 82 include one or more photodiodes, phototransistors, etc. The light receiving elements 82 convert incident radiation (e.g., photons) into an electrical signal. For example, the light receiving elements 82 generate electron-hole pairs from the incident radiation. In some embodiments, the incident radiation includes a range of one or more wavelengths. For example, the wavelengths may be in the visible spectrum, the infrared spectrum, etc. The electrical signal may be associated with the one or more wavelengths.

[0017] A plurality of transistor gate structures 20 are disposed along a first side (e.g., front side) of the substrate 140. The transistor gate structures 20 may be field effect transistor (FET) gate structures, such as planar FETs, FinFETs, nanostructured FETs, etc. The nanostructured FETs may include nanosheet FETs (NSFETs), nanowire FETs (NWFETs), etc.

[0018] An interconnect structure, which may be a back-end (BEOL) metal stack, is disposed along a first side of the substrate 140. The interconnect structure includes a dielectric structure 130 that surrounds a plurality of conductive interconnect layers 120. In some embodiments, the dielectric structure 130 includes a plurality of stacked interlevel dielectric (ILD) layers. In some embodiments, the plurality of conductive interconnect layers 120 include alternating layers of conductive vias and conductive lines electrically coupled to a plurality of transistor gate structures 20.

[0019] In some embodiments, an isolation structure (e.g., a shallow trench isolation structure, a deep trench isolation structure, an isolation implant, etc.) may be disposed in the substrate 140 at a location between adjacent ones of the plurality of pixel regions 110a-110d. For example, in some embodiments, a shallow trench isolation (STI) structure 160 may be disposed in a first side of the substrate 140 between adjacent ones of the plurality of pixel regions 110a-110d. In some embodiments, a backside deep trench isolation (BDTI) structure 165 may be disposed in a second side opposite the first side of the substrate 140, for example, between adjacent ones of the plurality of pixel regions 110a-110d. In some embodiments, the BDTI structure 165 may be directly above the shallow trench isolation structure 160. In some embodiments, the BDTI structure 165 may overlap the shallow trench isolation structure 160, for example, in a top view. In some embodiments, the BDTI structure 165 may extend completely through the substrate 140, and the shallow trench isolation structure 160 may be omitted. In some embodiments, the BDTI structure 165 is a single interconnect structure, as shown in the top view of FIG. 1B. Similarly, the shallow trench isolation structure 160 may be a single interconnect structure. The BDTI structure 165 and the STI structure 160 may have a grid shape including walls 166 that join or overlap at crossover regions 168. The walls 166 may include vertical walls that extend in a first direction (e.g., the Y-axis direction) and horizontal walls that extend in a second direction (e.g., the X-axis direction). The crossover regions 168 may be regions where the vertical walls and the horizontal walls overlap.

[0020] The second side of the substrate 140 may include a plurality of topographical features 118 disposed within the plurality of pixel regions 110a-110d. The plurality of topographical features 118 (e.g., pyramidal protrusions and / or depressions) include a plurality of inner surfaces of the substrate 140. In some embodiments, one or more dielectric layers 170 are disposed over the second side of the substrate 140, e.g., between the plurality of inner surfaces, if present. In some embodiments, the one or more dielectric layers 170 may include an oxide, a nitride, a carbide, or the like. The angle of the plurality of inner surfaces enhances absorption of radiation by the substrate 140 (e.g., by reducing reflection of radiation from uneven surfaces). The plurality of inner surfaces further serves to reduce the angle of incidence of incident radiation having a steep slope relative to the top of the one or more dielectric layers 170, thereby preventing the incident radiation from reflecting off the substrate 140. In some embodiments, the topographical features 118 are not present, e.g., the top surface of the substrate 140 is substantially coplanar with the top surface of the BDTI structure 165.

[0021] FIG 1C illustrates a cross-sectional side view of image sensor IC 10B according to various embodiments. The cross-sectional side view may be taken, for example, along line CC illustrated in FIG 1D. FIG 1D illustrates a cross-sectional top view of image sensor IC 10B taken along line DD in FIG 1C. Image sensor IC 10B is similar in many respects to image sensor IC 10A illustrated in FIG 1A and 1B, and like numerals refer to like elements or structures. Descriptions of some of the specific elements are omitted for brevity.

[0022] The image sensor IC 10B includes pixel regions 110a-110d. The image sensor IC 10B includes a substrate 140, a light receiving element 82 in the substrate 140, a first etch stop layer 131 along the bottom surface of the substrate 40, a dielectric layer 130 along the bottom surface of the first etch stop layer 131, a second etch stop layer 132 between the dielectric layer 130, and a first metal line 120 disposed in the dielectric layer 130 and the second etch stop layer 132. In some embodiments, the first metal line 120 may be used as a metal reflector. In some embodiments, the image sensor IC 10B includes an interconnect structure (not shown) below the substrate 140, which may be similar to the interconnect structure described with respect to FIG. 1A.

[0023] The pixel isolation structure includes a substrate isolation structure 163 and a dummy contact structure 160. The substrate isolation structure 163 includes an isolation segment 165 (e.g., a BDTI structure 165) that extends vertically through the substrate along the boundaries of the pixel regions 110a-110d. As a result, the isolation segment 165 laterally isolates a first region of the substrate 140 from an adjacent region of the substrate 140 (thus isolating the light receiving element 82 from an adjacent light receiving element 82 (see FIG. 1D) in the adjacent region of the substrate 140). The sidewalls of the isolation segment 165 border the first region of the substrate 140 that includes the light receiving element 82. The substrate isolation structure may be a grid or ring structure, as shown in FIG. 1D. The substrate isolation structure may extend vertically from a top surface of the substrate 140 to a bottom surface below the top surface of the substrate 140.

[0024] The dummy contact structures 160 include segments that extend from the first metal line 120 to respective isolation segments 165 such that the segments laterally separate the first region of the dielectric layer 130 from adjacent regions of the dielectric layer 130. In some embodiments, the pixel isolation structures and the first metal line 120 completely surround the first region of the substrate 140 and the first region of the first dielectric layer 130.

[0025] The pixel isolation structure can reduce the likelihood that a photon entering the pixel region 110a will leave the pixel region 110a and enter an adjacent pixel region (e.g., pixel region 110b or pixel region 110c). The substrate isolation structure reduces the likelihood that a photon will enter an adjacent pixel region at the substrate 140. Furthermore, the dummy contact structure 160 reduces the likelihood that a photon will enter an adjacent pixel region at the first dielectric layer 130. Thus, the pixel isolation structure 120 improves isolation of the pixel (pixel regions 110a-110d) from adjacent pixels. Thus, crosstalk between the pixel (pixel regions 110a-110d) and adjacent pixels is reduced, thereby improving the QE and other performance metrics of the image sensor IC 10B.

[0026] In some embodiments, the substrate isolation structure includes one or more isolation materials, which may include, for example, silicon dioxide, silicon nitride, low-k dielectrics, hafnium oxide, aluminum oxide, high-k dielectrics, tungsten, aluminum, other suitable materials, or combinations of the above. In some embodiments, the substrate isolation structure has a refractive index less than that of the substrate 140 to provide optical isolation via total internal reflection.

[0027] In some embodiments, the dummy contact structures 160 include a first metal material. The first metal material may include, for example, tungsten, copper, titanium, other suitable metals, or combinations thereof. The dummy contact structures 160 may have a width greater than the BDTI structures 165 at the interface between the dummy contact structures 160 and the BDTI structures 165 (e.g., along the top surface of the dummy contact structures 160). Furthermore, the dummy contact structures 160 may have a height less than the height of the BDTI structures 165. Furthermore, the dummy contact structures 160 may have other surface shapes (e.g., faceted or spherical shapes). It should be understood that the STI structures 160 illustrated in FIG. 1A are different from the dummy contact structures 160 illustrated in FIG. 1C. For example, the STI structures 160 may be formed in the substrate 140 and may be formed of a dielectric material such as silicon dioxide, and the dummy contact structures 160 may be formed on the substrate 140, in the dielectric layer 130 and the first etch stop layer 131 and may be formed of a first metal material. In some embodiments, both the STI structures 160 and the dummy contact structures 160 are present.

[0028] In some embodiments, image sensor IC 10B is a complementary metal-oxide semiconductor (CMOS) image sensor, etc. In some embodiments, substrate 140 may include a semiconductor material, such as, for example, silicon, etc.

[0029] In some embodiments, the dielectric layer 130 may include, for example, silicon dioxide, silicon nitride, a low-k dielectric, other suitable dielectric material, or a combination of the above. The first etch stop layer 131 and the second etch stop layer 132 may include, for example, silicon nitride, silicon carbide, silicon carbonitride, other suitable dielectric material, or a combination of the above.

[0030] In some embodiments, the first metal line 120 comprises a second metallic material, which may include, for example, copper, aluminum copper, tungsten, other suitable metals, or combinations thereof.

[0031] The light receiving element 82 may include a first doped semiconductor region and a surrounding region of the substrate 140. The first doped semiconductor region may form a pn junction with the surrounding region of the substrate 140.

[0032] The pixel transistor 20, including the gate, may be provided along a front side of the substrate 140, and a floating diffusion (FD) region 84 may be provided within the substrate 140 along the front side of the substrate. A first contact 122 may extend through the dielectric layer 130 to the first metal line 120, electrically coupling the pixel transistor 20 and / or the FD region 84 to the first metal line 120 or other suitable metal line. A buffer layer 167 may be provided on the back side of the substrate 140 and may extend above the photosensitive element 82.

[0033] A color filter 180 may be provided on the back side of the substrate 140 and above the light receiving elements 82. A composite metal grid (CMG) 195 may be provided on the back side of the substrate 140 above the isolation segments 165 and the dummy contact structures 160 along the border of the pixel region 110a. The CMG 195 includes a metal grid 194 and a dielectric grid layer 196 above the metal grid layer 194. The color filter 180 may be provided between the sidewalls of the CMG 195. A microlens 182 may be provided on the back side of the substrate 140 above the color filter 180, i.e., above the light receiving elements 82. Photons may enter the image sensor IC 10B through the microlens 182. Thus, photons enter the substrate 140 through the back side of the substrate 140, making the image sensor "back-illuminated".

[0034] In some embodiments, pixel transistor 20 may include, for example, a transfer transistor, a source follower transistor, a row select transistor, a reset transistor, another pixel transistor, or other transistor.

[0035] In some embodiments, the FD region 84 and the first doped semiconductor region 82 may include, for example, doped silicon.

[0036] In some embodiments, the first contact 122 may include, for example, tungsten, copper, titanium, other suitable metals, or combinations of the above.

[0037] In some embodiments, buffer region 167 may include, for example, silicon dioxide, silicon nitride, other suitable dielectric materials, or combinations of the above.

[0038] In some embodiments, the metal grid layer 194 may comprise, for example, tungsten, copper, other suitable metals, or combinations of the above. In some embodiments, the dielectric grid layer 196 may comprise, for example, silicon dioxide, silicon nitride, other suitable dielectrics, or combinations of the above.

[0039] It should be understood that the buffer layer 167, the color filter 180, the CMG 195, and the microlens 182 may be included in the image sensor IC 10A shown in FIG. 1A. For example, the buffer layer 167, the color filter 180, the CMG 195, and the microlens 182 may cover one or more dielectric layers 170 of the image sensor IC 10A. In some embodiments, the buffer layer 167 is one or more of the dielectric layers 170.

[0040] FIGURE 1E illustrates a side cross-sectional view of image sensor IC 10C according to various embodiments. The view in FIGURE 1E is taken along line EE in FIGURE 1F. FIGURE 1F illustrates a top cross-sectional view of image sensor IC 10C along section line FF in FIGURE 1E. Image sensor IC 10C is similar in many respects to image sensors ICs 10A and 10B, and like numbers represent like elements. Descriptions of some of the specific elements are omitted for brevity.

[0041] The image sensor IC 10C includes an interconnect structure 120 disposed along a front surface of a substrate 140. In some embodiments, the substrate 140 may include a semiconductor body (e.g., bulk silicon) and have a first doping type (e.g., p-type doping). The light receiving element 82 is disposed within the substrate 140 and configured to convert incident electromagnetic radiation (e.g., photons) into an electrical signal. The light receiving element 82 has a second doping type (e.g., n-type doping) different (e.g., opposite) from the first doping type. In some embodiments, the first doping type is n-type and the second doping type is p-type, or vice versa. The floating diffusion node 84 is disposed along a front surface of the substrate 140 and has a second doping type (e.g., n-type).

[0042] The vertical transfer transistor 20 and the dummy vertical transistor structure 20d are disposed along the front surface of the substrate 140. The vertical transfer transistor 20 and the dummy vertical transistor structure 20d may include a vertical gate electrode 290, a vertical gate dielectric layer 600, and a sidewall spacer structure 41. The vertical gate electrode 290 includes a conductor and a buried conductive structure extending from the conductor into the substrate 140. The buried conductive structure may extend from the front surface of the substrate 140 to a point vertically above the front surface. The vertical gate dielectric layer 600 surrounds the buried conductive structure and is configured to electrically isolate the vertical gate electrode 290 from the substrate 140. The sidewall spacer structure 41 may continuously surround an outer wall of the vertical gate electrode 290. In some embodiments, the vertical gate electrode 290 is a single continuous material, and the conductor and the buried conductive structure comprise the same material. The same material may be or include a conductive material such as, for example, intrinsic polysilicon, aluminum, titanium, tungsten, combinations of the above, and the like.

[0043] The interconnect structure 120 extends along the front surface of the substrate 140 and is configured to electrically couple the doped regions (e.g., the floating diffusion node 84, the photodetector element 82) and the pixel elements (e.g., the vertical transfer transistor 20) of the substrate 140 to one another. The interconnect structure 120 includes an interconnect dielectric structure 130, a plurality of conductive lines, and a plurality of conductive vias. The conductive vias may directly contact the bottom surface of the vertical gate electrode 290 of the vertical transfer transistor 20 such that the vertical transfer transistor 20 is electrically coupled to other conductive structures and / or layers (e.g., the conductive line 106) provided within the interconnect dielectric structure 130. The interconnect dielectric structure 130 extends continuously across the entire bottom surface of the vertical gate electrode 290 of the dummy vertical transistor structure 20d such that the dummy vertical transistor structure 20d is electrically isolated from the conductive structures and / or layers provided within the interconnect dielectric structure 130.

[0044] A deep trench isolation (DTI) structure 165 (e.g., BDTI structure 165) extends through the backside surface of the substrate 140 to a point below the backside surface. In some embodiments, the DTI structure 165 is disposed in a peripheral region of the image sensor IC 10C that laterally surrounds the light receiving element 82. The light receiving element 82 is disposed between inner walls of the DTI structure 165. The DTI structure 165 is configured to electrically isolate the light receiving element 82 from other semiconductor devices (e.g., other light receiving elements (not shown)) disposed in / on the substrate 140. The DTI structure 165 can optically isolate the light receiving element 82 from adjacent light receiving elements 82.

[0045] An upper dielectric structure 165 is provided above the backside surface of the substrate 140. A grid structure 195 covers the upper dielectric structure 165. The grid structure 195 may include, for example, a metal grid structure, a dielectric grid structure, or both. The grid structure 195 is configured to guide incident electromagnetic radiation to the underlying light receiving elements 82. In some embodiments, when the grid structure 195 includes a metal grid structure (e.g., aluminum, copper, tungsten, or a combination thereof), the incident electromagnetic radiation can be reflected from the sidewall of the metal grid structure to the underlying light receiving elements 82 (see FIG. 1F) instead of traveling to the adjacent light receiving elements. In such an embodiment, the grid structure 195 can reduce crosstalk between adjacent light receiving elements 82. The grid structure 195 surrounds the color filter 180. The color filter 180 covers the light receiving elements 82 and is configured to pass a first range of frequencies of the incident electromagnetic radiation while blocking a second range of frequencies of the incident electromagnetic radiation. The first range of frequencies is different from the second range of frequencies.

[0046] In some embodiments, when incident electromagnetic radiation strikes the backside surface of the substrate 140, the incident electromagnetic radiation may travel through the light receiving element 82 towards the front side surface of the substrate. A portion of the incident electromagnetic radiation may travel through the thickness of the light receiving element 82 towards the peripheral region. The incident electromagnetic radiation may then bounce and / or reflect off the vertical gate electrode 290 of the dummy vertical transistor structure 20d towards the front side surface of the substrate 140. Furthermore, the incident electromagnetic radiation may bounce and / or reflect off conductive layers or structures (e.g., conductive lines and / or conductive vias) provided within the interconnect structure 120. In addition, after reflecting off conductive structures or layers within the interconnect structure 120, the incident electromagnetic radiation may strike and / or be absorbed by the light receiving element 82. Thus, the dummy vertical transistor structure 20d is configured to redirect the incident electromagnetic radiation towards the interconnect structure 120 and / or towards the light receiving element 82 and away from the peripheral region of the image sensor IC 10C. This prevents incident electromagnetic radiation from crossing the peripheral region to other photodetectors disposed within substrate 140 and adjacent to photodetector 82 (e.g., photodetector 82 in pixel region 110b or pixel region 110c), thereby reducing crosstalk between adjacent photodetectors and increasing the sensitivity of photodetector 82.

[0047] The plurality of light receiving elements 82 may be in the substrate 140 at a point below the front surface of the substrate 140 and have a second doping type opposite to the first doping type (e.g., n-type doping). The plurality of light receiving elements 82 are disposed around a floating diffusion node 84, as shown in FIG. 1F. In some embodiments, a depletion region is formed in and / or around each light receiving element 82 (e.g., due to a pn junction between the light receiving element 82 and a p-type region of the substrate 140 that surrounds the light receiving element 82). The floating diffusion node 84 has the second doping type at a higher doping concentration than the substrate 140.

[0048] In some embodiments, as shown in FIG. 1E, the BDTI structure 165 overlaps the floating diffusion node 84 in a top view, for example, at the crossover region 168 (see FIG. 1F). The BDTI structure 165 is formed subsequent to the floating diffusion node 84 such that the floating diffusion node 84 is below the opening in which the BDTI structure 165 is formed. The etching process that forms the opening experiences a loading effect at the crossover region 168, causing the BDTI structure to be deeper at the crossover region 168 than at the walls 166. This effect is exacerbated when the opening is formed using a relatively low etching power. The exacerbated loading effect dramatically reduces isolation performance, as the depth of the walls 166 is reduced to prevent the depth of the deep crossover region 168 from contacting (e.g., breaking) the floating diffusion node 84.

[0049] 1G is a side cross-sectional view of an image sensor IC 10D according to various embodiments. Image sensor IC 10D is similar in many respects to image sensors ICs 10A, 10B, and 10C, and like numbers refer to like elements.

[0050] Dimensions H1, H2, H3, W3, W4, and W5 of BDTI structure 165 are depicted in FIG. 1G. As shown, BDTI structure 165 includes first, second, and third segments having first, second, and third heights H1, H2, and H3 along a vertical direction (e.g., Z-axis direction), respectively. The first segment overlaps floating diffusion node 84. The third segment is between the first segment and floating diffusion node 84. The second segment is between the first segment and third segment. The third segment may have a width W3, the second segment may taper from width W3 to width W5, and the first segment may taper from width W5 to width W4. For example, the first segment may have sidewalls that taper outwardly as the distance from floating diffusion node 84 decreases, and the second segment may have sidewalls that taper inwardly as the distance from floating diffusion node 84 decreases. In some embodiments, width W4 is less than width W5 and greater than width W3. Width W4 is related to the distance between protrusions 140P of substrate 140 (e.g., one of diagonal distances D168B, D168C) on the top surface of substrate 140 in crossover region 168 (see FIG. 1F).

[0051] 2A-2F depict cross-road region 168 of BDTI structure 165 according to various embodiments. Figure 2A is a top view of region 200A that includes cross-road region 168. Figure 2B is a side cross-sectional view of cross-road region 168 that includes region 200A.

[0052] In FIG. 2A, as shown, the wall 166 has a width D166A and the crossway region 168 has a width D168A. The width D168A is the distance between diagonally opposite sidewalls of the BDTI structure 165 in the crossway region 168. The width D168A is wider than the width D166A. In the region 200A shown in FIG. 2A, the ratio of the width D168A to the width D166A is greater than 1.414, such as 2 or greater. The BDTI structure 165 shown in FIG. 2A is formed without using the OPC technique described with respect to FIGS. 3E-3I. The substrate 140 has a corner region 140C that abuts the crossway region 168. In the region 200A, the corner region 140C has a smoothly rounded contour as shown and is substantially free of the protrusions 140P present in the regions 200B, 200C shown in FIGS. 2C and 2E.

[0053] 2B, wall 166 has a height H166A and crossover region 168 has a height H168A. Height LE is the difference between height H166A and height H168A. As shown, height H168A may not be uniform across BDTI structure 165 and height H166A may not be uniform across BDTI structure 165. The loading effect is height LE relative to height H168A. In region 200A, the loading effect is greater than about 30%.

[0054] In FIG. 2C, BDTI structure 165 in region 200B is formed using the OPC technique described with respect to FIGS. 3E-3I. In region 200B, as shown, wall 166 has width D166B, crossway region 168 has diagonal width D168B, and crossway region 168 has lateral width D169B. Diagonal width D168B is the distance between diagonally opposed sidewalls of BDTI structure 165 in crossway region 168. Lateral width D169B is the width (e.g., in the X-axis direction) between protrusions 140P in crossway region 168. FIG. 2B includes dashed line 210 outlining corner region 140C for illustrative purposes. Diagonal width D168B is greater than width D166B and lateral width D169B. The diagonal width F168B is reduced relative to the width D168A of the region 200A in FIG. 2A due to the presence of the protrusion 140P. In the region 200B, the ratio of the diagonal width D168B to the width D166B is less than 1.414. The ratio of the lateral width D169B to the width D166B is less than 1. The BDTI structure 165 shown in FIG. 2B is formed using one or more of the OPC techniques described with respect to FIGS. 3E-3I. The protrusion 140P of the substrate 140 abuts the crossover region 168. In the region 200B, as shown, the protrusion 140P has a sharper curved profile than the corner region 140C. For example, the radius of curvature of the protrusion 140P is less than the radius of curvature of the corner region 140C.

[0055] In FIG. 2D, the wall 166 has a height H166B and the crossover region 168 has a height H168B. The height LE' in FIG. 2D is the difference between the height H166B and the height H168B. As shown, the height H168B may not be uniform across the BDTI structure 165 and the height H166B may not be uniform across the BDTI structure 165. The loading effect is the height LE' relative to the height H168B. The height LE' is less than the height LE due to the protrusion 140P, which increases the uniformity of the etch between the crossover region 168 and the wall 166. In the region 200B, the loading effect is less than 30%, such as less than about 20%.

[0056] In FIG. 2E, BDTI structures 165 in region 200C are formed using the OPC technique described with respect to FIGS. 3E-3I. In region 200C, as shown, walls 166 have width D166C, crossroad region 168 has diagonal width D168C, and crossroad region 168 has lateral width D169C. Diagonal width D168C is the distance between diagonally opposed sidewalls of BDTI structure 165 in crossroad region 168. Lateral width D169C is the width (e.g., in the X-axis direction) between protrusions 140P in crossroad region 168. FIG. 2C includes dashed line 210 outlining corner region 140C for illustrative purposes, and dashed line 220 outlining protrusion 140P in region 200B for illustrative purposes. Diagonal width D168C is greater than width D166C and lateral width D169C. The diagonal width D168C is reduced relative to the widths D168A, D168B of the regions 200A, 200B in Figures 2A, 2B due to the presence of the protrusions 140P. In the region 200C, the ratio of the diagonal width D168C to the width D166C is less than 1.414, such as less than about 1.2. The ratio of the lateral width D169C to the width D166C is less than 1, such as less than about 0.8. The BDTI structure 165 shown in Figure 2C is formed using one or more of the OPC techniques described with respect to Figures 3E-3I. The protrusions 140P of the substrate 140 abut the crossover region 168. In the region 200C, the protrusions 140P have a sharper curvature profile than the protrusions 140P in the corner region 140C and in the region 200B. For example, the radius of curvature of the protrusion 140P in region 200C is less than the radius of curvature of the corner region 140C, and is less than the radius of curvature of the protrusion 140P in region 200B.

[0057] In FIG. 2F, wall 166 has height H166C and crossover region 168 has height H168C. ​​Height LE″ in FIG. 2F is the difference between height H166C and height H168C. ​​As shown, height H168C may not be uniform across BDTI structure 165 and height H166C may not be uniform across BDTI structure 165. The loading effect is height LE″ relative to height H168C. ​​Height LE″ is less than height LE and less than height LE′ due to protrusion 140P, which enhances the etch uniformity between crossover region 168 and wall 166. In region 200C, the loading effect is less than 30%, such as about 18% or about 20%.

[0058] In the embodiment shown in FIGS. 2C-2E, the "diagonal ratio" equal to the diagonal width D168B divided by the width D166B (or equal to the diagonal width D168C divided by the width D166C) may be in the range of about 0.5-1.414. When the diagonal ratio is less than about 0.5, the risk of the protrusions 140P merging in the intersection region 168 is insufficient. When the diagonal ratio is greater than 1.414, the loading effect of the BDTI structure 165 is insufficient. The "lateral ratio" equal to the lateral width D169B divided by the width D166B (or equal to the lateral width D169C divided by the width D166C) may be in the range of about 0.3-1. When the lateral ratio is less than about 0.3, the risk of the protrusions 140P merging in the intersection region 168 is insufficient. When the lateral ratio is greater than 1, the loading effect of the BDTI structure 165 is insufficient.

[0059] FIG. 4 depicts a flow diagram of a method 1000 for forming an IC device (e.g., an image sensor IC of FIGS. 10A, 10B, 10C) or a portion thereof from a workpiece in accordance with one or more aspects of the present invention. Method 1000 is merely exemplary and is not intended to limit the present invention to those explicitly depicted in method 1000. Additional acts may be provided before, during, or after method 1000, and some acts described may be replaced, omitted, or moved in additional embodiments of the method. For the sake of brevity, not all of the acts described herein will be described in detail. Method 1000 will be described below in conjunction with fragmentary perspective and / or cross-sectional views of a workpiece shown in FIGS. 3A-3P at different stages of fabrication according to an embodiment of method 1000. For the avoidance of doubt, throughout the figures, the X-direction is perpendicular to the Y-direction, and the Z-direction is perpendicular to both the X-direction and the Y-direction. It is noted that since the workpiece may be fabricated into a semiconductor device, the workpiece may be referred to as a semiconductor device when the context requires.

[0060] 3A-3P are diagrams of intermediate stages in the manufacture of an image sensor IC according to some embodiments.

[0061] In Figure 3A, a substrate 140 is provided, corresponding to operation 1100 of Figure 4. Substrate 140 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped or undoped (e.g., with p-type or n-type dopants). The semiconductor material of substrate 140 may include silicon, germanium, or compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium arsenide, and / or indium antimonide, or alloy semiconductors including silicon germanium, gallium arsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide, or combinations thereof. Other substrates, such as single layer, multilayer, and gradient substrates, may be used.

[0062] 3A, in some embodiments, a photodetector 82 is formed in the substrate 140. The photodetector 82 may include a first doped semiconductor region. The doping type of the first doped semiconductor region may be opposite to the doping type of the substrate 140, with the two together forming a pn junction (e.g., a photodiode). A floating diffusion (FD) region 84 may also be formed in the substrate 140. In some embodiments, the first doped semiconductor region and the FD region 84 are formed in the substrate 140 by ion implantation or other suitable process. In some embodiments, the substrate 140 may be provided with the photodetector 82, the floating diffusion region 84, or both already formed.

[0063] 3B, following the formation of the light-receiving element 82 and the floating diffusion region 84, the pixel transistor 20 may be formed on the top surface of the substrate 140. The pixel transistor 20 may overlap the light-receiving element 82. In some embodiments, the pixel transistor 20 overlaps the light-receiving element 82 and the floating diffusion region 84.

[0064] In FIG. 3C, following the formation of the pixel transistor 20, the interconnect structure 120 is formed above the top surface of the substrate 140. The interconnect structure 120 includes an interconnect dielectric structure 130, a plurality of conductive lines 121, and a plurality of conductive vias 123. In some embodiments, the interconnect dielectric structure 130 may be or include, for example, an oxide (e.g., silicon dioxide), a nitride, a low-k dielectric, other suitable dielectric material, etc. The interconnect dielectric structure 130 may be formed by CVD, PVD, ALD, or other suitable deposition process. The plurality of conductive lines 121 and / or the plurality of conductive vias 123 may be formed by a single damascene process or a dual damascene process. The plurality of conductive lines and conductive vias 121, 123 may be or include, for example, aluminum, copper, tungsten, titanium nitride, combinations thereof, etc.

[0065] 3D-3N, following the formation of interconnect structure 120, BDTI structure 165 is formed, corresponding to acts 1200-1500 of FIG.

[0066] As depicted in Figure 3D, the structure of Figure 3C is inverted and a patterning process is performed in the backside surface of the substrate 140. In some embodiments, the patterning process includes forming a masking layer 300 over the backside surface of the substrate 140 (e.g., operation 1200) and exposing the masking layer 300 to a lithography process, such as an extreme ultraviolet (EUV) process, a deep ultraviolet (DUV) process, etc., which may be performed by a lithography system, such as the lithography exposure system 2000 depicted in Figure 5. In the lithography process, the masking layer 300 is exposed to light 400 (e.g., EUV light, DUV light, etc.) having a pattern including OPCs, such as the pattern 500 depicted in Figure 3E, the pattern 500A depicted in Figure 3F, the pattern 500B depicted in Figure 3G, the pattern 500C depicted in Figure 3H, the pattern 500D depicted in Figure 3I, etc. (e.g., operation 1300). In some embodiments, the patterns 500, 500A, 500B, 500C, or 500D are part of a mask 700 of a lithographic exposure system, such as mask 2018 of lithographic exposure system 2000 (see FIG. 5). Mask 700 may be a photomask or a reticle, which may be reflective. Light 400 may be reflected by mask 700 towards masking layer 300 based on the patterns 500, 500A, 500B, 500C, or 500D. Following exposure to light 400 with patterns 500, 500A, 500B, 500C, or 500D, exposed or unexposed areas of masking layer 300 may be removed to form openings 35 (see FIG. 3J) exposing substrate 140.

[0067] 3E illustrates a pattern 500 including an OPC region 530 for exposing the masking layer 300 to light 400. The pattern 500 includes a protection region and an exposure region. The protection region includes four or more protection regions 510a, 510b, 510c, 510d, which may be collectively referred to as pixel protection regions 510a-510d. The pixel protection regions 510a-510d correspond to the pixel regions 110a-110d. The exposure region includes a wall exposure region 566 and a crossroads exposure region 568. The wall exposure region 566 corresponds, for example, to the wall 166 of FIG. 2C, and the crossroads exposure region corresponds, for example, to the crossroads region 168 of FIG. 2C.

[0068] The pixel protection regions 510a-510d are associated with the pixel regions 110a-110d, respectively. For example, the pixel protection regions 510a-510d may be configured to reflect or absorb a portion of the light 400 reflected onto a first region of the masking layer 300 that substantially directly covers the pixel regions 110a-110d, which first region of the masking layer 300 remains after the formation of the opening 35 in FIG. 3J. The pixel protection regions 510a-510d include a primary region 520 and an OPC region 530. The OPC region 530 may be referred to as a protrusion region 530. In the example shown in FIG. 3E, the OPC region 530 may be referred to as a triangular lobe region 530. Although depicted as separate elements in FIG. 3E, the triangular lobe region 530 and the primary region 520 generally exist as a single, continuous region with no visible interface between them. The triangular lobe regions 530 have a triangular shape and extend toward the center of the cross-way exposure region 568. The triangular lobe regions 530 are located in the corner regions of the main region 520.

[0069] The wall exposure region 566 is between adjacent pairs of pixel protection regions 510a-510d, such as pixel protection region 510a and pixel protection region 510c, labeled in Figure 3E. The crossroads exposure region 568 is between groups of four adjacent pixel protection regions, such as pixel protection regions 510a-510d. The exposure regions, including the wall exposure region 566 and the crossroads exposure region 568, may be configured to reflect or absorb a portion of the light 400 reflected onto a second region of the masking layer 300 that substantially directly covers the wall 166 and the crossroads region 168, respectively, which second region of the masking layer 300 is removed by the formation of the opening 35 in Figure 3J.

[0070] FIG. 3F is a diagram of a pattern 500A of a mask 700 according to various embodiments. The pattern 500A is similar in many respects to the pattern 500 of FIG. 3E, and the corresponding description of its elements is provided above with respect to FIG. 3E. The pattern 500A includes a square protrusion region 530A having a square shape. The square protrusion region 530A extends toward the center of the cross-way exposure region 568 and is located in a corner region of the main region 520. As shown in FIG. 3F, the square protrusion region 530A includes a first dimension W1 and a second dimension W2. The first dimension W1 is the dimension of the overlap of the main region 520 and the square protrusion region 530A. The second dimension W2 is the dimension of the extension of the square protrusion region 530A beyond the main region 520. The protrusion ratio is the ratio of the second dimension W2 to the first dimension W1. For the same square-shaped area of ​​the square protrusion region 530A, an increase in the protrusion ratio (W2÷W1) results in a decrease in the loading effect. For example, as shown in FIGS. 2A, 2C, and 2E, the protrusion ratio used to form the BDTI structure 165 in FIG. 2A is less than the protrusion ratio used to form the BDTI structure 165 in FIG. 2C, and the protrusion ratio used to form the BDTI structure 165 in FIG. 2C is less than the protrusion ratio used to form the BDTI structure 165 in FIG. 2E. As a result, the loading effect of the BDTI structure 165 shown in FIG. 2A is greater than the loading effect of the BDTI structure 165 shown in FIG. 2C, and the loading effect of the BDTI structure 165 shown in FIG. 2C is greater than the loading effect of the BDTI structure 165 shown in FIG. 2E. In some embodiments, the protrusion ratio is in the range of about 1.0 to about 10.

[0071] 3G is a diagram of a pattern 500B of a mask 700 according to various embodiments. Pattern 500B is similar in many respects to patterns 500, 500A, and corresponding descriptions of its elements are provided above with respect to FIGURES 3E and 3F. Pattern 500B includes a circular protrusion region 530B having a circular shape.

[0072] FIG. 3H is a diagram of a pattern 500C of a mask 700 according to various embodiments. Pattern 500C is similar in many respects to patterns 500, 500A, 500B, and corresponding descriptions of its elements are provided above with respect to FIGS. 3E, 3F, 3G. Pattern 500C includes rectangular protrusion regions 530C having a rectangular shape. In some embodiments, the rectangular shape has a length dimension that is longer than its width dimension. In some embodiments, the rectangular protrusion regions 530C all have the same orientation, with their long sides extending along the X-axis direction, as shown in FIG. 3H. In some embodiments, some of the rectangular protrusion regions 530C may extend in a first direction (e.g., the X-axis direction) and other rectangular protrusion regions 530C may extend in a second direction (e.g., the Y-axis direction) that is transverse to the first direction. In some embodiments, one or more of the rectangular protrusion regions 530C are oriented with an angular offset relative to the extension direction of the wall exposure region 566 (e.g., an angular offset relative to the X-axis direction or the Y-axis direction). The angular offset may be greater than 0° and less than 90°.

[0073] FIG. 3I is a diagram of a pattern 500D of a mask 700 according to various embodiments. Pattern 500D is similar in many respects to patterns 500, 500A, 500B, 500C, and corresponding descriptions of its elements are provided above with respect to FIGS. 3E, 3F, 3G, 3H. Pattern 500D includes N-sided overhanging regions 530D having an N-sided shape, where "N" is an integer equal to or greater than 5. In the example shown in FIG. 3I, "N" is equal to 6, and N-sided overhanging regions 530D are hexagonal. In some embodiments, the N-sided shape is substantially regular, the interior angles of the N-sided shape are all the same, and the lengths of the sides of the N-sided shape are all the same. In some embodiments, the hexagonal shape may be irregular, such that one or more of the N-sided angles or N-sided angles are different from the other N-sided angles or N-sided angles, respectively. In some embodiments, the N-sided overhanging regions 530D may all have the same orientation as shown in FIG. 3I. In some embodiments, some of the N-sided overhang regions 530D may be oriented in a first direction (e.g., an X-axis direction) and other N-sided overhang regions 530D may be oriented in a second direction transverse to the first direction (e.g., a Y-axis direction). In some embodiments, one or more of the N-sided overhang regions 530D are oriented with an angular offset relative to the extension direction of the wall exposure region 566 (e.g., an angular offset relative to the X-axis direction or the Y-axis direction). The angular offset may be greater than 0° and less than 90°.

[0074] In Figures 3J and 3K, following exposure to light 400 having patterns 500, 500A, 500B, 500C, 500D as shown in Figures 3D-3I, exposed or unexposed areas of masking layer 300 may be removed to form openings 35 exposing substrate 140. Openings 35 in masking layer 300 include wall exposure regions 366M and mask cross-road regions 368M. Wall exposure regions 366M may include parallel wall exposure regions and vertical wall exposure regions. Wall exposure regions 366M may have a width D366M. Masking layer 300 may include mask protrusion regions 300P. Mask protrusion regions 300P extend beyond mask pixel regions 310 into mask cross-road regions 368M. The mask protrusion regions 300P may be separated by a diagonal distance D368M and by a lateral distance D369M, as shown in Figure 3K. The mask crossover regions 368M may be associated with (e.g., substantially overlap in a top view) the crossover regions 168 of the BDTI structures 165. The protrusions of the mask protrusion regions 300P are conceptually illustrated in Figure 3K as portions of the masking layer 300 that extend beyond the dashed line 320, which corresponds to, for example, the simulated or intended location of the mask pixel regions 310.

[0075] In Figures 3L and 3M, following the formation of the opening 35, an opening 365 is formed in the area of ​​the substrate 140 exposed by the opening 35 in the masking layer 300, corresponding to operation 1400 in Figure 4. The opening 365 may be formed by exposing the unmasked area of ​​the substrate 140 to one or more etchants. As shown in Figure 3L, the opening 365 extends from the top surface (relative to the page of Figure 3L) of the substrate 140 to a level above the top surface of the floating diffusion region 84 and has a height H4. As shown in Figure 3M, the opening 365 includes a wall opening 366 and a crossover opening 368. The wall opening 366 has a width D366. As shown in Figure 3M, there is a lateral distance D369 between adjacent protruding regions 140P of the substrate 140. As shown, there is a diagonal distance D368 between the protruding regions 140P diagonally opposite each other. As shown in FIG. 3L, the sidewalls of the opening 35 may be tapered, for example narrowing (e.g., in the −Z direction) toward the floating diffusion region 84. In some embodiments, the aspect ratio of the opening 35 may be in the range of about 10 to about 100. In some embodiments, the aspect ratio of the opening 35 is greater than 100. The aspect ratio may be the ratio of the height H4 to the diagonal distance D368. The aspect ratio may be the ratio of the height H4 to the width D366. In some embodiments, the height H4 may be in the range of about 2 to about 4 micrometers or greater than about 4 micrometers. Following the formation of the opening 365, a removal process may be performed to remove the masking layer 300. In some embodiments, the opening 365 is a single opening, for example, in the shape of a grid.

[0076] 3N and 3O, BDTI structure 165 is formed in substrate 140, thereby filling (e.g., completely filling or partially filling) opening 365 of FIGS. 3L and 3M, corresponding to operation 1500 of FIG. 4. In some embodiments, BDTI structure 165 may be or include an oxide, such as, for example, silicon dioxide, other suitable oxides, or the like. In some embodiments, BDTI structure 165 is formed by a chemical vapor deposition (CVD) process, an atomic vapor deposition (ALD) process, or other suitable process. After depositing BDTI structure 165 by an ALD process, an optional planarization process (e.g., chemical mechanical polishing (CMP)) may be performed to remove excess material of BDTI structure 165 overlying substrate 140. In such embodiments, BDTI structure 165 has a substantially planar upper surface. In some embodiments, the CMP process removes portions of the excess material while leaving a layer of material above substrate 140, the layer having a substantially planar upper surface. In some embodiments, the BDTI structure 165 extends from the top surface of the substrate 140 to a point that is a height H4 below the top surface. In some embodiments, the height H4 may be in a range of about 2 micrometers to about 4 micrometers or greater than about 4 micrometers. The substrate 140 may have a thickness (e.g., in the Z-axis direction) that is in a range of about 3 micrometers to about 5 micrometers. In some embodiments, the aspect ratio of the BDTI structure 165 may be in a range of about 10 to about 100. In some embodiments, the aspect ratio of the BDTI structure 165 may be greater than 100. The aspect ratio may be the ratio of the height H4 to the diagonal distance D168. The aspect ratio may be the ratio of the height H4 to the width D166.

[0077] 3P, following the formation of BDTI structure 165, buffer layer 167, which may be a dielectric layer, is formed over an upper surface of BDTI structure 165. Buffer layer 167 may be formed by, for example, CVD, PVD, ALD, thermal oxidation, or other suitable growth or deposition process. Buffer layer 167 may be or include an oxide, such as silicon dioxide, or other suitable dielectric material. In some embodiments, after depositing buffer layer 167, a planarization process (e.g., CMP) is performed on buffer layer 167 such that buffer layer 167 has a substantially planar upper surface.

[0078] In FIG. 3Q, color filters 180 and microlenses are formed over the light receiving elements 82, corresponding to operation 1600 of FIG. 4. Following formation of the buffer layer 167, a grid structure 195 and color filters 180 are formed over the buffer layer 167. In some embodiments, the grid structure 195 may include a first grid layer 194 extending over a top surface of the buffer layer 167 and a second grid layer 196 covering the first grid layer 194. The first grid layer 194, the second grid layer 196, or both, may be or include a dielectric material, a conductive material, or both. In some embodiments, the first and second grid layers 194, 196 may be formed by CVD, PVD, ALD, sputtering, electroless plating, or other suitable growth or deposition processes.

[0079] Following deposition of the first and second grid layers 194, 196, a patterning process may be performed on the first and second grid layers 194, 196 to form color filter openings. A color filter 180 may then be formed in the color filter openings, with the grid structure 195 continuously surrounding the color filter 180. In some embodiments, the color filter 180 may be formed by forming various color filter layers and patterning the color filter layers. The color filter layers are formed of materials that transmit incident radiation (e.g., light) having a selected wavelength range while blocking light of wavelengths outside the selected wavelength range. In some embodiments, the color filter layers may be planarized (e.g., via CMP) following formation.

[0080] 3Q, a plurality of microlenses 182 are formed above the substrate 140. In some embodiments, the microlenses 182 may be formed by depositing (e.g., by a spin-on or evaporation process) a microlens material above the substrate 140. A microlens template (not shown) having a curved top surface is patterned above the microlens material. The microlenses 182 are then formed by selectively etching the microlens material based on the microlens template.

[0081] FIG. 5 is a schematic diagram of a lithography exposure system 2000 used to perform operation 1300 of FIG. 4 according to some embodiments. In some embodiments, the lithography exposure system 2000 is an extreme ultraviolet (EUV) lithography system designed to expose a resist layer, such as the masking layer 300 shown in FIG. 3D, to EUV radiation, and may be referred to as an EUV system 2000. The lithography exposure system 2000 may be an EUV scanner. The lithography exposure system 2000 includes a light source 2120, an illuminator 2140, a mask stage 2016, a projection optics module (or projection optics box (POB)) 2130, and a substrate stage 2024 according to some embodiments. Components of the lithography exposure system 2000 may be added or omitted, and the invention should not be limited by the embodiments.

[0082] The light source 2120, in certain embodiments, is configured to generate optical radiation having a wavelength in a range between about 1 nm and about 100 nm. In one particular example, the light source 2120 generates EUV radiation at a wavelength centered at about 13.5 nm. Thus, the light source 2120 may also be referred to as an EUV illumination source. However, it should be understood that the light source 2120 should not be limited to emitting EUV radiation. The light source 2120 may be used to effect high intensity photon emission from an excited target fuel.

[0083] In various embodiments, the illuminator 2140 includes various refractive optics components, such as a single lens or lens system with multiple reflectors 2100A, 2100B, and includes reflective optics (for EUV lithography exposure systems), such as a lens (zone plate), or a mirror system with a single mirror or multiple mirrors to direct light from the light source 2120 onto the mask stage 2016, and in particular onto the mask 2018 fixed onto the mask stage 2016. The mask 2018 may include any of the patterns 500, 500A, 500B, 500C, 500D described with respect to Figures 3E-3I. In this embodiment, where the light source 2120 generates light 2084 in the EUV wavelength range, reflective optics are employed to generate the light 2085, 2086. In some embodiments, the illuminator 2140 includes at least three lenses. The reflector 2100A may be a field facet mirror (FFM) in some embodiments. Reflector 2100B may be a pupil facet mirror (PFM) in some embodiments. Reflector 2100A is configured to block light reflected from contaminated regions of light source 2120.

[0084] The mask stage 2016 is configured to secure the mask 2018. In some embodiments, the mask stage 2016 includes an electrostatic chuck (e-chuck) to secure the mask 2018. This is because gas molecules absorb EUV radiation and lithography exposure systems for EUV lithography patterning are maintained in a vacuum environment to avoid EUV light loss. In the present invention, the terms mask, photomask, and reticle are used interchangeably. In this embodiment, the mask 2018 is a reflective mask. One exemplary structure of the mask 2018 includes a substrate having a suitable material, such as a low thermal expansion material (LTEM) or fused silica. In various examples, the LTEM includes SiO2 doped with TiO2, or other suitable low thermal expansion material. The mask 2018 includes a reflective multilayer deposited on the substrate. In some embodiments, the reflective multilayer includes one or more of the patterns 500, 500A, 500B, 500C, 500D described with respect to FIGS. 3E-3I.

[0085] The projection optics module (or projection optics box (POB)) 2130 is configured to image the pattern of the mask 2018 onto a semiconductor wafer 2022 fixed on a substrate stage 2024 of the lithography exposure system 2000. The POB 2130 comprises refractive optics in some embodiments (such as for a UV lithography exposure system) or reflective optics in various embodiments (such as for an EUV lithography exposure system). Light directed from the mask 2018 bearing an image of the pattern defined on the mask (e.g., light 400 shown in FIG. 3D) is collected by the POB 2130. The illuminator 2140 and the POB 2130 are collectively referred to as the optics module of the lithography exposure system 2000. In some embodiments, the POB 2130 includes at least six reflective optics. In some embodiments, the POB 2130 includes a first mirror 2110A, a second mirror 2110B, a third mirror 2110C, and a fourth mirror 2110D.

[0086] In this embodiment, the semiconductor wafer 2022 may be made of silicon or other semiconductor materials. Alternatively or additionally, the semiconductor wafer 2022 may include other base semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor wafer 2022 is made of a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the semiconductor wafer 2022 is made of an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP). In some embodiments, the semiconductor wafer 2022 may be a silicon-on-insulator (SOI) or germanium-on-insulator (GOI) substrate.

[0087] In addition, the semiconductor wafer 2022 may have various device elements. Examples of device elements formed in the semiconductor wafer 2022 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.), diodes, resistors, capacitors, other applicable elements, combinations thereof, etc. Various processes, such as deposition, etching, implantation, photolithography, annealing, and / or other suitable processes, are performed to form the device elements. In some embodiments, the semiconductor wafer 2022 is coated with a resist layer (e.g., masking layer 300) that is sensitive to EUV radiation in this embodiment. Various elements, including those described above, can be integrated and operated together to perform lithography processes.

[0088] Lithography exposure system 2000 may further include or be integrated (or coupled) with other modules, such as a cleaning module designed to provide hydrogen gas to light source 2120. The hydrogen gas helps reduce contamination of light source 2120.

[0089] Embodiments may provide advantages. An improved optical proximity effect (OPC) process for exposing masking layer 300 reduces the diagonal width D 368M of opening 35 in masking layer 300 used when etching opening 365 in which BDTI structure 165 is formed. By reducing the dimension of crossover region 368 of masking layer 300, loading effects at crossover region 168 of BDTI structure 165 are reduced. Improvements to BDTI structure 165, including improved depth uniformity, allow smaller pixel sizes for partial BDTI structure 165 as well as full BDTI structure 165, which allows for image sensor ICs with increased pixel density.

[0090] In at least one embodiment, a method includes forming a masking layer on a backside of a substrate, the substrate including a pixel region having a light receiving element and a transistor disposed on or within a front side of the substrate; forming a mask opening in the masking layer by exposing the masking layer to patterned light, the mask opening including a mask pixel region masking the pixel region and a mask protrusion region extending from the mask pixel region toward a mask intersection region; forming a substrate opening in the substrate by etching the substrate through the mask opening; and forming an isolation structure in the substrate opening. In some embodiments, exposing the masking layer to the patterned light includes forming the patterned light with a reticle and directing the patterned light to the masking layer, the reticle including a pattern, the pattern including pixel protection regions associated with the mask pixel regions and protrusion regions associated with the mask protrusion regions. In some embodiments, the protrusion region extends beyond the pixel-protecting region in a first direction by a first dimension and overlaps the pixel-protecting region in the first direction by a second dimension, the ratio of the first dimension to the second dimension being within the range of 0.1 to 10. In some embodiments, the substrate opening includes a wall opening and a cross-way opening. The wall opening includes a first wall opening having a first width extending in a first direction and a second wall opening extending in a second direction transverse to the first direction. The cross-way opening has a second width less than the first width located in a region where the first wall opening overlaps the second wall opening.

[0091] In some embodiments, the cross passage opening has a diagonal width between two protrusions of the substrate, the ratio of the diagonal width to the first width being less than 1.414, and the two protrusions are on opposite sides of the first wall opening and on opposite sides of the second wall opening.

[0092] In some embodiments, the second width is a lateral width between two protruding portions of the substrate, the two protruding portions being on opposite sides of the first wall opening.

[0093] In some embodiments, the ratio of the height of the first wall opening to the first width is in the range of 10-100.

[0094] In accordance with at least one embodiment, a device includes a substrate, a photodetector in the substrate, a transistor on or in a first side of the substrate, and an isolation structure in the substrate laterally surrounding the photodetector, the isolation structure including a first wall extending in a first direction and having a first width, a second wall extending in a second direction transverse to the first direction, and a crossover region located in a region where the first wall overlaps the second wall and having a second width narrower than the first width. In some embodiments, the substrate includes a first pixel region including a light receiving element, a second pixel region located across the first wall from the first pixel region along the second direction, a first protrusion extending from the first pixel region toward a center of the intersection region, and a second protrusion extending from the second pixel region toward the center of the intersection region.

[0095] In some embodiments, the first protrusion is separated from the second protrusion by a second width. In some embodiments, the substrate includes a first pixel region including a light receiving element, a second pixel region located diagonally across the first wall and the second wall from the first pixel region, a first protrusion extending from the first pixel region toward the center of the intersection region, and a second protrusion extending from the second pixel region toward the center of the intersection region.

[0096] In some embodiments, the first protrusion is separated from the second protrusion by a third width, and a ratio of the third width to the first width is less than 1.414. In some embodiments, the device further comprises a floating diffusion region in the substrate, the floating diffusion region overlapping the isolation structure.

[0097] In some embodiments, the intersection region has a cross-sectional shape including a first segment abutting at least two protrusions of the substrate overlapping the floating diffusion region, a third segment between the first segment and the floating diffusion region, and a second segment between the first segment and the third segment, the first segment having sidewalls that taper outward as the distance from the floating diffusion region decreases, and the second segment having sidewalls that taper inward as the distance from the floating diffusion region decreases.

[0098] In some embodiments, the height of the second segment is greater than the height of the first segment.

[0099] According to at least one embodiment, a method includes forming a light receiving element in a substrate, forming a transistor on a first side of the substrate, and forming a pattern mask on a second side of the substrate, the second side facing away from the first side. The pattern mask includes a wall exposure region. The wall exposure region includes a first wall exposure region having a first width extending in a first direction and a second wall exposure region extending in a second direction transverse to the first direction. The pattern mask further includes a crossover region in an area where the first wall exposure region overlaps with the second wall exposure region, the crossover region having a second width less than the first width. The method further includes forming an opening in the substrate by etching through the pattern mask and forming an isolation structure in the opening. In some embodiments, forming the patterned mask includes forming a patterned light with a reticle and directing the patterned light toward a masking layer on the second side of the substrate, the reticle including a pattern, the pattern including pixel protection regions associated with pixel regions of the substrate and protrusion regions extending from corners of the pixel protection regions.

[0100] In some embodiments, the protrusion regions are polygonal in shape, such as triangular, rectangular, pentagonal, hexagonal, or N-sided, where N is greater than six.

[0101] In some embodiments, the method further includes forming a floating diffusion region in the substrate.

[0102] In some embodiments, the protrusion region has a circular shape.

[0103] The foregoing outlines features of several embodiments to better enable those skilled in the art to understand aspects of the present invention. Those skilled in the art should appreciate that this disclosure may readily be used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and alterations may be made without departing from the spirit and scope of the present invention. [Industrial Applicability]

[0104] Embodiments of the present invention may be applied to image sensor applications. [Explanation of symbols]

[0105] 10A, 10B, 10C: Image sensor IC 20, 20d: Transistor 41: Spacer structure 82: Photodetector 84: Floating diffusion (FD) region 106: Conductive wire 110a, 110b, 110c, 110d: pixel areas 118: Topographical Features 120: interconnect layer, metal line 121: Conductive wire 122: First Contact 123: Conductive via 130: Dielectric structure, dielectric layer 131, 132: Etch stop layer 140: Substrate 140C: Corner area 140P:Protrusion 155, 195: CMG 160: Isolation structure, dummy contact structure 163, 165: Separated structure 166: Wall 167: Buffer layer 168: Crossroads area 170: Dielectric layer 180: Color filter 182: Microlens 194: Metal grid layer 196: Dielectric grid layer 100, 200A, 200B, 200C, 300P, 310, 365, 366, 368, 366M, 368M, 510a, 510b, 510c, 510d, 520, 566, 568: Area 210, 220: dashed line 290: Gate electrode 300: Masking layer 400: light 500, 500A, 500B, 500C, 500D: Pattern 600: Gate dielectric layer 700, 2018: Mask 1000: Method 1100, 1200, 1300, 1400, 1500, 1600: Operation 2000:System 2016: Mask Stage 2022: Semiconductor wafers 2110A, 2110B, 2110C: Mirror 2120:Light source 2130: Projection optical system module 2140: Irradiator D166, D168, D169, D166A, D168A, D166B, D168B, D169B, D166C, D168C, D169C, D366M, D368M, D369M: Width H1, H2, H3, W3, W4, W5: Dimensions H166A, H168A, H166B, H168B, H166C, H168C, LE, LE', LE'': Height

Claims

1. forming a masking layer on a backside of a substrate, the substrate including a pixel region having a light receiving element and a floating diffusion region and a transistor disposed on or in a front side of the substrate; forming a mask opening in the masking layer by exposing the masking layer to a pattern light, the mask opening including a mask pixel area masking the pixel area and a mask protrusion area extending from the mask pixel area toward a mask crossing area; forming a substrate opening in the substrate by etching the substrate through the mask opening; forming an isolation structure in the substrate opening; Including, The substrate opening is a first wall opening having a first width extending in a first direction; a second wall opening extending in a second direction transverse to the first direction; Including, Wall openings and a cross-way opening having a second width less than the first width, the cross-way opening being located in a region where the first wall opening overlaps the second wall opening; Including, The crossroad opening is a first segment overlapping the floating diffusion region, the first segment abutting at least two protruding portions of the substrate; a third segment between the first segment and the floating diffusion region; a second segment between the first segment and the third segment, the first segment has sidewalls that taper outwardly as the distance from the floating diffusion region decreases; the second segment has sidewalls that taper inwardly as the distance from the floating diffusion region decreases. having a cross-sectional profile, method.

2. exposing the masking layer to the patterned light; forming a patterned light by a reticle, the reticle including a pattern, the pattern comprising: a pixel protection region associated with the mask pixel region; a protrusion region associated with the mask protrusion region; and directing the patterned light to the masking layer; Including, The method of claim 1.

3. the protrusion region extends beyond the pixel-protecting region in a first direction by a first dimension and overlaps the pixel-protecting region in the first direction by a second dimension; a ratio of the first dimension to the second dimension is in the range of 0.1 to 10; The method of claim 2.

4. A substrate; A light receiving element in the substrate; a transistor on or in a first side of the substrate; an isolation structure in the substrate that laterally surrounds the light receiving element; a floating diffusion region in the substrate, the floating diffusion region overlapping the isolation structure; and Including, The isolation structure comprises: a first wall extending in a first direction and having a first width; a second wall extending in a second direction transverse to the first direction; a crossover region having a second width less than the first width, the crossover region being located in a region where the first wall overlaps the second wall; Including, The intersection area includes: a first segment overlapping the floating diffusion region, the first segment abutting at least two protruding portions of the substrate; a third segment between the first segment and the floating diffusion region; a second segment between the first segment and the third segment, the first segment has sidewalls that taper outwardly as the distance from the floating diffusion region decreases; the second segment has sidewalls that taper inwardly as the distance from the floating diffusion region decreases. having a cross-sectional profile, device.

5. The substrate is A first pixel region including the light receiving element; a second pixel region located across the first wall from the first pixel region along the second direction; a first protrusion extending from the first pixel region toward a center of the intersection region; a second protrusion extending from the second pixel region toward the center of the intersection region; Including, The device of claim 4.

6. The substrate is A first pixel region including the light receiving element; a second pixel region located diagonally across the first wall and the second wall from the first pixel region; a first protrusion extending from the first pixel region toward a center of the intersection region; a second protrusion extending from the second pixel region toward the center of the intersection region; Including, The device of claim 4.

7. forming a light receiving element on a substrate; forming a floating diffusion region in the substrate; forming a transistor on a first side of the substrate; forming a patterned mask on a second side of the substrate, the second side facing away from the first side, the patterned mask comprising: a first wall exposure area having a first width extending in a first direction; a second wall exposure area extending in a second direction transverse to the first direction; a wall exposure area including: a crossover region in an area where the first wall exposure region overlaps with the second wall exposure region, the crossover region having a second width smaller than the first width; containing, forming openings in the substrate by etching through the pattern mask; forming an isolation structure in the opening; Including, At the crossover region, the separation structure comprises: a first segment overlapping the floating diffusion region, the first segment abutting at least two protruding portions of the substrate; a third segment between the first segment and the floating diffusion region; a second segment between the first segment and the third segment, the first segment has sidewalls that taper outwardly as the distance from the floating diffusion region decreases; the second segment has sidewalls that taper inwardly as the distance from the floating diffusion region decreases. having a cross-sectional profile, method.

8. forming the pattern mask, forming a patterned light by a reticle, the reticle including a pattern, the pattern comprising: a pixel protection region associated with a pixel region of the substrate; a protruding region extending from a corner of the pixel protection region; and directing the patterned light toward a masking layer on the second side of the substrate; Including, The method according to claim 7.

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