Etching Method

Abstract

Provided is an etching method whereby a multilayer membrane, which has a silicon-containing membrane, and a single layer membrane are etched simultaneously. This etching method includes: a preparation step in which a substrate that has a first region and a second region is prepared, said first region having a multilayer membrane in which at least two types of silicon-containing membrane are stacked and said second region having a single layer membrane formed from one type of silicon-containing membrane; and an etching step in which the multilayer membrane and the single layer membrane are etched simultaneously. In the etching step, the multilayer membrane and the single layer membrane are etched simultaneously by a plasma generated by a treatment gas that includes a hydrogen fluoride gas, a phosphorus-containing gas and a carbon-containing gas. A first recessed section having a first width is formed in the multilayer membrane and a second recessed section having a second width that is greater than the first width is formed in the single layer membrane.

Description

[Technical field]

[0001] An exemplary embodiment of the present disclosure relates to an etching method. [Background technology]

[0002] Techniques for etching a silicon-containing film include the etching methods described in Patent Documents 1 and 2. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 0343580 [Patent Document 2] JP 2016-39310 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides an etching method for simultaneously etching a multi-layer film and a single layer film having a silicon-containing film. [Means for solving the problem]

[0005] In one exemplary embodiment of the present disclosure, an etching method is provided, which includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region, and an etching step of simultaneously etching the multilayer film and the monolayer film, in which the multilayer film and the monolayer film are simultaneously etched by plasma generated from a process gas containing hydrogen fluoride gas, a phosphorus-containing gas, and a carbon-containing gas, so that a first recess having a first width is formed in the multilayer film, and a second recess having a second width wider than the first width is formed in the monolayer film.

[0006] In one exemplary embodiment of the present disclosure, an etching method is provided, which includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region, and an etching step of simultaneously etching the multilayer film and the monolayer film, in which the multilayer film and the monolayer film are etched by plasma generated from a process gas containing hydrogen fluoride gas, a phosphorus-containing gas, and a carbon-containing gas, to form a first recess in the multilayer film and a second recess in the monolayer film.

[0007] In one exemplary embodiment of the present disclosure, an etching method is provided, which includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region, and an etching step of simultaneously etching the multilayer film and the monolayer film, in which the multilayer film and the monolayer film are etched by plasma generated from a process gas containing a phosphorus-containing gas, a fluorine-containing gas, a hydrofluorocarbon gas, and a halogen-containing gas containing a halogen element other than fluorine, so that a first recess having a first width is formed in the multilayer film, and a second recess having a second width wider than the first width is formed in the monolayer film.

[0008] In one exemplary embodiment of the present disclosure, an etching method is provided, which includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region, and an etching step of simultaneously etching the multilayer film and the monolayer film, in which the multilayer film and the monolayer film are etched by plasma generated from a process gas containing a phosphorus-containing gas, a fluorine-containing gas, a hydrofluorocarbon gas, and a halogen-containing gas containing a halogen element other than fluorine, to form a first recess in the multilayer film and a second recess in the monolayer film.

[0009] In one exemplary embodiment of the present disclosure, an etching method is provided. The etching method includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region; a first etching step of simultaneously etching the multilayer film and the monolayer film; and a second etching step of etching at least one of the multilayer film and the monolayer film, wherein in the first etching step, the multilayer film and the monolayer film are etched by plasma generated from a first process gas containing hydrogen fluoride gas and a phosphorus-containing gas, a first recess is formed in the multilayer film and a second recess is formed in the monolayer film, and in the second etching step, the multilayer film and the monolayer film are etched by plasma generated from a second process gas containing hydrogen fluoride gas and a phosphorus-containing gas, a third recess is formed in at least one of the multilayer film and the monolayer film, and a flow rate of the phosphorus-containing gas contained in the first process gas is different from a flow rate of the phosphorus-containing gas contained in the second process gas. Effect of the Invention

[0010] According to one exemplary embodiment of the present disclosure, multi-layer and single-layer films having silicon-containing films can be etched simultaneously. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic diagram illustrating a plasma processing apparatus according to an exemplary embodiment; [Diagram 2] 1 is a flow chart of an etching method according to an exemplary embodiment. [Diagram 3] 1 is a top view showing an example of a substrate W prepared in step ST1. FIG. [Figure 4] 4 is a diagram showing a part of the AA′ cross section of the substrate W shown in FIG. [Diagram 5] 13 is a diagram showing a cross-sectional structure of the substrate W etched in step ST2. FIG. [Figure 6] 13 is a graph showing the relationship between the flow rate of PF3 and the etching rates of the multilayer film ML and the single layer film SL. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Each embodiment of the present disclosure will be described below.

[0013] In one exemplary embodiment, an etching method is provided.

[0014] The etching method includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region, and an etching step of simultaneously etching the multilayer film and the monolayer film, in which the multilayer film and the monolayer film are simultaneously etched by plasma generated from a process gas containing hydrogen fluoride gas, a phosphorus-containing gas, and a carbon-containing gas, so that a first recess having a first width is formed in the multilayer film and a second recess having a second width wider than the first width is formed in the monolayer film.

[0015] The etching method includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region, and an etching step of simultaneously etching the multilayer film and the monolayer film, in which the multilayer film and the monolayer film are etched by plasma generated from a process gas containing hydrogen fluoride gas, a phosphorus-containing gas, and a carbon-containing gas, so that a first recess is formed in the multilayer film and a second recess is formed in the monolayer film.

[0016] The etching method includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region, and an etching step of simultaneously etching the multilayer film and the monolayer film, in which the multilayer film and the monolayer film are etched by plasma generated from a process gas containing a phosphorus-containing gas, a fluorine-containing gas, a hydrofluorocarbon gas, and a halogen-containing gas containing a halogen element other than fluorine, so that a first recess having a first width is formed in the multilayer film and a second recess having a second width wider than the first width is formed in the monolayer film.

[0017] The etching method includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region, and an etching step of simultaneously etching the multilayer film and the monolayer film, in which the multilayer film and the monolayer film are etched by plasma generated from a process gas containing a phosphorus-containing gas, a fluorine-containing gas, a hydrofluorocarbon gas, and a halogen-containing gas containing a halogen element other than fluorine, so that a first recess is formed in the multilayer film and a second recess is formed in the monolayer film.

[0018] In one exemplary embodiment, the substrate includes a mask film disposed on the multilayer film and the monolayer film, the mask film having a first sidewall that defines a first opening on the multilayer film and a second sidewall that defines a second opening on the monolayer film, and in the etching process, a first recess is formed by etching the multilayer film with plasma at the first opening, and a second recess is formed by etching the monolayer film with plasma at the second opening.

[0019] In one exemplary embodiment, one of the first recess and the second recess is a hole, and the other of the first recess and the second recess is a slit.

[0020] In one exemplary embodiment, the two or more silicon-containing films include a silicon oxide film and a silicon nitride film, and one silicon-containing film is a silicon oxide film.

[0021] In one exemplary embodiment, the phosphorus-containing gas is a phosphorus halide gas.

[0022] In one exemplary embodiment, the carbon-containing gas is a hydrocarbon gas, a fluorocarbon gas, or a hydrofluorocarbon gas.

[0023] The etching method includes a preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a monolayer film formed from one type of silicon-containing film in the second region; a first etching step of simultaneously etching the multilayer film and the monolayer film; and a second etching step of etching one of the multilayer film and the monolayer film, in which in the first etching step, the multilayer film and the monolayer film are etched by plasma generated from a first process gas containing hydrogen fluoride gas and a phosphorus-containing gas, and a first recess is formed in the multilayer film and a second recess is formed in the monolayer film, and in the second etching step, the multilayer film and the monolayer film are etched by plasma generated from a second process gas containing hydrogen fluoride gas and a phosphorus-containing gas, and a third recess is formed in one of the multilayer film and the monolayer film, and a flow rate of the phosphorus-containing gas contained in the first process gas is different from a flow rate of the phosphorus-containing gas contained in the second process gas.

[0024] In one exemplary embodiment, a first etching step is performed followed by a second etching step.

[0025] In one exemplary embodiment, the second etching step is performed before the first etching step.

[0026] In one exemplary embodiment, in a first etching step, a plurality of memory holes in which a plurality of memory cells are formed are formed as first recesses in the multilayer film, a plurality of contact holes in which a plurality of contacts are formed are formed as second recesses in the single layer film, and in a second etching step, a slit spanning from the first region to the second region is formed as a third recess in the multilayer film and the single layer film.

[0027] In one exemplary embodiment, in a first etching step, a plurality of memory holes in which a plurality of memory cells are formed are formed in the multilayer film as a first recess, a slit extending from the first region to the second region is formed in the multilayer film and the single layer film as a first recess, and in a second etching step, a plurality of contact holes in which a plurality of contacts are formed are formed in the single layer film as a second recess.

[0028] In one exemplary embodiment, in a first etching step, a plurality of contact holes in which a plurality of contacts are formed are formed in the single layer film as second recesses, slits extending from the first region to the second region are formed in the multilayer film and the single layer film as first recesses and second recesses, and in a second etching step, a plurality of memory holes in which a plurality of memory cells are formed are formed in the multilayer film as first recesses.

[0029] In one exemplary embodiment, in a first etching step, slits extending from a first region to a second region are formed in the multilayer film and the single layer film as a first recess and a second recess, and in a second etching step, a plurality of memory holes in which a plurality of memory cells are formed are formed in the multilayer film as the first recess, and a plurality of contact holes in which a plurality of contacts are formed are formed in the single layer film as the second recess.

[0030] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are given the same reference numerals, and duplicated explanations will be omitted. Unless otherwise specified, the positional relationship such as up, down, left, right, etc. will be described based on the positional relationship shown in the drawing. The dimensional ratio of the drawings does not indicate the actual ratio, and the actual ratio is not limited to the illustrated ratio.

[0031] FIG. 1 is a diagram that illustrates a schematic diagram of a plasma processing apparatus according to an exemplary embodiment. The plasma processing apparatus 1 illustrated in FIG. 1 includes a chamber 10. The chamber 10 provides an internal space 10s therein. The chamber 10 includes a chamber body 12. The chamber body 12 has a substantially cylindrical shape. The chamber body 12 is formed of, for example, aluminum. A corrosion-resistant film is provided on the inner wall surface of the chamber body 12. The corrosion-resistant film may be formed of a ceramic such as aluminum oxide or yttrium oxide.

[0032] A passage 12p is formed in a sidewall of the chamber body 12. The substrate W is transferred between the internal space 10s and the outside of the chamber 10 through the passage 12p. The passage 12p is opened and closed by a gate valve 12g. The gate valve 12g is provided along the sidewall of the chamber body 12.

[0033] A support 13 is provided on the bottom of the chamber body 12. The support 13 is made of an insulating material. The support 13 has a generally cylindrical shape. The support 13 extends upward from the bottom of the chamber body 12 in the internal space 10s. The support 13 supports a substrate support 14. The substrate support 14 is configured to support a substrate W in the internal space 10s.

[0034] The substrate support 14 has a lower electrode 18 and an electrostatic chuck 20. The substrate support 14 may further have an electrode plate 16. The electrode plate 16 is made of a conductor such as aluminum and has a substantially disk-like shape. The lower electrode 18 is provided on the electrode plate 16. The lower electrode 18 is made of a conductor such as aluminum and has a substantially disk-like shape. The lower electrode 18 is electrically connected to the electrode plate 16.

[0035] The electrostatic chuck 20 is provided on the lower electrode 18. The substrate W is placed on the upper surface of the electrostatic chuck 20. The electrostatic chuck 20 has a body and an electrode. The body of the electrostatic chuck 20 has a substantially disk shape and is formed from a dielectric material. The electrode of the electrostatic chuck 20 is a film-like electrode and is provided in the body of the electrostatic chuck 20. The electrode of the electrostatic chuck 20 is connected to a DC power supply 20p via a switch 20s. When a voltage from the DC power supply 20p is applied to the electrode of the electrostatic chuck 20, an electrostatic attractive force is generated between the electrostatic chuck 20 and the substrate W. The substrate W is attracted to the electrostatic chuck 20 by the electrostatic attractive force and is held by the electrostatic chuck 20.

[0036] An edge ring 25 is disposed on the substrate support 14. The edge ring 25 is a ring-shaped member. The edge ring 25 may be made of silicon, silicon carbide, quartz, or the like. The substrate W is disposed on the electrostatic chuck 20 and within a region surrounded by the edge ring 25.

[0037] A flow path 18f is provided inside the lower electrode 18. A heat exchange medium (e.g., a coolant) is supplied to the flow path 18f from a chiller unit provided outside the chamber 10 via a pipe 22a. The heat exchange medium supplied to the flow path 18f is returned to the chiller unit via a pipe 22b. In the plasma processing apparatus 1, the temperature of the substrate W placed on the electrostatic chuck 20 is adjusted by heat exchange between the heat exchange medium and the lower electrode 18.

[0038] The plasma processing apparatus 1 is provided with a gas supply line 24. The gas supply line 24 supplies a heat transfer gas (for example, He gas) from a heat transfer gas supply mechanism to the gap between the upper surface of the electrostatic chuck 20 and the back surface of the substrate W.

[0039] The plasma processing apparatus 1 further includes an upper electrode 30. The upper electrode 30 is provided above the substrate support 14. The upper electrode 30 is supported on the upper part of the chamber body 12 via a member 32. The member 32 is made of an insulating material. The upper electrode 30 and the member 32 close the upper opening of the chamber body 12.

[0040] The upper electrode 30 may include a top plate 34 and a support 36. The bottom surface of the top plate 34 is the bottom surface on the side of the internal space 10s and defines the internal space 10s. The top plate 34 may be formed of a low-resistance conductor or semiconductor that generates little Joule heat. The top plate 34 has a plurality of gas discharge holes 34a penetrating the top plate 34 in its plate thickness direction.

[0041] The support 36 detachably supports the top plate 34. The support 36 is made of a conductive material such as aluminum. A gas diffusion chamber 36a is provided inside the support 36. The support 36 has a plurality of gas holes 36b extending downward from the gas diffusion chamber 36a. The plurality of gas holes 36b are connected to the plurality of gas discharge holes 34a, respectively. A gas inlet 36c is formed in the support 36. The gas inlet 36c is connected to the gas diffusion chamber 36a. A gas supply pipe 38 is connected to the gas inlet 36c.

[0042] A gas source group 40 is connected to the gas supply pipe 38 via a flow rate controller group 41 and a valve group 42. The flow rate controller group 41 and the valve group 42 configure a gas supply unit. The gas supply unit may further include a gas source group 40. The gas source group 40 includes a plurality of gas sources. The plurality of gas sources include sources of processing gases used in the present etching method. The flow rate controller group 41 includes a plurality of flow rate controllers. Each of the plurality of flow rate controllers in the flow rate controller group 41 is a mass flow controller or a pressure-controlled flow rate controller. The valve group 42 includes a plurality of opening and closing valves. Each of the plurality of gas sources in the gas source group 40 is connected to the gas supply pipe 38 via a corresponding flow rate controller in the flow rate controller group 41 and a corresponding opening and closing valve in the valve group 42.

[0043] In the plasma processing apparatus 1, a shield 46 is detachably provided along the inner wall surface of the chamber body 12 and the outer periphery of the support part 13. The shield 46 prevents reaction by-products from adhering to the chamber body 12. The shield 46 is formed by forming a corrosion-resistant film on the surface of a base material made of, for example, aluminum. The corrosion-resistant film may be made of a ceramic such as yttrium oxide.

[0044] A baffle plate 48 is provided between the support 13 and the side wall of the chamber body 12. The baffle plate 48 is formed, for example, by forming a corrosion-resistant film (a film of yttrium oxide or the like) on the surface of a member made of aluminum. A plurality of through holes are formed in the baffle plate 48. An exhaust port 12e is provided below the baffle plate 48 and at the bottom of the chamber body 12. An exhaust device 50 is connected to the exhaust port 12e via an exhaust pipe 52. The exhaust device 50 includes a pressure regulating valve and a vacuum pump such as a turbo molecular pump.

[0045] A high frequency power supply 62 and a bias power supply 64 are coupled to the plasma processing apparatus 1. The high frequency power supply 62 is a power supply that generates a high frequency power HF. The high frequency power HF has a first frequency suitable for generating plasma. The first frequency is, for example, a frequency within a range of 27 MHz to 100 MHz. The high frequency power supply 62 is connected to the lower electrode 18 via a matching device 66 and the electrode plate 16. The matching device 66 has a circuit for matching the impedance of the load side (lower electrode 18 side) of the high frequency power supply 62 to the output impedance of the high frequency power supply 62. The high frequency power supply 62 may be connected to the upper electrode 30 via the matching device 66. The high frequency power supply 62 constitutes an example of a plasma generating unit.

[0046] The bias power supply 64 is a power supply that generates an electric bias. The bias power supply 64 is electrically connected to the lower electrode 18. The electric bias has a second frequency. The second frequency is lower than the first frequency. The second frequency is, for example, a frequency within a range of 400 kHz to 13.56 MHz. When the electric bias is used together with the high frequency power HF, it is applied to the substrate support 14 to attract ions to the substrate W. In one example, the electric bias is applied to the lower electrode 18. When the electric bias is applied to the lower electrode 18, the potential of the substrate W placed on the substrate support 14 fluctuates within a period defined by the second frequency. The electric bias may be applied to a bias electrode provided in the electrostatic chuck 20.

[0047] In one embodiment, the electric bias may be a high frequency power LF having a second frequency. When the high frequency power LF is used together with the high frequency power HF, it is used as a high frequency bias power for attracting ions to the substrate W. A bias power supply 64 configured to generate the high frequency power LF is connected to the lower electrode 18 via a matching box 68 and the electrode plate 16. The matching box 68 has a circuit for matching the impedance of the load side (lower electrode 18 side) of the bias power supply 64 to the output impedance of the bias power supply 64.

[0048] It is also possible to generate plasma using high frequency power LF without using high frequency power HF, that is, using only a single high frequency power. In this case, the frequency of the high frequency power LF may be a frequency higher than 13.56 MHz, for example, 40 MHz. In this case, the plasma processing apparatus 1 does not need to include the high frequency power supply 62 and the matching box 66. In this case, the bias power supply 64 constitutes an example of a plasma generating unit.

[0049] In another embodiment, the electrical bias may be a pulsed voltage. In this case, the bias power supply may be a DC power supply. The bias power supply may be configured to provide a pulsed voltage itself or may be configured to include a device for pulsing the voltage downstream of the bias power supply. In one example, the pulsed voltage is applied to the lower electrode 18 so as to generate a negative potential on the substrate W. The pulsed voltage may be a square wave, a triangular wave, an impulse, or may have other waveforms.

[0050] The period of the pulse voltage is determined by the second frequency. The period of the pulse voltage includes two periods. The pulse voltage in one of the two periods is a negative voltage. The level (i.e., absolute value) of the voltage in one of the two periods is higher than the level (i.e., absolute value) of the voltage in the other of the two periods. The voltage in the other period may be either negative or positive. The level of the negative voltage in the other period may be greater than zero or may be zero. In this embodiment, the bias power supply 64 is connected to the lower electrode 18 via the low-pass filter and the electrode plate 16. The bias power supply 64 may be connected to a bias electrode provided in the electrostatic chuck 20 instead of the lower electrode 18.

[0051] In one embodiment, the bias power supply 64 may provide a continuous wave of electrical bias to the lower electrode 18. That is, the bias power supply 64 may provide an electrical bias to the lower electrode 18 continuously.

[0052] In another embodiment, the bias power supply 64 may apply a pulse wave of an electric bias to the lower electrode 18. The pulse wave of the electric bias may be applied periodically to the lower electrode 18. The period of the pulse wave of the electric bias is defined by a third frequency. The third frequency is lower than the second frequency. The third frequency is, for example, 1 Hz or more and 200 kHz or less. In another example, the third frequency may be 5 Hz or more and 100 kHz or less.

[0053] The period of the pulse wave of the electric bias includes two periods, namely, an H period and an L period. The level of the electric bias in the H period (i.e., the level of the pulse of the electric bias) is higher than the level of the electric bias in the L period. That is, the pulse wave of the electric bias may be applied to the lower electrode 18 by increasing or decreasing the level of the electric bias. The level of the electric bias in the L period may be greater than zero. Alternatively, the level of the electric bias in the L period may be zero. That is, the pulse wave of the electric bias may be applied to the lower electrode 18 by alternately switching between supplying and stopping the supply of the electric bias to the lower electrode 18. Here, when the electric bias is a high frequency power LF, the level of the electric bias is the power level of the high frequency power LF. When the electric bias is a high frequency power LF, the level of the high frequency power LF in the pulse of the electric bias may be 2 kW or more. When the electric bias is a pulse wave of a negative polarity DC voltage, the level of the electric bias is the effective value of the absolute value of the negative polarity DC voltage. The duty ratio of the pulse wave of the electric bias, i.e., the ratio of the H period to the period of the pulse wave of the electric bias, is, for example, 1% or more and 80% or less. In another example, the duty ratio of the pulse wave of the electric bias may be 5% or more and 50% or less. Alternatively, the duty ratio of the pulse wave of the electric bias may be 50% or more and 99% or less.

[0054] In one embodiment, the high frequency power source 62 may supply a continuous wave of high frequency power HF, i.e., the high frequency power source 62 may supply the high frequency power HF continuously.

[0055] In another embodiment, the high frequency power supply 62 may supply a pulse wave of high frequency power HF. The pulse wave of high frequency power HF may be supplied periodically. The period of the pulse wave of high frequency power HF is defined by a fourth frequency. The fourth frequency is lower than the second frequency. In one embodiment, the fourth frequency is the same as the third frequency. The period of the pulse wave of high frequency power HF includes two periods, namely, an H period and an L period. The power level of the high frequency power HF in the H period is higher than the power level of the high frequency power HF in the L period of the two periods. The power level of the high frequency power HF in the L period may be greater than zero or may be zero.

[0056] The period of the pulse wave of the high frequency power HF may be synchronized with the period of the pulse wave of the electric bias. The H period in the period of the pulse wave of the high frequency power HF may be synchronized with the H period in the period of the pulse wave of the electric bias. Alternatively, the H period in the period of the pulse wave of the high frequency power HF may not be synchronized with the H period in the period of the pulse wave of the electric bias. The time length of the H period in the period of the pulse wave of the high frequency power HF may be the same as or different from the time length of the H period in the period of the pulse wave of the electric bias.

[0057] When plasma processing is performed in the plasma processing apparatus 1, a gas is supplied from a gas supply unit to the internal space 10s. In addition, a high-frequency electric field is generated between the upper electrode 30 and the lower electrode 18 by supplying high-frequency power HF and / or an electric bias. The generated high-frequency electric field generates plasma from the gas in the internal space 10s.

[0058] The plasma processing apparatus 1 may further include a control unit 80. The control unit 80 may be a computer including a processor, a storage unit such as a memory, an input device, a display device, a signal input / output interface, and the like. The control unit 80 controls each part of the plasma processing apparatus 1. In the control unit 80, an operator can use the input device to input commands and the like to manage the plasma processing apparatus 1. In addition, the control unit 80 can visualize and display the operating status of the plasma processing apparatus 1 using the display device. Furthermore, the storage unit stores a control program and recipe data. The control program is executed by the processor to execute various processes in the plasma processing apparatus 1. The processor executes the control program and controls each part of the plasma processing apparatus 1 according to the recipe data.

[0059] The plasma formed in the plasma processing space may be an inductively coupled plasma (ICP), an electron-cyclotron-resonance plasma (ECR plasma), a helicon wave plasma (HWP), or a surface wave plasma (SWP), in addition to a capacitively coupled plasma (CCP). Various types of plasma generating units may be used, including an alternating current (AC) plasma generating unit and a direct current (DC) plasma generating unit. In one embodiment, the AC signal (AC power) used in the AC plasma generating unit has a frequency in the range of 100 kHz to 10 GHz. Thus, the AC signal includes a radio frequency (RF) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 200 kHz to 150 MHz.

[0060] FIG. 2 is a flowchart showing an etching method according to an exemplary embodiment (hereinafter referred to as "the etching method"). The etching method includes a preparation step (ST1) of preparing a substrate, and an etching step (ST2) of etching a multilayer film and a single layer film provided on the substrate. The etching method may further include a step (ST3) of preparing a substrate and a step (ST4) of etching the multilayer film and / or the single layer film. When the etching method includes steps ST3 and ST4, steps ST1 and ST2 may be performed after steps ST3 and ST4 are performed. The etching method is performed on a substrate using, for example, a plasma processing apparatus 1 shown in FIG. 1.

[0061] Fig. 3 is a top view showing an example of the substrate W prepared in step ST1. Fig. 4 is a view showing a part of the AA' cross section of the substrate W shown in Fig. 3. The substrate W may be used for manufacturing semiconductor devices including semiconductor memory devices such as DRAMs and 3D-NAND flash memories.

[0062] The substrate W has a first region RE1 and a second region RE2. In a plan view of the substrate W (top view of FIG. 3), the first region RE1 and the second region RE2 are regions each having a predetermined range on the substrate W. The first region RE1 and the second region RE2 may be two regions adjacent to each other, or may be two regions separated from each other. The first region RE1 may be, for example, a memory cell region in a semiconductor memory device. The second region RE2 may be, for example, a contact region or a peripheral circuit region in a semiconductor memory device. In one example, the contact region is a region in which one or more contact holes are provided for electrically connecting one or more memory cells to the peripheral circuit.

[0063] The substrate W has an undercoat film UF provided across the first region RE1 and the second region RE2. The substrate W also has a multilayer film ML provided on the undercoat film UF in the first region RE1. The multilayer film ML is a laminated film in which two or more types of silicon-containing films are laminated. In this embodiment, the multilayer film ML is a laminated film in which silicon nitride films SF1 and silicon oxide films SF2 are alternately and repeatedly laminated.

[0064] The substrate W also has a single layer film SL provided on the undercoat film UF in the second region RE2. The single layer film SL is a film made of a silicon-containing film such as a silicon oxide film or a silicon nitride film. In this embodiment, the single layer film SL is a silicon oxide film. The multilayer film ML and the single layer film SL may have the same thickness or may have different thicknesses.

[0065] The substrate W further includes a mask film MK. The mask film MK is provided on the multilayer film ML and the single layer film SL. That is, the mask film MK is provided from the first region RE1 to the second region RE2. The mask film MK has a predetermined pattern. The mask film MK has one or more openings OPM in the first region RE1 (note that the circular opening provided in the first region RE1 is also called the opening OPM1, and the rectangular slit (opening) is also called the opening OPM2). In this embodiment, each of the one or more openings OPM is an opening defined by a sidewall formed in the mask film MK. The mask film MK also has one or more openings OPS in the second region RE2 (note that the circular opening provided in the second region RE2 is also called the opening OPS1, and the rectangular slit (opening) is also called the opening OPS2). In this embodiment, the one or more openings OPS is an opening defined by a sidewall formed in the mask film MK.

[0066] The openings OPM and OPS are, for example, openings for forming holes, contact holes, lines and spaces, slits, trenches, etc. in which memory cells are formed in the multilayer film ML and / or the single layer film SL. The openings OPM and OPS have, for example, a circular shape, an elliptical shape, a linear shape, a rectangular shape, etc. in a plan view. The openings OPM and OPS may have the same shape in a plan view, or may have different shapes. The opening OPS may have a width (for example, the diameter of a circular opening, the minor axis of an elliptical opening, the line width of a linear opening, and the length of the short side or long side of a rectangular opening) wider than the opening OPM. The openings OPM and OPS may be integrally formed openings. As an example, the openings OPM and OPS may be a part of one slit formed from the first region RE1 to the second region RE2.

[0067] In this embodiment, as shown in Fig. 3, for example, a first region RE1 of the mask film MK is provided with a plurality of openings OPM1 each having a circular shape in a planar view. Also, a second region RE2 of the mask film MK is provided with a plurality of openings OPS1 each having a circular shape in a planar view. For example, the width (diameter) of the openings OPM1 provided in the first region RE1 is smaller than the width (diameter) of the openings OPM1 provided in the second region RE2. The width (diameter) of the openings OPM1 may be larger than the width (diameter) of the openings OPS2, or may be the same as the width (diameter) of the openings OPS2.

[0068] In this embodiment, as shown in FIG. 3, an opening having a slit shape in a plan view is provided from the first region RE1 to the second region RE2 of the mask membrane MK. The opening has an opening OPM2, which is a portion provided in the first region RE1 of the mask membrane MK, and an opening OPS2, which is a portion provided in the second region RE2. The width of the opening OPM2 and the opening OPS2 may be wider or narrower than the width (diameter) of the opening OPM1 and / or the opening OPS1, and may be the same as the width (diameter) of the opening OPM1 and / or the opening OPS1. The width of the opening OPM2 may be different from the width of the opening OPS2. The opening having a slit shape in FIG. 3 may be provided in only one of the first region RE1 and the second region RE2. That is, the opening may be a slit having only one of the opening OPM2 and the opening OPS2.

[0069] The mask film MK is formed of a material having an etching rate lower than that of the multilayer film ML and the single layer film SL in step ST2. The mask film MK may be formed of an organic material. The mask film MK may be, for example, an amorphous carbon film, a photoresist film, or a SOC film (spin-on carbon film). The mask film MK may be a metal-containing mask formed of a metal-containing material such as titanium nitride, tungsten, or tungsten carbide.

[0070] 2 is performed on a substrate W in a plasma processing apparatus 1. In this example, a control unit 80 controls each unit of the plasma processing apparatus 1, whereby the etching method is performed in the plasma processing apparatus 1.

[0071] (Step ST1: Preparation of substrate W) In step ST1, the substrate W is prepared in the internal space 10s of the chamber 10. At least a part of the process for forming each component of the substrate W shown in Fig. 3 and Fig. 4 may be performed in the internal space 10s. Alternatively, after all or a part of each component of the substrate W is formed in an apparatus or chamber outside the plasma processing apparatus 1, the substrate W may be carried into the internal space 10s and placed on the electrostatic chuck 20.

[0072] (Step ST2: Etching of multilayer film ML and single layer film SL) Next, in step ST2, the multilayer film ML and the single layer film SL are etched. Step ST2 is an example of a first etching step. First, a process gas for generating plasma is supplied into the chamber 10. The process gas includes a gas species that generates HF species. In one example, the gas species that generates HF species may include HF gas (hydrogen fluoride gas). In another example, the gas species that generates HF species may include H2 and C x F y (x and y are natural numbers), H2 and C s H t F u , C s H t F u (s, t, and u are natural numbers) may be used alone. The process gas may include a gas containing fluorine or other halogen elements in addition to the gas that generates HF species. The process gas may include at least one halogen-containing molecule. The process gas may include at least one fluorocarbon or hydrofluorocarbon as the at least one halogen-containing molecule. The fluorocarbon is, for example, at least one of CF4, C3F8, C4F6, or C4F8. The hydrofluorocarbon is, for example, at least one of CH2F2, CHF3, or CH3F. The hydrofluorocarbon may include two or more carbons. The hydrofluorocarbon may include three carbons or four carbons. Hydrofluorocarbons include, for example, C2HF5, C2H2F4, C2H3F3, C2H4F2, C3HF7, C3H2F2, C3H2F6, C3H2F4, C3H3F5, C4H5F5, C4H2F6, and C5H2F 10and c-C5H3F7. In one example, the carbon-containing gas is at least one selected from the group consisting of C4F8, C3H2F4, and C4H2F6. The halogen-containing molecule may not contain carbon. The halogen-containing molecule may be, for example, nitrogen trifluoride gas (NF3 gas) or sulfur hexafluoride gas (SF6 gas). The process gas may further contain a halogen-containing gas containing a halogen element other than fluorine. The halogen-containing gas may be, for example, at least one selected from the group consisting of Cl2, SiH2Cl2, SiCl4, Si2Cl6, CHCl3, CCl4, and BCl3. The halogen-containing gas may be, for example, HBr, NF3. When HF gas is used, it is preferable to include a carbon-containing gas. The carbon-containing gas can form a carbon-containing deposit on the mask to protect the mask from etching.

[0073] The process gas used in step ST2 may further include at least one phosphorus-containing molecule. The phosphorus-containing molecule may be tetraphosphorus decaoxide (PO 10 The phosphorus-containing molecule may be an oxide such as phosphorus octoxide (P4O8), tetraphosphorus hexoxide (P4O6), etc. Tetraphosphorus decaoxide is sometimes called diphosphorus pentoxide (P2O5). The phosphorus-containing molecule may be a halide (phosphorus halide) such as phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), phosphorus trichloride (PCl3), phosphorus pentachloride (PCl5), phosphorus tribromide (PBr3), phosphorus pentabromide (PBr5), phosphorus iodide (PI3). That is, the phosphorus-containing molecule may contain fluorine as a halogen element, such as phosphorus fluoride. Alternatively, the phosphorus-containing molecule may contain a halogen element other than fluorine as a halogen element. The phosphorus-containing molecule may be a phosphoryl halide such as phosphoryl fluoride (POF3), phosphoryl chloride (POCl3), or phosphoryl bromide (POBr3). The phosphorus-containing molecule may be phosphine (PH3), calcium phosphide (such as Ca3P2), phosphoric acid (H3PO4), sodium phosphate (Na3PO4), hexafluorophosphoric acid (HPF6), etc. The phosphorus-containing molecule may be fluorophosphines (H x PF y), where the sum of x and y is 3 or 5. Examples of fluorophosphines include HPF2 and H2PF3. The process gas may contain one or more of the above phosphorus-containing molecules as the at least one phosphorus-containing molecule. For example, the process gas may contain at least one of PF3, PCl3, PF5, PCl5, POCl3, PH3, PBr3, or PBr5 as the at least one phosphorus-containing molecule. When each phosphorus-containing molecule contained in the process gas is liquid or solid, each phosphorus-containing molecule may be vaporized by heating or the like and supplied into the chamber 10.

[0074] The process gas used in step ST2 may further contain carbon and hydrogen. The process gas may contain H2, hydrocarbons (C x H y ), hydrofluorocarbons (C x H y F z ), or NH3. The hydrocarbon is, for example, CH4 or C3H6. Here, x and y are each a natural number. The process gas may include a fluorocarbon or a hydrocarbon (for example, CH4) as a molecule containing carbon. The process gas may further include oxygen. The process gas may include, for example, O2. Alternatively, the process gas may not include oxygen.

[0075] The process gas used in step ST2 may include a phosphorus-containing gas, a fluorine-containing gas, and a hydrogen-containing gas containing at least one selected from the group consisting of hydrogen fluoride, hydrogen (H2), ammonia, and a hydrocarbon. The fluorine-containing gas may be a fluorocarbon and / or a hydrofluorocarbon. The process gas may also be a phosphorus-containing gas, a fluorine-containing gas, a hydrofluorocarbon gas, and a halogen-containing gas containing a halogen element other than fluorine. The fluorine-containing gas is, for example, nitrogen trifluoride gas (NF3 gas) or sulfur hexafluoride gas (SF6 gas).

[0076] In step ST2, the pressure of the gas in the chamber 10 is set to a designated pressure. In step ST2, the pressure of the gas in the chamber 10 may be set to a pressure of 10 mTorr (1.3 Pa) or more and 100 mTorr (13.3 Pa) or less. In step ST2, a first high frequency power and / or a second high frequency power is supplied to generate plasma from the processing gas in the chamber 10. The level of the first high frequency power may be set to a level of 2 kW or more and 10 kW or less. The level of the second high frequency power may be set to a level of 2 kW (2.83 W / cm in terms of the power level per unit area of ​​the substrate W). 2 The level of the second high frequency power can be set to a level of 10 kW (14.2 W / cm in terms of the power level per unit area of ​​the substrate W) or more. 2 ) or higher.

[0077] In one embodiment, the temperature of the substrate W at the start of process ST2 may be set to a temperature of 20° C. or lower, for example, 0° C. or lower, for example, −40° C. or −70° C. In order to set the temperature of the substrate W at the start of process ST2, the control unit 80 may control the chiller unit and the pressure of the heat transfer gas (e.g., He) between the electrostatic chuck and the back surface of the substrate.

[0078] In step ST2, the multilayer film ML and the single layer film SL are simultaneously etched by chemical species from plasma formed from the processing gas (see FIG. 5). Specifically, the portion of the multilayer film ML exposed at the opening OPM is etched, and a recess RCM is formed in the multilayer film ML continuously from the mask film MK based on the shape of the opening OPM of the mask film MK. Also, the portion of the single layer film SL exposed at the opening OPS is etched, and a recess RCS is formed in the single layer film SL continuously from the mask film MK based on the shape of the opening OPS of the mask film MK.

[0079] As an example, a method for simultaneously etching the multilayer film ML and the single layer film SL to form recesses using a mask film MK having an opening pattern shown in Fig. 3 has been described above, but recesses corresponding to the opening pattern shown in Fig. 3 may be formed in multiple steps. For example, recesses corresponding to some of the openings shown in Fig. 3 may be formed by steps ST1 and ST2 described above, and then recesses corresponding to the rest of the openings may be formed by steps ST3 and ST4 described below. An example of such steps ST3 and ST4 will be described below.

[0080] (Step ST3: Preparation of substrate W) After step ST2 and other steps, in step ST3, a step similar to step ST1 is performed on the substrate W. As an example, when the substrate W is a substrate on which a 3D NAND flash memory is formed, the other step is, for example, a step of forming a memory cell in a recess (opening) formed in the multilayer film ML in step ST2.

[0081] The substrate W prepared in step ST3 has a mask film MK. The mask film MK has a different pattern from the mask film MK prepared in step ST1. The mask film MK prepared in step ST1 has one or more openings OPM in the first region RE1 and one or more openings OPS in the second region RE2. On the other hand, the mask film MK prepared in step ST3 has one or more openings OPM and / or openings OPS in at least one of the first region RE1 and the second region RE2.

[0082] For example, when the substrate W is a substrate on which a 3D NAND flash memory is formed, the first region RE1 may be, for example, a memory cell region in which a memory cell is formed. Also, the second region RE2 may be, for example, a contact region in which a contact for electrically connecting a memory cell to a peripheral circuit is formed. For example, the opening OPM may be an opening (for example, opening OPM1) for forming a memory hole in the multilayer film ML in which a memory cell is formed. Also, the opening OPS may be, for example, an opening (for example, opening OPS1) for forming a contact hole in the single layer film SL. Also, the opening OPM may be, for example, an opening (for example, opening OPM2) for forming a slit in the multilayer film ML in the memory cell region. The slit may be a slit provided from the memory cell region to the contact region. In this case, the opening OPS may be an opening (for example, opening OPS2) for forming the slit in the single layer film SL.

[0083] (Step ST4: Etching of multilayer film ML and / or single layer film SL) Next, in step ST4, the multilayer film ML and / or the single layer film SL are etched using the mask film MK prepared in step ST3. Step ST4 is an example of a second etching step. In step ST4, the multilayer film ML and the single layer film SL may be etched under the same conditions as in step ST2, or may be etched under different conditions. In one example, in step ST4, the process gas for etching the multilayer film ML and / or the single layer film SL may contain a phosphorus-containing gas, as in step ST2. The phosphorus-containing gas used in step ST4 may be a gas of the same type (material) as the phosphorus-containing gas used in step ST2, or may be a gas of a different type (material). In addition, in steps ST2 and ST4, the phosphorus-containing gas may be supplied to the chamber 10 at the same flow rate, or may be supplied at different flow rates. The type and / or flow rate of the phosphorus-containing gas used in step ST4 may be appropriately selected, for example, depending on the film to be etched (multilayer film, single layer film, etc.) and the opening width of the opening OPM and / or opening OPS.

[0084] <Example> The following describes an experiment conducted to evaluate this etching method. In this experiment, O2, C4F6H2, HF, and PF3 were used as processing gases. The flow rate of PF3 was changed to confirm the change in the etching rates of the multilayer film ML and the single layer film SL. The flow rate of PF3 in the processing gas was 4% to 19%. The flow rate of HF in the processing gas was 50% or more. The solid line in FIG. 6 indicates the etching rate of the multilayer film ML when the opening width of the mask film MK is 100 nm. The dashed line in FIG. 6 indicates the etching rate of the single layer film SL (hereinafter referred to as the "single layer film SL1") when the opening width of the mask film MK is 100 nm. The dashed line in FIG. 6 indicates the expected etching rate of the single layer film SL (hereinafter referred to as the "single layer film SL2") when the opening width of the mask film MK is about 150 nm. The multilayer film ML is a laminated film of a silicon oxide film and a silicon nitride film. The single layer film SL is a silicon oxide film. The temperature of the substrate W was set to -70°C.

[0085] FIG. 6 is a graph showing the relationship between the flow rate of PF3 and the etching rates of the multilayer film ML, the monolayer film SL1, and the monolayer film SL2. As shown in FIG. 6, it was confirmed that by controlling the flow rate of the phosphorus-containing gas, when the multilayer film ML and the monolayer film SL are etched simultaneously, the etching rates of the multilayer film ML and the monolayer film SL can be made closer to each other, and the ratio of the etching rate of the monolayer film SL to the etching rate of the multilayer film ML can be controlled. That is, as shown in FIG. 6, in the region where the flow rate of PF3 is low (the region where the flow rate ratio of PF3 in the processing gas is low), it was confirmed that the etching rate of the monolayer film SL is lower than the etching rate of the multilayer film ML. On the other hand, in the region where the flow rate of PF3 is high (the region where the flow rate ratio of PF3 in the processing gas is high), it was confirmed that the ratio of the etching rate of the monolayer film SL to the etching rate of the multilayer film ML can be made closer to 1. In a state where phosphorus chemical species generated from the plasma of the phosphorus-containing gas (the gas containing the above-mentioned phosphorus-containing molecules) is present on the surface of the silicon oxide film, the adsorption of hydrogen fluoride, i.e., the etchant, to the silicon oxide film is promoted. This causes phosphorus species generated from the phosphorus-containing gas to be present on the surface of the silicon oxide film exposed at the bottom of the opening OPS in the mask film MK, promoting the supply of etchant to the surface and increasing the etching rate of the monolayer film SL.

[0086] Moreover, the etching rates of the silicon oxide film and the silicon nitride film depend on the width (diameter) of the openings OPM and OPS due to the microloading effect. That is, the etching rates of the multilayer film ML and the single layer film SL may differ depending on the recess width (or the width of the openings OPM and OPS) of the multilayer film ML and the single layer film SL. In this embodiment, the recess width (width of the opening OPM) of the single layer film SL is made larger than the recess width (width of the opening OPM) of the multilayer film ML, and plasma is generated from a processing gas containing phosphorus-containing gas, so that the ratio of the etching rate of the single layer film SL to the etching rate of the multilayer film ML can be made 1 or more. In other words, even if the recess widths of the multilayer film ML and the single layer film SL are different, the etching rates of the multilayer film ML and the single layer film SL can be controlled by controlling the flow rate of the phosphorus-containing gas. For example, the etching rate of the single layer film SL2 can be made to be approximately the same as the etching rate of the multilayer film ML when PF3 is at a lower flow rate than the single layer film SL1.

[0087] The above embodiments have been described for the purpose of explanation, and various modifications may be made without departing from the scope and spirit of the present disclosure. For example, in addition to the capacitively coupled plasma processing apparatus 1, a substrate processing apparatus using any plasma source such as an inductively coupled plasma or a microwave plasma may be used. [Explanation of symbols]

[0088] 1...plasma processing apparatus, 10...chamber, 10s...internal space, 12...chamber body, 13...support, 14...substrate support, 16...electrode plate, 18...lower electrode, 20...electrostatic chuck, 24...gas supply line, 25...edge ring, 30...upper electrode, 32...member, 34...top plate, 36...support, 38...gas supply pipe, 40...gas source group, 41...flow rate controller group, 42...valve group, 46...seal , 48... baffle plate, 50... exhaust device, 52... exhaust pipe, 62... high frequency power supply, 64... bias power supply, 66... ​​matching box, 68... matching box, 80... control unit, MK... mask film, ML... multilayer film, OPM... opening, OPS... opening, RCM... recess, RCS... recess, RE1... first region, RE2... second region, SF1... silicon nitride film, SF2... silicon oxide film, SL... single layer film, UF... base film, W... substrate

Claims

1. A preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a single layer film formed of one type of silicon-containing film in the second region; an etching step of simultaneously etching the multilayer film and the single layer film; Including, In the etching step, the multilayer film and the single layer film are simultaneously etched by plasma generated from a process gas including hydrogen fluoride gas, a phosphorus-containing gas, and a carbon-containing gas; a first recess having a first width is formed in the multilayer film; a second recess having a second width wider than the first width is formed in the monolayer film; Etching method.

2. A preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a single layer film formed of one type of silicon-containing film in the second region; an etching step of simultaneously etching the multilayer film and the single layer film; Including, In the etching step, the multilayer film and the single layer film are etched by plasma generated from a process gas including a hydrogen fluoride gas, a phosphorus-containing gas, and a carbon-containing gas; A first recess is formed in the multilayer film; A second recess is formed in the monolayer film. Etching method.

3. A preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a single layer film formed of one type of silicon-containing film in the second region; an etching step of simultaneously etching the multilayer film and the single layer film; Including, In the etching step, the multilayer film and the single layer film are etched by plasma generated from a process gas including a phosphorus-containing gas, a fluorine-containing gas, a hydrofluorocarbon gas, and a halogen-containing gas containing a halogen element other than fluorine; a first recess having a first width is formed in the multilayer film; a second recess having a second width wider than the first width is formed in the monolayer film; Etching method.

4. A preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a single layer film formed of one type of silicon-containing film in the second region; an etching step of simultaneously etching the multilayer film and the single layer film; Including, In the etching step, the multilayer film and the single layer film are etched by plasma generated from a process gas including a phosphorus-containing gas, a fluorine-containing gas, a hydrofluorocarbon gas, and a halogen-containing gas containing a halogen element other than fluorine; A first recess is formed in the multilayer film; A second recess is formed in the monolayer film. Etching method.

5. The substrate is a mask film provided on the multilayer film and the single layer film, the mask film having a first sidewall that defines a first opening on the multilayer film and a second sidewall that defines a second opening on the single layer film; Including, In the etching step, the first recess is formed by etching the multilayer film in the first opening with the plasma; 5. The etching method according to claim 1, wherein the second recess is formed by etching the single layer film in the second opening with the plasma.

6. 6. The etching method according to claim 1, wherein one of the first recess and the second recess is a hole, and the other of the first recess and the second recess is a slit.

7. the two or more types of silicon-containing films include a silicon oxide film and a silicon nitride film; The etching method according to claim 1 , wherein the one type of silicon-containing film is a silicon oxide film.

8. 8. The etching method according to claim 1, wherein the phosphorus-containing gas is a halogenated phosphorus gas.

9. 3. The etching method according to claim 1, wherein the carbon-containing gas is a hydrocarbon gas, a fluorocarbon gas, or a hydrofluorocarbon gas.

10. A preparation step of preparing a substrate having a first region and a second region, the substrate having a multilayer film in which two or more types of silicon-containing films are stacked in the first region and a single layer film formed of one type of silicon-containing film in the second region; a first etching step of simultaneously etching the multilayer film and the single layer film; a second etching step of etching at least one of the multilayer film and the single layer film; Including, In the first etching step, the multilayer film and the single layer film are etched by plasma generated from a first process gas including hydrogen fluoride gas and a phosphorus-containing gas; A first recess is formed in the multilayer film; A second recess is formed in the monolayer film; In the second etching step, the multilayer film and the single layer film are etched by plasma generated from a second process gas including hydrogen fluoride gas and a phosphorus-containing gas; a third recess is formed in at least one of the multilayer film and the single layer film; a flow rate of the phosphorus-containing gas contained in the first process gas is different from a flow rate of the phosphorus-containing gas contained in the second process gas; Etching method.

11. The etching method according to claim 10 , wherein the second etching step is performed after the first etching step is performed.

12. The etching method according to claim 10 , wherein the first etching step is performed after the second etching step is performed.

13. the substrate is a substrate on which a plurality of semiconductor memory devices are formed, the first region is a region in which a plurality of memory cells are formed in each of the plurality of semiconductor memory devices; 13. The etching method according to claim 10, wherein the second region is a region in which a plurality of contacts are formed that electrically connect the plurality of memory cells to a circuit that controls the plurality of memory cells in each of the plurality of semiconductor memory devices.

14. In the first etching step, a plurality of memory holes in which the plurality of memory cells are formed are formed in the multilayer film as the first recesses; a plurality of contact holes in which the plurality of contacts are to be formed are formed in the single layer film as the second recesses; In the second etching step, 14. The etching method according to claim 13, wherein a slit extending from the first region to the second region is formed as the third recess in the multilayer film and the single layer film.

15. In the first etching step, a plurality of memory holes in which the plurality of memory cells are formed are formed in the multilayer film as the first recesses; a slit extending from the first region to the second region is formed in the first recess and in the multilayer film and the single layer film; In the second etching step, 14. The etching method according to claim 13, wherein a plurality of contact holes in which the plurality of contacts are to be formed are formed in the single layer film as the second recesses.

16. In the first etching step, a plurality of contact holes in which the plurality of contacts are to be formed are formed in the single layer film as the second recesses; a slit extending from the first region to the second region is formed in the multilayer film and the single layer film as the first recess and the second recess, In the second etching step, 14. The etching method according to claim 13, wherein a plurality of memory holes in which the plurality of memory cells are to be formed are formed in the multilayer film as the first recesses.

17. In the first etching step, a slit extending from the first region to the second region is formed in the multilayer film and the single layer film as the first recess and the second recess, In the second etching step, a plurality of memory holes in which the plurality of memory cells are formed are formed in the multilayer film as the first recesses; 14. The etching method according to claim 13, wherein a plurality of contact holes in which the plurality of contacts are to be formed are formed in the single layer film as the second recesses.

Images