Wiring board and method for manufacturing the same

Abstract

To provide a wiring substrate with high reliability of a wiring unit against warping of the substrate during heating and stress inside a conductor layer, and a manufacturing method of the same in a system where a fine conductor layer is formed on a support substrate and mounted on an FC-BGA substrate.SOLUTION: A wiring substrate includes a first wiring substrate and a second wiring substrate on which a wiring pattern finer than that of the first wiring substrate is formed and which is bonded to the first wiring substrate. In the wiring substrate in which a semiconductor element is mounted on the opposite side of a bonding surface of the second wiring substrate with the first wiring substrate, a cross-sectional structure of the wiring unit of the second wiring substrate is a convex shape that is higher than a photosensitive resin layer of the same layer.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] In recent years, as semiconductor devices become faster and more highly integrated, there is a demand for narrower pitches for connection terminals with semiconductor elements and finer board wiring for FC-BGA (Flip Chip-Ball Grid Array) wiring boards. On the other hand, there is a demand for connection between FC-BGA wiring boards and motherboards using connection terminals with almost the same pitch as before. To achieve this narrower pitch for connection terminals with semiconductor elements and finer board wiring, a method is known in which wiring is formed on silicon to serve as a substrate (silicon interposer) for connecting semiconductor elements and then connected to the FC-BGA wiring board.

[0003] Patent Document 1 discloses a method of forming fine wiring after planarizing the surface of an FC-BGA wiring board by CMP (Chemical Mechanical Polishing) or the like. Patent Document 2 discloses a method of forming a narrow-pitch wiring board by forming a fine wiring layer on a support substrate, mounting it on an FC-BGA wiring board, and then peeling off the support substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-225671 A [Patent Document 2] International Publication No. 2018 / 047861 [Patent Document 3] JP 2015-012237 A Summary of the Invention [Problem to be solved by the invention]

[0005] Silicon interposers are manufactured using silicon wafers with equipment for semiconductor front-end processing. Silicon wafers are limited in shape and size, and only a small number of interposers can be manufactured from one wafer. In addition, the manufacturing equipment is expensive, so the interposers are also expensive. In addition, because silicon wafers are semiconductors, there is a problem of degradation of transmission characteristics.

[0006] In addition, in the method of flattening the surface of an FC-BGA wiring substrate and then forming a fine wiring layer on top of it, the degradation in transmission characteristics seen with silicon interposers is small, but there are problems with reduced yield within the same substrate due to the combination of manufacturing defects in the FC-BGA wiring substrate and defects during the highly difficult formation of the fine wiring, as well as problems in mounting semiconductor elements due to warping and distortion of the FC-BGA wiring substrate.

[0007] On the other hand, forming a fine wiring layer on a support substrate and mounting it on a wiring board for FC-BGA poses the following problems: A fine wiring layer is formed by forming trenches in a photosensitive resin layer, filling them with wiring material, and using the damascene method with CMP.

[0008] In this case, when a wiring section consisting of a wiring pattern section, a connection via section, a land section, etc. is formed by CMP, the wiring section made of a metal material is over-polished, and the cross-sectional shape of the wiring pattern section, the connection via section, and the land section is finished in a concave shape.

[0009] When forming a connection via on the concave land portion through an insulating resin layer, the insulating resin layer is exposed to light and developed. The thickness of the photosensitive resin layer to be removed increases by the amount of the depression, and resin residue remains at the bottom of the resin trench portion of the connection via in the opened photosensitive resin layer, causing poor conductivity in the formed connection via portion.

[0010] Furthermore, in reliability tests, there was a problem in that migration progressed between adjacent wirings through the interface between the lower and upper photosensitive resin layers formed by stacking wiring layers using the damascene method, resulting in reduced reliability.

[0011] SUMMARY OF THE PRESENT DISCLOSURE The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a wiring board having high connection reliability of wiring portions and a method for manufacturing the wiring board. [Means for solving the problem]

[0012] As a means for solving the above problems, the present invention as set forth in claim 1 provides a semiconductor device comprising a first wiring board and a second wiring board joined to the first wiring board and having finer wiring than the first wiring board, the second wiring board has a resin trench portion formed of a wiring pattern portion, a connection via portion, and a land portion opened in a photosensitive resin layer, a seed adhesion layer and a seed layer covering the side and bottom surfaces of the resin trench portion, and a wiring portion in which the inside of the resin trench portion is filled with a conductive material, and has a structure in which two or more conductor layers formed of the wiring portion are laminated; The wiring board is characterized in that the cross-sectional shapes of the wiring pattern portion, the connection via portion and the land portion of the wiring portion are convex shapes higher than the surface of the photosensitive resin layer of the same layer.

[0013] With this configuration, the present invention has an advantage that it is possible to manufacture a highly reliable wiring board free from breaks and short circuits.

[0014] The invention described in claim 2 is as follows: a difference between the height of the surface of the photosensitive resin layer of the same layer as the wiring portion of the second wiring board and the height of the top of the convex shape of the wiring portion is a D value; an upper photosensitive resin layer on a surface of the photosensitive resin layer; 2. The wiring board according to claim 1, wherein the height of the interface between the photosensitive resin layer and the upper photosensitive resin layer is lower by a value D than the height of the top of the wiring portion.

[0015] The invention described in claim 3 is a wiring board characterized in that the height D value of the top of the convex shape of the wiring portion of the second wiring board from the surface of the photosensitive resin layer of the same layer is 1 μm or less, and the length W from the top surface of the wiring portion to the end of the resin trench is a width of 1 / 2*D to 1*D.

[0016] In addition, the invention described in claim 4 is a wiring board in which the second wiring board is a multilayer wiring board, and a via wiring portion connecting layers of the multilayer wiring board is convex in shape and has a seed adhesion layer on one side on which a semiconductor element is mounted and on a side surface.

[0017] The invention described in claim 5 is a wiring board, wherein the conductor layer is a layer containing copper.

[0018] The invention described in claim 6 is a wiring board, wherein the seed layer is a layer containing copper.

[0019] The invention described in claim 7 is a wiring board, wherein the seed adhesion layer is a layer containing titanium.

[0020] In addition, the invention described in claim 8 is such that the interlayer insulating layer of the second wiring board is a photosensitive insulating resin. The wiring board is characterized in that

[0021] The invention described in claim 9 provides a method for forming a conductor layer of a second wiring board, comprising: 1) forming a photosensitive resin layer having a resin trench portion on a support; 2) providing a seed adhesion layer and a seed layer on the resin trench portion and the photosensitive resin layer; 3) depositing a conductive material on the seed layer as a solid film; 4) chemically polishing the conductive material formed as a solid film from the laminated surface of the substrate, and polishing and removing unnecessary conductive material formed on the surface of the photosensitive resin layer other than the resin trench; 5) polishing and removing the seed adhesion layer, the seed layer, the conductive material, and the surface of the photosensitive resin layer on the substrate surface exposed in 4) to form a conductor layer having a wiring portion in which the resin trench is filled with a conductive material; 6) A method for manufacturing a wiring board, characterized in that steps 1) to 5) are repeated for the required number of layers to form two or more stacked conductor layers.

[0022] The invention described in claim 10 is a method for manufacturing a wiring board, characterized in that the seed adhesion layer and the seed layer are formed by a sputtering method.

[0023] The invention according to claim 11 provides a method for manufacturing a wiring board, wherein the support is made of glass. Effect of the Invention

[0024] According to the present invention, in a second wiring board in which a fine wiring layer is formed on a support substrate and mounted on an FC-BGA substrate, the electrical connection reliability of the via connection portion between the wiring layers and the insulation reliability between the wirings can be improved, thereby eliminating breaks and short circuits and improving the reliability of the wiring board. [Brief description of the drawings]

[0025] [Figure 1] 1A is a cross-sectional view showing a state in which a release layer has been formed on a support, FIG. 1B is a cross-sectional view showing a state in which a photosensitive resin layer has been formed, and FIG. 1C is a cross-sectional view showing a state in which a seed adhesion layer has been formed. [Diagram 2] 1D is a cross-sectional view showing a state where a seed layer is formed, FIG. 1E is a cross-sectional view showing a state where a conductor layer is formed, and FIG. 1F is a cross-sectional view showing a state where the conductor layer and the seed layer are polished by surface polishing. [Diagram 3] 1A and 1B are cross-sectional views showing a state in which the seed adhesion layer and the photosensitive resin layer are polished by surface polishing to form an electrode for bonding with a semiconductor element, a state in which the photosensitive resin layer of the connection via portion is formed, and a state in which the photosensitive resin layer of the connection via portion and the wiring pattern portion are formed. [Figure 4] 13A to 13C are cross-sectional views showing a state where a seed adhesion layer is formed, a state where a seed layer is formed, and a state where a conductor layer is formed, respectively. [Diagram 5] 1M is a cross-sectional view showing the state in which a connection via portion and a wiring pattern portion have been formed by surface polishing. [Figure 6]3(A) is a cross-sectional view showing a state in which a multilayer wiring is formed by repeating the steps of FIG. 3(H) to FIG. 5(M), and FIG. [Figure 7] 1C is a cross-sectional view showing a state in which a seed adhesion layer has been formed, and FIG. [Figure 8] 4E is a cross-sectional view showing a state in which a resist pattern is formed, and FIG. 4F is a cross-sectional view showing a state in which a conductor layer is formed. [Figure 9] 1G is a cross-sectional view showing a state after the resist pattern has been removed, and FIG. 1H is a cross-sectional view showing a state after the unnecessary seed adhesion layer and seed layer have been etched away. [Figure 10] 1(I) is a cross-sectional view showing a state where a solder resist layer is formed, and FIG. 1(J) is a cross-sectional view showing a state where a surface treatment layer and a solder joint are formed and a wiring board on a support is completed. [Figure 11] 1A is a cross-sectional view showing a state in which a wiring board on a support body and an FC-BGA substrate are joined and sealed with an underfill layer, and FIG. 1B is a cross-sectional view showing a state in which a release layer is irradiated with laser light. [Figure 12] 1C is a cross-sectional view showing a state where the support body has been removed, and FIG. [Figure 13] FIG. 4 is an enlarged detailed cross-sectional view of the portion surrounded by AA′ in FIG. [Figure 14] FIG. 4 is an enlarged detailed cross-sectional view of the AA′ surrounding portion of the structure corresponding to FIG. 3(H) in a comparative example. [Figure 15] 6 is an enlarged detailed cross-sectional view of the BB' surrounding portion in FIG. 5(M) in this embodiment. [Figure 16] FIG. 6 is an enlarged detailed cross-sectional view of a BB′ surrounding portion of a structure corresponding to FIG. 5(M) in a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0027] In addition, the embodiments shown below are merely examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0028] An example of a manufacturing process for a wiring board using a support 1 according to one embodiment of the present invention will be described with reference to FIGS.

[0029] First, as shown in FIG. 1(A), a release layer 2 necessary for peeling off the support 1 in a later step is formed on one surface of the support 1.

[0030] The release layer 2 may be, for example, a resin that becomes peelable by absorbing light such as UV light and generating heat or by being altered, or a resin that becomes peelable by foaming due to heat. When using a resin that becomes peelable by light such as UV light, for example laser light 13, light is irradiated onto the support 1 from the side opposite to the side where the release layer 2 is provided, and the support 1 is removed from the bonded body of the wiring board 11 on the support and the FC-BGA substrate 12.

[0031] The release layer 2 can be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, and inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers. Furthermore, the release layer 2 may contain additives such as a photodecomposition accelerator, a light absorber, a sensitizer, and a filler.

[0032] Furthermore, the release layer 2 may be composed of multiple layers, and for example, for the purpose of protecting the multilayer conductor layer formed on the support 1, a protective layer may be further provided on the release layer 2, or a layer for improving adhesion to the support 1 may be provided under the release layer 2. Furthermore, a laser light reflecting layer or a metal layer may be provided between the release layer 2 and the multilayer conductor layer, and the configuration is not limited by this embodiment.

[0033] The support 1 is preferably transparent, for example, glass, since light may be irradiated onto the peeling layer 2 through the support 1. Glass has excellent flatness and high rigidity, making it suitable for forming a fine pattern on the wiring board 11 on the support. In addition, glass has a small CTE (coefficient of thermal expansion) and is resistant to distortion, making it excellent for ensuring pattern arrangement accuracy and flatness.

[0034] When glass is used as the support 1, the glass is preferably thicker in order to suppress the occurrence of warping in the manufacturing process, for example, 0.7 mm or more, preferably 1.1 mm or more. The CTE of the glass is preferably 3 ppm or more and 15 ppm or less, and more preferably about 9 ppm in terms of the CTE of the FC-BGA wiring board 12 and the semiconductor element 15. As the glass, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, or the like is used.

[0035] On the other hand, in cases where light transmittance is not required for the support 1 when peeling off the support 1, for example, when a resin that foams when heated is used for the peel-off layer 2, the support 1 can be made of a material with less distortion, such as metal or ceramics.

[0036] In one embodiment of the present invention, the release layer 2 is made of a resin that absorbs UV light and becomes peelable, and the support 1 is made of glass.

[0037] 1(B), a photosensitive resin layer 3 is formed as an insulating layer. In this embodiment, for example, a photosensitive epoxy resin is formed by spin coating as the photosensitive resin layer 3. Photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little due to curing after formation, so it is excellent for the subsequent formation of fine patterns.

[0038] When a liquid photosensitive resin is used, the method for forming the photosensitive resin layer 3 can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like photosensitive resin is used, lamination, vacuum lamination, vacuum pressing, and the like can be applied.

[0039] For the photosensitive resin layer 3, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, or a modified product thereof can be used as an insulating resin.

[0040] Next, a resin trench portion 21 is provided in the photosensitive resin layer 3 by photolithography. A plasma treatment may be performed on the resin trench portion 21 for the purpose of removing resin residues remaining after development. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the opening, and in one embodiment of the present invention, the thickness is set to, for example, 7 μm.

[0041] The shape of the openings in plan view is set according to the pitch and shape of the bonding electrode pads TP for the semiconductor element 15. In one embodiment of the present invention, the openings have a diameter of 25 μm and are formed at a pitch of 55 μm.

[0042] Next, as shown in Fig. 1(C) and Fig. 2(D), a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum. The seed adhesion layer 4 is a layer that improves the adhesion of the seed layer 5 to the photosensitive resin layer 3 and prevents the seed layer 5 from peeling off.

[0043] The seed layer 5 acts as a power supply layer for electrolytic plating in forming the wiring portion. The seed adhesion layer 4 and the seed layer 5 are formed by, for example, a sputtering method or a vapor deposition method. For example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, Cu alloys, or combinations of two or more of these can be applied.

[0044] In the present invention, taking into consideration electrical characteristics, ease of manufacture, and cost, a titanium layer is formed on the seed adhesion layer 4, and then a copper layer of the seed layer 5 is formed in this order by sputtering. The total thickness of the titanium of the seed adhesion layer 4 and the copper layer of the seed layer 5 is preferably 1 μm or less as a power supply layer for electrolytic plating. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are formed.

[0045] 2(E), a conductor layer 6 is formed as a solid film by electrolytic plating. The conductor layer 6 becomes an electrode pad portion TP for bonding with the semiconductor element 15.

[0046] Examples of the electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. Of these, electrolytic copper plating is preferred because it is simple, inexpensive, and has good electrical conductivity.

[0047] The thickness of the electrolytic copper plating is desirably 1 μm or more from the viewpoint of solder bonding and 30 μm or less from the viewpoint of productivity, since the electrolytic copper plating serves as an electrode for bonding to the semiconductor element 15. In one embodiment of the present invention, Cu: 9 μm is formed in the openings of the photosensitive resin layer 3, and Cu: 2 μm is formed on the upper part of the photosensitive resin layer 3.

[0048] 2(F), the copper conductor layer 6 of the solid film on the surface of the photosensitive resin layer is polished and removed by CMP (chemical mechanical polishing) which has a chemical polishing effect on the conductive material of the conductor layer, and polishing is performed so that the seed adhesion layer 4 and the conductor layer 6 become the surface. In one embodiment of the present invention, Cu: 2 μm of the conductor layer 6 on the top of the photosensitive resin layer 3 and Cu: 300 nm constituting the seed layer 5 are removed by polishing.

[0049] Next, as shown in FIG. 3(G), the seed layer 5, the seed adhesion layer 4, the photosensitive resin layer 3, and a portion of the conductor layer 6, as well as the seed layer 5 and the seed adhesion layer 4, are physically polished and removed by physical polishing.

[0050] Since the polishing is performed on dissimilar materials, the seed adhesion layer 4 and the photosensitive resin layer 3, chemical polishing is less effective and physical polishing using an abrasive is predominant.

[0051] By adjusting the polishing speed of the conductor layer 6 and the photosensitive resin layer 3 and increasing the polishing speed of the photosensitive resin layer 3, the conductor layer 6 of the present invention can be made to have a convex, elevated shape as shown in FIG.

[0052] As shown in the cross-sectional view of Fig. 13 showing the details of the portion surrounded by AA' in the cross-sectional view of Fig. 3(G), the conductor layer 6 is formed in a convex shape. That is, the conductor layer 6 in the portion of the bonding electrode pad portion TP is formed in a convex shape with its upper surface being higher than the upper surface of the photosensitive resin layer 3 in the same layer. This has the effect of making it possible to form a lower opening Pa without resin residue 22 at the bottom as in Fig. 14 of the comparative example when opening a lower opening Pa for a connection via portion 19 in the photosensitive resin layer 3b formed on the upper layer of the conductor layer 6.

[0053] The height D of the convex shape in Fig. 13 may be set to 1 µm or less in order to ensure the flatness of the upper photosensitive resin layer 3b when the photosensitive resin layer 3b is laminated in the next process. If the height of the wiring pattern section 18 formed later in Fig. 5(M) is less than 3 µm, it is desirable to form the height D to be 1 / 3 or less of the height of the wiring pattern section 18. If this occurs, the wiring pattern portion 18 may fall off during polishing, or the flat portion of the upper surface of the wiring pattern portion 18 may disappear, making it difficult to control the height and wiring resistance of the wiring pattern portion 18.

[0054] Other effects of physical polishing and the W value will be described in detail in the manufacturing process from FIG. 4(L) onwards, as their effects become more pronounced.

[0055] For the purpose of simplifying the process, an appropriate amount of abrasive particles may be added to the abrasive for the chemical polishing described above (FIG. 2(F)) to adjust the polishing speed of the conductor layer 6 and the photosensitive resin layer 3 to realize the cross-sectional shape of the present invention, and for the purpose of improving the efficiency of polishing, the polishing method may be changed depending on the material types of the seed adhesion layer 4 and the photosensitive resin layer 3. Then, the conductor layer 6 remaining after polishing becomes the bonding electrode pad portion TP with the semiconductor element 15.

[0056] Next, as shown in Fig. 3(H), a photosensitive resin layer 3b is formed as an insulating layer on the upper surface in the same manner as in Fig. 1(B). The thickness of the photosensitive resin layer 3b is set according to the height of the connection via portion 19 formed by the thickness of the conductor layer 6b filled in the lower opening Pa of the photosensitive resin layer 3b, and in one embodiment of the present invention, the thickness is, for example, 2 µm. This lower opening Pa has a shape that becomes the connection via portion 19 that connects the upper and lower layers of the multilayer conductor layer. The shape of the lower opening Pa in plan view is set from the viewpoint of the connection of the connection via portion 19 of the conductor layer 6 and the conductor layer 6b, and in one embodiment of the present invention, an opening shape of, for example, φ10 µm is formed.

[0057] Furthermore, as shown in Fig. 3(I), a photosensitive resin layer 3c is formed on the upper surface in the same manner as in Fig. 1(B). The wiring openings Pc of the photosensitive resin layer 3c are openings for forming the wiring pattern portion 18 of the multilayer conductor layer. The thickness of the photosensitive resin layer 3c is set according to the thickness of the wiring pattern portion 18 formed by the thickness of the conductor layer 6b filled in the wiring openings Pc of the photosensitive resin layer 3c, and in one embodiment of the present invention, the thickness is set to, for example, 2 µm.

[0058] Moreover, the upper opening Pb of the photosensitive resin layer 3c has a shape that allows the conductor layer 6b to be filled therein to become the land portion 20. The shape of the upper opening Pb in a plan view is set from the viewpoint of the connectivity of the laminate, and is formed so as to surround the outside of the shape of the lower opening Pa. In one embodiment of the present invention, the shape of the upper opening Pb forms an opening shape of, for example, φ25 μm.

[0059] The lower opening Pa of the photosensitive resin layer 3b and the upper opening Pb of the photosensitive resin layer 3c are resin trench portions 21 which become connection via portions 19 and land portions 20 which connect the upper and lower layers.

[0060] As will be described below, the connection via portion 19 and the land portion 20 formed in the resin trench portion 21, and the wiring pattern portion 18 formed in the wiring opening portion Pc are initially formed from an integral conductor layer 6b.

[0061] Next, as shown in Figures 4(J) and 4(K), a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum in the same manner as in Figures 1(C) and 2(D). In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are formed.

[0062] Next, as shown in Fig. 4(L), a conductor layer 6b is formed as a solid film by electrolytic plating. The conductor layer 6b becomes a wiring section consisting of a connection via section 19, a land section 20, and a wiring pattern section 18. Examples of electrolytic plating include nickel electrolytic plating, copper electrolytic plating, chromium electrolytic plating, Pd electrolytic plating, gold electrolytic plating, rhodium electrolytic plating, and iridium electrolytic plating. However, copper electrolytic plating is preferable because it is simple, inexpensive, and has good electrical conductivity.

[0063] The thickness of the electrolytic copper plating is desirably 0.5 μm or more from the viewpoint of electrical resistance of the wiring portion, and 30 μm or less from the viewpoint of productivity. In the double opening formed by the inner opening Pa and the upper opening Pb of the photosensitive resin layer 3c, Cu: 6 μm is formed, in the single opening formed by the wiring opening Pc of the photosensitive resin layer 3c, Cu: 4 μm is formed, and in the upper part of the photosensitive resin layer 3c, Cu: 4 μm is formed.

[0064] Next, as shown in FIG. 5(M), the solid copper conductor layer 6b on the upper part of the photosensitive resin layer 3c is polished and removed by CMP (chemical mechanical polishing), which has a chemical polishing effect on the conductive material of the conductor layer 6b, and polishing is performed so that the seed adhesion layer 4 and the conductor layer 6b become the surface.

[0065] Next, the seed layer 5 and the seed adhesion layer 4 are removed by physical polishing, which physically polishes and removes the photosensitive resin layer 3c, part of the conductor layer 6b, and the seed layer 5 and the seed adhesion layer 4, and removes the photosensitive resin layer 3c and part of the conductor layer 6b, thereby forming a structure as shown in Figure 15.

[0066] That is, the conductor layer 6b remaining in the resin trench portion 21 after polishing becomes a wiring portion consisting of the connection via portion 19, the land portion 20, and the wiring pattern portion 18.

[0067] In one embodiment of the present invention, 4 μm of Cu of the conductor layer 6b on the upper part of the photosensitive resin layer 3c and 300 nm of Cu constituting the seed layer 5 are removed by polishing.

[0068] Moreover, the conductor layer 6b is formed into a convex shape by physical polishing, and the end of the upper surface of the conductor layer 6b is curved. That is, the wiring portion is formed into a convex shape with the height of its upper surface being higher than the height of the upper surface of the photosensitive resin layer 3c in the same layer. By adjusting the ratio of the polishing speed of the photosensitive resin layer 3c and the conductor layer 6b, the value of the length W from the end point of the R-shaped upper surface portion of the wiring pattern portion 18 to the end of the resin trench portion 21 (W value) can be adjusted.

[0069] If the polishing speed is equal between {photosensitive resin layer 3c} and {conductor layer 6b}, the D value becomes small and the W value becomes large.

[0070] By setting the polishing speed to be {photosensitive resin layer 3c}>{conductor layer 6b}, the D value can be made large and the W value can be made small.

[0071] 15, the greater the difference D in height between the insulating resin interface 17 at the interface between the lower photosensitive resin layer 3c and the upper photosensitive resin layer 3b2 and the upper surface of the conductor layer 6b, the less the effect of stress concentrated at the upper surface end of the conductor layer 6b during a reliability test involving thermal history will be on the insulating resin interface 17, and delamination at the insulating resin interface 17 between the lower photosensitive resin layer 3c and the upper photosensitive resin layer 3b2 can be avoided, which is desirable. Also, short circuits due to migration 23 at the insulating resin interface 17 between adjacent wiring parts such as wiring pattern parts 18 and land parts 20 can be suppressed, which is desirable.

[0072] On the other hand, the height D of the convex shape of the wiring parts such as the wiring pattern part 18 and the land part 20 in FIG. 15 is desirably set to D: 1 μm or less, similar to the height D of the convex shape in FIG. 13, in order to ensure the flatness of the upper photosensitive resin layer 3b2 when the photosensitive resin layer 3b2 is laminated in the next process.

[0073] Also, the smaller the W value, the higher the upper surface position where the stress of the conductor layer 6b is concentrated, and migration 23 occurring at the insulating resin interface 17 between the wiring pattern portions 18 can be suppressed, so that W value = 1 / 2*D to 1*D is preferable. Note that * is a symbol that represents a product.

[0074] As shown in Fig. 6(A), a multilayer wiring is formed by adding a conductor layer 6b2 and insulating resin layers 3b2 and 3c2 as interlayer insulating layers by repeating Fig. 3(H) to Fig. 5(M). In one embodiment of the present invention, a multilayer wiring board is manufactured in which two wiring layers, a wiring layer of a conductor layer 6b and a wiring layer of a conductor layer 6b2, are formed.

[0075] Next, a description will be given of a process for forming an electrode TIN for bonding to the FC-BGA substrate 12. As shown in Fig. 6(B), a photosensitive resin layer 3d is formed on the upper surface in the same manner as in Fig. 1(B), and a resin trench portion 21 is formed.

[0076] Next, as shown in FIGS. 7(C) and 7(D), a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum in the same manner as in FIGS. 1(C) and 2(D).

[0077] Next, a resist pattern 7 is formed as shown in Fig. 8(E). Thereafter, a conductor layer 6c is formed by electrolytic plating as shown in Fig. 8(F). The conductor layer 6c becomes an electrode for bonding to the FC-BGA substrate 12. It is desirable that the thickness of the electrolytic copper plating is 1 µm or more from the viewpoint of solder bonding, and 30 µm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 9 µm is formed in the openings of the photosensitive resin layer 3d, and Cu: 7 µm is formed on the upper part of the photosensitive resin layer 3d.

[0078] Thereafter, the resist pattern 7 is removed as shown in Fig. 9(G). Thereafter, the unnecessary seed adhesion layer 4 and the seed layer 5 are etched away as shown in Fig. 9(H). The conductor layer 6c remaining on the surface in this state becomes the electrode TIN for bonding with the FC-BGA substrate 12.

[0079] Next, as shown in FIG. 10(I), a solder resist layer 8 is formed. The solder resist layer 8 is exposed to light and developed so as to cover the photosensitive resin layer 3d, and is formed to have an opening so that the conductor layer 6c is exposed. Note that, as the material of the solder resist layer 8, an insulating resin such as an epoxy resin or an acrylic resin can be used. In the embodiment of the present invention, the solder resist layer 8 is formed using a photosensitive epoxy resin containing farol.

[0080] Next, as shown in FIG. 10(J), a surface treatment layer 9 is provided to prevent oxidation of the surface of the conductor layer 6c and improve wettability of the solder bump. In the embodiment of the present invention, an electroless Ni / Pd / Au plating is formed as the surface treatment layer 9. Note that an OSP (Organic Soiderability Preservative) film may be formed on the surface treatment layer 9. Alternatively, electroless tin plating, electroless Ni / Au plating, or the like may be appropriately selected according to the application. Next, a solder material is mounted on the surface treatment layer 9 on the conductor layer 6c of the bonding electrode TIN, and then melted and cooled once to be fixed, thereby obtaining a solder joint 10. This completes the wiring board 11 on the support 1.

[0081] 11(A), the wiring board 11 on the support is joined to the FC-BGA substrate 12 by the solder joint 10, and the joint is then sealed with an underfill layer. For example, the underfill layer is made of a material in which one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins, is added with silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like as a filler. The underfill layer is formed by filling with a liquid resin.

[0082] Next, as shown in Fig. 11(B), the support 1 is peeled off. The peeling layer 2 is irradiated with laser light 13 to make it peelable. The peeling layer 2 formed at the interface with the support 1 is irradiated with laser light 13 from the rear surface of the support 1, i.e., from the surface of the support 1 opposite to the FC-BGA substrate 12, to make it peelable, thereby making it possible to remove the support 1. Next, as shown in Fig. 12(C), the support 1 is peeled off and removed, and then the peeling layer 2, the seed adhesion layer 4, and the seed layer 5 are removed to obtain a BGA substrate 14 with an interposer.

[0083] 12(D), the electrodes of the semiconductor element 15 are soldered to the bonding electrode pads TP of the BGA substrate 14 with the interposer to complete the semiconductor device 16. Prior to the mounting of the semiconductor element 15, the conductor layer 6 exposed on the surface of the BGA substrate 14 with the interposer as the bonding electrode pads TP with the semiconductor element 15 may be subjected to a surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, electroless Ni / Au plating, etc. to prevent oxidation and improve the wettability of the solder bumps. The semiconductor device 16 is thus completed. EXAMPLES

[0084] Next, the effects of using the configuration of the BGA substrate 14 with an interposer and its manufacturing method as described above will be described with reference to the process explanations of Figures 1 to 10(J), Figure 13 in which the upper surface of the conductor layer 6 in an embodiment illustrating the effects of the present invention is formed in a convex shape, Figure 15 in which the upper surface of the conductor layer 6b is formed in a convex shape, Figure 14 in which the upper surface of the conductor layer 6 in a comparative example is formed in a concave shape, and Figure 16 in which the upper surface of the conductor layer 6b is formed in a concave shape.

[0085] Fig. 13 and Fig. 14 of a comparative example are enlarged detailed sectional views of A-A' portion in Fig. 3(G) and Fig. 3(H), and are sectional views of the bonding electrode pad portion TP with the semiconductor element 15. Fig. 15 and Fig. 16 of a comparative example are enlarged detailed sectional views of B-B' portion in Fig. 5(M) and Fig. 6(A), and are sectional views of the wiring pattern portion 18.

[0086] In this embodiment, the wiring pattern portion 18 of the wiring board 11 on the support, the connection via portion 19, and the bonding electrode pad portion TP with the semiconductor element 15 are formed by patterning the conductor layers 6 and 6b by CMP (chemical mechanical polishing) and physical polishing (the so-called damascene method). Therefore, as shown in Figures 6(A) and 9(H), it is possible to arrange a seed adhesion layer 4 between the conductor layer 6 and the photosensitive resin layer 3 on the side of the wiring pattern portion 18, the side of the connection via portion 19, and the side of the bonding electrode pad portion TP with the semiconductor element 15.

[0087] 11(A) to 12(D), the wiring board 11 on the support is turned upside down, the solder joints 10 of the bonding electrodes TIN are bonded to the FC-BGA substrate 12, and then the support 1 is removed to obtain an interposer-equipped BGA substrate 14. Therefore, in the wiring pattern portion 18 and the connection via portion 19 of the interposer-equipped BGA substrate 14, the seed adhesion layer 4 can be disposed on the upper surface and side surfaces, and in the bonding electrode pad portion TP with the semiconductor element 15, the seed adhesion layer 4 can be disposed on the side surfaces.

[0088] 13, the conductor layer 6 for the bonding electrode TIN was formed in a convex shape higher than the photosensitive resin layer 3. The height D of the conductor layer 6 was set to 0.8 μm, and the W value was set to 0.8 μm. By forming the conductor layer 6 in a convex shape, it was possible to form an opening without resin residue 22 at the bottom of the lower opening Pa when opening the lower opening Pa for the connection via portion 19 in the photosensitive resin layer 3b formed on the upper layer.

[0089] 15, the wiring pattern portion 18 and the land portion 20 were formed in a convex shape by the conductor layer 6b. The wiring pattern portion 18 and the land portion 20 were formed with a height D value of 0.5 μm and a W value of 0.5 μm. By controlling the convex shape with the height D value, when the photosensitive resin layer 3b2 to be laminated on the wiring pattern portion 18 was applied, there were no recessed portions 24 in the photosensitive resin layer 3b2, and surface waviness could be reduced.

[0090] At the same time, the variation in height of the resin trench portion 21, the polishing residue of the conductor layer 6b due to CMP and physical polishing, and the variation in height of the wiring pattern portion 18 were able to be suppressed.

[0091] In addition, by providing a step of D value between the height of the upper surface of the wiring pattern portion 18 and the height of the upper surface of the photosensitive resin layer 3c of the same layer, i.e., the height of the insulating resin interface portion 17 at the interface between the photosensitive resin layer 3c and the photosensitive resin layer 3b2, it is possible to avoid interfacial peeling at the insulating resin interface portion 17 between the photosensitive resin layers 3c and 3b2 due to stress concentration on the upper surface of the wiring pattern portion 18, and to avoid short circuits due to migration 23 occurring at the insulating resin interface portion 17 between adjacent wiring pattern portions 18.

[0092] As described above, by forming the conductor layer 6 for the bonding electrode TIN and the wiring layer 6b consisting of the wiring pattern portion 18 and the land portion 20 in a convex shape, it is possible to stably control the dimensions and shape of the upper wiring layer to be laminated, and this is effective in improving the reliability of electrical connection and the reliability of insulation between wirings.

[0093] As a comparative example, the wiring pattern portion 18 of the wiring board 11 on the support, the connection via portion 19, and the joining electrode pad portion TP with the semiconductor element 15 are described, in which the conductor layer 6 and the conductor layer 6b are patterned (the so-called damascene method) only by CMP (chemical mechanical polishing).

[0094] In the comparative example, the wiring pattern portion 18 of the wiring board 11 on the support, the connection via portion 19, and the bonding electrode pad portion TP with the semiconductor element 15 are patterned (so-called damascene method) by only CMP (chemical mechanical polishing) using an abrasive that selectively chemically polishes the conductor layer 6 and the conductor layer 6b. Next, the seed adhesion layer 4 that cannot be polished by CMP is dissolved and removed by chemical polishing using wet etching, and as shown in Figures 6(A) and 9(H), it is possible to arrange the seed adhesion layer 4 between the conductor layer 6 and 6b and the photosensitive resin layer 3, 3b, or 3c on the side of the wiring pattern portion 18 and the connection via portion 19, and on the side of the conductor layer 6 of the bonding electrode pad portion TP.

[0095] 11(A) to 12(D), the wiring board 11 on the support is turned upside down and bonded to the FC-BGA substrate 12, and then the support 1 is removed to obtain a BGA substrate with an interposer. Therefore, in the wiring pattern portion 18 and the connection via portion 19, the seed adhesion layer 4 can be disposed on the upper surface and side surfaces, and the seed adhesion layer 4 can be disposed on the side surfaces of the conductor layer 6 of the bonding electrode pad portion TP with the semiconductor element 15.

[0096] However, as shown in FIGS. 14 and 16, since the photosensitive resin layers 3 and 3c are not polished by CMP, the outermost surfaces of the conductor layer 6 in which the bonding electrode pad portions TP are formed and the conductor layer 6b in which the wiring pattern portions 18 and the land portions 20 are formed have a concave shape lower than the photosensitive resin layer 3 and the photosensitive resin layer 3c in the same layer.

[0097] Because the wiring pattern portion 18 and the land portion 20 have a concave shape, when forming an opening for the connection via portion 19 in the resin trench portion 21 of the photosensitive resin layer 3b or 3b2 formed on the upper layer, the coating thickness of the photosensitive resin layer 3b or 3b2 on the conductor layer 6 or the land portion 20 becomes thicker, making it easier for resin residue 22 to remain at the via bottom of the opening in the photosensitive resin layer 3b2 on the land portion 20.

[0098] 16, the upper surface of the wiring pattern portion 18 is concave, which causes a concave 24 in the coating film of the photosensitive resin layer 3b2 or 3d formed on the upper layer. The concave 24 extends to the uppermost surface of the photosensitive resin layer 3c2 on the photosensitive resin layer 3b, and when the conductor layer 6b is formed on the surface of the photosensitive resin layer 3c2 and then the conductor layer on the surface of the photosensitive resin layer 3c2 is removed by CMP, the concave 24 causes a polishing residue of the conductor layer 6b. Therefore, depending on the variation in the height of the resin trench portion 21 and the CMP and chemical polishing, the polishing residue of the conductor layer 6b2 or 6b occurs in the concave 24 on the surface of the photosensitive resin layer 3c2 in FIG. 16 and in the concave portion 24 on the surface of the photosensitive resin layer 3c in FIG. 14, which causes a defective formation of the wiring pattern portion 18.

[0099] In addition, the ends of the recesses in the wiring pattern portions 18 in FIG. 16 and the heights of the insulating resin interface portions 17 between the same layer and the upper layer of the photosensitive resin layer 3 were the same height, and migration 23 occurred at the insulating resin interface portions 17 between adjacent wiring pattern portions 18, causing short circuits in the wiring pattern portions 18.

[0100] <Confirmation of action and effect> To confirm the effect of this embodiment, a reflow test (based on JEDEC J-STD-020) was repeatedly performed at a peak temperature of 260°C on the BGA substrate with interposer 14 produced in the example and the BGA substrate with interposer produced in the comparative example. In the BGA substrate with interposer produced in the comparative example, peeling was observed between the connection via portion 19 and the land portion 20 of the conductor layer 6b and the conductor layer 6 of the bonding electrode pad portion TP, and poor electrical continuity was confirmed. On the other hand, no peeling was observed in the BGA substrate with interposer 14 produced in the example, and no poor electrical continuity occurred.

[0101] In addition, the bias HAST test (130℃*85%RH, 1.3V, 192hr) In the BGA substrate with an interposer produced in the comparative example, delamination and migration 23 were observed at the insulating resin interface 17 between adjacent wiring pattern portions 18 due to the conductor layer 6b, and an electrical short circuit was confirmed. On the other hand, in the BGA substrate with an interposer 14 produced in the example, delamination and electrical short circuit did not occur, and the insulation resistance was 10. 6 We achieved over Ω.

[0102] It should be noted that the above-described embodiment is merely an example, and other specific details and the like can of course be modified as appropriate.

[0103] Furthermore, the present invention is not limited to a BGA substrate with an interposer, but can be used in a semiconductor device having a wiring substrate with an interposer or the like interposed between a main substrate and an IC chip. [Explanation of symbols]

[0104] 1 Support 2. Peel layer 3, 3b, 3b2, 3c, 3c2, 3d photosensitive resin layer 4 Seed adhesion layer 5 Seed layer 6, 6b, 6b2 Conductor layers 7 Resist Pattern 8 Solder resist layer 9 Surface treatment layer 10 Solder joints 11 Wiring board on support 12 FC-BGA board 13 Laser light 14 BGA board with interposer 15 Semiconductor elements 16 Semiconductor Devices 17 Insulating resin interface 18 Wiring pattern section 19 Connection via 20 Land Department 21 Resin Trench 22 Resin Residue 23 Migration 24 Depression in photosensitive resin layer D Height of convex shape Pa Lower opening Pb Top opening PC wiring opening TP bonding electrode pad TIN bonding electrode W: Length from the top surface of the wiring part to the end of the resin trench

Claims

1. A first wiring board; a second wiring board joined to the first wiring board and having finer wiring than the first wiring board; In the wiring board, a semiconductor element is mounted on a surface of the second wiring board opposite to a bonding surface of the first wiring board, the second wiring board has a resin trench portion consisting of a wiring pattern portion, a connection via portion, and a land portion opened in a photosensitive resin layer, a seed adhesion layer and a seed layer covering the side and bottom surfaces of the resin trench portion, and a wiring portion in which the inside of the resin trench portion is filled with a conductive material, and has a structure in which two or more conductor layers consisting of the wiring portion are laminated; the cross-sectional shapes of the wiring pattern portion, the connection via portion, and the land portion of the wiring portion are convex and higher than the surface of the photosensitive resin layer of the same layer; the second wiring board further includes another resin trench portion including a bonding electrode pad portion for bonding with a semiconductor element that is opened in the photosensitive resin layer, a seed adhesion layer and a seed layer that cover the side and bottom surfaces of the other resin trench portion, and another wiring portion in which the inside of the other resin trench portion is filled with a conductive material; a bonding electrode pad portion for bonding to a semiconductor element is located below a connection via portion of the lowest conductor layer formed by laminating; A wiring board characterized in that the cross-sectional shape of the electrode pad portion for bonding to the semiconductor element of the other wiring portion is a convex shape higher than the surface of the photosensitive resin layer of the same layer.

2. a difference between the height of the surface of the photosensitive resin layer of the second wiring board, which is the same layer as the wiring portion, and the height of the top of the convex shape of the wiring portion is a value D; an upper photosensitive resin layer on a surface of the photosensitive resin layer; 2. The wiring board according to claim 1, wherein the height of the interface between the photosensitive resin layer and the upper photosensitive resin layer is lower by a value D than the height of the top of the wiring portion.

3. The wiring board according to claim 2, characterized in that the height D value of the top of the convex shape of the wiring portion of the second wiring board from the surface of the photosensitive resin layer of the same layer is 1 μm or less, and the length W from the top surface of the wiring portion to the end of the resin trench is a width of 1 / 2 * D to 1 * D.

4. The wiring board according to any one of claims 1 to 3, characterized in that the second wiring board is a multilayer wiring board, and a connection via portion connecting layers of the multilayer wiring board has a convex shape, and a seed adhesion layer is provided on one side on which a semiconductor element is mounted and on a side surface.

5. 5. The wiring board according to claim 1, wherein the conductive material is a layer containing copper.

6. 6. The wiring board according to claim 1, wherein the seed layer is a layer containing copper.

7. 7. The wiring board according to claim 1, wherein the seed adhesion layer is a layer containing titanium.

8. 8. The wiring board according to claim 1, wherein the interlayer insulating layer of the second wiring board is a photosensitive insulating resin.

9. The method for forming a conductor layer of the second wiring board includes the steps of: 1) forming a photosensitive resin layer having a resin trench portion on a support; 2) providing a seed adhesion layer and a seed layer on the resin trench portion and the photosensitive resin layer; 3) forming a solid film of a conductive material on the seed layer; 4) chemically polishing the conductive material formed as a solid film from the laminated surface of the substrate, and polishing and removing unnecessary conductive material formed on the surface of the photosensitive resin layer other than the resin trench; 5) polishing and removing the seed adhesion layer, the seed layer, the conductive material, and the surface of the photosensitive resin layer on the substrate surface exposed in 4) to form a conductor layer having a wiring portion in which the resin trench is filled with a conductive material; 6) The method for manufacturing a wiring board according to any one of claims 1 to 8, further comprising repeating steps 1) to 5) for a required number of layers to form two or more layers of conductor layers.

10. 10. The method for manufacturing a wiring board according to claim 9, wherein the seed adhesion layer and the seed layer are formed by a sputtering method.

11. 11. The method for manufacturing a wiring board according to claim 9, wherein the support is made of glass.

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