Manufacturing sequence for high density interconnect printed circuit boards and high density interconnect printed circuit boards - Patents.com

Abstract

The present invention provides a method for fabricating a high density interconnect printed circuit board (HDI PCB) or IC substrate containing copper filled through holes and / or grid structures, comprising: (a) preparing a multilayer substrate, the multilayer substrate comprising: (i) an insulating core layer having a peripheral surface; or (i') a stack assembly comprising an insulating core layer embedded between two conductive intermediate layers, and at least one outer insulating layer mounted on the conductive intermediate layers and having a peripheral surface; (ii) an optional cover layer covering the peripheral surface; and (iii) at least one through hole extending through all layers of the multilayer board; and A lattice structure having a plurality of slots extending through the optional cover layer and partially into the insulating core layer, or extending through at least one of the optional cover layer and the outer insulating layer. and (b) forming a non-copper conductive layer or a copper layer on the inner surface of the lattice structure, on the cover layer, and on the inner surface of each of the through holes; (c) forming a patterned masking film on the non-copper conductive layer or on the copper layer; (d) in one step, electrolytically depositing a copper inner encapsulant inside the through-holes sufficient to form two blind microvias each, and electrolytically depositing a copper inlay on the non-copper conductive layer or copper layer of the inner surface of the lattice structure, and on the remaining peripheral surface of the non-copper conductive layer or copper layer; (e) removing the masking film; (f) electrolytically depositing a copper fill in the blind microvia, in the copper inlay, and on the first copper layer in one step; The present invention relates to a method including:

Description

[Technical field]

[0001] The present invention relates to a manufacturing sequence for a high density interconnect printed circuit board (HDI PCB) and to the high density interconnect printed circuit board obtained by the manufacturing sequence. [Background technology]

[0002] Currently, high density interconnect printed circuit boards (HDI PCBs) are manufactured by methods such as subtractive, semi-additive (SAP), modified semi-additive (mSAP), or advanced modified semi-additive (amSAP), etc. In particular, mSAP and amSAP constitute promising variants for manufacturing the next generation of HDI PCBs that enable ultra-fine microvia structures, line / space widths (L / S) of ≦30 μm, and thus realizing interconnects of higher complexity.

[0003] Furthermore, to prevent localized overheating, a heat dissipation structure needs to be integrated into the HDI PCB. Such a heat dissipation structure can include, for example, through holes extending through the HDI PCB and filled with a thermally conductive material such as copper. Another heat dissipation structure can be a grid provided on the top or bottom surface of the HDI PCB. Also, the holes of the grid structure are filled with a thermally conductive material such as copper. Therefore, the manufacturing process of the HDI PCB can also take into account filling such heat dissipation structures with copper.

[0004] A conventional mSAP sequence starts with a copper clad substrate, where the copper cover layer may be 3-9 μm thick and the substrate contains single or double sided blind microvias (BMVs). The first step of the process is electroless deposition of copper, which distributes a thin metal seed layer (0.35-0.6 μm) on the peripheral surface of the copper clad substrate and on the inner surface of the microvias to provide a conductive base for the subsequent electrolytic deposition step. A subsequent electrolytic deposition of about 3 μm flash copper constitutes the first copper layer, resulting in partially filled microvias. In the next step, the negative of the line pattern (conductive traces) is defined by laminating a patterned dry film (mask). That is, the patterned dry film defines the spacing areas between the conductive traces of the final PCB. In the following step, the substrate is treated with a second electrolytic deposition step using a specific microvia filling electrolyte. However, the use of such a particular electrolyte in the previous step then results in undesirable copper thickness variations between the microvia pad (the outer end of the microvia) and the patterned copper surface that present difficulties in the subsequent etching step, as revealed by the subsequent removal of the dry film.Finally, the trace-to-trace isolation will be achieved by completely etching away the first and second copper layers and the seed and cover layers in the areas previously defined by the dry film.

[0005] As L / S separation shrinks due to the ever-increasing demand for smaller trace widths, excess copper removal becomes an increasingly complex problem. There is a significant risk of unacceptable width reduction as well as undercutting for traces <30 μm wide, as there has always been a tendency to "over-etch" to accommodate plated copper thickness variations and ensure clean inter-trace separation. As a result, reducing the copper layer thickness as well as thickness variations is a desirable objective of the present invention in order to reduce the above-mentioned risks during the etching process. These problems also naturally arise when heat dissipation structures such as through-holes or lattice structures are filled with copper.

[0006] Furthermore, areas of the substrate surface that are perforated to varying degrees are characterized by a high hole density (HHD) surface factor, which is defined as the ratio between the total surface, including interior surfaces, e.g., all vias and / or grid structures (also called total grid area or total grid surface), and the peripheral surface of the corresponding area (also called grid area or grid surface), where: HHD The surface factor is 1 when there are no vias or other structures. The calculation of the inner surface will be affected by the diameter of the vias and lattice structures, the distance of the vias relative to each other, the number of vias in an area, and the thickness of the substrate. A higher HHD surface factor corresponds to more vias, a smaller pitch of the holes (the distance between the via midpoints), a smaller diameter of the vias, and a thicker substrate, e.g., plate, over which the vias and lattice structures extend. The lattice structure may be an important heat dissipation element for efficient temperature regulation of HDI PCBs. However, the lattice structure still constitutes an area with a high HHD factor due to the very close wall-to-wall arrangement of the multiple slots, due to the very small wall-to-wall distance, respectively.

[0007] The HHD surface factor determines the resulting local current density when a voltage is applied; i.e., the higher the HHD surface factor, the lower the current density. As a result, in electrochemical deposition processes, this means that different material states (changing local current densities) result in varying layer thicknesses. However, layer thickness variations can lead to problems with subsequent etching (smoothing) and even reduced layer adhesion in stacked PCB substrates. If the resulting layer thickness variations after filling are too large compared to the complexity of the substrate's surface (areas with high and low HHD surface factors), subsequent process steps cannot be performed and the substrate will be rejected by the customer.

[0008] In this context, filling of microvias, through-holes and / or lattice structures with high HHD surface factors, or again filling of combinations of microvias, through-holes and / or lattice structures with different HHD surface factors, is particularly challenging.

[0009] In the state of the art, various processes are described for filling through-holes.

[0010] For example, US2007 / 0163887A1 describes a method for manufacturing a circuit carrier, which includes the steps of preparing a printed circuit board, coating the circuit board with a dielectric on at least one side thereof, and configuring the dielectric to create trenches and vias therein using laser ablation. A primer layer is then deposited on the dielectric, either on its entire surface or only in the created trenches and vias. A metal layer is deposited on the primer layer, and the trenches and vias are completely filled with metal to form conductor structures therein. Finally, when the primer layer is deposited on its entire surface, the excess metal and primer layer are removed until the dielectric is exposed, leaving the conductor structures intact.

[0011] However, the use of subtractive methods creates a very uneven copper surface distribution between areas with trenches and vias and areas without such structures. This difference cannot be removed, for example, by etching, since all areas would be etched the same way, where the surface height differences would not disappear. Therefore, this method is not suitable for HDI PCB manufacturing with areas of high HHD surface factor. Furthermore, the use of additive methods results in a complete filling with metal, but strong overplating in areas with trenches and vias. This metal must be removed afterwards.

[0012] For example, by using the subtractive method of the prior art, an area of ​​a substrate surface having an HHD surface factor of 1 under given conditions can achieve a metal plating thickness of 10 μm. If, under the same conditions, a substrate surface area A having an HHD surface factor of 1 and an adjacent substrate surface area B having an HHD surface factor of 1.2 are plated (completely filled), the achievable metal plating thickness in area A is again 10 μm, while at the same time, the achievable metal thickness in substrate surface area B is only 8.3 μm, due to the total grid surface being 17% larger. These different heights of the copper surface in the different surface areas result in a height (or plating thickness) difference of 1.7 μm or 17% in this example. As a further example, an HHD surface factor of 3 would result in a 3.3 μm thickness in area B in this example, resulting in a height difference of 6.7 μm or 67%. Such surface thickness differences on the surface of the substrate cannot be easily equalized later. Therefore, the method is not suitable for application in the field of plating of HHD surfaces.

[0013] WO2006 / 032346A1 describes a two-step deposition technique in which two holes are first made from a through-hole by completely or nearly completely filling the hole center, thereby creating a blind via, each closed at one end closer to the hole center. The shape of the deposit in the area of ​​the through-hole center was adjusted by increasing the scattering in the area of ​​the through-hole center to achieve a V-shaped or rounded narrow portion deposit. Subsequent processes for filling the blind via are also known and described in the state of the art.

[0014] One example may be EP1264918A1, which describes an electrolytic copper deposition process that is particularly suitable for filling micro-blind vias, where the use of an insoluble anode in the empty electrolytic treatment phase helps to maintain and improve the filling capacity of the electrolyte.

[0015] However, the efficiency of both steps depends on the perfect control of the (reverse) current pulse applied in these electrochemical processes as the driving force for metal deposition. Since the metal base layer (seed layer) acts as the cathode in these redox systems, obviously the material properties (e.g. conductivity, melting point) constitute a key factor. Typically, the seed layer is made of copper and is formed by electroless deposition. A drawback of such electroless copper seed layers is that their low etching resistance causes problems, especially when high current pulse parameters are applied to allow lower current efficiencies. Moreover, copper seed layers may also not be suitable due to physical properties such as melting point, especially when high current densities are applied to increase the throughput during the filling process. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] US2007 / 0163887A1 [Patent Document 2] WO2006 / 032346A1 [Patent Document 3] EP1264918A1 [Patent Document 4] WO2010 / 094998A1 [Patent Document 5] WO2007 / 112971A2 [Patent Document 6] U.S. Patent No. 5,976,341 [Patent Document 7] U.S. Patent No. 6,099,711 Summary of the Invention [Problem to be solved by the invention]

[0017] It is therefore an object of the present invention to overcome or reduce at least one of the above mentioned disadvantages, as described below. [Means for solving the problem]

[0018] The present invention refers to a method for making a high density interconnect printed circuit board (HDI PCB) or IC substrate containing copper filled through holes and / or grid structures as defined in claim 1. The method comprises the following steps: (a) preparing a multi-layer substrate, the multi-layer substrate comprising: (i) an insulating core layer having a peripheral surface; (i') a stack assembly of an insulating core layer embedded between two conductive intermediate layers, and at least one outer insulating layer mounted on the conductive intermediate layer and having a peripheral surface; (ii) an optional cover layer, preferably made of copper, covering the peripheral surface; and (iii) at least one through hole extending through all layers of the multilayer board; and / or A lattice structure having a plurality of slots extending through the optional cover layer and partially into the insulating core layer, or extending through at least one of the optional cover layer and the outer insulating layer. and (b) forming a non-copper conductive layer or a copper layer on the inner surface of the lattice structure, on the cover layer and on the inner surface of each of the through holes; (c) forming a patterned masking film on the non-copper conductive layer or on the copper layer; (d) in one step, electrolytically depositing a copper inner encapsulant inside the through holes sufficient to form two blind microvias each, and electrolytically depositing a copper inlay on the non-copper conductive layer or copper layer of the inner surface of the lattice structure, and on the remaining peripheral surface of the non-copper conductive layer or copper layer; (e) removing the masking film; (f) electrolytically depositing a copper fill in the blind microvia, in the copper inlay, and on the first copper layer in one step; Includes.

[0019] The electrolytic deposition of step (d) is preferably carried out by reverse pulse plating.

[0020] The electrolytic deposition of step (f) is, for example, Fe 2+ and / or Fe 3+ ions and / or V 4+ and / or V 5+ The plating can be carried out by using a redox system with a source of other suitable redox couples as ions. The plating can be carried out as reverse pulse plating, pulse plating, or DC plating, preferably as reverse pulse plating.

[0021] According to another aspect of the present invention, there is provided a high density interconnect printed circuit board (HDI PCB) or IC substrate comprising copper filled through holes, the HDI PCB being obtained by the method described above.

[0022] Further aspects of the invention can be gleaned from the dependent claims or the following description.

[0023] The expressions "through-holes and / or lattice structures" and "areas of through-hole structures and / or lattice structures" are considered interchangeable in the following description.

[0024] In the present invention, it is particularly possible to fill structures such as through-holes and / or lattice structures, which can be defined as areas of through-hole structures and / or lattice structures with a high HHD surface factor. The higher the HHD surface factor, the more advantageous the use of the present invention becomes. The HHD surface factor is preferably in the range of 1.1 to 5, more preferably 1.1 to 3, most preferably 1.1 to 2.

[0025] It is also possible to fill areas having through-hole structures and / or lattice structures with a high HHD surface factor, preferably 1.1 to 5, more preferably 1.1 to 3, most preferably 1.1 to 2, and at the same time plate areas on the surface of the substrate having an HHD surface factor of 1.

[0026] The HHD surface factors used in the present invention were calculated as follows:

[0027] HHD surface factor = total grid area / grid area The total grid area (also the total grid surface) includes the surface of the area in which the through holes (or at least one through hole) are located, and the surface of the walls of the through holes (which depend on the number, diameter and thickness of the substrate, e.g., board). The surface dimensions are therefore influenced by the wall-to-wall distance between the through holes, the hole pitch (the distance from two adjacent centers of two through holes), the number and diameter of the through holes, and the thickness of the board. A frame area is located around the area of ​​at least one through hole, which also belongs to the total grid area (see FIG. 6(A)). A part of the perimeter of the at least one through hole or the perimeter of the outermost through hole of a number of through holes is directly adjacent to the frame area. While the wall-to-wall distance between the through holes, the number and diameter of the through holes may vary, the frame dimensions of the frame area are fixed for calculating the HHD surface factor up to 1 mm wide (see FIG. 6(B)).

[0028] The grid area (also grid surface) includes the theoretical surface of the area in which the through-hole (or at least one through-hole) is located, but is calculated without said at least one through-hole. Around the area, the same frame area (as in the total grid area) with its theoretical surface is located, which also belongs to the grid area (see FIG. 6(C)).

[0029] As a practical example to obtain a HHD surface factor of 1.76, the following parameters are given: Grid 5x5 through holes - Plate thickness 1.5mm - Hole diameter 0.2mm - Hole pitch 0.4mm - Wall distance 0.2mm - Frame width 1mm - Total grid surface 40.8mm2 - Grid area 28.8mm 2

[0030] The area with through holes preferably has 400-20000 holes, a hole pitch of 0.05-2.0 mm, a hole diameter of 0.05-2.0 mm and a plate thickness of 0.2-3.2 mm.

[0031] After the copper filling step (f), the height difference of the resulting copper plating thickness above the through-holes and / or lattice structures is 0-40% compared to the height without the through-holes and / or lattice structures. The substrate can also include areas without through-holes or lattice structures, as well as areas with through-hole structures and / or lattice structures.

[0032] The copper plating thickness resulting from the copper filling step (f) shall be evenly distributed in terms of height above the through-holes and / or grid structures or, respectively, in terms of height in different areas, where the difference in height of areas with different HHD surface factors is 0-40%, preferably 0-20% of the copper plating thickness.

[0033] In one embodiment of the present invention, a substrate can be applied that includes only areas having through-holes with a higher HHD surface factor, e.g., 2-5, and areas having an HHD surface factor of 1 on the surface of the substrate, the difference in height of the areas being 0-20%.

[0034] In one embodiment of the present invention, a substrate may be provided that includes areas with through-holes and / or lattice structures with different HHD surface factors, e.g., 1.1 to 5, and areas with an HHD surface factor of 1 on the surface of the substrate, the difference in height of the areas being 0 to 40%. The more complex the surface of the substrate, the more tolerable the difference in height of the different areas becomes.

[0035] Furthermore, the method of the present invention can be used to provide a very uniform, comparatively thin and uniform copper surface layer over the filled through-hole and / or lattice structures or areas of the through-hole and / or lattice structures, thereby eliminating or reducing an etching or polishing step after step (f).

[0036] The features will become apparent to those skilled in the art by reading the detailed description of the exemplary embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0037] [Figure 1] 1A to 1F are cross-sectional views illustrating a schematic sequence of steps (a) to (f) of a method according to one embodiment of the present invention. [Diagram 2] 4A to 4F are cross-sectional views illustrating a schematic sequence of steps (a) to (f) of a method according to another embodiment of the present invention. [Diagram 3] 5A-5F are cross-sectional views illustrating the general sequence of steps (a)-(f) of a method according to a further embodiment of the present invention. [Figure 4a] 1A and 1B are schematic cross-sectional and top plan views illustrating a lattice structure according to a first embodiment; [Figure 4b] 5A and 5B are schematic cross-sectional and top plan views illustrating a lattice structure according to a second embodiment. [Diagram 5] 5A-5F are cross-sectional views illustrating the general sequence of steps (a)-(f) of a method according to a further embodiment of the present invention. [Figure 6] 1 is a diagram illustrating HHD surface factors (A) to (C). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. Advantages and features of the exemplary embodiments, as well as methods of implementation thereof, will be described with reference to the accompanying drawings. In the drawings, like reference numerals indicate like elements and redundant description is omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Furthermore, the use of "may" when describing embodiments of the present invention refers to "one or more embodiments of the present invention."

[0039] In the following description of embodiments of the present invention, singular terms may include plurals unless the context clearly dictates otherwise.

[0040] In the drawings, the size of elements may be exaggerated for clarity. For example, in the drawings, the size or thickness of each element may be appropriately illustrated for illustrative purposes, and therefore, the embodiments of the present invention should not be considered as being limited thereto.

[0041] The features of the concept of the present invention and the method of achieving it can be more easily understood by referring to the following detailed description of the embodiments and the attached drawings. Hereinafter, exemplary embodiments will be described in more detail with reference to the attached drawings, in which like reference numerals refer to like elements throughout. However, the present invention can be embodied in various different forms and should not be considered limited to only the embodiments described herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present invention to those skilled in the art. Thus, processes, elements, and techniques that are not necessary for those skilled in the art to fully understand the aspects and features of the present disclosure may not be described.

[0042] As used herein, "approximately," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for inherent variations in measurements or calculations that would be appreciated by one of ordinary skill in the art. Furthermore, when the term "approximately" is used in conjunction with a feature that can be expressed using a numerical value, the term "approximately" indicates a range of + / - 5% of the value around that value. Furthermore, the use of "may" when describing an embodiment of the invention refers to "one or more embodiments of the invention." In this specification, the terms "top" and "bottom" are defined according to the z-axis. For example, the cover is positioned at the top of the z-axis, while the ground plate is positioned at the bottom.

[0043] As used herein, the term "copper plating thickness" or "height" refers to the thickness of the deposited / plated copper layer in step (f). The thickness of the copper layer or their height may be different if the layer is deposited to fill through-holes and / or lattice structures located in the plane of the substrate. Thus, a given value of the thickness or height of the copper layer is calculated starting from the face of the substrate (including the conformal layer of the above mentioned step) that does not contain the through-holes or lattice structures (HHD surface factor 1) or is calculated from the face of the substrate where the through-holes or lattice structures start to extend into the substrate (HHD surface factor >1). Both "faces" are at the same level. The resulting thickness of the copper filling in step (f) preferably results in a comparatively thin and uniform copper layer thickness over the through-holes and / or lattice structures or over the areas of the through-holes and / or lattice structures (having a HHD surface factor >1.1, more preferably 1.1 to 5) of 10 to 300 μm, more preferably 10 to 100 μm, even more preferably 10 to 30 μm. The word "comparable" in this context means that as the through-hole becomes longer (or the thickness of the board becomes thicker, such as a plate), the first copper layer may become thicker.

[0044] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the disclosure described herein can be implemented utilizing any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on one integrated circuit (IC) chip or separate IC chips. Furthermore, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate as an IC substrate. Furthermore, the various components of these devices can be processes or threads in one or more computing devices that run on one or more processors, execute computer program instructions, and interact with other system components to perform the various functionalities described herein. The computer program instructions are stored in a memory that can be implemented in the computing device using standard memory devices such as, for example, a random access memory (RAM). The computer program instructions can also be stored on other non-transitory computer readable media such as, for example, a CD-ROM, a flash drive, and the like. Additionally, those skilled in the art should understand that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices, without departing from the scope of the exemplary embodiments of the invention.

[0045] Typically, HDI PCBs offer the finest trace structures, smallest holes, and blind and buried vias (microvias). Thus, HDI technology enables highly compact and reliable PCB designs, achieved using via-in-pad and multiple microvia layers (stacked and interleaved vias). Signals on conductive intermediate layers can be connected and disconnected by pressing further layers using SBU (sequential build-up) or SSBU (semi-sequential build-up) technology. This leaves space on the outer layers for components with high pin density. IPC standards define HDI circuit boards with microvias of ≦0.15 mm and track width / distance of ≦0.1 mm.

[0046] HDI layers can be built from double-sided core boards or multi-layer PCBs. HDI layers can be built on both sides of the PCB. The SBU / SSBU process consists of several steps: layer stacking, via formation, via metallization, and via filling. For each step, there are multiple choices of materials and / or techniques. In particular, microvias can be filled with different materials and processes. However, stacked microvias are usually filled with electroplated copper to provide electrical interconnection between multiple HDI layers and to provide structural support for the outer levels of the microvias or for components mounted on the outermost copper pads.

[0047] Additionally, HDI PCBs may include heat dissipation structures such as copper filled through-holes or lattice structures, etc. The present invention relates to a manufacturing sequence in which the through-holes and / or lattice structures are filled with copper.

[0048] The present invention can be used to build IC substrates. IC substrates serve as connections between IC chips and PCBs through a conductive network of traces and holes. IC substrates support important functions including circuit support and protection, heat dissipation, and signal and power distribution. IC substrates represent the highest level of miniaturization in PCB manufacturing and share many similarities with semiconductor manufacturing. The method of the present invention for fabricating high density interconnect printed circuit boards (HDI PCBs) or IC substrates including copper filled through holes and / or lattice structures will now be described in detail with reference to the exemplary embodiments illustrated in Figures 1 to 5.

[0049] 1 shows a schematic sequence, including cross-sectional views, of steps (a)-(f) of the method, in which an HDI PCB includes through-holes 20 that must be filled with copper, as well as a lattice structure 30. Details of the sequence are explained below.

[0050] Figures 2 and 3 illustrate a further schematic sequence including cross-sectional views of each step (a)-(f) of the method when the HDI PCB includes a through-hole 20. In the embodiment of Figure 2, the stack assembly comprises an insulating core layer 12 embedded between two conductive intermediate layers 14. At least one outer insulating layer 13 is attached onto the conductive intermediate layer 14. In the embodiment of Figure 3, the through-hole 20 is provided in an area of ​​the HDI PCB without any conductive intermediate layer. Details of the sequence are also described below.

[0051] 4a and 4b illustrate schematic cross-sectional and respective schematic top views of two exemplary lattice structures 30, 32.

[0052] According to a first embodiment illustrated in Fig. 4a, a lattice structure 30 is provided on both sides of the HDI PCB. The lattice structure 30 includes 25 slots 36 arranged in five rows and columns. The slots 36 are separated by thin walls 34. The dimensions of each of the slots 36 may be the same as those of the through holes 20. The slots 36 extend through the cover layer 16 and the outer insulating layer 13. The walls 32 have a height that is less than the thickness of the insulating layer 13.

[0053] According to a second embodiment illustrated in FIG. 4b, the lattice structure 32 is distinguished from the lattice structure 30 of FIG. 4a in that the thin walls 35 extend flush with the insulating layer 13 and are covered by the cover layer 16.

[0054] Figure 5 illustrates a schematic sequence including cross-sectional views of steps (a) to (f) of the method for filling the lattice structure 30 illustrated in Figure 4a. Details of the sequence are explained below.

[0055] The method of the present invention for making a high density interconnect printed circuit board (HDI PCB) or IC substrate containing copper filled through holes 20 and / or grid structures 30, 32 comprises the following steps: (a) preparing a multilayer substrate 10, the multilayer substrate 10 being: (i) an insulating core layer 12 having a peripheral surface; or (i') a stack assembly comprising an insulating core layer 12 embedded between two conductive intermediate layers 14, and at least one outer insulating layer 13 mounted on the conductive intermediate layers 14 and having a peripheral surface; (ii) an optional cover layer 16, preferably made of copper, covering the peripheral surface; and (iii) at least one through hole 20 extending through all layers of the multi-layer substrate 10; and / or A lattice structure 30, 32 having a plurality of slots 36 extending through the optional cover layer 16 and partially into the insulating core layer 12, or at least extending through at least one of the optional cover layer 16 and the outer insulating layer 13. and (b) forming a non-copper conductive layer 40 or a copper layer 40 on the inner surfaces of the lattice structures 30, 32, on the cover layer 16 and on the inner surfaces 22 of each of the through holes 20; (c) forming a patterned masking film 50 on the non-copper conductive layer 40 or on the copper layer 40; (d) in one step, electrolytically depositing a copper inner encapsulant 62 inside the through holes 20 sufficient to form two blind microvias 64 each, and electrolytically depositing a copper inlay 66 on the non-copper conductive layer 40 or copper layer 40 on the inner surface of the lattice structure 30, 32, and on the remaining peripheral surface of the non-copper conductive layer 40 or copper layer; (e) removing the masking film 50; (f) electrolytically depositing, in one step, a copper fill 70 in the blind microvia 64, the copper inlay 66, and on the first copper layer 60, respectively; Includes.

[0056] In other words, the manufacturing sequence starts with step (a) of preparing a multi-layer substrate 10 with through holes 20 and / or lattice structures 30, 32, where the multi-layer substrate 10 can be laminated with a cover layer 16 on top of the outermost layer of the stack assembly. For HDI applications, the cover layer 16 is preferred as mSAP. The outermost layer of the stack assembly can be an insulating core layer 12 or an outer insulating layer 13, which is then attached to a conductive intermediate layer 14. At least one conductive intermediate layer can be embedded between the insulating core layer and the outer insulating layer. Furthermore, a conductive intermediate layer can be embedded between two outer insulating layers, as long as at least one conductive intermediate layer can be embedded between the insulating core layer and the outer insulating layer. Preferably, the multi-layer substrate 10 includes both the through holes 20 and the lattice structures 30, 32.

[0057] According to one embodiment, the through holes 20 have a diameter in the range of 30 μm to 1000 μm and / or the plurality of slots 36 have a diameter in the range of 30 μm to 300 μm.

[0058] The aspect ratio of the diameter of the through-hole 20 to the thickness of the substrate 10 is 0.5 to 13, and preferably 1 to 4. The aspect ratio of the diameter of the plurality of slots (36) to the depth of the slot is 0.5 to 3.

[0059] In step (b), a non-copper conductive layer 40 or copper layer 40 is formed on the cover layer 16 and on the inner surface 22 of the through-hole 20 and / or the inner surface of the lattice structure 30, 32. For some applications, such as IC substrate applications as SAP processes with even smaller line-to-space ratios, the cover layer 16 is preferably not applied. The non-copper conductive layer 40 in step (b) may be a metal or alloy, a conductive metal oxide (such as titanium oxide), a carbon-based material (such as graphite, graphine, and graphiyne), a conductive organic material such as a conductive polymer (such as Ecopact CP).

[0060] If a copper layer 40 is formed, this is understood to mean a copper layer made of pure copper and having a copper content of ≧97%, preferably ≧99%, more preferably ≧99.5%. This layer is preferably formed by wet-chemical copper deposition, preferably after activation of the peripheral surface, in particular if a cover layer 16 is not formed.

[0061] In the case of metals or alloys, the term "non-copper" in the context of the non-copper conductive layer 40 can be understood as a metal or alloy containing a copper content of ≦95%, preferably ≦50%, more preferably ≦10%, most preferably ≦1%, as determined by standard chemical / instrumental analysis methods. ICP-MS (Inductively Coupled Plasma Mass Spectroscopy) can be used for the analysis of copper traces in the respective material used as the non-copper conductive layer 40. In other words, the non-copper conductive layer 40 is not made of pure copper or high purity copper. The non-copper conductive layer 40 is preferably formed because the copper-containing layer is more sensitive to strong etching and / or unwanted dissolution during the electrolytic deposition in step (d) of the present invention, since the conditions and parameters in step (d) can be more aggressively selected. In other words, the non-copper conductive layer 40 can be etch-resistant. In particular, the degree of etch resistance of the non-copper conductive layer 40 can be adjusted to prevent etching by the acid and / or electrolyte applied during the subsequent electrolytic deposition step, but absolute etch resistance is not implied.

[0062] The non-copper conductive layer 40 in step (b) may be formed by one or more of an electroless plating process, an electroless deposition process, a physical deposition process, a chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process.

[0063] The application of the non-copper conductive layer 40 can allow for the use of high reverse pulse parameters with low current efficiency to perform plating without encapsulation, but can also allow for the use of higher current densities for higher throughput during through-hole filling.

[0064] In step (c), a patterned masking film 50 is formed on the non-copper conductive layer 40. The masking film 50 is removed in step (e).

[0065] In step (d), in the case of the through-hole 20, a copper inner encapsulant 62 is formed inside the through-hole 20 by electrolytic deposition, thereby forming two blind microvias 64. In the case of the lattice structures 30, 32, a copper inlay 66 is formed on the non-copper conductive layer 40 on the inner surface of the lattice structures 30, 32 by electrolytic deposition. In addition, a first copper layer 60 is formed on the remaining peripheral surface of the non-copper conductive layer 40. The process is performed in one step.

[0066] Step (d) of electrolytically depositing in one step the copper inner seal 62 inside each of the through-holes 20, the copper inlay 66 on the lattice structure 30, 32 and the first copper layer 60 may include immersing the multilayer substrate 10 in an electrolytic bath in an electrolytic copper plating system to which the non-copper conductive layer 40 is connected as a cathode, the plating system further comprising an insoluble, dimensionally stable anode and a source of copper metal, the electrolytic bath comprising an acid, a source of copper ions, a source of ferrous and / or ferric ions, and at least one additive for controlling the physical-mechanical properties of the deposited copper.

[0067] Following the immersion step (d), a voltage is applied between the insoluble, dimensionally stable anode and the non-copper conductive layer 40 such that a current flows therebetween for a time sufficient to electrolytically deposit copper to form a copper inner encapsulant 62 and / or copper inlay 66 and a first copper layer 60 on the surrounding non-copper conductive layer 40, where Fe 2+ / Fe 3+ A redox system is established in the electrolytic cell to effect the electrolytic deposition of additional copper ions by dissolving copper ions from a source of copper metal. "One step" is defined herein as one plating machine run, i.e., the multilayer substrate is conveyed one time through the electrolytic copper plating system.

[0068] Step (f) of electrolytically depositing copper filling 70 in the blind microvias 64 of the through holes 20, on the copper inlay 66, and on the first copper layer 60 in one step may include immersing the multilayer substrate 10 in an electrolytic bath in an electrolytic copper plating system to which the non-copper conductive layer 40 is connected as a cathode, the plating system further comprising an insoluble, dimensionally stable anode and a source of copper metal, the electrolytic bath comprising an acid, a source of copper ions, a source of ferrous and / or ferric ions, and at least one additive for controlling the physical-mechanical properties of the deposited copper.

[0069] Following the immersion step (f), a voltage is applied between the insoluble, dimensionally stable anode and the copper or non-copper conductive layer 40, such that the thickness of the first copper layer 60 is reduced while a current flows therebetween for a time sufficient to electrolytically deposit copper to form the copper fill 70 in the blind microvia 64 and the copper inlay 66. Here, Fe 2+ / Fe 3+ A redox system is established in the electrolytic cell to achieve electrolytic deposition of additional copper ions by dissolving copper ions from a source of copper metal. "One step" is defined here as one plating machine run, i.e. the multilayer board is conveyed once through the electrolytic copper plating system. For electrolytic deposition of copper, reverse pulse plating is used. As a result, a thin and uniform copper layer is obtained from this step (f).

[0070] The method comprising steps (d), (e) and (f), respectively, significantly reduces process steps, realizes cost reduction and allows for inclusion-free and recess-free electrolytic deposition of copper.One objective problem of the present invention may therefore be to provide a method that allows time- and cost-effective copper filling for multi-layer boards with through-holes and lattice structures, thereby providing a high quality PCB with improved thermal management of the through-holes.

[0071] Using the present invention, it is further possible to obtain a copper fill that provides a uniform copper surface of copper plating thickness across the entire processed substrate without uneven height in terms of the filled structure, such as the filled through-hole or the filled lattice structure, compared to an adjacent area without the underlying filled structure, e.g., an area between the at least one through-hole and a lattice structure also comprising copper created by step (f).

[0072] The difference in height of the resulting copper layer in the areas of different HHD surface factors is, after step (f), 0-40% of the copper plating thickness, preferably 0-20%.

[0073] Preferably, HHD When the surface factor is 1.1 to 5, the resulting height difference of the copper layer is 0 to 40%. More preferably, HHD For a surface factor between 1.1 and 3, the resulting copper layer height difference is between 0 and 20%; and / or HHD For surface factors between 2 and 5, the resulting copper layer height difference is between 10 and 40%.

[0074] 1.1 to 5 and 1 HHD Just two different HHD When surface factors are present, the difference may be 0 to 10%. HHD At least three different HHD For more complex surfaces having areas with surface factors between 1.1 and 5, the difference is between 10 and 40%, preferably between 10 and 30%.

[0075] For areas with through holes HHD When the surface factor is between 1.1 and 5, more preferably between 1.1 and 3, and most preferably between 1.1 and 2, a resulting copper layer height difference of between 0 and 40% is preferred. Also preferred is HHD When the surface factor is 1.1-2, the resulting height difference of the copper layer is 0-20%. HHD Just two different HHD If surface factors are present, the difference may be 0-10%. HHD Three or more different HHD In the case of having an area with a surface factor of 1.1 to 5, the difference is 10 to 40%, preferably 10 to 30%.

[0076] For areas with lattice structure HHD When the surface factor is between 1.1 and 3, preferably between 1.1 and 2, a non-uniform height difference of the resulting copper layer of between 0 and 40% is preferred. More preferably, HHD When the surface factor is 1.1-2, the resulting height difference of the copper layer is 0-20%.

[0077] The acid in step (d) and step (f) may be selected from the group consisting of sulfuric acid, methanesulfonic acid, pyrophosphoric acid, fluoroboric acid, and amidosulfuric acid.

[0078] According to one embodiment, the source of copper ions is a copper(II) salt, preferably selected from the group consisting of copper(II) sulfate, copper(II) sulfate pentahydrate, copper(II) sulfate heptahydrate, copper(II) methanesulfonate, copper(II) pyrophosphate, copper(II) fluoroborate, and copper(II) sulfamate.

[0079] As noted above, Fe(II) and / or Fe(III) salts are included in the bath. Suitable iron salts may be both iron(II) sulfate heptahydrate and iron(II) sulfate nonahydrate, either or both of which provide effective Fe(II) sulfate after a short operating time. 2+ / Fe 3+ A (Fe(II) / Fe(III)) redox system is formed.

[0080] According to another embodiment, the source of ferrous ions is an Fe(II) salt, preferably selected from the group consisting of iron(II) sulfate heptahydrate, iron(II) acetate, iron(II) propionate, iron(II) benzoate, and iron(II) hexafluorosilicate.

[0081] According to one embodiment, the source of ferric ions comprises an Fe(III) salt, preferably selected from the group consisting of iron(III) sulfate nonahydrate, iron(III) acetate, iron(III) propionate, iron(III) benzoate, and iron(III) hexafluorosilicate.

[0082] These salts are primarily suitable for aqueous copper acid baths. Other aqueous iron salts can also be used, such as, for example, iron perchlorate. Salts without (hard) complexing agents are advantageous. Such complexing agents may be biologically non-degradable or barely degradable, and therefore such salts may cause problems when discarding the rinse water (e.g., ferric ammonium alum). Iron compounds with anions that lead to undesirable secondary reactions in the case of copper deposition solutions, such as, for example, chlorides or nitrates, should not be used. As a result, carboxylates of the iron ion, such as acetates, propionates, and benzoates, as well as hexafluorosilicates, are also advantageous. Fe 2+ / Fe 3+ Suitable systems employing redox systems are disclosed, for example, in WO2010 / 094998A1, WO2007 / 112971A2, and U.S. Patent Nos. 5,976,341 and 6,099,711, which may be consulted for further details regarding the present systems. 2+ / Fe 3+ The disclosures of the above mentioned patents relating to the use of redox systems are incorporated herein by reference.

[0083] Suitable addition compounds may be, for example, polymeric oxygen-containing compounds, organosulfur compounds, thiourea compounds, polymeric phenazonium compounds, and polymeric nitrogen compounds, and mixtures or combinations of any two or more of any of these addition compounds.

[0084] Suitable exemplary polymeric oxygen-containing compounds can include one or more of the following: carboxymethyl cellulose, nonylphenol polyglycol ether, octanediol bis(polyalkylene glycol ether), octanol polyalkylene glycol ether, oleic acid polyglycol ether, polyethylene propylene glycol copolymer polyethylene glycol, polyethylene glycol dimethyl ether, polyoxypropylene glycol, polypropylene glycol, polyvinyl alcohol, stearic acid polyglycol ether, stearyl alcohol polyglycol ether, and beta naphthol polyglycol ether.

[0085] Suitable exemplary thiourea type compounds can include one or more of the following: thiourea, N-acetylthiourea, N-trifluoroacetylthiourea, N-ethylthiourea, N-cyanoacetylthiourea, N-allylthiourea, o-tolylthiourea, N,N'-butylenethiourea, thiazolidinethiol, 4-thiazolinethiol, imidazolidinethiol (N,N'-ethylenethiourea), 4-methyl-2-pyrimidinethiol, 2-thiouracil.

[0086] Suitable exemplary phenazonium compounds can include one or more of the following: poly(6 methyl 7 dimethylamino 5 phenyl phenazonium sulfate), poly(2 methyl 7 diethylamino 5 phenyl phenazonium chloride), poly(2 methyl 7 dimethylamino 5 phenyl phenazonium sulfate), poly(5 methyl 7 dimethylamino phenazonium acetate), poly(2 methyl 7 anilino 5 phenyl phenazonium sulfate), poly(2 methyl 7 dimethylamino phenazonium sulfate), poly(7 methylamino 5 phenyl phenazonium acetate), poly(7 ethylamino 2,5 diphenyl phenazonium chloride), poly(2,8 dimethyl 7 diethylamino 5 p tolyl phenazonium chloride), poly(2,5,8 triphenyl 7 dimethylamino phenazonium sulfate), poly(2,8 dimethyl 7 amino 5 phenyl phenazonium sulfate), and poly(7 dimethylamino 5 phenyl phenazonium chloride).

[0087] Suitable exemplary polymeric nitrogen-containing compounds can include one or more of the following: polyethyleneimine, polyethyleneimide, polyacrylic acid amide, polypropyleneimine, polybutyleneimine, N-methylpolyethyleneimine, N-acetylpolyethyleneimine, and N-butylpolyethyleneimine.

[0088] In principle, copper ions are consumed during the electrolytic deposition process on the multilayer substrate. However, to recover the copper ions in the electrolytic bath, they cannot be directly provided by an insoluble, dimensionally stable anode. Instead, the copper ions can be provided by chemically dissolving a source of copper metal, i.e. a sacrificial anode made of copper or a molded body containing copper. The dissolution of the source of copper metal can be realized and / or controlled in a secondary reactor, and the electrolytic deposition can be realized and / or controlled in a primary reactor, both reactors being connected. The secondary reactor can be connected with the primary reactor to realize the circulation of the electrolytic bath with a suitable flow rate between the secondary reactor and the primary reactor.

[0089] In this redox system, copper ions are formed from a source of copper metal (either a sacrificial anode or a copper-containing molded body) in a redox reaction using dissolved Fe(III) salts as the oxidizing agent. In other words, the source copper metal is oxidized to form Cu(II) ions while the Fe(III) ions are reduced to Fe(II) ions. This redox reaction keeps the total concentration of copper ions required for the electrolytic deposition process relatively constant in the electrolytic cell. Furthermore, the insoluble, dimensionally stable anode, to which the voltage is actually applied, remains the same uniform size. As will be appreciated, the following reaction occurs: Insoluble, dimensionally stable anodes (electrolytic deposition process) Fe 2+ →Fe 3+ +e - At the cathode, i.e. in multilayer substrates (electrolytic deposition process), Cu 2+ +2e - →Cu° (main reaction) Fe 3+ +e - →Fe 2+ (Side reactions) Source of copper metal (Cu 2+ In the case of electroless recovery of Cu°+2Fe 3+ →Cu 2+ +2Fe 2+

[0090] When applying a voltage to the substrate, the local current density not only depends on the via hole density in a particular area, but also distributes between areas with vias and lattice structures (so-called high hole density areas, HHD areas) and areas without vias or areas without multiple vias. HHD areas typically have a lower local current density compared to areas without vias. Furthermore, the higher the via hole density, the lower the local current density. In that context, the HHD surface factor for a particular area of ​​the substrate is defined as the ratio between the total surface (also called the total grid area or total grid surface) including the inner surfaces of all vias or lattice structures and the peripheral surface of the corresponding area (also called the grid surface). A higher HHD surface factor corresponds to more vias, a smaller hole pitch (distance between via midpoints), a smaller via diameter, and a lower current density, respectively.

[0091] In the electrodeposition process described above, the local current efficiency, i.e., the efficiency with which electrons are transferred in the system to facilitate the electrochemical reaction (here, copper deposition), correlates with the local current density. Thus, a higher HHD surface factor results in a lower local current density, which in turn results in a lower local current efficiency, i.e., a smaller layer thickness due to copper deposition.

[0092] In the redox system described above, the local current efficiency is determined by the amount of Fe in the electrolytic cell. 3+ It depends more on the concentration, i.e., Fe 3+ The higher the concentration, the thinner the copper layer that is deposited.

[0093] Furthermore, in the redox systems described above, the local current efficiency is temperature dependent: the higher the temperature, the smaller the thickness of the deposited copper layer.

[0094] Furthermore, in the redox systems described above, the local current efficiency depends on the duration of the reverse current pulse: the longer the duration of the reverse current pulse, the smaller the thickness of the deposited copper layer.

[0095] According to one embodiment, the voltage is applied in a reverse pulse format having bidirectional pulses including a forward current pulse and a reverse current pulse.

[0096] In another embodiment, the local current efficiency is controlled by adjusting at least one of the concentration of the source of copper ions, the concentration of the source of ferrous ions, the concentration of the source of ferric ions, the duration of the reverse current pulse, and the temperature of the electrolytic cell. Preferably, the local current efficiency is controlled by adjusting at least one of the concentration of the source of ferric ions, the duration of the reverse current pulse, and the temperature of the electrolytic cell.

[0097] In particular, the current efficiency decreases when the concentration of ferrous ions and / or the temperature of the electrolytic cell increase. Moreover, the current efficiency also decreases when the duration of the reverse current pulse is shortened. On the other hand, the current efficiency increases with increasing copper(II) ion concentration.

[0098] According to one embodiment, the electrolytic cell comprises a source of copper ions at a concentration in the range of 20 to 150 g / l and / or a source of ferrous ions at a concentration in the range of 1 to 40 g / l and / or a source of ferric ions at a concentration in the range of 0.1 to 40 g / l.

[0099] The duration of the reverse current pulse can be adjusted in the range of 0 to 200 ms.

[0100] Furthermore, the duration of the forward current pulse can be adjusted in the range of 0 to 200 ms.

[0101] In another aspect of the present invention, a high density interconnect printed circuit board (HDI PCB) containing copper filled through holes 20 is obtained by the method described above. [Explanation of symbols]

[0102] 10 Multilayer board 12 Insulating layer 14 Conductive Interlayer 16 Cover Layer 20 through hole 22 Inner Surface 30, 32 lattice structure 34, 35 Lattice wall 36 Slots 40 Non-copper conductive layer or copper layer 50 Patterned masking film 60 1st copper layer 62 Copper internal encapsulation 64 Blind Microvia 66 Copper Inlay 70 Copper filling

Claims

1. 1. A method for making a high density interconnect printed circuit board (HDI PCB) or IC substrate containing copper filled through holes and / or grid structures, comprising: (a) providing a substrate (10), the substrate (10) comprising: (i) an insulating core layer (12) having a peripheral surface; or (i') a stack assembly comprising an insulating core layer (12) embedded between two conductive intermediate layers (14), and at least one outer insulating layer (13) mounted on said conductive intermediate layers (14) and having a peripheral surface; (ii) an optional cover layer (16) covering said peripheral surface; and (iii) at least one through hole (20) extending through all layers of said substrate (10); and / or a lattice structure (30, 32) having a plurality of slots (36) extending through said optional cover layer (16) and partially into said insulating core layer (12), or at least extending through at least one of said optional cover layer (16) and said outer insulating layer (13); and (b) forming a non-copper conductive layer (40) or a copper layer (40) on the inner surface of the lattice structure (30, 32), on the cover layer (16) and on the inner surface (22) of each of the through holes (20); (c) forming a patterned masking film (50) on said non-copper conductive layer (40) or on said copper layer (40); (d) in one step, electrolytically depositing a copper inner encapsulant (62) inside said through-holes (20) sufficient to form two blind microvias (64) each, a copper inlay (66) on said non-copper conductive layer (40) or on said copper layer (40) of said inner surface of said lattice structure (30, 32), and a first copper layer (60) on the remaining peripheral surface of said non-copper conductive layer (40) or said copper layer (40); (e) removing the masking film (50); (f) electrolytically depositing, in a single step, a copper fill (70) into said blind microvias (64), into said copper inlay (66), and onto said first copper layer (60); The method includes:

2. The method of claim 1, wherein the through holes (20) have a diameter in the range of 30 μm to 1000 μm and / or the plurality of slots (36) have a diameter in the range of 30 μm to 300 μm.

3. 3. The method of claim 1 or 2, wherein the non-copper conductive layer (40) of step (b) is selected from the group consisting of a metal or alloy layer, a conductive metal oxide layer, a carbon layer made from graphite, graphene, and graphdiyne, and an organic layer.

4. 4. The method of claim 1, wherein the non-copper conductive layer (40) is formed by one or more of an electroless plating process, an electroless deposition process, a physical deposition process, a chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process.

5. The step (d) of electrolytically depositing the copper inner seal (62) and the first copper layer (60) inside the through-hole (20) comprises immersing the substrate (10) in an electrolytic bath in an electrolytic copper plating system to which the non-copper conductive layer (40) is connected as a cathode, the plating system further comprising an insoluble, dimensionally stable anode and a source of copper metal, the electrolytic bath containing an acid, a source of copper ions, Fe ２＋ and / or Fe ３＋ providing a source of ions and at least one additive for controlling the physical-mechanical properties of the deposited copper; applying a voltage between the insoluble, dimensionally stable anode and the non-copper conductive layer (40) such that a current flows therethrough for a time sufficient to electrolytically deposit copper to form a first copper layer (60) on the copper inner encapsulant (62) and the surrounding non-copper conductive layer (40), and depositing Fe. ２＋ / Fe ３＋ A method according to any one of claims 1 to 4, comprising the steps of: establishing a redox system in the electrolytic cell to provide for the electrolytic deposition of additional copper ions by dissolving copper ions from the source of copper metal.

6. The step (f) of electrolytically depositing the copper fill (70) comprises immersing the substrate (10) in an electrolytic bath in an electrolytic copper plating system to which the non-copper conductive layer (40) is connected as a cathode, the plating system further comprising an insoluble, dimensionally stable anode and a source of copper metal, the electrolytic bath containing an acid, a source of copper ions, Fe ２＋ and / or Fe ３＋ providing a source of ions and at least one additive for controlling the physical-mechanical properties of the deposited copper; applying a voltage between the insoluble, dimensionally stable anode and the copper layer (40) or non-copper conductive layer (40) such that a current flows therethrough for a time sufficient to electrolytically deposit copper to form the copper fill (70) in the blind microvias (64) and copper inlays (66) while reducing the thickness of the first copper layer (60); ２＋ / Fe ３＋ and a step of establishing a redox system in the electrolytic bath to provide for electrolytic deposition of additional copper ions by dissolving copper ions from the source of copper metal other than the copper of the first copper layer (60).

7. 7. The method of claim 5 or 6, wherein the acid is selected from the group consisting of sulfuric acid, methanesulfonic acid, pyrophosphoric acid, fluoroboric acid, and amidosulfuric acid.

8. 8. The method of any one of claims 5 to 7, wherein the source of copper ions is a copper(II) salt selected from the group consisting of copper(II) sulfate, copper(II) sulfate pentahydrate, copper(II) sulfate heptahydrate, copper(II) methanesulfonate, copper(II) pyrophosphate, copper(II) fluoroborate, and copper(II) sulfamate.

9. 9. The method of any one of claims 5 to 8, wherein the source of ferrous ions is an Fe(II) salt selected from the group consisting of iron(II) sulfate heptahydrate, iron(II) acetate, iron(II) propionate, iron(II) benzoate, and iron(II) hexafluorosilicate.

10. 10. The method of any one of claims 5 to 9, wherein the source of ferric ions comprises an Fe(III) salt and is selected from the group consisting of iron(III) sulfate nonahydrate, iron(III) acetate, iron(III) propionate, iron(III) benzoate, and iron(III) hexafluorosilicate.

11. 11. The method according to claim 5, wherein the voltage is applied in a reverse pulse format having bidirectional pulses including a forward current pulse and a reverse current pulse.

12. The local current efficiency is the concentration of said source of copper ions; the concentration of said source of ferrous ions; the concentration of said source of ferric ions; the duration of the reverse current pulse, and Temperature of the electrolytic cell 12. The method according to claim 5, wherein the control is performed by adjusting at least one of the following:

13. The electrolytic cell comprises: A source of copper ions in a concentration ranging from 20 to 150 g / l, and / or A source of ferrous ions in a concentration ranging from 1 to 40 g / l, and / or A source of ferric ions in concentrations ranging from 0.1 to 40 g / l The method of claim 12, comprising:

14. The method according to claim 12 or 13, wherein the duration of the reverse current pulse is adjusted in the range of 0 to 200 milliseconds.

15. the at least one through hole (20) extending through all layers of the substrate (10); and / or the lattice structure (30, 32) having a plurality of slots (36) extending through the optional cover layer (16) and partially into the insulating core layer (12), or at least extending through at least one of the optional cover layer (16) and the outer insulating layer (13); The method according to any one of claims 1 to 14, wherein the HHD surface factor is 1.1 to 5.

16. 16. The method of any one of claims 1 to 15, wherein the resulting thickness of the copper filling of step (f) results in a thin and uniform copper layer thickness over the through-holes and / or lattice structures with a copper layer thickness of 10 to 300 μm.

17. 17. The method according to any one of claims 1 to 16, wherein the height difference of the resulting copper plating thickness over the through-holes and / or lattice structures of step (f) is 0-40% compared to the height without the through-holes and / or lattice structures.

18. 18. A high density interconnect printed circuit board (HDI PCB) or IC substrate comprising copper filled through holes (20), said HDI PCB being obtained by the method of any one of claims 1 to 17.

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