Ring transport employing clock wake suppression

Abstract

The integrated circuit (IC) device includes a ring transport having a plurality of nodes and a wire interconnect coupling the plurality of nodes in a ring configuration. The wire interconnect includes a wire for transmitting a clock wake signal around the ring transport prior to data signaling representing a data packet. Each node switches from a clock gating state to a clock state in response to receiving the clock wake signal. The ring transport further includes a sleep controller coupled to a selected node among the plurality of nodes. The sleep controller configures the selected node into a clock inhibit state for a specified period in response to identifying an idle condition of the ring transport by monitoring the wire. During the clock inhibit state, the node inhibits further transmission of the clock wake signal received at the selected node.

Description

[Background technology]

[0001] Integrated circuit (IC) devices often use ring transports to communicate data and commands between various components connected to the ring transport. A typical ring transport configuration uses a clock wake signal that precedes each packet by one or more clock cycles in the ring transport. When a clock wake signal is received at a node in the ring transport, it serves to activate the stage in preparation for receiving a subsequent packet. However, such a clock wake signal often travels around the ring transport indefinitely, eventually causing each node to be clocked at all times. This inhibits nodes from going into low-power modes, causing the ring transport to consume excessive power.

[0002] The present disclosure can be better understood, and its numerous features and advantages made apparent to those skilled in the art by reference to the following drawings, in which the use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0003] [Figure 1] 1 is a block diagram illustrating an integrated circuit (IC) device having a double buffering transport with a sleep controller in accordance with some embodiments of the present disclosure. [Diagram 2] 2 illustrates a more detailed diagram of the nodes and sleep controller of the ring transport of FIG. 1 according to an embodiment of the present disclosure. [Diagram 3] 3 is a flow diagram illustrating a method representing a portion of a state diagram illustrating the operation of the sleep controller of FIGS. 1 and 2 in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] Clock distribution of the components of the ring transport often consumes significant power, and this power consumption is exacerbated by conventional implementations where false clock wake signals circulate around the ring transport indefinitely, leading to the ring transport being flooded with clock wake signals and therefore continuously clocked. The following disclosure describes systems and techniques for reducing the power consumption of the ring transport through the implementation of a sleep controller that functions to suppress or "squash" false clock wake signals passing through the ring transport. Upon suppressing these false clock wake signals, nodes of the ring transport can be switched to a non-clocked state, thereby reducing the power consumption of the nodes when the ring transport is idle.

[0005] In at least one embodiment, the ring transport includes a number of nodes connected in a ring via a wire interconnect composed of a number of wires, including a wire for control signaling and a wire for data signaling. A sleep controller is connected to a selected node and operates to control the operation of the node with respect to forwarding or "repeat" a clock wake signal received at the node. The sleep controller monitors the wire interconnect of the controlled node for clock wake signals and data packets. When a specified idle period has elapsed without the node receiving data traffic, the sleep controller configures the node into an active clock inhibit state. In this state, the node is controlled to inhibit (i.e., refrain from forwarding) received clock wake signals. In at least one embodiment, the sleep controller maintains the node in this clock inhibit state for a period of time sufficient to clear spurious clock wake signals passing through the ring transport. After a specified period of time in the clock inhibit state has elapsed, the sleep controller transitions to a hibernate state, in which the node is permitted to forward newly received clock wake signals, and if the clock wake signal is followed by a data packet, the sleep controller returns to an active state and the node is controlled to perform active operation.

[0006] In this way, the sleep controller, via the controlled node, functions to actively clear the false clock wake signal from the ring transport after an idle period, and then return the node to a state where it can react to a new clock wake signal appearing on the ring transport, which may indicate the resumption of data traffic on the ring transport. This active clock wake signal suppression allows the ring transport to switch to a true idle state in the absence of a false clock signal, and thus allows the node to remain in a non-clocked state during this idle state, with a corresponding reduction in power.

[0007] 1 illustrates an integrated circuit (IC) device 100 having a ring transport 102 employing active clock wake suppression, according to some embodiments. The IC device 100 may include a single IC chip, such as a system on a chip (SoC), an application specific integrated circuit (ASIC), or multiple IC chips mounted on a common substrate, circuit board, or other carrier, such as a multi-chip module (MCM). Examples of IC devices 100 include central processing units (CPUs), graphics processing units (GPUs), accelerated processing units (APUs), digital signal processors (DSPs), other processors, and other systems typically implemented on one or more IC chips.

[0008] The ring transport 102 includes a number of nodes 104 connected in a ring shape via wire interconnects 106, such as the four nodes 104-1 to 104-4 shown, whereby control and data signaling is transmitted from node to node in one direction (e.g., clockwise direction 108) in a unidirectional ring implementation, or in either direction in a bidirectional ring implementation. This control and data signaling continues to circulate around the ring shape until it is consumed or suppressed at one node 104. Each node 104 is connected to one or more components 110 of the IC device 100, such as components 110-1 to 110-4 connected to the nodes 104-1 to 104-4, respectively. These components 110 operate to either inject data traffic into the ring transport 102 via the corresponding node 104 for transmission to one or more other nodes 104, or to consume data traffic transmitted by the ring transport 102 from the other nodes 104, or both. Components 110 may include any of the various elements of IC device 100, such as a processing element, a storage element, a bus or interface element, an input / output device element, and the like.

[0009] The nodes 104 and components 110 are clocked based on a ring clock signal 112 (also referred to herein as "RING_CLK" 112) that is distributed among the nodes 104 and components 110 via a clock distribution tree 114. The ring clock signal 112 may be, for example, a system clock of the IC device 100 or a clock specific to the ring transport 102 derived therefrom. If the ring transport 102 and associated components 110 remain active and thus clocked while the IC device 100 is supplied with at least minimal power, significant power will be consumed by the clock distribution tree 114 and its clock sinks. To avoid this unnecessary power consumption, the ring transport 102 employs a clock wake scheme in which the nodes 104 and components 110 clocked by RING_CLK 112 are clock gated between transmissions of data packets on the ring transport 102. Thus, when a node is preparing to transmit a data packet on the ring transport 102, the node inserts a clock wake signal 116 (also referred to herein as "CLK_EN" 116) a predetermined number of clock cycles (e.g., one clock cycle) ahead of the signaling representing the data packet. Thus, a node 104 receiving a clock wake signal 116 responds by switching from a clock gating state to a clock state by deactivating clock gating at the node 104 and its associated one or more components 110, and is ready to receive and process the data packet following the clock wake signal 116.

[0010] The use of such clock wake signaling allows the node 104 to receive data traffic from the upstream with short notice while facilitating the use of a low-power clock-gated idle state between data packets that would otherwise often result in the entire ring transport 102 remaining clocked, thereby never being able to transition to a low-power idle state. To explain, unless the receiving node can determine that a given data packet is being consumed at the next node, it cannot notify the next node that a given clock wake signal should not be propagated any further. In this manner, the clock wake signal preceding a data packet may remain in the ring transport even after the subsequent data packet has been consumed and removed, and thus the ring transport 102 will eventually be "filled" with clock wake signals, which in effect results in the ring transport 102 being continuously clocked. One solution to this false clock-wake signaling is to implement additional wires and logic to allow a given node to calculate whether a received data packet has been consumed by the next node and will not be propagated further, and to use faster circuitry and wires to send that indicator to the next node more quickly in time to enable the clock. However, such wires and logic are often impractical and consume enough power to negate the power savings achievable by a clock-wake scheme.

[0011] To mitigate the effects of erroneous clock wake signaling without relying on additional high power wiring and logic at each node, in at least one embodiment, the ring transport 102 employs a sleep controller 118 at a selected one of the nodes 104 (e.g., node 104-1 in the illustrated example). In at least one embodiment, the sleep controller 118 operates to transition to an active clock inhibit state in response to an idle condition at the associated node 104-1. The idle condition may include, for example, that the node 104-1 is idle for a specified period of time. In this active clock inhibit state, the sleep controller 118 controls the node 104-1 to inhibit forwarding of the received clock wake signal 116, i.e., to "squash" the received clock wake signal 116, until either a valid data packet is received or the specified period of time has elapsed. If a valid data packet is received during the active clock inhibit state, the sleep controller 118 ceases control of the node 104-1 to inhibit the received clock wake signal 116 and transitions to a normal active state. After the specified period of time has elapsed, the sleep controller 118 transitions to a dormant state and the node 104-1 is no longer controlled to actively suppress the received clock wake signal 116 (i.e., the node 104-1 is permitted to forward the clock wake signal 116), so that the node 104-1 can quickly respond to the clock wake signal 116 and subsequent data packets back to an active state. In this approach, actively suppressing the clock wake signal 116 at the node 104-1 for the specified period of time allows the node 104-1 and the sleep controller 118 to remove the false clock wake signal 116 from the ring transport 102 and transition to a dormant state. In the dormant state, the next clock wake signal 116 received must be a valid clock wake signal 116 preceding a data packet, thus signaling that the ring transport 102 has returned to active data transmission.

[0012] Figure 2 illustrates in more detail an embodiment of node 104-1 and sleep controller 118 of ring transport 102 of Figure 1, in accordance with some embodiments. For ease of explanation, node 104-1 and sleep controller 118 are shown in a unidirectional ring configuration transmitting signaling in a clockwise direction 108 (Figure 1). It will be understood that in a bidirectional ring configuration, the components and operations described below are duplicated for control and data signaling traveling in the opposite direction (e.g., counterclockwise).

[0013] In one embodiment, the wire interconnect 106 includes a plurality of wires (also commonly referred to as traces, leads, conductors, etc.), including wires for control signaling and wires for data signaling. The data signaling wires include K data wires 202 for transmitting K data bits (bits D0 to DK-1) (K>=1) of a data packet in parallel, or 2×K data wires 202 for a differential signaling implementation. The control signaling wires include a valid wire 204 for transmitting a VALID signal that is asserted to indicate that the state of the data wires 202 represents valid data in conjunction with the insertion of data on the K data wires for a data packet. The control signaling wires further include a CLK_EN wire 206 for communicating a clock wake signal 116 (e.g., a pulse or other temporary assertion of the CLK_EN wire 206) a specified number of clock cycles (e.g., one clock cycle) prior to the insertion of the corresponding data packet on the data wires 202. The nodes 104, including node 104-1, implement a repeater 205 that functions to buffer, amplify, and forward signaling on the wire interconnects 106 received at the inputs of the nodes 104. In one embodiment, the repeater 205 is implemented as multiple digital buffers 208, one for each wire of the wire interconnects with each digital buffer 208 having an input connected to a corresponding upstream wire segment on the input side of the node 104 and an output connected to a corresponding downstream wire segment on the output side of the node 104. Although a single digital buffer per wire implementation is shown, the repeater 205 can be implemented using other circuit configurations using the guidelines provided herein. Each of the nodes 104 further includes a skid buffer 212 located at the input or output side (as shown) of the node 104. Skid buffer 212 includes dual buffers 214, 216, multiplexing / demultiplexing circuits 218, 220, and a controller 224, and operates to buffer incoming data packets received on data wire 202 for downstream transfer.The dual buffers 214, 216 allow the skid buffer 212 to buffer incoming data packets while previously received data packets are being processed for subsequent downstream transmission.

[0014] Each node 104 further includes a node interface 225 that serves as an interface between the node's wire interconnect 106 and one or more components 110 of that node. The node interface 225 is coupled to various wires of the wire interconnect 106 and operates to inject data packets received from the components 110 into the ring transport 102 for transmission to downstream nodes, while simultaneously controlling the CLK_EN wire 206 and the valid wire 204 to provide a clock wake signal 116 that precedes the injected data packet and valid signaling that is used to indicate that the state of the data wire 202 represents valid data. On the receiving side, the node interface 225 operates to receive the clock wake signal 116 at the input side of the CLK_EN wire 206 and, in response, deactivate the clock gating applied to the ring clock signal 112 at the node 104 or one or more components 110, thereby causing the node 104 and one or more components 110 to be activated and clocked in time for the reception of the data packet that is expected to follow the reception of the clock wake signal 116. If such a data packet follows, the node interface 225 operates to determine whether the data packet is intended for a component 110 associated with the node, and if so, to provide a copy of the data in the data packet to the intended component 110.

[0015] Turning to sleep controller 118, in one embodiment, this component includes a state machine 226 and a set of countdown timers, including idle timer 228 and inhibit timer 230, that are clocked by ring clock signal 112 or a clock derived therefrom. State machine 226 is implemented using hard-coded logic, programmable logic, a processor executing firmware or hardware, or a combination thereof. The state machine 226 has an input coupled to the input side of the CLK_EN wire 206 to monitor for receipt of a clock wake signal 116 at the node 104-1, an input coupled to the input side of the valid wire 204 to monitor for receipt of a valid data packet at the node 104-1 (assertion of the valid wire 204 invokes an indication that the “data” signaled by the data wire 202 is valid), and an output providing a sleep signal 232 used to control the digital buffer 208 of the CLK_EN wire 206 such that when the sleep signal 232 is asserted (i.e., SLEEP=1) and there is no valid incoming data packet (i.e., VALID=0), the digital buffer 208 is effectively disabled during this state and does not repeat the received clock wake signal 116 (i.e., suppresses or “squishes” the received clock wake signal 116). In the illustrated embodiment, this configuration is implemented using an AND gate 234 disposed between the upstream segment of the CLK_EN wire 206 and an input of the digital buffer 208, whereby the AND gate 234 has an inverted input that receives an inverted representation of the sleep signal 232, an input coupled to the upstream segment of the CLK_EN wire 206, and an output that serves as an input to the digital buffer 208 of the CLK_EN wire 206. In other embodiments, different logic implementations are used in accordance with the teachings provided herein.

[0016] The operation of state machine 226 in controlling the operation of node 104-1 is represented by the illustrated state diagram 240 and includes four operational states: active state 242, idle state 244, clock inhibit state 246, and sleep state 248. State machine 226 monitors CLK_EN wire 206 and enable wire 204 as described above to detect the presence of clock wake signal 116 (CLK_EN) and data traffic passing through node 104-1. While there is active data traffic, state machine 226 remains in active state 242 during which sleep signal 232 is not asserted (or deasserted), thus allowing received clock wake signal 116 to be forwarded by repeater 205. If clock wake signal 116 is received without a subsequent data packet, state machine 226 transitions to idle state 244. Similar to the active state 242, in the idle state, the sleep signal 232 is not asserted, allowing the received clock wake signal 116 to be forwarded to downstream nodes. After a specified idle condition occurs, such as after a first specified period of idle state 244 (measured by the idle timer 228 without any data traffic being received at node 104-1), the state machine 226 transitions to the clock inhibit state 246. During the clock inhibit state 246, the sleep controller 118 actively inhibits the clock wake signal 116 received at node 104-1 by asserting the sleep signal 232, thereby essentially disabling the digital buffer 208 on the CLK_EN wire 206. This prevents the repeater 205 from repeating the received clock wake signal 116 received at the input side of node 104-1.

[0017] The state machine 226 remains in the clock inhibit state 246 for a second specified period of time (measured via inhibit timer 230) unless data traffic is received at node 104-1. This second specified period of time is selected or otherwise specified in one embodiment to represent a period of time expected to allow any erroneous clock wake signals 116 present on the ring transport 102 to reach node 104-1 and then be inhibited before transitioning to a dormant state 248. If data traffic is received during the clock inhibit state 246 before the second specified period of time has elapsed, the state machine 226 returns to the active state. Otherwise, while in the dormant state 248, node 104-1 switches to a clock gating state and the state machine 226 deasserts the sleep signal 232 to allow downstream propagation of the clock wake signal 116 received by the repeater 205. If a clock wake signal 116 is received and a data packet follows, the state machine 226 returns to the active state 242. If the clock wake signal 116 is received and no data packet follows, the state machine 226 returns to the idle state 244 .

[0018] FIG. 3 illustrates a method 300 that illustrates the transition of the state machine 226 from an idle state to a clock inhibit state to a hibernate state implemented by the sleep controller 118, according to some embodiments. It should be noted that although certain blocks are illustrated in FIG. 3 in a predetermined order, the processes represented by these blocks may be performed simultaneously or in a different order. Block 302 represents the state machine 226 transitioning to the idle state 244 after detecting receipt of the clock wake signal 116 that is not followed by a data packet. In response to transitioning to the idle state 244, at block 304, the state machine 226 resets the idle timer 228 to a value M that represents a first designated period of time. The first designated period of time may be fixed or programmable and is designated based on any of a variety of considerations, such as from modeling the operation of the ring transport 102, or based on real-time feedback during actual operation of the ring transport 102. The idle timer 228 then counts down from M every cycle of the ring clock signal 112. While the idle timer 228 is elapsed, the state machine 226 monitors for receipt of a data packet at node 104-1, at block 306. If a data packet is received, the state machine 226 transitions back to the active state 242, at block 308. Otherwise, if M cycles have elapsed since transitioning to the idle state 244 (i.e., the idle timer 228 has elapsed), as determined at block 310, the state machine 226 transitions to the clock inhibit state 246, at block 312.

[0019] In response to transitioning to the clock inhibit state, at block 314, the state machine 226 resets the inhibit timer 230 to a value N representing a second specified period of time, which may be fixed or programmable. In at least one embodiment, the value N is set as a time (measured in clock cycles) sufficient to allow all erroneous clock wake signals 116 present on the ring transport 102 to be inhibited at the node 104-1. To illustrate, if it takes 20 clock cycles for the clock wake signal 116 to complete a circuit on the ring transport 102, the value N may be set to a value slightly greater than 20, such as 22, to allow sufficient time for any given erroneous clock wake signal 116 on the ring transport 102 to reach the node 104-1 and be inhibited. Once reset to the value N, the inhibit timer 230 counts down from N for every cycle of the ring clock signal 112.

[0020] Further, in response to transitioning to the clock inhibit state 246, the state machine 226 asserts the sleep signal 232 at block 316. The assertion of the sleep signal 232 then configures the digital buffer 208 on the CLK_EN wire 206 not to repeat any received clock wake signals 116, thus squashing or suppressing any erroneous clock wake signals 116 received at node 104-1 during the clock inhibit state 246.

[0021] As represented by decision block 318, the state machine 226 monitors the expiration of the inhibit timer 230 (i.e., whether N clock cycles have elapsed since transitioning to the clock inhibit state 246). If the inhibit timer 230 has expired, then at block 320 the state machine 226 transitions to the dormant state 248 and deasserts the sleep signal 232. Once the sleep signal 232 is deasserted in the dormant state 248, the digital buffer 208 is activated and the clock wake signal 116 received from the upstream node 104 may be forwarded to the downstream node 104. Thus, at block 322 the state machine 226 monitors for receipt of a data packet at the node 104-1, and at block 324 the state machine 226 monitors for receipt of the clock wake signal 116 without a subsequent data packet. Upon receipt of a data packet at the node 104-1 during the dormant state 248, the state machine 226 transitions back to the active state 242 at block 308. If, during the sleep state 248 , a clock wake signal 116 without a subsequent data packet is received at node 104 - 1 , the state machine transitions back to the idle state 244 at block 302 .

[0022] Returning to block 318, while in the clock inhibit state 246, the state machine 226 monitors for receipt of a data packet in block 326 while the second specified period has not elapsed. Note that in the active, idle and dormant states, there is no active clock wake signal inhibit. Thus, when a data packet is received at the node 104-1 in any of these states, the clock wake signal preceding the data packet is forwarded by the repeater 205, and the received data packet is then processed in the next clock cycle as normal. However, in the clock inhibit state 246, the clock wake signal is inhibited at the node 104-1. Thus, when a data packet is detected as being received at the node 104-1 in block 326, this means that the clock wake signal preceding the data packet has been inhibited, and therefore, since there is no repeated clock wake signal to process the data packet, the data packet cannot be immediately processed and sent downstream. Instead, node 104-1 generates a new clock wake signal 116 that precedes the data packet to be repeated toward downstream node 104-2.

[0023] Thus, during the clock inhibit state 246, in response to receiving a data packet, the data packet is buffered in one of the dual buffers 214, 216 of the skid buffer 212 at block 328, the sleep signal 232 is deasserted to reactivate the tri-state digital buffer 208 on the CLK_EN wire 206 at block 330, and the state machine 226 generates a clock wake signal 116 by the tri-state digital buffer 208 for transmission to the downstream node 104-2 via the CLK_EN wire 206 at block 332. During the clock cycle following the generation of the clock wake signal 116, the skid buffer outputs the buffered data packet on the data wire 202 at block 334, and after the generated clock wake signal, asserts the valid wire 204 to forward the data packet and the valid signal downstream. Additionally, another data packet may be received during this process, since there is a delay caused by the need to regenerate the inhibited clock wake signal 116 before the data packet can be repeated. Thus, the skid buffer 212 can utilize other buffers to temporarily store this second received data packet until the first received packet is transmitted, at which point the second data packet can be provided for similar forwarding to the next node 104-2.

[0024] In some embodiments, the above apparatus and techniques are implemented in a system that includes one or more integrated circuit (IC) devices (also called integrated circuit packages or microchips), such as the IC device 100 described with reference to FIGS. 1-3. Electronic design automation (EDA) and computer-aided design (CAD) software tools are used to design and manufacture these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system that operates the computer system to operate on the code representing the circuits of the one or more IC devices to perform at least a portion of the processing to design or adapt a manufacturing system for manufacturing the circuits. This code may include instructions, data, or a combination of instructions and data. The software instructions representing the design or manufacturing tools are typically stored in a computer readable storage medium accessible by the computing system. Similarly, the code representing one or more phases of the design or manufacture of the IC device may be stored in or accessed from the same or different computer readable storage medium.

[0025] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0026] In some embodiments, some aspects of the above techniques may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored in or tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by one or more processors, operate the one or more processors to perform one or more aspects of the above techniques. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or one or more other non-volatile memory devices, etc. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats that can be interpreted or executed by one or more processors.

[0027] According to one aspect, a method includes, at a node of a ring transport of an integrated circuit (IC) device, monitoring a wire used to transmit a clock wake signal around the ring transport. The method further includes, in response to identifying an idle condition of the ring transport via monitoring the wire, configuring the node into a clock inhibit state for a first specified time period, while in the clock inhibit state, the node inhibits further transmission of a clock wake signal received at the node. In some embodiments, the method further includes, at each node of a plurality of nodes of the ring transport, switching from a clock gating state to a clock state in response to receiving the clock wake signal at the node.

[0028] According to another aspect, an IC device includes a ring transport having a plurality of nodes and a wire interconnect coupling the plurality of nodes in a ring, the wire interconnect including a wire configured to transmit a clock wake signal around the ring transport. The ring transport further includes a sleep controller coupled to a selected node of the plurality of nodes, the sleep controller configures the selected node to a clock inhibit state for a first specified time period in response to identifying an idle condition of the ring transport by monitoring the wire, during which the node inhibits further transmission of the clock wake signal received at the selected node. In some embodiments, each node of the plurality of nodes is configured to switch from a clock gating state to a clock state in response to receiving the clock wake signal at the node. Furthermore, in some embodiments, the idle condition includes the lapse of a second specified time period after a clock wake signal without a subsequent data packet is received at the selected node. Further, in some embodiments, the first designated period is represented by a first designated number of clock cycles of a clock signal used to clock the ring transport, the first designated number of clock cycles having a corresponding period at least equal to a period required for the clock wake signal to circumnavigate the ring transport, and the second designated period is represented by a second designated number of clock cycles of the clock signal. Further, in some embodiments, the sleep controller configures the selected node to a dormant state in response to the passage of the first designated period and no data traffic being received at the selected node while in the clock inhibit state, and while in the dormant state, the selected node is permitted to forward clock wake signals received at the selected node.

[0029] According to yet another aspect, a device includes a ring transport configured to transport data packets between a plurality of nodes, each node being selectively clocked by a clock signal, and each data packet being preceded by a clock wake signal on the ring transport, a select node of the plurality of nodes configured to, in response to the ring transport being idle for a first designated period of time, suppress the clock wake signal received at the select node during a second designated period of time subsequent to the first designated period of time.

[0030] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0031] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and features by which any benefit, advantage, or solution may occur or be manifested are not to be construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as set forth in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. At a node of a ring transport of an integrated circuit (IC) device, monitoring a wire used to transmit a clock wake signal around said ring transport; configuring the node into a clock inhibit state for a first specified time period in response to identifying an idle condition of the ring transport by monitoring the wire; While in the clock inhibit state, the node inhibits further transmission of clock wake signals received at the node. method.

2. and, at each node of the plurality of nodes of the ring transport, switching from a clock gating state to a clock state in response to receiving a clock wake signal at the node.

2. The method of claim 1.

3. the idle condition includes a second specified period of time elapses after a clock wake signal is received at the node without a subsequent data packet; 2. The method of claim 1.

4. configuring the first specified period as a first specified number of clock cycles of a clock signal used to clock the ring transport, the first specified number of clock cycles having a corresponding period at least equal to a period required for a clock wake signal to cycle around the ring transport; configuring the second specified period as a second specified number of clock cycles of the clock signal. The method of claim 3.

5. and configuring the node into a dormant state in response to the first specified period of time having elapsed and no data traffic being received at the node during the clock inhibit state, the node being permitted to forward clock wake signals received at the node.

2. The method of claim 1.

6. in response to receiving a first data packet at the node while in the clock inhibit state, buffering the first data packet in a first buffer of a skid buffer of the node; generating a clock wake signal at said node and transmitting said clock wake signal to a next node in said ring transport; transmitting the first data packet from the first buffer to the next node following transmission of the generated clock wake signal.

2. The method of claim 1.

7. in response to receiving a second data packet at the node while buffering the first data packet, buffering the second data packet in a second one of the skid buffers; subsequent to transmitting the first data packet, transmitting the second data packet to the next node. The method of claim 6.

8. 1. An integrated circuit (IC) device comprising a ring transport, comprising: The ring transport comprises: A plurality of nodes; a wire interconnect coupling the plurality of nodes in a ring, the wire interconnect including a wire configured to transmit a clock wake signal around the ring transport; a sleep controller coupled to a selected node of the plurality of nodes; the sleep controller configures the selected node into a clock inhibited state for a first specified time period in response to identifying an idle condition of the ring transport by monitoring the wire; While in the clock inhibit state, the node inhibits further transmission of clock wake signals received at the selected node. Integrated circuit (IC) devices.

9. each node of the plurality of nodes is configured to switch from a clock gating state to a clock state in response to receiving a clock wake signal at the node; The IC device of claim 8.

10. the idle condition includes a second specified period of time elapses after a clock wake signal is received at the selected node without a subsequent data packet; The IC device of claim 8.

11. the first specified period is represented by a first specified number of clock cycles of a clock signal used to clock the ring transport, the first specified number of clock cycles having a corresponding period at least equal to a period required for a clock wake signal to cycle around the ring transport; the second specified period being represented by a second specified number of clock cycles of the clock signal. The IC device of claim 10.

12. the sleep controller configures the selected node into a dormant state in response to the first specified period of time having elapsed and no data traffic being received at the node while in the clock inhibited state; During the dormant state, the selected node is permitted to forward a clock wake signal received at the selected node. The IC device of claim 8.

13. in response to receiving a first data packet at the selected node while in the clock inhibited state, The selection node is buffering the first data packet in a first one of the skid buffers of the selected node; generating a clock wake signal at the selected node and transmitting the clock wake signal to a next node in the ring transport; transmitting the first data packet from the first buffer to the next node following the transmission of the generated clock wake signal. The IC device of claim 8.

14. in response to receiving a second data packet at the selected node while buffering the first data packet, The selection node is buffering the second data packet in a second buffer of the skid buffer; transmitting the second data packet to the next node subsequent to transmitting the first data packet; The IC device of claim 13.

15. the IC device includes a processor; The IC device of claim 8.

16. 1. A device comprising: a ring transport configured to transport data packets between a plurality of nodes, each node being selectively clocked by a clock signal, each data packet being preceded in the ring transport by a clock wake signal, the device comprising: a selected node of the plurality of nodes is configured, in response to the ring transport satisfying an idle condition for a first designated period of time, to suppress a clock wake signal received at the selected node during a second designated period of time subsequent to the first designated period of time. device.

17. each node of the plurality of nodes is configured to switch from a clock gating state to a clock state in response to receiving a clock wake signal at the node; 17. The device of claim 16.

18. the idle condition includes a second specified period of time elapses after a clock wake signal is received at the selected node without a subsequent data packet; 17. The device of claim 16.

19. the second specified period being represented by a first specified number of clock cycles of the clock signal, the first specified number of clock cycles having a corresponding period at least equal to a period required for a clock wake signal to complete one revolution of the ring transport; the first specified period being represented by a second specified number of clock cycles of the clock signal.

20. The device of claim 18.

20. in response to receiving a first data packet at the selected node while suppressing a clock wake signal; The selection node is buffering the first data packet in a first one of the skid buffers of the selected node; generating a clock wake signal at the selected node and transmitting the clock wake signal to a next node in the ring transport; transmitting the first data packet from the first buffer to the next node following the transmission of the generated clock wake signal.

17. The device of claim 16.

21. in response to receiving a second data packet at the selected node while buffering the first data packet, The selection node is buffering the second data packet in a second buffer of the skid buffer; transmitting the second data packet to the next node subsequent to transmitting the first data packet; 21. The device of claim 20.

22. The device includes a processor.

17. The device of claim 16.

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