Wiring board and manufacturing method thereof

Abstract

To provide a wiring board capable of suppressing damage to a thin film capacitor.SOLUTION: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, a wiring layer electrically connected to the thin film capacitor, and a sealing resin layer laminated on the thin film capacitor, and the wiring layer includes a pad protruding from the thin-film capacitor, the sealing resin layer is a mold resin containing a non-photosensitive thermosetting resin as a main component, and the sealing resin layer exposes the top surface of the pad and covers at least a part of the side surface of the pad.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board and a manufacturing method thereof. [Background technology]

[0002] Conventionally, wiring boards on which electronic components such as semiconductor chips are mounted are known in which a plurality of wiring layers and insulating layers are alternately laminated by a build-up method in order to increase the density of the wiring pattern. As this type of wiring board, a structure in which a thin-film capacitor is embedded inside in order to improve the transmission characteristics has been considered (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-179865 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to further improve the transmission characteristics of a wiring board, it is necessary to mount a thin-film capacitor on the top surface side close to the semiconductor chip. However, when mounting a semiconductor chip on a wiring board with a thin-film capacitor mounted on the top surface side, there is a risk that the thin-film capacitor will be damaged due to thermal stress and pressure during mounting.

[0005] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a wiring board capable of suppressing damage to a thin-film capacitor. [Means for solving the problem]

[0006] The wiring board has an insulating layer, a thin-film capacitor laminated on the insulating layer, a wiring layer electrically connected to the thin-film capacitor, and a sealing resin layer laminated on the thin-film capacitor, the thin-film capacitor having a dielectric provided between the insulating layer and the sealing resin layer, a first electrode provided on one surface of the dielectric, and a second electrode provided on a surface opposite to the one surface of the dielectric, the wiring layer has a first via wiring in contact with the first electrode, a second via wiring in contact with the second electrode, and a plurality of pads protruding from the thin-film capacitor, the first via wiring penetrating the sealing resin layer, the first electrode, and the dielectric, the second via wiring penetrating the sealing resin layer, the dielectric, and the second electrode, the sealing resin layer is a mold resin mainly composed of a non-photosensitive thermosetting resin, and the sealing resin layer exposes an upper surface of the pad and has a side All The pads have a uniform height, and upper surfaces of the pads are flush with an upper surface of the sealing resin layer. Effect of the Invention

[0007] According to the disclosed technique, it is possible to provide a wiring board capable of suppressing damage to a thin-film capacitor. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of the wiring board according to the first embodiment; [Diagram 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4] 6A to 6C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; [Diagram 5] 4A to 4D are views illustrating the manufacturing process of the wiring board according to the first embodiment; [Figure 6] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment; [Figure 7]6 is a diagram illustrating a manufacturing process of the wiring board according to the first embodiment; FIG. [Figure 8] 1 is a cross-sectional view illustrating a multilayer wiring board according to Application Example 1 of the first embodiment. [Figure 9] 11 is a cross-sectional view illustrating a semiconductor device according to Application Example 2 of the first embodiment. FIG. [Figure 10] 1 is a cross-sectional view illustrating a wiring board according to a first modified example of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted.

[0010] First Embodiment [Wiring board structure] First, a description will be given of the structure of the wiring board according to the first embodiment. Fig. 1 is a cross-sectional view illustrating the wiring board according to the first embodiment.

[0011] 1, the wiring board 1 according to the first embodiment has a first wiring structure 1L, a second wiring structure 1H laminated on the first wiring structure 1L, and a sealing resin layer 34 laminated on the second wiring structure 1H. The planar shape of the wiring board 1 can be, for example, a square or rectangular shape. However, the planar shape is not limited to this, and the wiring board 1 can be any planar shape.

[0012] The first wiring structure 1L is a low-density wiring layer having a wiring layer with a lower wiring density than the second wiring structure 1H, and includes a wiring layer 11, an insulating layer 12, and a wiring layer 13. In contrast, the second wiring structure 1H is a high-density wiring layer having a wiring layer with a higher wiring density than the first wiring structure 1L, and includes a wiring layer 14, an insulating layer 15, a wiring layer 16, an insulating layer 17, a wiring layer 18, an insulating layer 19, a thin-film capacitor 20, and a wiring layer 31.

[0013] In this embodiment, for convenience, the sealing resin layer 34 side of the wiring board 1 is referred to as the upper side or one side, and the insulating layer 12 side is referred to as the lower side or the other side. Also, the surface of each part on the sealing resin layer 34 side is referred to as one side or upper side, and the surface on the insulating layer 12 side is referred to as the other side or lower side. However, the wiring board 1 can be used upside down or placed at any angle. Also, the planar view refers to viewing the object from the normal direction of the upper surface 34a of the sealing resin layer 34, and the planar shape refers to the shape of the object viewed from the normal direction of the upper surface 34a of the sealing resin layer 34.

[0014] The wiring layer 11 is the lowest wiring layer exposed on the lower surface side of the insulating layer 12, and its upper surface and side surfaces are covered by the insulating layer 12. The lower surface of the wiring layer 11 is exposed, for example, at a position recessed from the lower surface 12b of the insulating layer 12 toward the wiring layer 13 side. However, if necessary, the lower surface of the wiring layer 11 may be flush with the lower surface 12b of the insulating layer 12. Alternatively, a part of the side surface and the lower surface of the wiring layer 11 may protrude downward from the lower surface 12b of the insulating layer 12.

[0015] The wiring layer 11 is, for example, a circular pad with a planar shape of about 150 μm in diameter, but may include a wiring pattern. The interval between adjacent wiring layers 11 may be, for example, about 200 μm. The material of the wiring layer 11 may be, for example, copper (Cu), etc. The thickness of the wiring layer 11 may be, for example, about 10 to 20 μm. The wiring layer 11 may be used as an external connection terminal (pad) for electrically connecting to another wiring board.

[0016] A surface treatment layer 110 may be formed on the lower surface of the wiring layer 11. Examples of the surface treatment layer 110 include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and a Au layer in this order), a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and a Au layer in this order), etc. In addition, an oxidation prevention treatment such as an OSP (Organic Solderability Preservative) treatment may be performed on the lower surface of the wiring layer 11.

[0017] The insulating layer 12 covers the top and side surfaces of the wiring layer 11. The insulating layer 12 is mainly composed of a non-photosensitive thermosetting resin, and has a reinforcing member 128. The insulating layer 12 can be configured by impregnating the reinforcing member 128 with a non-photosensitive thermosetting resin. Here, "mainly composed of a non-photosensitive thermosetting resin" means that the insulating layer 12 may contain other components such as a filler in addition to the thermosetting resin.

[0018] Examples of the non-photosensitive thermosetting resin used in the insulating layer 12 include epoxy resin, imide resin, phenol resin, and cyanate resin. Examples of the reinforcing member 128 include woven or nonwoven fabrics of glass fiber, carbon fiber, aramid fiber, and the like. Examples of the filler contained in the insulating layer 12 include silica (SiO 2 ), Kaolin (Al 2 S 2 O 5 (OH 4 )), Talc(Mg 3 S 4 O 10 (OH 2 )), alumina (Al 2 O 3 ) and the like. These may also be used in combination.

[0019] The thickness of the insulating layer 12 may be, for example, about 60 to 70 μm. The thermal expansion coefficient of the insulating layer 12 may be, for example, 5 ppm / ° C. or more and 10 ppm / ° C. or less. The thermal expansion coefficient of the insulating layer 12 can be adjusted to a predetermined value by, for example, the filler content, the composition of the insulating resin, etc. The thermal expansion coefficient of the insulating layer 12 is lower than the thermal expansion coefficients of the insulating layers 15, 17, and 19.

[0020] The wiring layer 13 is a via wiring buried in the insulating layer 12. More specifically, the wiring layer 13 is a via wiring filled in a via hole 12x that penetrates the insulating layer 12 and exposes the upper surface of the wiring layer 11, and is electrically connected to the wiring layer 11. The via hole 12x may be an inverted truncated cone-shaped recess in which the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 11. The diameter of the opening of the via hole 12x may be, for example, about 60 to 70 μm.

[0021] The upper surface of the wiring layer 13, which is a via wiring, is exposed from the upper surface 12a of the insulating layer 12. The upper surface of the wiring layer 13 may be flush with the upper surface 12a of the insulating layer 12, for example. The upper surface of the wiring layer 13 is directly bonded to the lower surface of the wiring layer 14. In addition, the lower surface of the wiring layer 13 is directly bonded to the wiring layer 11 within the insulating layer 12. The material of the wiring layer 13 may be the same as that of the wiring layer 11, for example.

[0022] In this embodiment, the wiring layer 13 is composed only of via wiring formed in the via hole 12x of the insulating layer 12. In other words, the wiring layer 13 does not have a wiring pattern integrally formed on the upper surface 12a of the insulating layer 12. The wiring layer 13 and the wiring layer 14 are electrically connected but are not integral. Specifically, in a manufacturing method described later, when the wiring layer 14 is formed by a semi-additive method, a seed layer is interposed at the boundary between the upper surface of the wiring layer 13 and the lower surface of the wiring layer 14. The reason for adopting such a structure is to form a high-density wiring pattern (for example, a line / space of about 3 μm / 3 μm) as the wiring layer 14 described later. Details will be described in the section on the manufacturing method of the wiring board 1.

[0023] The wiring layer 14 is formed on the upper surface 12a of the insulating layer 12. The wiring layer 14 is formed directly on the upper surface 12a of the insulating layer 12, and includes wiring (wiring patterns and pads) electrically connected to the wiring layer 11 via the wiring layer 13. That is, a part of the lower surface of the wiring layer 14 contacts the upper surface of the wiring layer 13, and the two are electrically connected. For example, copper (Cu) or the like can be used as the material of the wiring layer 14. The wiring layer 14 may be a laminated film in which a plurality of conductor layers are laminated.

[0024] The wiring layer 14 has a higher wiring density (narrower line / space) than the wiring layer 11, and is thinner than the wiring layer 11. In this specification, a wiring layer with a line / space of 8 μm / 8 μm or less is defined as a wiring layer with a high wiring density. The line / space of the wiring layer 14 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm. The thickness of the wiring layer 14 can be, for example, about 1 to 3 μm.

[0025] In line / space, the line represents the wiring width, and the space represents the distance between adjacent wirings (wiring distance). For example, if the line / space is described as 2 μm / 2 μm, it means that the wiring width is 2 μm and the distance between adjacent wirings is 2 μm.

[0026] The insulating layer 15 is an insulating layer mainly composed of a photosensitive resin. "Mainly composed of a photosensitive resin" means that the insulating layer 15 may contain other components such as a filler in addition to the photosensitive resin. For example, the insulating layer 15 may contain silica (SiO 2 ) may be contained as a filler.

[0027] The insulating layer 15 is formed on the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 14. Examples of the photosensitive resin used for the insulating layer 15 include insulating resins such as phenolic resins and polyimide resins. The thickness of the insulating layer 15 can be, for example, 5 μm or more and 10 μm or less. The thermal expansion coefficient of the insulating layer 15 can be, for example, 40 ppm / ° C. or more and 60 ppm / ° C. or less. The thermal expansion coefficient of the insulating layer 15 can be adjusted to a predetermined value by, for example, the content of the filler, the composition of the insulating resin, etc.

[0028] However, in the insulating layer 15 mainly composed of a photosensitive resin, the amount of filler that can be contained is limited (upper limit) because exposure becomes impossible if the filler content is too high. Therefore, the thermal expansion coefficient of the insulating layer 15 mainly composed of a photosensitive resin tends to be larger than the thermal expansion coefficient of the insulating layer 12 mainly composed of a non-photosensitive thermosetting resin and the thermal expansion coefficient of the sealing resin layer 34.

[0029] The wiring layer 16 is formed on one side of the insulating layer 15 and is electrically connected to the wiring layer 14. The wiring layer 16 includes via wiring filled in a via hole 15x that penetrates the insulating layer 15 and exposes the upper surface of the wiring layer 14, and a wiring pattern formed on the upper surface of the insulating layer 15. The via hole 15x may be an inverted truncated cone-shaped recess in which the diameter of the opening on the insulating layer 17 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 14. The diameter of the opening of the via hole 15x may be, for example, about 10 to 20 μm. The material of the wiring layer 16 and the thickness of the wiring pattern constituting the wiring layer 16 may be, for example, the same as that of the wiring layer 14.

[0030] The line / space of the wiring layer 16 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm, but it is possible to make the line / space narrower than that of the wiring layer 14. That is, the upper surface 12a of the insulating layer 12 is a polished surface and is smoother than the lower surface 12b of the insulating layer 12. However, the upper surface of the insulating layer 15, which is mainly composed of a photosensitive resin, is smoother than the upper surface 12a of the insulating layer 12, which is mainly composed of a non-photosensitive thermosetting resin. Therefore, the line / space of the wiring layer 16 can be narrower than that of the wiring layer 14. For example, the line / space of the wiring layer 14 can be 3 μm / 3 μm, and the line / space of the wiring layer 16 can be 1 μm / 1 μm. The same applies to the wiring layer 18 described later.

[0031] The insulating layer 17 is formed on one surface of the insulating layer 15 so as to cover the wiring layer 16. The material, thickness, and thermal expansion coefficient of the insulating layer 17 may be, for example, similar to those of the insulating layer 15. The insulating layer 17 is made of silica (SiO 2 ) may be contained as a filler.

[0032] The wiring layer 18 is formed on one side of the insulating layer 17 and is electrically connected to the wiring layer 16. The wiring layer 18 includes via wiring filled in a via hole 17x that penetrates the insulating layer 17 and exposes the upper surface of the wiring layer 16, and a wiring pattern formed on the upper surface of the insulating layer 17. The via hole 17x may be an inverted truncated cone-shaped recess in which the diameter of the opening opened on the insulating layer 19 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 16. The diameter of the opening of the via hole 17x may be, for example, about 10 to 20 μm. The material of the wiring layer 18 and the thickness of the wiring pattern constituting the wiring layer 18 may be, for example, the same as that of the wiring layer 14. The line / space of the wiring pattern constituting the wiring layer 18 may be, for example, the same as that of the wiring layer 16.

[0033] The insulating layer 19 is formed on one surface of the insulating layer 17 so as to cover the wiring layer 18. In the second wiring structure 1H, the insulating layer 19 is the uppermost insulating layer. The material, thickness, and thermal expansion coefficient of the insulating layer 19 may be the same as those of the insulating layer 15, for example. The insulating layer 19 is made of silica (SiO 2 ) may be contained as a filler.

[0034] The thin film capacitor 20 is laminated on one side of the insulating layer 19. The thin film capacitor 20 is a sheet-like capacitor with a thickness of about 50 μm, and includes, for example, a dielectric 21, a first electrode 22, a second electrode 23, and an adhesive layer 24. The first electrode 22 is formed on one side of the dielectric 21 and is connected, for example, to the ground of the circuit. The second electrode 23 is formed on the other side of the dielectric 21 and is connected, for example, to a power source of the circuit. The adhesive layer 24 is formed on the other side of the dielectric 21 so as to cover the second electrode 23, and is adhered to the insulating layer 19. The material of the dielectric 21 can be, for example, barium titanate. The material of the first electrode 22 and the second electrode 23 can be, for example, copper.

[0035] The wiring layer 31 is formed on one side of the thin-film capacitor 20 and is electrically connected to the thin-film capacitor 20. In the second wiring structure 1H, the wiring layer 31 is the uppermost wiring layer. The wiring layer 31 includes via wirings 32 filled in via holes 20x penetrating the thin-film capacitor 20 and via holes 19x penetrating the insulating layer 19 and exposing the upper surface of the wiring layer 18, and a plurality of pads 33 protruding from the upper surface side of the thin-film capacitor 20.

[0036] The via wiring 32 is formed continuously with the pad 33 and is electrically connected to the wiring layer 18. Some of the via wirings 32 penetrate the dielectric 21 and the first electrode 22 or the second electrode 23 and the adhesive layer 24 of the thin-film capacitor 20. That is, the first electrode 22 and the second electrode 23 are electrically connected to the wiring layer 18 through the via wiring 32. By having the via wiring 32 that penetrates and is electrically connected to the first electrode 22 and the via wiring 32 that penetrates and is electrically connected to the second electrode 23, a large capacitor structure is formed as a whole.

[0037] The via hole 19x may be an inverted truncated cone-shaped recess with an opening diameter on the adhesive layer 24 side of the thin-film capacitor 20 larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 18. The opening diameter of the via hole 19x may be, for example, about 10 to 20 μm.

[0038] The via hole 20x communicates with the via hole 19x. The via hole 20x is cylindrical with a substantially constant diameter at the opening, and the diameter at the opening of the via hole 20x is larger than the diameter at the opening of the via hole 19x. The diameter at the opening of the via hole 20x may be, for example, about 20 to 40 μm.

[0039] The material of the wiring layer 31 may be, for example, the same as that of the wiring layer 14. The thickness of the wiring layer 31 (the sum of the thickness of the via wiring 32 and the thickness of the pad 33) may be, for example, about 10 μm. The planar shape of the pad 33 may be, for example, a circle with a diameter of about 20 to 30 μm. The pitch of the pads 33 may be, for example, about 40 to 50 μm. The size relationship between the diameter of the pad 33 and the diameter of the opening of the via hole 20x may be determined arbitrarily. The portion of the pad 33 exposed from the sealing resin layer 34 may be used as an external connection terminal for electrical connection to a semiconductor chip.

[0040] A surface treatment layer 310 similar to the surface treatment layer 110 may be formed on the upper surface of the pad 33. When a part of the side surface and the upper surface of the pad 33 protrudes from the upper surface 34a of the sealing resin layer 34, the surface treatment layer 310 is formed only on the upper surface of the pad 33, or on a part of the side surface and the upper surface.

[0041] The sealing resin layer 34 is laminated on the thin-film capacitor 20, exposes the upper surface of each pad 33, and covers at least a part of the side surface of each pad 33. The sealing resin layer 34 may expose the upper surface of the pad 33 and cover the entire side surface of the pad 33. In this case, the upper surface of the pad 33 is flush with the upper surface 34a of the sealing resin layer 34, for example. However, a part of the side surface and the upper surface of the pad 33 may be protruded from the upper surface 34a of the sealing resin layer 34, or the upper surface of the pad 33 may be exposed at a position recessed from the upper surface 34a of the sealing resin layer 34. When a part of the side surface and the upper surface of the pad 33 are protruded from the upper surface 34a of the sealing resin layer 34, a gap between the sealing resin layer 34 and the semiconductor chip can be secured, so that it is easy to fill the gap between the sealing resin layer 34 and the semiconductor chip with underfill resin.

[0042] As the material of the sealing resin layer 34, for example, a mold resin can be used. The mold resin is an insulating resin mainly composed of a non-photosensitive thermosetting resin that can be used in a transfer molding method, a compression molding method, an injection molding method, etc. The mold resin is, for example, an insulating resin such as a non-photosensitive thermosetting epoxy resin, and may contain a filler similar to that of the insulating layer 12, but does not contain a reinforcing member such as glass fiber.

[0043] From the viewpoint of reducing warpage of the wiring board 1, the thickness of the sealing resin layer 34 is preferably thicker than the thickness of the insulating layer 12. If the thickness of the insulating layer 12 is 60 μm or more and 70 μm or less, the thickness of the sealing resin layer 34 can be, for example, 80 μm or more and 150 μm or less. The thermal expansion coefficient of the sealing resin layer 34 is preferably lower than the thermal expansion coefficients of the insulating layers 15, 17, and 19. Note that in FIG. 1, the thickness of the sealing resin layer 34 is drawn thinner than the thickness of the insulating layer 12 for convenience of drawing.

[0044] In order to reduce warping of the wiring board 1, it is preferable that the thermal expansion coefficient of the sealing resin layer 34 is approximately equal to the thermal expansion coefficient of the insulating layer 12. Here, approximately equal means that the thermal expansion coefficient of the sealing resin layer 34 is within ±20% of the thermal expansion coefficient of the insulating layer 12.

[0045] For example, if the thermal expansion coefficient of the insulating layer 12 is 5 ppm / ° C. or more and 10 ppm / ° C. or less, it is preferable that the thermal expansion coefficient of the sealing resin layer 34 is also 5 ppm / ° C. or more and 10 ppm / ° C. or less. The thermal expansion coefficient of the sealing resin layer 34 can be adjusted to a predetermined value by, for example, the filler content, the composition of the insulating resin, etc.

[0046] [Method for manufacturing wiring board according to the first embodiment] Next, a method for manufacturing a wiring board according to the first embodiment will be described. Figs. 2 to 7 are diagrams illustrating the manufacturing process of a wiring board according to the first embodiment. Here, an example of a process for manufacturing one wiring board is shown, but a process in which a plurality of parts that will become wiring boards are manufactured and then diced into individual wiring boards may be used. Here, an example of a process for forming a layer structure only on one side of a support is shown, but a process in which a layer structure is formed on both one side and the other side of a support may be used.

[0047] First, in the process shown in FIG. 2(a), a support 100 is prepared, a wiring layer 11 and an insulating layer 12 are formed on the support 100, a via hole 12x is formed in the insulating layer 12, and then a laminated structure of a seed layer 131 and an electrolytic plating layer 132 is formed on the insulating layer 12 and in the via hole 12x.

[0048] The support 100 has a structure in which, for example, a copper foil 104 with a carrier is laminated on one side of a core substrate 101. The core substrate 101 is, for example, a resin substrate having a thickness of about 0.7 mm, and may have a reinforcing member such as glass fiber. The copper foil 104 with a carrier has a structure in which a thin foil 104a made of, for example, copper and having a thickness of about 1.5 to 5 μm is peelably attached to a thick foil (carrier foil) 104b made of, for example, copper and having a thickness of about 10 to 50 μm, via a peeling layer (not shown). The thick foil 104b is provided as a support material to facilitate handling of the thin foil 104a.

[0049] The above-mentioned structure of the support 100 is an example, and the support 100 is not limited thereto. For example, in the support 100, a laminate in which a plurality of prepregs are laminated may be used instead of the core substrate 101. The support 100 may have a structure in which a carrier-attached copper foil 104 is disposed on one side of a glass substrate, a metal substrate, or the like, via a release layer.

[0050] After the support 100 is prepared, first, the wiring layer 11 is formed on one side of the support 100. Specifically, a resist layer having an opening in a portion where the wiring layer 11 is to be formed is formed on the upper surface of the carrier-attached copper foil 104 (upper surface of the thin foil 104a) using a dry film resist or the like. Then, by an electrolytic plating method using the carrier-attached copper foil 104 as a power supply layer, the wiring layer 11, which is an electrolytic plating layer, is formed on the upper surface of the carrier-attached copper foil 104 exposed in the opening. The material and thickness of the wiring layer 11 are as described above. Thereafter, the resist layer is peeled off.

[0051] Next, the insulating layer 12 that covers the wiring layer 11 is formed on the upper surface of the copper foil 104 with the carrier. Specifically, a semi-cured film-like insulating resin that is mainly composed of a non-photosensitive thermosetting resin and has a reinforcing member 128 is prepared. Then, this insulating resin is laminated on the upper surface of the copper foil 104 with the carrier, and cured under heat and pressure to form the insulating layer 12. The material, thickness, thermal expansion coefficient, etc. of the insulating layer 12 are as described above.

[0052] Next, a via hole 12x is formed in the insulating layer 12 so as to penetrate the insulating layer 12 and expose the upper surface of the wiring layer 11. The via hole 12x is formed by, for example, CO 2 The via holes 12x can be formed by a laser processing method using a laser, a YAG laser, an excimer laser, etc. After the via holes 12x are formed, it is preferable to perform a desmear process to remove resin residues adhering to the surfaces of the wiring layer 11 exposed at the bottoms of the via holes 12x.

[0053] Next, a laminated structure of a seed layer 131 and an electrolytic plating layer 132 is formed on the upper surface 12a of the insulating layer 12 and in the via holes 12x, for example, by using a semi-additive method. Specifically, first, the seed layer 131 is formed on the upper surface 12a of the insulating layer 12, the inner wall surface of the via holes 12x, and the upper surface of the wiring layer 11 exposed in the via holes 12x, by electroless plating or sputtering. As the seed layer 131, for example, a copper layer having a thickness of about 100 to 350 nm can be used. Alternatively, as the seed layer 131, a laminated film in which a titanium layer having a thickness of about 20 to 50 nm and a copper layer having a thickness of about 100 to 300 nm are laminated in this order may be used. By forming a titanium layer under the seed layer 131, the adhesion between the insulating layer 12 and the wiring layer 13 can be improved. Titanium nitride or the like may be used instead of titanium. Note that titanium and titanium nitride are metals having higher corrosion resistance than copper. Then, an electrolytic plating layer 132 (eg, a copper layer) is formed on the seed layer 131 by electrolytic plating using the seed layer 131 as a power supply layer.

[0054] 2(b), the upper surface side of the laminated structure of the seed layer 131 and the electrolytic plating layer 132 shown in FIG. 2(a) is polished to expose the upper surface 12a of the insulating layer 12, and the wiring layer 13, which is the via wiring filled in the via hole 12x, is formed. For example, a chemical mechanical polishing (CMP) method or the like can be used to polish the wiring layer 13. For example, the upper surface of the wiring layer 13 can be flush with the upper surface 12a of the insulating layer 12.

[0055] When the wiring layer 13 is polished, a part of the upper surface 12a of the insulating layer 12 may be polished and removed at the same time. By polishing the upper surface 12a of the insulating layer 12 together with the wiring layer 13 and removing a part of the upper surface 12a of the insulating layer 12, the roughness of the upper surface 12a of the insulating layer 12 can be made smaller than that before polishing. That is, the smoothness of the upper surface 12a of the insulating layer 12 can be improved. The roughness of the upper surface 12a of the insulating layer 12 is, for example, about Ra 300 to 400 nm before performing the CMP method (before polishing), and can be made about Ra 15 to 40 nm by performing the CMP method. In this way, by reducing the roughness of the upper surface 12a of the insulating layer 12 and improving the smoothness, it becomes possible to form fine wiring (a wiring layer with a high wiring density) in a later process. The roughness of the lower surface 12b of the insulating layer 12 is, for example, about Ra 180 to 280 nm.

[0056] 2(c), a wiring layer 14 having a predetermined pattern is formed on the upper surface of the wiring layer 13 and the upper surface 12a of the insulating layer 12. The wiring layer 14 can be formed, for example, by a semi-additive method, like the wiring layer 13. Specifically, a seed layer is first formed by electroless plating or sputtering so as to continuously cover the upper surface of the wiring layer 13 and the upper surface 12a of the insulating layer 12. Note that although electroless plating may be used to form the seed layer, sputtering is more advantageous for densifying the wiring layer, since a thinner film can be formed by sputtering.

[0057] Then, a photosensitive resist layer is formed on the entire upper surface of the seed layer, and the resist layer is exposed and developed to form an opening that exposes the portion where the wiring layer 14 is to be formed. Then, an electrolytic plating layer is formed on the upper surface of the seed layer exposed in the opening by electrolytic plating using the seed layer as a power supply layer. Then, after peeling off the resist layer, the electrolytic plating layer is used as a mask to remove the seed layer in the portion not covered by the electrolytic plating layer by etching. This forms the wiring layer 14 in which the electrolytic plating layer is laminated on the seed layer. The material, thickness, line / space, etc. of the wiring layer 14 are as described above. Note that the wiring layer 14 has a structure in which the electrolytic plating layer is laminated on the seed layer, but the distinction between the seed layer and the electrolytic plating layer is omitted in FIG. 2(c) and the like (the same may be omitted for other wiring layers).

[0058] 3(a), a liquid or paste-like photosensitive resin is applied to the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 14, and then heated at a temperature at which the resin does not harden to form the insulating layer 15 in a semi-hardened state. The material and thickness of the insulating layer 15 are as described above. Next, for example, via holes 15x are formed by photolithography, and the insulating layer 15 is heated to a hardening temperature or higher to harden it. The upper surface of the insulating layer 15, which is mainly composed of a photosensitive resin, is smoother than the upper surface 12a of the insulating layer 12. The roughness of the upper surface of the insulating layer 15 can be, for example, about Ra 2 to 6 nm.

[0059] 3(b), the same steps as those shown in FIG. 2(c) and FIG. 3(a) are repeated to form a wiring layer 16, an insulating layer 17, a wiring layer 18, and an insulating layer 19, and then a via hole 19x is formed that penetrates the insulating layer 19 and exposes the upper surface of the wiring layer 18. The subsequent steps shown in FIG. 4 to FIG. 6 will be described with reference to an enlarged view of part A in FIG. 3(b).

[0060] 4(a), the thin-film capacitor 20 is prepared, and a plurality of via holes 20x are formed in the thin-film capacitor 20 by laser processing or the like. The plurality of via holes 20x includes at least a via hole that opens to the first electrode 22 and a via hole that opens to the second electrode 23. The diameters of the via holes 20x do not need to be the same.

[0061] 4(b), the thin-film capacitor 20 is placed on the insulating layer 19 with the adhesive layer 24 facing the insulating layer 19. At this time, the via holes 19x and 20x communicate with each other. The adhesive layer 24 is then cured by heating or the like to fix the thin-film capacitor 20 onto the insulating layer 19.

[0062] Next, in the steps shown in Fig. 4(c) to Fig. 5(c), the wiring layer 31 is formed by, for example, a semi-additive method. First, as shown in Fig. 4(c), a seed layer 311 is formed by electroless plating or sputtering on the upper surface of the dielectric 21, the upper surface and side surface of the first electrode 22, the inner wall surfaces of the via holes 19x and 20x, and the upper surface of the wiring layer 18 exposed in the via hole 19x. As the seed layer 311, for example, a copper layer having a thickness of about 100 to 350 nm can be used.

[0063] 5(a), a photosensitive resist layer 500 is formed on the seed layer 311, and the resist layer 500 is exposed and developed to form an opening 500x that exposes a portion where the wiring layer 31 is to be formed. The resist layer 500 can be formed, for example, by laminating a dry film resist on the seed layer 311.

[0064] 5(b), an electrolytic plating layer 312 (e.g., a copper layer) is formed on the seed layer 311 exposed in the opening 500x by electrolytic plating using the seed layer 311 as a power supply layer. Then, in a process shown in FIG. 5(c), after the resist layer 500 is peeled off, the electrolytic plating layer 312 is used as a mask to remove the seed layer 311 in the portion not covered by the electrolytic plating layer 312 by etching. As a result, a wiring layer 31 is formed, which is composed of the seed layer 311 and the electrolytic plating layer 312 shown in FIG. 5(b), and includes the via wiring 32 filling the via holes 19x and 20x, and the pad 33 protruding from the upper surface side of the thin film capacitor 20.

[0065] Next, in the step shown in FIG. 6(a), the sealing resin layer 34 is formed on the thin film capacitor 20 so as to cover the upper and side surfaces of the pads 33 of the wiring layer 31. The sealing resin layer 34 can be formed, for example, by a molding method using a mold resin. For example, the structure shown in FIG. 5(c) is placed in a metal mold, and a mold resin that has been fluidized by applying pressure (for example, 5 to 10 MPa) is introduced into the metal mold. Thereafter, the mold resin is heated at a temperature of about 180° C. to harden it, thereby forming the sealing resin layer 34. Then, after the required sealing process is completed, the structure covered with the sealing resin layer 34 is removed from the metal mold. For example, a transfer molding method, a compression molding method, an injection molding method, or the like can be used as the molding method.

[0066] 6(b), the upper surface side of the sealing resin layer 34 shown in FIG. 6(a) is polished to expose at least the upper surface of the pad 33. For example, a CMP method or the like can be used to polish the sealing resin layer 34. The upper surface of the pad 33 can be flush with the upper surface 34a of the sealing resin layer 34. However, by adjusting the amount of polishing of the sealing resin layer 34, a part of the side surface and the upper surface of the pad 33 may be made to protrude from the upper surface 34a of the sealing resin layer 34, or the upper surface of the pad 33 may be exposed at a position recessed from the upper surface 34a of the sealing resin layer 34.

[0067] Next, in the step shown in FIG. 7(a), a dicing blade or the like is used to cut the outer periphery of the entire structure partially shown in FIG. 6(b). Next, in the step shown in FIG. 7(b), the support 100 shown in FIG. 7(a) is removed, and if necessary, a surface treatment layer 310 is formed on the upper surface of the pad 33, and a surface treatment layer 110 is formed on the lower surface of the wiring layer 11. To remove the support 100, first, the core substrate 101 and the thick foil 104b are mechanically peeled off from the thin foil 104a. Then, the thin foil 104a is removed by wet etching using, for example, an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like. At this time, if the wiring layer 11 is made of copper, the lower surface side of the wiring layer 11 is also etched, and the lower surface of the wiring layer 11 is recessed from the lower surface 12b of the insulating layer 12 toward the wiring layer 13. The surface treatment layers 110 and 310 may be formed by, for example, forming the above-mentioned metal layer or a laminate of metal layers by electroless plating, or may be subjected to an oxidation prevention treatment such as OSP treatment.

[0068] Thus, in wiring board 1, thin film capacitor 20 is disposed directly below pad 33. Pad 33 is used as an external connection terminal for electrical connection with a semiconductor chip, so when a semiconductor chip is mounted on wiring board 1, thin film capacitor 20 is disposed in a position close to the semiconductor chip. This makes it possible to reduce the equivalent series inductance of thin film capacitor 20, enabling the semiconductor chip to operate at high frequencies (e.g., 100 MHz or higher).

[0069] Furthermore, in the wiring board 1, an encapsulating resin layer 34 is laminated on the thin-film capacitor 20, exposing the top surfaces of the pads 33 and covering at least a portion of the side surfaces of the pads 33. When mounting a semiconductor chip on the wiring board 1, the pads 33 and the electrode pads of the semiconductor chip are connected by solder. If the thin-film capacitor were exposed on the surface of the wiring board, there would be a risk that the thin-film capacitor would crack due to thermal stress and pressure generated when mounting the semiconductor chip. However, in the wiring board 1, the encapsulating resin layer 34 laminated on the thin-film capacitor 20 makes the thin-film capacitor 20 less susceptible to the effects of thermal stress and pressure generated when mounting the semiconductor chip, and therefore damage to the thin-film capacitor can be suppressed.

[0070] Furthermore, in the wiring board 1, the upper surface side of the sealing resin layer 34 is polished to expose the upper surfaces of the pads 33, so that the height of the upper surfaces of the multiple pads 33 is uniform. Here, uniform height refers to a case where the highest pad is at a height of +10 μm or less than the lowest pad. Furthermore, the multiple pads 33 exposed from the sealing resin layer 34 have a uniform upper surface area and are polished to a smooth flat surface, so that when a semiconductor chip is mounted, the solder spreads uniformly, improving the mounting reliability of the semiconductor chip. Here, uniform area refers to a case where the upper surface of the largest pad is at most +20% of the upper surface of the smallest pad.

[0071] In addition, in conventional wiring boards, pads are not polished by CMP, which results in variations in pad height. Also, in conventional wiring boards, the entire side of the pad is exposed, so in the lower parts of the pad, the solder spreads to the side, resulting in a shortage of solder on the top surface. Wiring board 1 solves these problems.

[0072] In addition, in the wiring board 1, a first wiring structure 1L including an insulating layer 12 mainly made of a non-photosensitive thermosetting resin and a sealing resin layer 34 mainly made of a non-photosensitive thermosetting resin are arranged on either side of a second wiring structure 1H including insulating layers 15, 17, and 19 mainly made of a photosensitive resin. The thermal expansion coefficients of the insulating layer 12 and the sealing resin layer 34 are lower than the thermal expansion coefficients of the insulating layers 15, 17, and 19. This structure improves the imbalance of the thermal expansion coefficients in the thickness direction of the wiring board 1, thereby reducing warping of the wiring board 1.

[0073] Furthermore, by reducing warping of wiring board 1, it becomes easier to mount a semiconductor chip on the sealing resin layer 34 side of wiring board 1, or to mount wiring board 1 on another wiring board.

[0074] 7(a) may be the shipping form, that is, the wiring board 1 with the support 100 attached thereto.

[0075] <Application Example 1 of the First Embodiment> Application example 1 of the first embodiment shows an example of a laminated wiring board in which the wiring board according to the first embodiment is mounted on another wiring board. Note that in application example 1 of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0076] 8 is a cross-sectional view illustrating a laminated wiring board according to Application Example 1 of the first embodiment. Referring to Fig. 8, laminated wiring board 3 is a multilayer wiring board in which wiring board 1 is mounted on wiring board 2.

[0077] The wiring board 2 is a multilayer wiring board in which wiring layers and insulating layers are laminated on both sides of a core layer 50, and can be produced by, for example, a well-known build-up method. Each wiring layer of the wiring board 2 has a lower wiring density (wider lines / spaces) than wiring layers 14, 16, 18, and 31 of the wiring board 1. The lines / spaces of each wiring layer of the wiring board 2 can be, for example, about 20 μm / 20 μm.

[0078] In the wiring board 2, a wiring layer 52, an insulating layer 53, a wiring layer 54, an insulating layer 55, a wiring layer 56, a solder resist layer 57, and a wiring layer 58 are laminated in this order on one surface of a core layer 50. In addition, a wiring layer 62, an insulating layer 63, a wiring layer 64, an insulating layer 65, a wiring layer 66, and a solder resist layer 67 are laminated in this order on the other surface of the core layer 50.

[0079] The core layer 50 may be, for example, a so-called glass epoxy substrate in which a glass cloth is impregnated with an insulating resin such as an epoxy resin. The core layer 50 may be, for example, a substrate in which a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber is impregnated with an epoxy resin or a polyimide resin. The thickness of the core layer 50 may be, for example, about 60 to 400 μm. The core layer 50 is provided with a through hole 50x that penetrates the core layer 50 in the thickness direction. The planar shape of the through hole 50x is, for example, a circle.

[0080] The wiring layer 52 is formed on one surface of the core layer 50. The wiring layer 62 is formed on the other surface of the core layer 50. The wiring layer 52 and the wiring layer 62 are electrically connected by a through-wire 51 formed in the through hole 50x. The wiring layers 52 and 62 are patterned into a predetermined planar shape. The wiring layers 52 and 62 and the through-wire 51 may be made of, for example, copper (Cu). The thickness of the wiring layers 52 and 62 may be, for example, about 10 to 30 μm. The wiring layer 52, the wiring layer 62, and the through-wire 51 may be integrally formed.

[0081] The insulating layer 53 is formed on one surface of the core layer 50 so as to cover the wiring layer 52. The material of the insulating layer 53 may be, for example, a non-photosensitive thermosetting insulating resin mainly composed of an epoxy resin or a polyimide resin. The thickness of the insulating layer 53 may be, for example, about 30 to 40 μm. The insulating layer 53 is made of silica (SiO 2 ) may be contained as a filler.

[0082] The wiring layer 54 is formed on one side of the insulating layer 53. The wiring layer 54 includes via wiring filled in a via hole 53x that penetrates the insulating layer 53 and exposes the upper surface of the wiring layer 52, and a wiring pattern formed on the upper surface of the insulating layer 53. The wiring pattern constituting the wiring layer 54 is electrically connected to the wiring layer 52 through the via wiring. The via hole 53x can be an inverted truncated cone-shaped recess in which the diameter of the opening opened on the insulating layer 55 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 52. The material of the wiring layer 54 and the thickness of the wiring pattern can be the same as those of the wiring layer 52, for example.

[0083] The insulating layer 55 is formed on the upper surface of the insulating layer 53 so as to cover the wiring layer 54. The material and thickness of the insulating layer 55 may be, for example, the same as those of the insulating layer 53. The insulating layer 55 is made of silica (SiO 2 ) may be contained as a filler.

[0084] The wiring layer 56 is formed on one side of the insulating layer 55. The wiring layer 56 includes via wiring filled in the via hole 55x that penetrates the insulating layer 55 and exposes the upper surface of the wiring layer 54, and a wiring pattern formed on the upper surface of the insulating layer 55. The wiring pattern constituting the wiring layer 56 is electrically connected to the wiring layer 54 through the via wiring. The via hole 55x can be an inverted truncated cone-shaped recess in which the diameter of the opening opened on the solder resist layer 57 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 54. The material of the wiring layer 56 and the thickness of the wiring pattern can be the same as those of the wiring layer 52, for example.

[0085] The solder resist layer 57 is formed on the upper surface of the insulating layer 55 so as to cover the wiring layer 56. The solder resist layer 57 may be formed from, for example, a photosensitive resin such as an epoxy resin or an acrylic resin. The thickness of the solder resist layer 57 may be, for example, about 15 to 35 μm.

[0086] The wiring layer 58 is formed on one side of the solder resist layer 57. The wiring layer 58 includes via wiring filled in a via hole 57x that penetrates the solder resist layer 57 and exposes the upper surface of the wiring layer 56, and a pad formed on the upper surface of the solder resist layer 57. The pad constituting the wiring layer 58 is electrically connected to the wiring layer 56 through the via wiring. The via hole 57x can be an inverted truncated cone-shaped recess in which the diameter of the opening opened on the wiring board 1 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 56. The material of the wiring layer 58 and the thickness of the wiring pattern can be, for example, the same as those of the wiring layer 52. The planar shape of the pad constituting the wiring layer 58 can be, for example, circular. If necessary, the above-mentioned surface treatment layer may be formed on the surface (only the upper surface, or the upper surface and side surface) of the pad constituting the wiring layer 58.

[0087] The insulating layer 63 is formed on the other surface of the core layer 50 so as to cover the wiring layer 62. The material and thickness of the insulating layer 63 may be, for example, the same as those of the insulating layer 53. The insulating layer 63 is made of silica (SiO 2 ) may be contained as a filler.

[0088] The wiring layer 64 is formed on the other side of the insulating layer 63. The wiring layer 64 includes via wiring filled in a via hole 63x that penetrates the insulating layer 63 and exposes the lower surface of the wiring layer 62, and a wiring pattern formed on the lower surface of the insulating layer 63. The wiring pattern constituting the wiring layer 64 is electrically connected to the wiring layer 62 through the via wiring. The via hole 63x can be a truncated cone-shaped recess in which the diameter of the opening opened on the insulating layer 65 side is larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 62. The material and thickness of the wiring layer 64 can be the same as those of the wiring layer 52, for example.

[0089] The insulating layer 65 is formed on the lower surface of the insulating layer 63 so as to cover the wiring layer 64. The material and thickness of the insulating layer 65 may be, for example, similar to those of the insulating layer 53. The insulating layer 65 is made of silica (SiO 2 ) may be contained as a filler.

[0090] The wiring layer 66 is formed on the other side of the insulating layer 65. The wiring layer 66 includes via wiring filled in via holes 65x that penetrate the insulating layer 65 and expose the lower surface of the wiring layer 64, and a wiring pattern formed on the lower surface of the insulating layer 65. The wiring pattern constituting the wiring layer 66 is electrically connected to the wiring layer 64 through the via wiring. The via holes 65x can be truncated cone-shaped recesses whose openings on the solder resist layer 67 side have a diameter larger than the diameter of the bottom of the openings formed by the lower surface of the wiring layer 64. The material and thickness of the wiring layer 66 can be the same as those of the wiring layer 52, for example.

[0091] The solder resist layer 67 is formed on the lower surface of the insulating layer 65 so as to cover the wiring layer 66. The material and thickness of the solder resist layer 67 may be, for example, the same as those of the solder resist layer 57. The solder resist layer 67 has an opening 67x, and a part of the lower surface of the wiring layer 66 is exposed in the opening 67x. The planar shape of the opening 67x may be, for example, a circle. The wiring layer 66 exposed in the opening 67x may be used as a pad for electrically connecting to a mounting board (not shown) such as a motherboard. If necessary, the above-mentioned surface treatment layer may be formed on the lower surface of the wiring layer 66 exposed in the opening 67x.

[0092] Wiring board 1 is mounted on wiring board 2. Specifically, surface treatment layer 110 of wiring board 1 and wiring layer 58, which is an external connection terminal of wiring board 2, are joined by melted and then hardened solder layer 41. Underfill resin 42 is filled between the lower surface of wiring board 1 (the lower surface of insulating layer 12) and the upper surface of wiring board 2 (the upper surface of solder resist layer 57), and covers part of the side surface of wiring board 1, bonding wiring board 1 and wiring board 2 together.

[0093] A stiffener 70 is fixed to the outer periphery of the upper surface of the wiring board 2 (the upper surface of the solder resist layer 57). The stiffener 70 has, for example, a frame-like planar shape, and is provided to reinforce the strength of the entire laminated wiring board 3 and to reduce warping that occurs when the laminated wiring board 3 is mounted on a motherboard or the like. The material of the stiffener 70 may be, for example, SUS304 (stainless steel mainly composed of Cr and Ni: 0.08C-18Cr-8Ni), etc. The material of the stiffener 70 may be a metal plate such as copper or a copper alloy, or a resin plate such as a glass epoxy board. The stiffener 70 may be provided as necessary.

[0094] In this way, by mounting wiring board 1 having a wiring layer with high wiring density on wiring board 2 having a wiring layer with low wiring density, a stacked wiring board 3 on which a semiconductor chip can be mounted can be easily manufactured.

[0095] Furthermore, since wiring board 1 has small warpage, there is little variation in the distance between each wiring layer 11 of wiring board 1 and the opposing wiring layer 58 of wiring board 2. This improves the connection reliability between wiring layer 11 and wiring layer 58 via solder layer 41.

[0096] <Application Example 2 of the First Embodiment> Application Example 2 of the first embodiment shows an example of a semiconductor device in which a semiconductor chip is mounted on the stacked wiring substrate according to Application Example 1 of the first embodiment. Note that in Application Example 2 of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0097] Fig. 9 is a cross-sectional view illustrating a semiconductor device according to Application Example 2 of the first embodiment. Referring to Fig. 9, a semiconductor device 5 has the multilayer wiring substrate 3 shown in Fig. 8, a semiconductor chip 80, bumps 90, and an underfill resin 95. A plurality of semiconductor chips 80 are flip-chip mounted on the multilayer wiring substrate 3.

[0098] The semiconductor chip 80 is, for example, a semiconductor integrated circuit (not shown) and the like formed on a thinned semiconductor substrate 81 made of silicon or the like. Electrode pads 82 electrically connected to the semiconductor integrated circuit (not shown) are formed on the circuit formation surface of the semiconductor substrate 81.

[0099] The electrode pads 82 of the semiconductor chip 80 are electrically connected to the surface treatment layer 310 of the laminated wiring substrate 3 via the bumps 90. An underfill resin 95 is filled between the circuit formation surface of the semiconductor chip 80 and the upper surface of the wiring substrate 1, and covers the side surfaces of the semiconductor chip 80. The bumps 90 are, for example, solder bumps. As a material for the solder bumps, for example, SnBi solder or the like can be used.

[0100] The semiconductor chips 80 may be the same size or different sizes. Furthermore, the semiconductor chips 80 may have the same function or different functions. Examples of the functions of the semiconductor chips 80 include memory (DRAM, etc.) and logic (CPU, etc.). Furthermore, one or two semiconductor chips 80 may be mounted on the stacked wiring substrate 3, or four or more semiconductor chips 80 may be mounted on the stacked wiring substrate 3.

[0101] In this way, by mounting the semiconductor chip 80 on the laminated wiring board 3 according to the application example 1 of the first embodiment, the semiconductor device 5 can be realized. Since the semiconductor chip 80 is mounted on the wiring board 1 having a wiring layer with a high wiring density, it becomes possible to easily connect signals between the semiconductor chips 80 by a wiring pattern with a high wiring density. Furthermore, in the wiring board 1 constituting the semiconductor device 5, the thin film capacitor 20 is disposed directly under the pad 33 close to the semiconductor chip 80, so that the equivalent series inductance of the thin film capacitor 20 can be reduced, and the semiconductor chip 80 can operate at high frequencies.

[0102] First Modification of the First Embodiment The first modification of the first embodiment shows an example in which a thin film capacitor is mounted on the wiring board 2. Note that in the first modification of the first embodiment, the description of the same components as those in the embodiments already described may be omitted.

[0103] FIG. 10 is a cross-sectional view illustrating a wiring board according to Modification 1 of the first embodiment. The wiring board 6 shown in FIG. 10 is obtained by replacing the solder resist layer 57 in the wiring board 2 shown in FIG. 8 with an insulating layer 57A, and providing the thin-film capacitor 20, the wiring layer 31, and the sealing resin layer 34 on the insulating layer 57A instead of the wiring layer 58. The insulating layer 57A is formed of a non-photosensitive thermosetting insulating resin, similar to the insulating layer 53 and the like. The wiring layer 31 is electrically connected to the wiring layer 56 through the via hole 20x and the via wiring 32 in the via hole 57x that communicates with the via hole 20x. When forming the via hole 57x in the insulating layer 57A, for example, a laser processing method can be used.

[0104] In this manner, the thin-film capacitor 20 may be provided on a photosensitive insulating resin as in the wiring board 1, or on a non-photosensitive thermosetting insulating resin as in the wiring board 6. In the wiring board 6, a semiconductor chip can be mounted on the sealing resin layer 34.

[0105] In wiring board 6, similarly to wiring board 1, thin-film capacitor 20 is disposed directly below pad 33. Pad 33 is used as an external connection terminal for electrical connection with a semiconductor chip, so when a semiconductor chip is mounted on wiring board 6, thin-film capacitor 20 is disposed in a position close to the semiconductor chip. This makes it possible to reduce the equivalent series inductance of thin-film capacitor 20, enabling the semiconductor chip to operate at high frequencies.

[0106] Furthermore, in wiring board 6, like wiring board 1, thin-film capacitor 20 is structured to be less susceptible to the effects of thermal stress and pressure generated when mounting a semiconductor chip due to sealing resin layer 34 laminated on thin-film capacitor 20, thereby suppressing damage to the thin-film capacitor. Furthermore, in wiring board 6, like wiring board 1, solder spreads uniformly when mounting a semiconductor chip, improving the mounting reliability of the semiconductor chip.

[0107] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0108] 1. Wiring board 1H 2nd wiring structure 1L 1st wiring structure 11, 13, 14, 16, 18, 31 wiring layer 12, 15, 17, 19 Insulating layer 12a, 34a top surface 12b Bottom side 12x, 15x, 17x, 19x via holes 20 Thin-film capacitors 21 Dielectrics 22 1st electrode 23 2nd electrode 24 Adhesive layer 32 Via wiring 33 Pad 34 Sealing resin layer 41 Solder layer 42 Underfill resin 50 Core layer 50x through holes 51 Through Wiring 52, 54, 56, 58, 62, 64, 66 wiring layer 53, 55, 57A, 63, 65 Insulation layer 53x, 55x, 57x, 63x, 65x via holes 57, 67 Solder resist layer 57y, 67x opening 59 Pad 80 Semiconductor Chips 81 Semiconductor Substrate 82 Electrode Pads 90 Bump 95 Underfill Resin 100 support 101 Core Board 104 Copper foil with carrier 104a thin foil 104b thick foil 110, 310 Surface treatment layer 128 Reinforcement member 131, 311 Seed layer 132, 312 Electrolytic plating layer

Claims

1. An insulating layer; a thin film capacitor laminated on the insulating layer; a wiring layer electrically connected to the thin film capacitor; a sealing resin layer laminated on the thin film capacitor, the thin-film capacitor includes a dielectric provided between the insulating layer and the sealing resin layer, a first electrode provided on one surface of the dielectric, and a second electrode provided on a surface of the dielectric opposite to the one surface; the wiring layer has a first via wiring in contact with the first electrode, a second via wiring in contact with the second electrode, and a plurality of pads protruding from the thin-film capacitor; the first via wiring penetrates the sealing resin layer, the first electrode, and the dielectric, and the second via wiring penetrates the sealing resin layer, the dielectric, and the second electrode; the sealing resin layer is a molding resin containing a non-photosensitive thermosetting resin as a main component, the sealing resin layer exposes an upper surface of the pad and covers the entire side surface of the pad; The pads have a uniform height, and upper surfaces of the pads are flush with an upper surface of the sealing resin layer.

2. a second wiring layer covered with the insulating layer; The wiring board according to claim 1 , wherein the first via wiring and the second via wiring are directly connected to the second wiring layer.

3. 3. The wiring board according to claim 1, wherein a surface treatment layer is formed on upper surfaces of the pads.

4. The wiring board according to claim 1 , wherein the pads have a uniform upper surface area.

5. 5. The wiring board according to claim 1, wherein the pads are external connection terminals for electrically connecting to a semiconductor chip.

6. The wiring board according to claim 1 , wherein the insulating layer is mainly composed of a photosensitive resin.

7. The wiring board according to claim 1 , wherein the sealing resin layer has a thermal expansion coefficient lower than a thermal expansion coefficient of the insulating layer.

8. laminating a thin film capacitor on the insulating layer; forming a wiring layer electrically connected to the thin film capacitor; and laminating an encapsulating resin layer on the thin film capacitor. the thin-film capacitor includes a dielectric provided between the insulating layer and the sealing resin layer, a first electrode provided on one surface of the dielectric, and a second electrode provided on a surface of the dielectric opposite to the one surface; the wiring layer has a first via wiring in contact with the first electrode, a second via wiring in contact with the second electrode, and a plurality of pads protruding from the thin-film capacitor; the first via wiring penetrates the sealing resin layer, the first electrode, and the dielectric, and the second via wiring penetrates the sealing resin layer, the dielectric, and the second electrode; the sealing resin layer is a molding resin containing a non-photosensitive thermosetting resin as a main component, A method for manufacturing a wiring board, in which, in the process of stacking the sealing resin layer, the sealing resin layer is formed so as to cover the upper and side surfaces of the pads, and the upper surface side of the sealing resin layer and the upper surface side of the pads are polished by a CMP method to expose the upper surfaces of the pads, thereby making the heights of the multiple pads uniform.

9. The method for manufacturing a wiring board according to claim 8 , wherein the polishing step causes upper surfaces of the pads to be flush with an upper surface of the sealing resin layer.

Images