COMPOSITE BRIDGE DIE-TO-DIE INTERCONNECT FOR INTEGRATED CIRCUIT PACKAGING - Patent application

Abstract

To provide a multi-chip package (MCP) integrated circuit device having a high interconnection density between a plurality of chips without a power transmission problem such as an inductance loop and an impedance peak profile.SOLUTION: An integrated circuit (IC) package 300 comprises a composite bridge die-to-die interconnection 332 which is on a die surface 343 of an IC package substrate 342, and is contacted to a receiving device 312 and a receiving device 368, existed in a first IC die 10, a second IC die 20, and a mold material 320. The mold material 320 is also contacted to the IC die 10 and the IC die 20.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to power delivery to integrated circuit device packages. [Background technology]

[0002] The integration of multiple integrated circuit chips within a package, for example a multi-chip package (MCP) integrated circuit device having a high interconnect density between multiple chips, presents power delivery issues such as undesirable inductance loops and impedance peak profiles. [Brief description of the drawings]

[0003] The disclosed embodiments in the several figures of the accompanying drawings are illustrated by way of example and not by way of limitation, and in which like reference numerals may refer to similar elements. [Figure 1A] 1 is a cross-sectional front view 101 during assembly of a composite bridge die-to-die interconnect that becomes part of an integrated circuit package according to some embodiments. [Figure 1B] FIG. 1B is a cross-sectional front view of the assembly shown in FIG. 1A after further assembly according to one embodiment. [Figure 1C] FIG. 1C is a cross-sectional front view of the assembly shown in FIG. 1B after further processing according to one embodiment. [Figure 1D] FIG. 1D is a cross-sectional front view of the assembly shown in FIG. 1C after further processing according to one embodiment. [Figure 1E] FIG. 1E is a cross-sectional front view of the assembly shown in FIG. 1D after further processing according to one embodiment. [Figure 1F] 1D is a cross-sectional front view of a composite bridge die-to-die interconnect in an integrated circuit device after further processing of the structure shown in FIG. 1E, according to one embodiment. [Figure 1G] FIG. 1C is a cross-sectional front view of the composite bridge die-to-die interconnect in the integrated circuit device shown in FIG. 1F after further processing of the structure according to one embodiment. [Figure 1H]FIG. 1C is a cross-sectional front view of a composite bridge die-to-die interconnect 132 as part of the integrated circuit device shown in FIG. 1G after further processing of the structure according to one embodiment. [Figure 1I] FIG. 1C is a cross-sectional front view of an integrated circuit package arrangement, such as an IC package including the composite bridge die-to-die interconnect shown in FIG. 1H, according to some embodiments. [Figure 1J] FIG. 1C is a top view of an integrated circuit package apparatus including the composite bridge die-to-die interconnect shown in FIG. 1I according to some embodiments. [Figure 1K] 1 is a detailed cross-sectional portion of a composite bridge die-to-die interconnect as it interfaces with an integrated circuit package and an integrated circuit die. [Diagram 2] 1 is a cross-sectional front view of an integrated circuit package apparatus with a composite bridge die-to-die interconnect according to one embodiment. [Diagram 3] FIG. 1 is a cross-sectional front view of an integrated circuit package with a composite bridge die-to-die interconnect according to one embodiment. [Figure 3A] FIG. 4 is a top view of an integrated circuit package apparatus including the composite bridge die-to-die interconnect shown in FIG. 3 according to some embodiments. [Figure 3B] FIG. 4 is a top view of an integrated circuit packaging device including a composite bridge die-to-die interconnect, such as the integrated circuit packaging device including the composite bridge die-to-die interconnect shown in FIG. 3, according to some embodiments. [Figure 4] 1 is a cross-sectional front view of an integrated circuit package apparatus with a composite bridge die-to-die interconnect according to one embodiment. [Diagram 5] FIG. 1 illustrates a process flow diagram for assembling a composite bridge die-to-die interconnect in an integrated circuit package device according to some embodiments. [Figure 6] It is included to show an example of an upper device application for the disclosed embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] Disclosed embodiments include a composite bridge die-to-die interconnect assembled to a die side of an integrated circuit (IC) package substrate, with passive devices located in a mold layer between integrated circuit (IC) dies mounted on the die side. Power delivery networks (PDNs) are facilitated and passive devices such as decoupling capacitors are located in a mold layer with the IC die, which is assembled to the composite bridge die-to-die interconnect. Such passive device interconnects facilitate decoupling power delivery problems that are made more difficult by the close location of the passive devices. In one embodiment, the capacitor is a multi-layer ceramic capacitor. In one embodiment, the capacitor is a silicon capacitor.

[0005] Ball grid array density is made easier for input / output (I / O) density changes, where keep-out zone issues are addressed, passive device location is closer to the integrated circuit die, mitigating integrated circuit package substrate real estate issues, and increasing interconnect density.

[0006] Power integrity of electrical performance is achieved through reduced package inductance loops. Decoupling capacitors are directly coupled to the power (Vcc) rails and ground reference voltage (Vss) to provide a low power delivery network impedance (Z PDN ) and jitter works.

[0007] 1A is a cross-sectional front view 101 of a composite bridge die-to-die interconnect during assembly that becomes part of an integrated circuit package according to some embodiments. The vertical direction is reversed compared to further disclosed applications of the composite bridge die-to-die interconnect. (See, e.g., FIG. 1I.)

[0008] A first integrated circuit (IC) die 10 and a subsequent IC die 20 are fixed on a carrier 110 along with passive devices 112 according to one embodiment. The first IC die 10 has an active layer and metallization 9 that includes transistors and other active devices fabricated from semiconductor materials. Similarly, the subsequent IC die 20 has an active layer and metallization 19.

[0009] Figure 1B is a cross-sectional front view 102 of assembly 101 shown in Figure 1A after further assembly according to one embodiment. A mask 114, such as dry film resist (DFR) 114, has been patterned over portions of first IC die 10 and subsequent IC die 20, with the DFR covering larger, package connection bond pads 116 and 116' and leaving composite bridge bond pads 118 and 118', respectively, exposed for further connection to composite bridge die-to-die interconnect 132 (see Figure 1H).

[0010] 1C is a cross-sectional front view 103 of the assembly 102 shown in FIG. 1B after further processing according to one embodiment. Mold layer 120 is filled into the space between the first IC die 10 and the subsequent IC die 20 such that passive device 112 is located within the mold layer between the first IC die 10 and the subsequent IC die 20. Mold layer 120 also covers composite bridge bond pads 118 and 118′ in preparation for cutting contact paths to form interconnect vias. Composite bridge bond pads 118 and 118′ create tighter bump pitch geometry, which is facilitated by the composite bridge die-to-die interconnect embodiment.

[0011] FIG. 1D is a cross-sectional front view 104 of the assembly 103 shown in FIG. 1C after further processing according to one embodiment. Patterning of the mold layer 120 has been achieved to open contact vias 122 to the composite bridge bond pads 118 and 118′. In the case of a capacitor passive device 120, such as a decoupling capacitor 120, patterning of the mold layer 120 has also been achieved to open contact vias 124 to the respective anode and cathode contacts. In one embodiment, laser drilling techniques are performed to open the contact vias 122 and 124. In one embodiment, photolithography techniques, such as etching or patterning through a mask, are performed to open the contact vias 122 and 124. In one embodiment, laser drilling is used as well as photolithography processing.

[0012] Figure 1E is a cross-sectional front view 105 of the assembly 104 shown in Figure 1D after further processing according to one embodiment. Composite bridge contacts 126 and 126' are filled into contact via 122 (see Figure 1D), such as by electroplating techniques, followed by a directional etch to remove material from the top surface of mold layer 120. Similarly, passive device contacts 128 are simultaneously filled into contact via 124 to contact electrodes of passive devices 112.

[0013] In one embodiment, the lateral interconnects 130 and 130' (first lateral interconnect 130 and subsequent lateral interconnects 130') couple the passive device 112 to the composite bridge contacts 126 and 126'. Patterning of the molding layer 120 has been accomplished to open up the contact paths 122 to the composite bridge bond pads 118 and 118'. In the case of the capacitor passive device 112, patterning of the molding layer 120 has also been accomplished to couple the passive device 112 to the composite bridge bond pads 118 and 118'. In one embodiment, the traces 130 and 130' are formed simultaneously with the contacts 126 and 128 by plating the contacts and traces, followed by a masked directional etch on the top surface of the molding material 120, followed by removing the mask to reveal the traces 130 and 130'.

[0014] Figure 1F is a cross-sectional front view of a composite bridge die-to-die interconnect 132 in an integrated circuit device 106 after further processing of the structure shown in Figure 1E, according to one embodiment. Composite bridge die-to-die interconnect 132 has contacts 126 and 126', passive device contacts 128, and lateral interconnects 130 and 130', along with conductive traces 134 (die-to-die traces 134) that bypass passive devices 112. These structures couple passive devices 112 to composite bridge die-to-die interconnect 132, and there are interlayer dielectrics 136 and 138 that support, for example, conductive traces 134, as a non-limiting example.

[0015] FIG. 1G is a cross-sectional front view of the composite bridge die-to-die interconnect 132 in the integrated circuit device 106 shown in FIG. 1F after further processing of the structure according to one embodiment. The IC device 107 has further structures assembled to the composite bridge die-to-die interconnect 132. These include interlevel dielectric layers (ILDs), such as a first ILD 136 and a subsequent ILD 138. The further structures have a conductive shield 140 that may be secured onto the die side of an integrated circuit package substrate. As shown, the conductive shield 140 protrudes over the composite bridge bond pads 118 and 118′ and over the passive device 112. The conductive shield 140 provides protection from electromagnetic coupling between some of the conductive traces, such as 130, 130′, and 134, and any conductive traces and vias in close proximity to the integrated circuit package substrate (see, for example, IC package substrate 142 in FIG. 1H).

[0016] FIG. 1H is a cross-sectional front view of composite bridge die-to-die interconnect 132 as part of integrated circuit device 107 shown in FIG. 1G after further processing of the structure according to one embodiment.

[0017] Integrated circuit package 108 comprises IC dies 10 and 20, a composite bridge die-to-die interconnect 132 joining IC dies 10 and 20, and the assembly inverted and secured onto die side 143 of an IC package substrate 142 according to one embodiment. Composite bridge die-to-die interconnect 132 exposes package connection bond pads 116 and 116' on each side of first IC die 10 and subsequent IC die 20, and composite bridge die-to-die interconnect 132 contacts composite bridge bond pads 118 and 118'.

[0018] Larger bond pads 116 and 116′ are reliable connected to die-side electrical bumps 117 and 117′, respectively, which may either originate on IC package die face 143 or be pre-attached to individual larger bond pads 116 and 116′ after removal of carrier 110 (see FIG. 1G ) and inversion of IC dies 10 and 20 and composite bridge die-to-die interconnect 132. In any event, the standoffs created by die-side electrical bumps 117 and 117′ will receive the standoffs of composite bridge die-to-die interconnect 132 after reflow onto die face 143.

[0019] In one embodiment, the IC package substrate 142 includes a core layer 144 for rigidity. Above and below the core layer 144, the build-up layer 146 has organic layers that receive interconnects such as package vias 148 and traces 150 to facilitate interconnecting the integrated circuit (IC) dies 10 and 20 with the composite bridge die-to-die interconnect 132 to an electrical bump array 152 as well as pin-out connections on the land side 141 of the IC package substrate 142. In one embodiment, the organic layers 146 are fabricated from a composite of epoxy polymer resin and silica particulate material. In one embodiment, the width of the traces 150 ranges from 5 μm to 40 μm. In one embodiment, the IC package substrate 142 may omit the core layer 144 to reduce the z-direction height (or thickness) of the package. In any event, the composite bridge die-to-die interconnect 132 eliminates the need for a silicon bridge interposer that would require additional z-direction height. Furthermore, composite bridge die-to-die interconnect 132 also eliminates the need for a silicon bridge, such as an embedded multi-die interconnect bridge (EMIB), under IC dies 10 and 20 that would take up useful under-die real estate.

[0020] Figure 1I is a cross-sectional front view of an integrated circuit package apparatus 100, such as an IC package including a composite bridge die-to-die interconnect 132 shown in Figure 1H, according to some embodiments. The apparatus 100, including a first IC die 10 and a subsequent IC die 20, the composite bridge die-to-die interconnect 132, and the passive device 112, is secured onto a die side 143 of an IC package substrate 142. An underfill mass 154 is poured onto the die side 143 beneath the IC dies 10 and 20 and in contact with the composite bridge die-to-die interconnect 132.

[0021] In the case where the passive device 112 is a decoupling capacitor 112, improved power integrity is made possible by the shortened loop inductance between the capacitor 112 and the IC die it serves, thereby facilitating uninterrupted current flow that is beneficial to direct current (DC) load line performance and, ultimately, to the computing performance of the IC die and any computing system of which the IC die is a part.

[0022] In the case where passive device 112 is a decoupling capacitor 112, passive device 112 is coupled to ground (Vss) and power (Vcc) portions of some of the conductive traces in composite bridge die-to-die interconnect 132. Other conductive traces and vias in composite bridge die-to-die interconnect 132 are used as signal connections, such as data transmission connections.

[0023] As shown in one embodiment, IC package substrate 142 carrying IC dies 10 and 20 and composite bridge die-to-die interconnect 132 is brought to a substrate 156, such as a motherboard 156 or printed wiring board 156. Electrical contact is made by an electrical bump array, one bump of which is shown by reference numeral 152. In one embodiment, substrate 156 has an exterior shell 157 that provides at least one of physical and electrical isolation protection to components on substrate 156. For example, exterior shell 157 is an integral part of substrate 156 that is part of a handheld computing system, such as a communications device. In one embodiment, exterior shell 157 is an integral part of substrate 156 that is part of the exterior of a mobile computing platform, such as a drone.

[0024] Figure 1J is a top view 109 of an integrated circuit package apparatus 100 including the composite bridge die-to-die interconnect shown in Figure 1I, according to some embodiments. The cross-sectional front view shown in Figure 1I may be taken from section line AA' in Figure 1J. Substrate 156 is not shown. Die face 143 supports first IC die 10 and subsequent IC die 20, and composite bridge die-to-die interconnect 132 with some passive devices in the molding material between IC dies 10 and 20.

[0025] In one embodiment, passive device 112 is a first capacitor 112 and subsequent passive device 158 is a subsequent capacitor 158 that couples to composite bridge die-to-die interconnect 132, where passive device 112 is a first passive device in molding material 120, and additional passive devices include subsequent passive device 158, third passive device 160, fourth passive device 162, and fifth passive device 164 according to some embodiments. Some passive devices are in molding material 120 and are an integral part of composite bridge die-to-die interconnect 132, such that some passive devices support IC dies 10 and 20 without needing to be embedded in IC package substrate 142.

[0026] In one embodiment, the passive devices are decoupling capacitors 112, 158, 160, 162, and 164. In one embodiment, a subset of the capacitors are separately coupled to power rails at different potentials, such as a 1.0 volt power rail for the first capacitors 112 and 158 and a 1.5 V power rail for the capacitors 160, 162, and 164. In one embodiment, the capacitors have a thickness in the range of 20 μm to 500 μm. In one embodiment, at least one passive device shown is a resistor. In one embodiment, at least one passive device shown is an inductor.

[0027] In one embodiment, the first integrated circuit die 10 is a central processing unit, such as a processor formed by Intel Corporation of Santa Clara, Calif. In one embodiment, the subsequent IC die 20 is a graphics processor 20. In one embodiment, the first IC die 10 is pressed onto die face 143 with bump arrays 117 and 117′ (see FIG. 1I) with a bump pitch geometry in the range of 70 micrometers (μm) to 150 μm.

[0028] Figure 1K is a detailed cross-sectional portion of a composite bridge die-to-die interconnect as it interfaces with an integrated circuit package and an integrated circuit die. The detailed portion may be taken, for example, from the integrated circuit package arrangement 100 shown in Figure 1I. Active devices and metallization 9 and 19 are further shown, along with separate active devices 8 and 18 on separate IC dies 10 and 20.

[0029] 2 is a cross-sectional front view of an integrated circuit package apparatus 200 with a composite bridge die-to-die interconnect 232 according to one embodiment. The IC package 200 includes a first IC die 10 and a subsequent IC die 20, respectively, a composite bridge die-to-die interconnect 232, and a passive device 212 located within a mold layer 220 between the IC dies 10 and 20, while the IC dies 10 and 20 and the composite bridge die-to-die interconnect 232 are fixed on a die side 243 of an IC package substrate 242. An underfill mass 254 is poured onto the die side 243 beneath the IC dies 10 and 20 and in contact with the composite bridge die-to-die interconnect 232.

[0030] In one embodiment, land side passive devices 266 are mounted in an "opossum" style on land side 241 of IC package substrate 242. Land side passive devices 266 are coupled substantially vertically from land side 241 to die side 243 by vertical package interconnects (VPIs) and into composite bridge die-to-die interconnect 232. According to one embodiment, land side capacitors 266 in conjunction with capacitors 212 provide improved power source noise suppression. In one embodiment, passive devices 212 are resistors.

[0031] Electrical bumps 217 and 217′ help bond IC dies 10 and 20 to IC package substrate 242. Electrical bumps 217 and 217′ create standoffs after reflow onto die face 243 to usefully secure composite bridge die-to-die interconnect 232 onto die face 243.

[0032] In one embodiment, IC package substrate 242 includes a core layer 244 for rigidity. Above and below core layer 244, build-up layer 246 includes organic layers that receive interconnects such as package vias 248 and traces 250 to facilitate interconnecting integrated circuit (IC) dies 10 and 20 with composite bridge die-to-die interconnect 232 to electrical bump array 252 as well as pin-out connections on land side 241 of IC package substrate 242. In one embodiment, organic layer 246 is fabricated from a composite of epoxy polymer resin and silica particulate material. In one embodiment, traces 250 have a width in the range of 5 μm to 40 μm. In one embodiment, IC package substrate 242 may omit core layer 244 to reduce the z-direction height (or thickness) of the package.

[0033] As shown in one embodiment, IC package substrate 242 holding IC dies 10 and 20 and composite bridge die-to-die interconnect 232 is carried towards a substrate 256, such as a motherboard 256 or printed wiring board 256, and land side passive devices 266 have a through path from land side 241 towards die side 243 into composite bridge die-to-die interconnect 232.

[0034] In one embodiment, the substrate 256 has an exterior shell 257 that provides at least one of physical and electrical isolating protection for the components on the substrate 256 .

[0035] 3 is a cross-sectional front view of an integrated circuit package 300 with a composite bridge die-to-die interconnect 332 according to one embodiment. The IC package 300 includes a first IC die 10 and a subsequent IC die 20, a composite bridge die-to-die interconnect 332, and an upper passive device 312 located in a mold layer 320 between the IC dies 10 and 20, respectively, while the IC dies 10 and 20 and the composite bridge die-to-die interconnect 332 are fixed on a die side 343 of an IC package substrate 342. An underfill mass 354 is poured onto the die side 343 below the IC dies 10 and 20 and to contact the composite bridge die-to-die interconnect 332.

[0036] In one embodiment, the internal passive device 368 is mounted in a manner such that the first, upper passive device 312 "straddles" the internal passive device 368, while each of the passive devices 312 and 368 contacts the composite bridge die-to-die interconnect 332. In any event, the molding material 320, along with the stacked passive components 312 and 368, are separated from each other.

[0037] In one embodiment, the first IC die 10 has through silicon vias (TSVs) 370 that communicate a first backside die chiplet 11, such as a memory die, to the active layers and metallization 29. Similarly, the first IC die, the subsequent backside die chiplet 12, is also on the first IC die 10 and is coupled through the TSVs. In one embodiment, the subsequent IC die 20 has through silicon vias (TSVs) 372 that communicate a first backside die chiplet 21, such as a memory die, to the active layers and metallization 39. Similarly, the subsequent IC die, the subsequent backside die chiplet 22, is also on the subsequent IC die 20 and is coupled through the TSVs.

[0038] First electrical bumps 317 and subsequent electrical bumps 317′ aid in bonding the individual first IC die 10 and subsequent IC die 20 to IC package substrate 342. Electrical bumps 317 and 317′ create standoffs after reflow onto die face 343 for usefully securing composite bridge die-to-die interconnect 332 onto die face 343.

[0039] In one embodiment, IC package substrate 342 includes a core layer 344 for rigidity. Above and below core layer 344, build-up layer 346 has organic layers that receive interconnects such as package vias 348 and traces 350 to facilitate interconnecting integrated circuit (IC) dies 10 and 20 with composite bridge die-to-die interconnect 332 to electrical bump array 352 as well as pin-out connections on land side 341 of IC package substrate 342. In one embodiment, organic layer 346 is fabricated from a composite of epoxy polymer resin and silica particulate material. In one embodiment, the width of trace 350 ranges from 5 μm to 40 μm. In one embodiment, IC package substrate 342 may omit core layer 344 to reduce the z-direction height (or thickness) of the package.

[0040] As shown in one embodiment, IC package substrate 342 holding IC dies 10 and 20 and composite bridge die-to-die interconnect 332 is brought towards a substrate 356 , such as a motherboard 356 or a printed wiring board 356 .

[0041] In one embodiment, the substrate 356 has an exterior shell 357 that provides at least one of physical and electrical isolating protection for the components on the substrate 356 .

[0042] Figure 3A is a top view 301 of an integrated circuit package apparatus 300 including the composite bridge die-to-die interconnect shown in Figure 3, according to some embodiments. The cross-sectional front view shown in Figure 3 may be taken from section line AA' in Figure 3A. Substrate 356 is not shown. Die face 343 supports first IC die 10 and subsequent IC die 20, and composite bridge die-to-die interconnect 332 with several passive devices in mold layer 320 between IC dies 10 and 20.

[0043] In plan view, a first IC die 10 holds several chiplets 11, 11', 12 and 12', and a subsequent IC die 20 holds several chiplets 21, 21', 22 and 22'.

[0044] In plan view, the internal passive device 368 (see FIG. 3 ) is obscured by the first upper passive device 312. In one embodiment, the passive device 312 is a first capacitor 312 and the subsequent passive device 358 is a subsequent capacitor 358 that couples to the composite bridge die-to-die interconnect 332. In one embodiment, the subsequent internal passive device is located below the subsequent passive device 358, where the passive device 312 is the first passive device in the molding material 320, and further passive devices include the subsequent passive device 358, a third passive device 360, a fourth passive device 362, and a fifth passive device 364 according to some embodiments. In one embodiment, at least two of the multiple upper passive devices straddle one internal passive device, for example, as shown in FIG. 3, first passive device 312 and subsequent passive device 358 each straddle first internal passive device 368. In one embodiment, there are more than two internal passive devices below some of the upper passive devices, as shown. In one embodiment, there are more than three internal passive devices below some of the upper passive devices, as shown. In one embodiment, there are more than four internal passive devices below some of the upper passive devices, as shown.

[0045] Some of the top and internal passive device embodiments are within the molding material 320 and are an integral part of the composite bridge die-to-die interconnect 332, thereby supporting the IC dies 10 and 20 without the need for some of the top and internal passive devices to be embedded in the IC package substrate 342.

[0046] In one embodiment, some of the passive devices are decoupling capacitors 312, 358, 360, 362, and 364, and some of the internal passive device embodiments are also decoupling capacitors. In one embodiment, a subset of the capacitors are separately coupled to power rails at different potentials, such as a 1.0 volt power rail for the first capacitor 312 and the subsequent capacitors 358, and a 1.5 V power rail for the capacitors 360, 362, and 364. In one embodiment, some of the internal passive devices have and use the same power rail connection to the 1.0 V power rail. In one embodiment, some of the internal passive devices have and use the same power rail connection to the 1.0 V power rail, and some of the internal passive devices have power rail connections for either higher than 1.0 V applications or lower than 1.0 V applications. In one embodiment, the capacitors have a thickness in the range of 20 μm to 500 μm, and the internal capacitors have a width or length that is less than the width or length of the capacitors that span the internal capacitors.

[0047] In one embodiment, first integrated circuit die 10 is a central processing unit, such as a processor formed by Intel Corporation of Santa Clara, Calif. In one embodiment, subsequent IC die 20 is a graphics processor 20. In one embodiment, first IC die 10 is a processor die supporting more than one TSV-connected memory die, such as dies 11 and 11'. In one embodiment, subsequent IC die 20 is a graphics processor die supporting more than one TSV-connected memory die, such as dies 21 and 21'.

[0048] In one embodiment, the first IC die 10 is pressed onto the die face 343 with bump arrays 317 and 317' (see FIG. 3) with a bump pitch geometry in the range of 70 micrometers (μm) to 150 μm.

[0049] 3B is a top view 302 of an integrated circuit packaging apparatus including a composite bridge die-to-die interconnect, such as the integrated circuit packaging apparatus 300 including a composite bridge die-to-die interconnect shown in FIG. 3, according to some embodiments. The cross-sectional front view shown in FIG. 3 may be taken from section line BB′ in FIG. 3B. Substrate 356 is not shown. In one embodiment, the first passive device 312 straddles the first internal passive device 368 (see FIG. 3). In one embodiment, the first passive device 312 is fixed above the first lower passive device 476, as shown in FIG. 4.

[0050] Die side 343 supports a first IC die 10 and a subsequent IC die 20, and a composite bridge die-to-die interconnect 332 having several passive devices in mold layer 320 between IC dies 10 and 20. In addition, a third IC die 30 and a fourth IC die 40 are also on die side 343 of IC package substrate 342.

[0051] In plan view, a first IC die 10 holds several chiplets 11 and 12 , and a subsequent IC die 20 holds several chiplets 21 and 22 .

[0052] In a plan view, the first passive device 312, the subsequent passive device 358, and the third passive device 360 ​​are in the molding material 320 and in contact with the composite bridge die-to-die interconnect 332. In one embodiment, the fourth passive device 362 is in the molding material 320 between the first IC die 10 and the fourth IC die 40. In one embodiment, the fifth passive device 364 is in the molding material 320 between the first IC die 10 and the fourth IC die 40 and adjacent to the subsequent passive device 358. In one embodiment, the sixth passive device 368 is in the molding material 320 between the subsequent IC die 20 and the fourth IC die 40 and adjacent to the subsequent passive device 358. In one embodiment, the seventh passive device 374 is in the molding material 320 between the subsequent IC die 20 and the fourth IC die 40 and is adjacent to the sixth passive device 368 .

[0053] Some passive device embodiments are within the molding material 320 and are an integral part of the composite bridge die-to-die interconnect 332, which allows some passive devices to support the IC dies 10, 20, 30 and 40 without requiring them to be embedded in the IC package substrate 342.

[0054] In one embodiment, some of the passive devices are decoupling capacitors 312, 358, 360, 362, 364, 368, and 374. In one embodiment, subsets of the capacitors are separately coupled to power rails of different potentials, such as a 1.0 volt power rail for capacitors 312 and 358, and a 1.5 V power rail for capacitors 360, 362, and 364. In one embodiment, some of the passive devices have and use the same power rail connection to the 1.0 V power rail. In one embodiment, some of the passive devices 368 and 374 have and use the same power rail connection to the 1.0 V power rail, and some of the passive devices 368 and 374 have power rail connections for either higher than 1.0 V applications or lower than 1.0 V applications. In one embodiment, the capacitors have a thickness in the range of 20 μm to 500 μm.

[0055] In one embodiment, the first integrated circuit die 10 is a central processing unit, such as a processor formed by Intel Corporation of Santa Clara, Calif. In one embodiment, the subsequent IC die 20 is a graphics processor 20. In one embodiment, the third IC die 30 is a platform controller hub 30. In one embodiment, the fourth IC die 40 is a baseband processor 40. In one embodiment, some of the dies 10, 20, 30 and 40 have the functionality of a CPU, a GPU, a memory, a field programmable gate array (FPGA), and a baseband processor.

[0056] In one embodiment, the first IC die 10 is a processor die that supports more than one TSV-connected memory die, such as dies 11 and 12. In one embodiment, the subsequent IC die 20 is a graphics processor die that supports more than one TSV-connected memory die, such as dies 21 and 22.

[0057] In one embodiment, the first IC die 10 is pressed onto the die face 343 with bump arrays 317 and 317' (see FIG. 3) with a bump pitch geometry in the range of 70 micrometers (μm) to 150 μm.

[0058] In one embodiment shown, composite bridge die-to-die interconnect 332 is a die-to-die bridge 332 in which an arrangement of several dies are directly connected, similar to die-to-die trace 134 shown in FIG. 1G. For example, composite bridge die-to-die interconnect 332 includes die-to-die traces between any adjacent IC dies, such as, in non-identical embodiments, between IC dies 10 and 20, between IC dies 10 and 30, between IC dies 10 and 40, between IC dies 20 and 40, and between IC dies 20 and 30. Additionally, and similar to die-to-die trace 134 coupling IC dies 10 and 20 in FIG. 1G, die-to-die traces in composite bridge die-to-die interconnect 332 couple third and fourth IC dies 30 and 40.

[0059] 4 is a cross-sectional front view of an integrated circuit package apparatus 400 with a composite bridge die-to-die interconnect 432 according to one embodiment. The IC package 400 includes a first IC die 10 and a subsequent IC die 20, a composite bridge die-to-die interconnect 432, and an upper passive device 412 located in a mold layer 420 between the IC dies 10 and 20, respectively, while the IC dies 10 and 20 and the composite bridge die-to-die interconnect 432 are fixed on a die side 443 of an IC package substrate 442. An underfill mass 454 is poured onto the die side 443 below the IC dies 10 and 20 and to contact the composite bridge die-to-die interconnect 432.

[0060] In one embodiment, the lower passive device 476 is mounted in a manner such that the first upper passive device 412 is above and on the top surface of the lower passive device 476 (e.g., in direct soldered contact), while the lower passive device 476 is in contact with the composite bridge die-to-die interconnect 432.

[0061] In one embodiment, the first IC die 10 has through silicon vias (TSVs) 470 that communicate a first backside die chiplet 11, such as a memory die, to the active layers and metallization 49. Similarly, the first IC die, the subsequent backside die chiplet 12, is also on the first IC die 10 and is coupled through the TSVs. In one embodiment, the subsequent IC die 20 has through silicon vias (TSVs) 472 that communicate a first backside die chiplet 21, such as a memory die, to the active layers and metallization 49. Similarly, the subsequent IC die, the subsequent backside die chiplet 22, is also on the subsequent IC die 20 and is coupled through the TSVs.

[0062] Electrical bumps 417 and 417′ help bond IC dies 10 and 20 to IC package substrate 442. Electrical bumps 417 and 417′ create standoffs after reflow onto die face 443 to usefully secure composite bridge die-to-die interconnect 432 onto die face 443.

[0063] In one embodiment, the IC package substrate 442 includes a core layer 444 for rigidity. Above and below the core layer 444, the build-up layer 446 has organic layers that receive interconnects such as package vias 448 and traces 450 to facilitate interconnecting the integrated circuit (IC) dies 10 and 20 with the composite bridge die-to-die interconnect 432 to an electrical bump array 452, as well as pin-out connections on the land side 441 of the IC package substrate 442. In one embodiment, the organic layer 446 is fabricated from a composite of epoxy polymer resin and silica particulate material. In one embodiment, the width of the traces 450 ranges from 5 μm to 40 μm. In one embodiment, the IC package substrate 442 may omit the core layer 444 to reduce the z-direction height (or thickness) of the package.

[0064] As shown in one embodiment, IC package substrate 442 holding IC dies 10 and 20 and composite bridge die-to-die interconnect 432 is brought towards a substrate 456 , such as a motherboard 456 or a printed wiring board 456 .

[0065] In one embodiment, the substrate 456 has an exterior shell 457 that provides at least one of physical and electrical isolating protection for the components on the substrate 456 .

[0066] It may now be understood that integrated circuit package 400 with composite bridge die-to-die interconnect 432 shown in Figure 4 may also be displayed according to Figure 3A with upper and lower passive devices, e.g., 412 and 476 in Figure 4, replacing first upper passive device 312 and first internal passive device 358 in Figures 3 and 3A, respectively. Thus, several different voltage ratings described for several capacitors in Figures 3 and 3A may be mapped to equivalent capacitors in Figure 4 that are rated in series, with the restriction that capacitors 412 and 476 are in direct contact.

[0067] It may now be understood that integrated circuit package 400 with composite bridge die-to-die interconnect 432 shown in Figure 4 may also be displayed according to Figure 3B with upper and lower passive devices, such as 412 and 476 in Figure 4, replacing some of capacitors 312, 358 and 360 in Figure 3B with stacked upper and lower capacitors. Thus, the different voltage ratings described for some of the capacitors in Figure 3B may be mapped to equivalent capacitors in Figure 4 that are rated in series, with the restriction that capacitors 412 and 476 are in direct contact.

[0068] FIG. 5 is a process flow diagram for assembling a composite bridge die-to-die interconnect in an integrated circuit packaging device according to some embodiments.

[0069] At step 510, the process includes assembling a composite bridge die-to-die interconnect onto the first IC die and onto the subsequent IC die, and to passive devices between the first IC die and the subsequent IC die. In a non-limiting exemplary embodiment, the first IC die 10 and the subsequent IC die 20, and the composite bridge die-to-die interconnect 132 in FIG. 1G are assembled with the passive devices 112 by using a molding layer 120.

[0070] At step 520, the process includes assembling the composite bridge die-to-die interconnect to an integrated circuit package substrate. In a non-limiting exemplary embodiment, an integrated circuit device arrangement including IC dies 10 and 20, composite bridge die-to-die interconnect 132, and passive devices 112 are secured onto bumps 117 and 117′ on die side 143 of IC package substrate 142, as shown in FIG. 1H. It may be understood that any of the IC device packages shown in FIG. 1A, 2, 3, 3A, 3B, and 4 with their respective disclosed arrangements may be assembled to the die side of an IC package substrate.

[0071] At step 530, the process comprises assembling the IC package with the composite bridge die-to-die interconnect into a computing system. In a non-limiting exemplary embodiment, a computing system 600 shown in FIG.

[0072] FIG. 6 is included to illustrate an example of an upper device application for the disclosed embodiments. The composite bridge die-to-die interconnect embodiment may be found in several parts of a computing system. In one embodiment, the composite bridge die-to-die interconnect embodiment may be part of a communication device such as one that is affixed to a cellular communication tower. In one embodiment, the computing system 600 includes, but is not limited to, a desktop computer. In one embodiment, the computing system 600 includes, but is not limited to, a laptop computer. In one embodiment, the computing system 600 includes, but is not limited to, a tablet. In one embodiment, the computing system 600 includes, but is not limited to, a notebook computer. In one embodiment, the computing system 600 includes, but is not limited to, a personal digital assistant (PDA). In one embodiment, the computing system 600 includes, but is not limited to, a server. In one embodiment, the computing system 600 includes, but is not limited to, a workstation. In one embodiment, the computing system 600 includes, but is not limited to, a cellular telephone. In one embodiment, the computing system 600 includes, but is not limited to, a mobile computing device. In one embodiment, computing system 600 includes, but is not limited to, a smart phone. In one embodiment, computing system 600 includes, but is not limited to, an Internet appliance. Other types of computing devices may be configured that include small electronic devices with embodiments of the composite bridge die-to-die interconnect.

[0073] In one embodiment, processor 610 includes one or more processing cores 612 and 612N, where 612N represents the Nth processor core in processor 610, where N is a positive integer. In one embodiment, electronic device system 600 uses a composite bridge die-to-die interconnect embodiment with multiple processors, including 610 and 605, where processor 605 includes logic circuitry similar or identical to that of processor 610. In one embodiment, processing core 612 includes, but is not limited to, prefetch logic circuitry for fetching instructions, decode logic circuitry for decoding instructions, execute logic circuitry for executing instructions, etc. In one embodiment, processor 610 includes a cache memory 616 for caching at least one of a plurality of instructions and data for composite bridge die-to-die interconnect elements on an integrated circuit package substrate in system 600. Cache memory 616 may be organized into a hierarchical structure including one or more levels of cache memory.

[0074] In one embodiment, processor 610 comprises a memory controller 614 operable to perform functions that allow processor 610 to access and communicate with memory 630, including at least one of volatile memory 632 and non-volatile memory 634. In one embodiment, processor 610 is coupled to memory 630 and chipset 620. In one embodiment, chipset 620 is part of a composite bridge die-to-die interconnect embodiment shown, for example, in Figures 1A, 2, 3, 3A, 3B, and 4.

[0075] The processor 610 may also be coupled to a wireless antenna 678 for communicating with any device configured to at least one of transmit and receive wireless signals. In one embodiment, the wireless antenna interface 678 operates according to, but is not limited to, the IEEE 802.11 standard and its related family, HomePlug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMAX, or any form of wireless communication protocol.

[0076] In one embodiment, the volatile memory 632 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Rambus dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 634 includes, but is not limited to, flash memory, phase change memory (PCM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), or any other type of non-volatile memory device.

[0077] Memory 630 stores information and instructions executed by processor 610. In one embodiment, memory 630 may also store temporary variables or other intermediate information while processor 610 is executing instructions. In the embodiment shown, chipset 620 connects to processor 610 via point-to-point (PtP or PP) interfaces 617 and 622. Any of these PtP embodiments may be achieved by using composite bridge die-to-die interconnect embodiments described in this disclosure. Chipset 620 allows processor 610 to connect to other elements of composite bridge die-to-die interconnect embodiments in system 600. In one embodiment, interfaces 617 and 622 operate according to a PtP communication protocol, such as Intel® QuickPath Interconnect (QPI). In other embodiments, different interconnects may be used.

[0078] In one embodiment, chipset 620 is operable to communicate with processors 610, 605N, display device 640, and other devices 672, 676, 674, 660, 662, 664, 666, 677, etc. Chipset 620 may also be coupled to a wireless antenna 678 that communicates with any device configured to at least one of transmit and receive wireless signals.

[0079] Chipset 620 connects to a display device 640 via interface 626. Display 640 may be, for example, a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other form of visual display device. In one embodiment, processor 610 and chipset 620 are integrated into a composite bridge die-to-die interconnect embodiment in a system. Chipset 620 further connects to one or more buses 650 and 655 that interconnect various elements 674, 660, 662, 664, and 666. Buses 650 and 655 may be interconnected with each other via at least one bus bridge 672, such as a composite bridge die-to-die interconnect embodiment. In one embodiment, chipset 620 couples to non-volatile memory 660, mass storage device(s) 662, keyboard / mouse 664, network interface 666, smart TV 676, and consumer electronics products 677, etc., via interface 624.

[0080] In one embodiment, mass storage device 662 includes, but is not limited to, a solid state drive, a hard disk drive, a Universal Serial Bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 666 is implemented by any type of well-known network interface standard, including, but not limited to, an Ethernet interface, a Universal Serial Bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface, and / or any other suitable type of interface. In one embodiment, the wireless interface operates according to, but is not limited to, the IEEE 802.11 standard and its related family, HomePlug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMAX, or any form of wireless communication protocol.

[0081] 6 are shown as separate blocks within an embodiment of a composite bridge die-to-die interconnect in computing system 600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit, or may be implemented using two or more separate integrated circuits. For example, while cache memory 616 is shown as a separate block within processor 610, cache memory 616 (or selected aspects of 616) may be incorporated into processor core 612.

[0082] A non-limiting list of examples is provided herein to illustrate the composite bridge die-to-die interconnect IC package embodiments and methods disclosed herein.

[0083] Example 1 is an integrated circuit device comprising: a first integrated circuit (IC) die, a subsequent IC die, a composite bridge die-to-die interconnect in contact with composite bridge bond pads on a top surface of each of the first IC die and the subsequent IC die, a passive device between the first IC die and the subsequent IC die in contact with the composite bridge die-to-die interconnect, and a molding material in contact with the first IC die and the subsequent IC die, the passive device, and the composite bridge die-to-die interconnect, wherein the composite bridge die-to-die interconnect exposes package connection bond pads on a top surface of each of the first IC die and the subsequent IC die.

[0084] In Example 2, the subject matter of Example 1 optionally includes a first lateral interconnect within the composite bridge die-to-die interconnect, the first lateral interconnect coupling to a first IC die and a passive device, and a subsequent lateral interconnect within the composite bridge die-to-die interconnect coupling to a subsequent IC die and a passive device.

[0085] In Example 3, the subject matter of any one or more of Examples 1-2 optionally includes a die-to-die trace within a composite bridge die-to-die interconnect that bypasses passive devices and couples to the first IC die and the subsequent IC die.

[0086] In Example 4, the subject matter of any one or more of Examples 1-3 optionally includes a conductive shield within the composite bridge die-to-die interconnect, the conductive shield having a protruding area over the composite bridge bond pad and over the passive device.

[0087] In Example 5, the subject matter of any one or more of Examples 1-4 optionally includes a first lateral interconnect in the composite bridge die-to-die interconnect, the first lateral interconnect coupling to the first IC die and a passive device, a subsequent lateral interconnect in the composite bridge die-to-die interconnect coupling to the subsequent IC die and a passive device, and a die-to-die trace in the composite bridge die-to-die interconnect bypassing the passive device and coupling to the first IC die and the subsequent IC die.

[0088] In Example 6, the subject matter of any one or more of Examples 1-5 optionally includes a first lateral interconnect in the composite bridge die-to-die interconnect, the first lateral interconnect coupling to a first IC die and a passive device, a subsequent lateral interconnect in the composite bridge die-to-die interconnect coupling to a subsequent IC die and a passive device, and a conductive shield in the composite bridge die-to-die interconnect, the conductive shield protruding a dedicated area onto the composite bridge bond pad and onto the passive device.

[0089] In Example 7, the subject matter of any one or more of Examples 1-6 optionally includes a first lateral interconnect in the composite bridge die-to-die interconnect, the first lateral interconnect coupling to the first IC die and the passive device; a subsequent lateral interconnect in the composite bridge die-to-die interconnect coupling to the subsequent IC die and the passive device; a die-to-die trace in the composite bridge die-to-die interconnect bypassing the passive device and coupling to the first IC die and the subsequent IC die; and a conductive shield in the composite bridge die-to-die interconnect, the conductive shield protruding a dedicated area onto the composite bridge bond pad and onto the passive device.

[0090] In Example 8, the subject matter of any one or more of Examples 1-7 optionally includes an integrated circuit package substrate and package connection electrical bumps in contact with package connection bond pads, the electrical bumps being on a die face side of the integrated circuit package substrate.

[0091] In Example 9, the subject matter of any one or more of Examples 1-8 optionally includes an integrated circuit package substrate and package connection electrical bumps in contact with package connection bond pads, the electrical bumps being on a die side of the integrated circuit package substrate, and a composite bridge die-to-die interconnect also being on the die side.

[0092] In Example 10, the subject matter of any one or more of Examples 1-9 optionally includes the passive device being an embedded passive device, further comprising an integrated circuit package substrate having a die side and a land side, package connection electrical bumps in contact with the package connection bond pads, and a bottom passive device on the land side, the electrical bumps on the die side of the integrated circuit package substrate, and the bottom passive device coupled to at least one of the first IC die and the subsequent IC die.

[0093] Example 11 is an integrated circuit package apparatus comprising: an integrated circuit package substrate having a die side and a land side; a first integrated circuit (IC) die on the die side; a subsequent IC die on the die side; a composite bridge die-to-die interconnect contacting composite bridge bond pads on a top surface of each of the first IC die and the subsequent IC die; package connection bond pads on the die side contacting the first IC die and the subsequent IC die; passive devices between the first IC die and the subsequent IC die and coupled to the composite bridge die-to-die interconnect; and a molding material in contact with the first IC die and the subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect, wherein the composite bridge die-to-die interconnect exposes the package connection bond pads on the top surface of each of the first IC die and the subsequent IC die.

[0094] In Example 12, the subject matter of Example 11 optionally includes the passive device being in contact with a composite bridge die-to-die interconnect.

[0095] In Example 13, the subject matter of any one or more of Examples 11-12 optionally includes at least one chiplet on a first IC die and coupled to the first IC die by a through-silicon via.

[0096] In Example 14, the subject matter of any one or more of Examples 11-13 optionally includes at least one chiplet on a first IC die and coupled to the first IC die by a through-silicon via, and at least one chiplet on a subsequent IC die and coupled to the subsequent IC die by a through-silicon via.

[0097] In Example 15, the subject matter of any one or more of Examples 11-14 optionally includes the passive device being a first passive device, further comprising a subsequent passive device between the first IC die and the subsequent IC die and within the molding material, the subsequent passive device contacting the composite bridge die-to-die interconnect.

[0098] In Example 16, the subject matter of any one or more of Examples 11-15 optionally includes the passive device being a first passive device, further comprising a first internal passive device below the first passive device and within the molding material, the first internal passive device contacting the composite bridge die-to-die interconnect.

[0099] In Example 17, the subject matter of any one or more of Examples 11-16 optionally includes the passive device being a first passive device, and further including a first internal passive device below the first passive device, in the molding material and in contact with the composite bridge die-to-die interconnect, a subsequent passive device between the first IC die and the subsequent IC die, in the molding material and in contact with the composite bridge die-to-die interconnect, and a subsequent internal passive device below the subsequent passive device, in the molding material and in contact with the composite bridge die-to-die interconnect.

[0100] In Example 18, the subject matter of any one or more of Examples 11-17 optionally includes the passive device being a first passive device, and further including a subsequent passive device between the first IC die and the subsequent IC die, in the molding material and in contact with the composite bridge die-to-die interconnect; a third IC die on the die surface and adjacent each of the first IC die and the subsequent IC die; a fourth IC die on the die surface and adjacent each of the first IC die and the subsequent IC die; and a third passive device between the first IC die and the fourth IC die, in the molding material and in contact with the composite bridge die-to-die interconnect.

[0101] In Example 19, the subject matter of any one or more of Examples 11-18 optionally includes the passive device being a first upper passive device, further comprising a first lower passive device below and in contact with the first upper passive device and within the molding material, the first lower passive device in contact with the composite bridge die-to-die interconnect.

[0102] In Example 20, the subject matter of any one or more of Examples 11-19 optionally includes a printed wiring board coupled to the land surface and a chipset coupled to the printed wiring board.

[0103] In Example 21, the subject matter of Example 20 optionally includes the printed wiring board having an exterior shell that is a dielectric material, the exterior shell being at least a portion of an exterior of a device selected from a mobile computing system and a drone.

[0104] Example 22 is a method of assembling an integrated circuit device, comprising assembling a composite bridge die-to-die interconnect on a first integrated circuit die, on a passive device, and on a subsequent integrated circuit die, and contacting a molding material with the composite bridge die-to-die interconnect, the first integrated circuit die, the subsequent integrated circuit die, and the passive device, wherein the passive device is between the first integrated circuit die and the subsequent integrated circuit die.

[0105] In Example 23, the subject matter of Example 22 optionally includes assembling the composite bridge die-to-die interconnect to an integrated circuit package substrate on a die side and underfilling the first integrated circuit die and the subsequent integrated circuit die, wherein electrical bumps on the first integrated circuit die and the subsequent integrated circuit die are in contact with the die side.

[0106] In Example 24, the subject matter of any one or more of Examples 22-23 optionally includes assembling a composite bridge die-to-die interconnect to an integrated circuit package substrate on a die side, underfilling the first integrated circuit die and the subsequent integrated circuit die, and assembling the integrated circuit package substrate on a land side to a printed wiring board, wherein electrical bumps on the first integrated circuit die and the subsequent integrated circuit die are in contact with the die side.

[0107] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, for illustrative purposes, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Furthermore, the inventors also contemplate examples using any combination or permutation of the shown or described elements (or one or more aspects thereof) in conjunction with a particular example (or one or more aspects thereof) shown or described herein or in conjunction with other examples (or one or more aspects thereof).

[0108] In the event of inconsistent usage between this document and any document incorporated by reference, the usage in this document shall control.

[0109] As is common in patent documents, the terms "a" or "an" are used herein to include one or more, independent of any other examples or independent of the use of "at least one" or "one or more." In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive "or," such as "A or B" including "A but not B," "B but not A," and "A and B." In this document, the terms "including" and "in which" are used as the plain English equivalents of the terms "comprising" and "wherein," respectively. Also, in the following claims, the terms "including" and "comprising" are open-ended, i.e., a system, device, article, composition, method, or process that includes other elements in addition to the elements recited after such terms in the claim, is still deemed to be within the scope of the claim. Moreover, in the following claims, the terms "first," "second," "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0110] The method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer readable medium or machine readable media encoded with instructions operable to configure an electrical device to perform the method described in the above examples. Such method implementations may include code, such as microcode, assembly language code, higher level language code, etc. Such code may include computer readable instructions for performing various methods. The code may form part of a computer program product. Further, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer readable media, such as during execution or at other times. Examples of these tangible computer readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), etc.

[0111] The above description is intended to be illustrative, not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art upon reviewing the above description. The Abstract is provided to comply with 37 CFR 1.72(b) to allow the reader to quickly ascertain the nature of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be construed as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as an example or embodiment, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the disclosed embodiments should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0112] [Other possible items] [Item 1] 1. An integrated circuit device, comprising: a first integrated circuit (IC) die; The subsequent IC die, a composite bridge die-to-die interconnect contacting the composite bridge bond pads on the top surface of each of the first IC die and the subsequent IC die and exposing package connection bond pads on the top surface of each of the first IC die and the subsequent IC die; a passive device between the first IC die and the subsequent IC die and in contact with the composite bridge die-to-die interconnect; a molding material in contact with the first and subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; Equipped with. [Item 2] The integrated circuit device according to item 1, further comprising: a first lateral interconnect in the composite bridge die-to-die interconnect, the first lateral interconnect coupling to the first IC die and the passive device; Subsequent lateral interconnects within the composite bridge die-to-die interconnect, which couple to subsequent IC die and passive devices Equipped with. [Item 3] Item 1, the integrated circuit device further comprising a die-to-die trace within the composite bridge die-to-die interconnect, bypassing the passive devices and coupling the first IC die and the subsequent IC die. [Item 4] The integrated circuit device of item 1, further comprising a conductive shield within the composite bridge die-to-die interconnect, the conductive shield having a protruding exclusive area over the composite bridge bond pad and over the passive device. [Item 5] The integrated circuit device according to item 1, further comprising: a first lateral interconnect in the composite bridge die-to-die interconnect, the first lateral interconnect coupling to the first IC die and the passive device; a subsequent lateral interconnect within the composite bridge die-to-die interconnect, coupling to a subsequent IC die and passive devices; a die-to-die trace in the composite bridge die-to-die interconnect, bypassing the passive devices and coupling the first IC die and the subsequent IC die; Equipped with. [Item 6] The integrated circuit device according to item 1, further comprising: a first lateral interconnect in the composite bridge die-to-die interconnect, the first lateral interconnect coupling to the first IC die and the passive device; a subsequent lateral interconnect within the composite bridge die-to-die interconnect, coupling to a subsequent IC die and passive devices; Conductive shielding within composite bridge die-to-die interconnects and wherein the conductive shield protrudes a dedicated area onto the composite bridge bond pad and onto the passive device. [Item 7] The integrated circuit device according to item 1, further comprising: a first lateral interconnect in the composite bridge die-to-die interconnect, the first lateral interconnect coupling to the first IC die and the passive device; a subsequent lateral interconnect within the composite bridge die-to-die interconnect, coupling to a subsequent IC die and passive devices; a die-to-die trace in the composite bridge die-to-die interconnect, bypassing the passive devices and coupling the first IC die and the subsequent IC die; Conductive shielding within composite bridge die-to-die interconnects and wherein the conductive shield protrudes a dedicated area onto the composite bridge bond pad and onto the passive device. [Item 8] The integrated circuit device according to item 1, further comprising: an integrated circuit package substrate; a package interconnect electrical bump contacting a package interconnect bond pad; Equipped with The electrical bumps are on the die side of the integrated circuit package substrate. [Item 9] The integrated circuit device according to item 1, further comprising: an integrated circuit package substrate; a package interconnect electrical bump contacting a package interconnect bond pad; Equipped with The electrical bumps are on a die side of the integrated circuit package substrate; A composite bridge die-to-die interconnect is also on the die surface. [Item 10] Item 1, the integrated circuit device according to the present invention, wherein the passive device is an embedded passive device, an integrated circuit package substrate having a die side and a land side; a package connect electrical bump on the die side of the integrated circuit package substrate in contact with the package connect bond pad; a bottom passive device on the land side and coupled to at least one of the first IC die and the subsequent IC die; Equipped with. [Item 11] 1. An integrated circuit package apparatus comprising: an integrated circuit package substrate having a die side and a land side; a first integrated circuit (IC) die on a die surface; a subsequent IC die on the die surface; a composite bridge die-to-die interconnect contacting the composite bridge bond pads on the top surface of each of the first IC die and the subsequent IC die and exposing package connection bond pads on the top surface of each of the first IC die and the subsequent IC die; package connection bond pads contacting the first and subsequent IC die on the die surface; a passive device between the first IC die and the subsequent IC die and coupled to the composite bridge die-to-die interconnect; a molding material in contact with the first and subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; Equipped with. [Item 12] Item 12. The integrated circuit package apparatus of item 11, wherein the passive device is in contact with the composite bridge die-to-die interconnect. [Item 13] Item 12. The integrated circuit package apparatus of item 11, further comprising at least one chiplet on the first IC die and coupled to the first IC die by a through silicon via. [Item 14] Item 12. The integrated circuit package device according to item 11, further comprising: at least one chiplet on a first IC die and coupled to the first IC die by a through silicon via; at least one chiplet on a subsequent IC die and coupled to the subsequent IC die by a through silicon via; Equipped with. [Item 15] Item 12. The integrated circuit package apparatus of item 11, wherein the passive device is a first passive device, and further comprising a subsequent passive device between the first IC die and the subsequent IC die, within the molding material, and in contact with the composite bridge die-to-die interconnect. [Item 16] Item 12. The integrated circuit package apparatus of item 11, wherein the passive device is a first passive device and further comprises a first internal passive device below the first passive device, within the molding material, and in contact with the composite bridge die-to-die interconnect. [Item 17] Item 12. The integrated circuit package apparatus according to item 11, wherein the passive device is a first passive device, and further comprising: a first internal passive device below the first passive device, within the molding material, and in contact with the composite bridge die-to-die interconnect; a subsequent passive device between the first IC die and the subsequent IC die, within the molding material, and in contact with the composite bridge die-to-die interconnect; a subsequent internal passive device located below the subsequent passive device, within the molding material, and in contact with the composite bridge die-to-die interconnect; Equipped with. [Item 18] Item 12. The integrated circuit package apparatus according to item 11, wherein the passive device is a first passive device, and further comprising: a subsequent passive device between the first IC die and the subsequent IC die, within the molding material, and in contact with the composite bridge die-to-die interconnect; a third IC die on the die surface and adjacent to each of the first IC die and the subsequent IC die; a fourth IC die on the die surface and adjacent to each of the first IC die and the subsequent IC die; a third passive device between the first IC die and the fourth IC die, within the molding material, and in contact with the composite bridge die-to-die interconnect; and Equipped with. [Item 19] Item 12. The integrated circuit package apparatus of item 11, wherein the passive device is a first upper passive device, and further comprising a first lower passive device below the first upper passive device, in contact with the first upper passive device, within the molding material, and in contact with the composite bridge die-to-die interconnect. [Item 20] Item 12. The integrated circuit package device according to item 11, further comprising: a printed wiring board coupled to the land surface; a chipset coupled to a printed wiring board; Equipped with. [Item 21] 21. The integrated circuit package device of item 20, wherein the printed wiring board has an outer shell that is a dielectric material, and the outer shell is at least a portion of the exterior of a device selected from a mobile computing system and a drone. [Item 22] 1. A method of fabricating an integrated circuit device, comprising the steps of: assembling a composite bridge die-to-die interconnect on a top surface of a first integrated circuit die, a passive device, and a subsequent integrated circuit die, the passive device being between the first integrated circuit die and the subsequent integrated circuit die; contacting a molding material to the composite bridge die-to-die interconnect, the first integrated circuit die and the subsequent integrated circuit die, and the passive devices; Equipped with. [Item 23] 23. The method of claim 22, further comprising assembling a composite bridge die-to-die interconnect on a die side of the integrated circuit package substrate, wherein electrical bumps on a top surface of the first integrated circuit die and the subsequent integrated circuit die are in contact with the die side; underfilling the first integrated circuit die and the subsequent integrated circuit die; Equipped with. [Item 24] 23. The method of claim 22, further comprising assembling the composite bridge die-to-die interconnect on a die side of the integrated circuit package substrate, wherein the electrical bumps on the top surfaces of the first integrated circuit die and the subsequent integrated circuit die are in contact with the die side; underfilling the first integrated circuit die and the subsequent integrated circuit die; assembling the integrated circuit package substrate on the land side of the printed wiring board; Equipped with.

Claims

1. 1. An integrated circuit device, comprising: a first integrated circuit (IC) die; a subsequent IC die; a package connection bond pad on a top surface of each of the first IC die and the subsequent IC die; a composite bridge die-to-die interconnect means contacting composite bridge bond pads on the top surfaces of the first IC die and the subsequent IC die; a passive device between the first IC die and the subsequent IC die and in contact with the composite bridge die-to-die interconnect; a molding material in contact with the first and subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; Equipped with The molding material covers the composite bridge bond pads but does not cover the package connection bond pads.

2. An integrated circuit device, comprising: a first integrated circuit (IC) die; a subsequent IC die; a package connection bond pad on a top surface of each of the first IC die and the subsequent IC die; a composite bridge die-to-die interconnect means contacting composite bridge bond pads on the top surfaces of the first IC die and the subsequent IC die; a passive device between the first IC die and the subsequent IC die and in contact with the composite bridge die-to-die interconnect; a molding material in contact with the first and subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; a conductive shield within the composite bridge die-to-die interconnect means and projecting a dedicated area onto the composite bridge bond pads and onto the passive devices; An integrated circuit device comprising:

3. a first lateral interconnect in the composite bridge die-to-die interconnect means and coupled to the first IC die and the passive device; a subsequent lateral interconnect within the composite bridge die-to-die interconnect means and coupled to the subsequent IC die and the passive device; The integrated circuit device of claim 1 , further comprising:

4. a die-to-die trace in the composite bridge die-to-die interconnect means, bypassing the passive devices and coupling to the first IC die and the subsequent IC die; 4. The integrated circuit device of claim 1 , further comprising:

5. an integrated circuit package substrate; a package connection electrical bump on a die side of the integrated circuit package substrate, the package connection electrical bump contacting the package connection bond pad; 5. The integrated circuit device of claim 1 , further comprising:

6. an integrated circuit package substrate; a package connection electrical bump on a die side of the integrated circuit package substrate, the package connection electrical bump contacting the package connection bond pad; Further comprising: the composite bridge die-to-die interconnect means is also on the die surface; 6. An integrated circuit device according to any one of claims 1 to 5.

7. the passive device is an embedded passive device; an integrated circuit package substrate having a die side and a land side; a package connect electrical bump on a die side of the integrated circuit package substrate in contact with the package connect bond pad; a bottom passive device on the land side and coupled to at least one of the first IC die and the subsequent IC die; 7. The integrated circuit device of claim 1 further comprising:

8. 1. An integrated circuit package apparatus comprising: an integrated circuit package substrate having a die side and a land side; a first integrated circuit (IC) die on the die surface; a subsequent IC die on said die surface; package connection bond pads on the die surface contacting the first IC die and the subsequent IC die; a composite bridge die-to-die interconnect contacting composite bridge bond pads on the top surfaces of the first IC die and the subsequent IC die; a passive device between the first IC die and the subsequent IC die and coupled to the composite bridge die-to-die interconnect; a molding material in contact with the first IC die and the subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; Equipped with The molding material covers the composite bridge bond pads but does not cover the package connection bond pads.

9. An integrated circuit packaging apparatus comprising: an integrated circuit package substrate having a die side and a land side; a first integrated circuit (IC) die on the die surface; a subsequent IC die on said die surface; package connection bond pads on the die surface contacting the first IC die and the subsequent IC die; a composite bridge die-to-die interconnect contacting composite bridge bond pads on the top surfaces of the first IC die and the subsequent IC die; a passive device between the first IC die and the subsequent IC die and coupled to the composite bridge die-to-die interconnect; a molding material in contact with the first and subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; at least one chiplet on the first IC die and coupled to the first IC die by a through silicon via; 1. An integrated circuit packaging apparatus comprising:

10. The integrated circuit package apparatus of claim 9, further comprising at least one chiplet on the subsequent IC die and coupled to the subsequent IC die by a through-silicon via.

11. An integrated circuit packaging apparatus comprising: an integrated circuit package substrate having a die side and a land side; a first integrated circuit (IC) die on the die surface; a subsequent IC die on said die surface; package connection bond pads on the die surface contacting the first IC die and the subsequent IC die; a composite bridge die-to-die interconnect contacting composite bridge bond pads on the top surfaces of the first IC die and the subsequent IC die; a passive device between the first IC die and the subsequent IC die and coupled to the composite bridge die-to-die interconnect; a molding material in contact with the first IC die and the subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; Equipped with the passive device is a first passive device, a first internal passive device being below the first passive device, within the molding material, and in contact with the composite bridge die-to-die interconnect; The integrated circuit packaging apparatus further comprises:

12. An integrated circuit packaging apparatus comprising: an integrated circuit package substrate having a die side and a land side; a first integrated circuit (IC) die on the die surface; a subsequent IC die on said die surface; package connection bond pads on the die surface contacting the first IC die and the subsequent IC die; a composite bridge die-to-die interconnect contacting composite bridge bond pads on the top surfaces of the first IC die and the subsequent IC die; a passive device between the first IC die and the subsequent IC die and coupled to the composite bridge die-to-die interconnect; a molding material in contact with the first IC die and the subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; Equipped with the passive device is a first passive device; a first internal passive device below the first passive device, within the molding material, and in contact with the composite bridge die-to-die interconnect; a subsequent passive device between the first IC die and the subsequent IC die, within the molding material, and in contact with the composite bridge die-to-die interconnect; a subsequent internal passive device below the subsequent passive device, within the molding material, and in contact with the composite bridge die-to-die interconnect; The integrated circuit packaging apparatus further comprises:

13. An integrated circuit packaging apparatus comprising: an integrated circuit package substrate having a die side and a land side; a first integrated circuit (IC) die on the die surface; a subsequent IC die on said die surface; package connection bond pads on the die surface contacting the first IC die and the subsequent IC die; a composite bridge die-to-die interconnect contacting composite bridge bond pads on the top surfaces of the first IC die and the subsequent IC die; a passive device between the first IC die and the subsequent IC die and coupled to the composite bridge die-to-die interconnect; a molding material in contact with the first IC die and the subsequent IC die, the passive devices, and the composite bridge die-to-die interconnect; Equipped with the passive device is a first upper passive device, and further a first lower passive device below and in contact with the first upper passive device, within the molding material, and in contact with the composite bridge die-to-die interconnect.

1. An integrated circuit packaging apparatus comprising:

14. the passive device is in contact with the composite bridge die-to-die interconnect; 14. An integrated circuit package arrangement as claimed in any one of claims 8 to 13.

15. the passive device is a first passive device, and further a subsequent passive device is between the first IC die and the subsequent IC die, within the molding material, and in contact with the composite bridge die-to-die interconnect.

15. The integrated circuit package apparatus of claim 8, further comprising:

16. the passive device is a first passive device; a subsequent passive device between the first IC die and the subsequent IC die, within the molding material, and in contact with the composite bridge die-to-die interconnect; a third IC die on the die face and adjacent each of the first IC die and the subsequent IC die; a fourth IC die on the die face and adjacent each of the first IC die and the subsequent IC die; a third passive device between the first IC die and the fourth IC die, within the molding material, and in contact with the composite bridge die-to-die interconnect; and 16. The integrated circuit package apparatus of claim 8, further comprising:

17. a printed wiring board coupled to the land surface; a chipset coupled to the printed wiring board; 17. The integrated circuit package apparatus of claim 8, further comprising:

18. the printed wiring board has an exterior shell that is a dielectric material, the exterior shell being at least a portion of an exterior of a device selected from a mobile computing system and a drone; 20. The integrated circuit package apparatus of claim 17.

19. 1. A method of fabricating an integrated circuit device, comprising the steps of: assembling a composite bridge die-to-die interconnect on a top surface of a first integrated circuit die, a passive device, and a subsequent integrated circuit die, the passive device being between the first integrated circuit die and the subsequent integrated circuit die; contacting a molding material to the composite bridge die-to-die interconnect, the first integrated circuit die and the subsequent integrated circuit die, and the passive devices; Equipped with the molding material covers composite bridge bond pads on the top surfaces of the first integrated circuit die and the subsequent integrated circuit die, but does not cover package connection bond pads on the top surfaces of each of the first integrated circuit die and the subsequent integrated circuit die.

20. A method of fabricating an integrated circuit device, comprising the steps of: assembling a composite bridge die-to-die interconnect on a top surface of a first integrated circuit die, a passive device, and a subsequent integrated circuit die, the passive device being between the first integrated circuit die and the subsequent integrated circuit die; contacting a molding material to the composite bridge die-to-die interconnect, the first integrated circuit die and the subsequent integrated circuit die, and the passive devices; Equipped with the integrated circuit device includes a conductive shield within the connection means of the composite bridge die-to-die interconnect and projecting a dedicated area onto composite bridge bond pads on the top surfaces of the first integrated circuit die and the subsequent integrated circuit die and onto the passive device; method.

21. assembling the composite bridge die-to-die interconnect onto a die side of an integrated circuit package substrate, wherein electrical bumps on a top surface of the first integrated circuit die and the subsequent integrated circuit die are in contact with the die side; underfilling the first integrated circuit die and the subsequent integrated circuit die; 21. The method of claim 19 or 20, further comprising:

22. assembling the composite bridge die-to-die interconnect onto a die side of an integrated circuit package substrate, wherein electrical bumps on a top surface of the first integrated circuit die and the subsequent integrated circuit die are in contact with the die side; underfilling the first integrated circuit die and the subsequent integrated circuit die; assembling the integrated circuit package substrate on a land side of a printed wiring board; 21. The method of claim 19 or 20, further comprising:

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