Apparatus and method for performing stable, low-latency reordering operations - Patents.com

Abstract

To provide an apparatus for stable short delay sorting operation, and to provide a method therefor.SOLUTION: A method includes: receiving a set of N input values that are rearranged in a sorted order; comparing each input value in parallel with all other input values in order to generate N*(N - 1) / 2 comparison result values; generating a result matrix having a row associated with each input value, where the plurality of bits of each row includes a comparison result value indicating a result of comparison with other input values, and a region of a result matrix stores a bit set containing N*(N- 1) / 2 comparison result values, and a region of the result matrix on an opposite side of the region stores the bit set including an inverse of the N*(N- 1) / 2 comparison result values. In addition, the method includes: performing a parallel addition of bits of each row in order to generate N unique result values: and indexing the N unique result values in order to return the sorted order.SELECTED DRAWING: Figure 56

Description

[Technical field]

[0001] The present invention relates generally to the field of graphics processors, and more particularly to an apparatus and method for performing stable, low latency reordering operations. [Background technology]

[0002] Ray tracing is a technique that simulates the transport of light through physically based rendering. It is widely used in cinematic rendering and was considered too resource intensive for real-time performance until just a few years ago. One of the key operations of ray tracing is processing visibility queries for ray scene intersections, known as "ray traversal", which calculates the ray scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH). [Brief description of the drawings]

[0003] A better understanding of the present invention can be obtained from the following detailed description taken in conjunction with the following drawings.

[0004] [Figure 1] FIG. 1 is a block diagram of an embodiment of a computer system including a processor having one or more processor cores and a graphics processor.

[0005] [Figure 2A] FIG. 1 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. [Figure 2B] FIG. 1 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. [Figure 2C]FIG. 1 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. [Figure 2D] FIG. 1 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0006] [Figure 3A] FIG. 1 is a block diagram of one embodiment of a graphics processor, which may be a separate graphics processing unit or may be a graphics processor integrated with multiple processing cores. [Figure 3B] FIG. 1 is a block diagram of one embodiment of a graphics processor, which may be a separate graphics processing unit or may be a graphics processor integrated with multiple processing cores. [Figure 3C] FIG. 1 is a block diagram of one embodiment of a graphics processor, which may be a separate graphics processing unit or may be a graphics processor integrated with multiple processing cores.

[0007] [Figure 4] FIG. 1 is a block diagram of an embodiment of a graphics processing engine for a graphics processor.

[0008] [Figure 5A] FIG. 2 is a block diagram of another embodiment of a graphics processor. [Figure 5B] FIG. 2 is a block diagram of another embodiment of a graphics processor.

[0009] [Figure 6] 1 shows an example of implementation circuitry and logic.

[0010] [Figure 7] 1 illustrates a graphics processor execution unit instruction format according to one embodiment.

[0011] [Figure 8] FIG. 2 is a block diagram of another embodiment of a graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a rendering output pipeline.

[0012] [Figure 9A] FIG. 2 is a block diagram illustrating a graphics processor command format according to one embodiment.

[0013] [Figure 9B] FIG. 2 is a block diagram illustrating a graphics processor command sequence according to one embodiment.

[0014] [Figure 10] 1 illustrates an exemplary graphics software architecture for a data processing system according to one embodiment.

[0015] [Figure 11A] 1 illustrates an exemplary IP core development system that may be used to manufacture an integrated circuit and an exemplary package assembly. [Figure 11B] 1 illustrates an exemplary IP core development system that may be used to manufacture an integrated circuit and an exemplary package assembly. [Figure 11C] 1 illustrates an exemplary IP core development system that may be used to manufacture an integrated circuit and an exemplary package assembly. [Figure 11D] 1 illustrates an exemplary IP core development system that may be used to manufacture an integrated circuit and an exemplary package assembly.

[0016] [Figure 12] 1 illustrates an exemplary system-on-chip integrated circuit that can be manufactured using one or more IP cores, according to one embodiment.

[0017] [Figure 13] 1 illustrates an exemplary graphics processor of a system-on-chip integrated circuit that may be manufactured using one or more IP cores.

[0018] [Figure 14] 1 illustrates an exemplary graphics processor architecture.

[0019] [Figure 15] 1 illustrates an architecture for performing initial training of a machine learning architecture.

[0020] [Figure 16] Show how a machine learning engine is continuously trained and updated at runtime.

[0021] [Figure 17] Show how a machine learning engine is continuously trained and updated at runtime.

[0022] [Figure 18A] Shows how machine learning data is shared across networks. [Figure 18B] Shows how machine learning data is shared across networks.

[0023] [Figure 19] A method for training a machine learning engine is presented.

[0024] [Figure 20] 1 illustrates how nodes exchange ghost region data to perform distributed denoising operations.

[0025] [Figure 21] 1 illustrates an architecture in which image rendering and denoising operations are distributed across multiple nodes.

[0026] [Figure 22]Further details of the architecture for distributed rendering and denoising are presented.

[0027] [Diagram 23] A method for performing distributed rendering and denoising is presented.

[0028] [Figure 24] Demonstrate machine learning methods.

[0029] [Diagram 25] 1 shows multiple interconnected general-purpose graphics processors.

[0030] [Figure 26] A set of convolutional and fully connected layers for machine learning implementation is shown.

[0031] [Figure 27] Here is an example of a convolutional layer.

[0032] [Figure 28] 1 shows an example of a set of interconnected nodes in a machine learning implementation.

[0033] [Figure 29] We present a training framework in which a neural network learns using a training dataset.

[0034] [Figure 30A] Illustrates model parallelism and data parallelism.

[0035] [Figure 30B] Indicates a system on chip (SoC).

[0036] [Diagram 31] 1 illustrates a processing architecture including ray tracing cores and tensor cores.

[0037] [Diagram 32] 1 shows an example of a beam.

[0038] [Diagram 33] 1 shows an apparatus for performing beam tracing.

[0039] [Diagram 34] 1 shows an example of a beam hierarchy.

[0040] [Diagram 35] 1 illustrates a method for performing beam tracing.

[0041] [Diagram 36] 1 shows an example of a distributed ray tracing engine.

[0042] [Figure 37] Illustrates the compression performed by the ray tracing system. [Figure 38] Illustrates the compression performed by the ray tracing system.

[0043] [Figure 39] We present our method implemented in a ray tracing architecture.

[0044] [Diagram 40] 1 illustrates an exemplary hybrid ray tracing apparatus.

[0045] [Diagram 41] Indicates the stack used for ray tracing operations.

[0046] [Diagram 42] 2 shows further details of a hybrid ray tracing apparatus.

[0047] [Diagram 43] 2 shows the bounding volume hierarchy.

[0048] [Diagram 44] FIG. 2 illustrates the call stack and storage of traversal state.

[0049] [Diagram 45] Shows methods of traversal and intersection.

[0050] [Figure 46A] Shows how multiple dispatch cycles may be required to execute a particular shader. [Figure 46B] Shows how multiple dispatch cycles may be required to execute a particular shader.

[0051] [Figure 47] Shows how a single dispatch cycle can execute multiple shaders.

[0052] [Figure 48] Shows how a single dispatch cycle can execute multiple shaders.

[0053] [Figure 49] 1 illustrates an architecture for executing ray tracing instructions.

[0054] [Figure 50] A method for executing ray tracing instructions within a thread is presented.

[0055] [Figure 51] 1 illustrates one embodiment of an architecture for asynchronous ray tracing.

[0056] [Figure 52A] 1 illustrates an embodiment of a ray traversal circuit.

[0057] [Figure 52B] 4 illustrates a process performed in one embodiment to manage ray storage banks.

[0058] [Figure 53] 1 illustrates one embodiment of a priority selection circuit / logic.

[0059] [Figure 54] 4 illustrates a reordering circuit and / or logic according to one embodiment of the present invention.

[0060] [Figure 55] 1 illustrates an exemplary results matrix according to one embodiment of the present invention.

[0061] [Figure 56] 1 illustrates a method according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0062] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to one skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the principles underlying embodiments of the invention. Exemplary Graphics Processor Architecture and Data Types System Overview

[0063] 1 is a block diagram of a processing system 100, according to one embodiment. System 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform embedded in a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices, such as in Internet of Things (IoT) devices having wired or wireless connections to local or wide area networks.

[0064] In an embodiment, the system 100 may include, be coupled to, or be integrated within a server-based gaming platform, a gaming console, including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, the system 100 is part of a mobile Internet-connected device, such as a mobile phone, a smart phone, a tablet computing device, or a laptop with low internal storage capacity. The processing system 100 may also include, be coupled to, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear or smart clothing enhanced with augmented reality (AR) or virtual reality (VR) capabilities to provide visual, audio, or haptic output to complement a real-world visual, audio, or haptic experience, or otherwise provide text, audio, graphics, video, holographic images or videos, or haptic feedback, other augmented reality (AR) devices, or other virtual reality (VR) devices. In some embodiments, the processing system 100 includes or is part of a television or set-top box device. In one embodiment, system 100 may include, be coupled to, or be integrated within an autonomous vehicle, such as a bus, a trailer truck, an automobile, a motorcycle or electric bike, an airplane or glider (or any combination thereof), etc. The autonomous vehicle may use system 100 to process the sensed environment around the vehicle.

[0065] In some embodiments, the one or more processors 102 each include one or more processor cores 107 for processing instructions that, when executed, perform operations of the system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via Very Long Instruction Words (VLIW). The one or more processor cores 107 may process different instruction sets 109, which may include instructions to facilitate emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as digital signal processors (DSPs).

[0066] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherency techniques. A register file 106 may further be included in the processor 102 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0067] In some embodiments, one or more processor(s) 102 are coupled to one or more interface bus(es) 110 for transmitting communication signals, such as address, data, or control signals, between the processor 102 and other components in the system 100. In one embodiment, the interface bus 110 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (PCI, PCI Express, etc.), memory buses, or other types of interface buses. In one embodiment, the processor(s) 102 include an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, and the platform controller hub (PCH) 130 provides connectivity to I / O devices via a local I / O bus.

[0068] The memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance to function as a process memory. In one embodiment, the memory device 120 may operate as a system memory of the system 100 to store data 122 and instructions 121 for use by the one or more processors 102 when executing applications or processes. The memory controller 116 may also optionally couple to an external graphics processor 118, which may communicate with one or more graphics processors 108 in the processor 102 to perform graphics and media operations. In some embodiments, the graphics, media, and / or computation operations may be assisted by an accelerator 112, which is a co-processor that may be configured to perform a specialized set of graphics, media, or computation operations. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or computation operations. In one embodiment, accelerator 112 is a ray tracing accelerator that can be used to perform ray tracing operations in cooperation with graphics processor 108. In one embodiment, external accelerator 119 can be used instead of or in cooperation with accelerator 112.

[0069] In some embodiments, a display device 111 can be connected to the processor(s) 102. The display device 111 can be one or more internal display devices, such as a mobile electronic device or laptop device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display device 111 can be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0070] In some embodiments, the platform controller hub 130 allows peripherals to connect to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long Term Evolution (LTE) transceiver. Firmware interface 128 allows communication with system firmware and can be, for example, a unified extensible firmware interface (UEFI). Network controller 134 allows network connectivity to a wired network. In some embodiments, a high performance network controller (not shown) couples to interface bus 110. In one embodiment, audio controller 146 is a multi-channel high definition audio controller. In one embodiment, system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. Platform controller hub 130 can also connect to one or more universal serial bus (USB) controllers 142 for connecting input devices such as a keyboard and mouse combination 143, a camera 144, or other USB input devices.

[0071] It will be understood that the illustrated system 100 is exemplary and not limiting as other types of data processing systems with different configurations may also be used. For example, instances of memory controller 116 and platform controller hub 130 may be integrated into a separate external graphics processor, such as external graphics processor 118. In one embodiment, platform controller hub 130 and / or memory controller 116 may be external to one or more processor(s) 102. For example, system 100 may include external memory controller 116 and platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset in communication with processor(s) 102.

[0072] For example, the circuit board ("sled") on which the CPU, memory, and other components are located may be designed to improve thermal performance. In some examples, the processing components, such as the processor, are located on the top side of the sled, while the memory, such as DIMMs, are located on the bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than typical systems, thereby improving performance. Additionally, the sleds are configured to conditionally mate with the power and data communication cables in the rack, thereby allowing for rapid removal, upgrade, reinstallation, and / or replacement. Similarly, the individual components located on the sled, such as the processor, accelerators, memory, and data storage drives, are configured to be easily upgraded, since they are spaced apart from one another. In an exemplary embodiment, the components further include hardware authentication features to attest to their authenticity.

[0073] Data centers can utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and Omnipath. The threads can be coupled to switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Cat 5, Cat 5e, Cat 6, etc.). The high bandwidth, low latency interconnect and network architecture allows data centers to pool resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.), and data storage drives that are physically distributed during use, and provide them with computational resources (e.g., processors) as needed, allowing the computational resources to access the pooled resources as if they were local.

[0074] The power source can provide voltage and / or current to system 100 or any component or system described herein. In one example, the power source includes an AC-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar power) source. In one example, the power source includes a DC power source, such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware for charging in proximity to a charging field. In one example, the power source can include an internal battery, an AC power source, a motion-based power source, a solar power source, or a fuel cell power source.

[0075] 2A-2D illustrate a computing system and a graphics processor provided by embodiments described herein. Elements of FIG. 2A-2D having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to, but not limited to, that described elsewhere herein.

[0076] FIG. 2A is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. The processor 200 may include additional cores up to additional core 202N, represented by a dashed box. Each of the processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core may also have access to one or more shared cache units 206. The internal cache units 204A-204N and the shared cache unit 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level cache, where the highest level of cache before external memory is classified as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.

[0077] In some embodiments, processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. System agent core 210 provides management functions for various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 for managing access to various external memory devices (not shown).

[0078] In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A-202N during multithreaded processing. The system agent core 210 may further include a power control unit (PCU) that includes logic and components for coordinating the power state of the processor cores 202A-202N and the graphics processor 208.

[0079] In some embodiments, processor 200 further includes a graphics processor 208 for performing graphics processing operations. In some embodiments, graphics processor 208 couples to a set of system agent cores 210 that include a shared cache unit 206 and one or more integrated memory controllers 214. In some embodiments, system agent core 210 also includes a display controller 211 for driving graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled with the graphics processor via at least one interconnect or may be integrated within graphics processor 208.

[0080] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of processor 200. However, alternative interconnect units, such as a point-to-point interconnect, a switched interconnect, or other technologies, including technologies known in the art, may be used. In some embodiments, graphics processor 208 couples to ring interconnect 212 via I / O link 213.

[0081] The exemplary I / O link 213 represents at least one of several types of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 can use the embedded memory module 218 as a shared last-level cache.

[0082] In some embodiments, the processor cores 202A-202N are homogenous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 202A-202N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or another instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively high power consumption are combined with one or more power cores having a lower power consumption. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of computational power. Additionally, the processor 200 may be implemented on one or more chips or as a SoC integrated circuit having the illustrated components, in addition to other components.

[0083] FIG. 2B is a block diagram of hardware logic of a graphics processor core 219 according to some embodiments described herein. Elements of FIG. 2B having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, including, but not limited to, the graphics processor core 219 may be referred to as a core slice and may be one or more graphics cores in a modular graphics processor. The graphics processor core 219 is an example of one graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 may include a fixed function block 230 coupled with multiple sub-cores 221A-221F, also referred to as sub-slices, that include modular blocks of general purpose logic and fixed function logic.

[0084] In some embodiments, fixed function block 230 includes a geometry / fixed function pipeline 231 that may be shared by all sub-cores within graphics processor core 219, e.g., in lower performance and / or lower power graphics processor implementations. In various embodiments, geometry / fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., 3D pipeline 312, as in FIGS. 3A-3C and 4 described below), a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer (e.g., unified return buffer 418 of FIG. 4 as described below).

[0085] In one embodiment, the fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores in the system-on-chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that is configurable to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and preemption. The media pipeline 234 (e.g., media pipeline 316 of FIGS. 3A-3C and 4) includes logic to facilitate decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. The media pipeline 234 implements media operations via requests to computation or sampling logic in the sub-cores 221-221F.

[0086] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with general-purpose application processor cores (e.g., CPUs) and / or other components in the SoC, including memory hierarchy elements such as shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 232 also enables communication with fixed function devices in the SoC, such as a camera imaging pipeline, and enables the use and / or implementation of global memory atomics that may be shared between the graphics processor core 219 and CPUs in the SoC. The SoC interface 232 can also implement power management control of the graphics processor core 219 and enable an interface between the clock domain of the graphics core 219 and other clock domains in the SoC. In one embodiment, the SoC interface 232 enables the receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. Commands and instructions can be dispatched to the media pipeline 234 if media operations are to be performed, or to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 231, geometry and fixed function pipelines 237) if graphics processing operations are to be performed.

[0087] Graphics microcontroller 233 can be configured to perform various scheduling and management tasks for graphics processor core 219. In one embodiment, graphics microcontroller 233 can execute graphics on various graphics parallel engines in execution unit (EU) arrays 222A-222F, 224A-224F in sub-cores 221A-221F and / or compute workload scheduling. In this scheduling model, host software executing on a CPU core of a SoC including graphics processor core 219 can submit a workload on one of multiple graphics processor doorbells that invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting the workload to a command streamer, preempting existing workloads running on the engines, monitoring the progress of the workload, and notifying host software when the workload is completed. In one embodiment, graphics microcontroller 233 can also facilitate low power or idle states for graphics processor core 219 and can provide graphics processor core 219 with the ability to save and restore registers within graphics processor core 219 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0088] Graphics processor core 219 may have up to N modular sub-cores, more or less than the illustrated sub-cores 221A-221F. For each set of N sub-cores, graphics processor core 219 may also include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipeline 237, and additional fixed function logic 238 for accelerating various graphics and computational processing operations. Shared function logic 235 may include logic units related to shared function logic 420 of FIG. 4 (e.g., sampler, computation, and / or inter-thread communication logic) that may be shared by each of the N sub-cores in graphics processor core 219. Shared and / or cache memory 236 may be a last-level cache for the set of N sub-cores 221A-221F in graphics processor core 219 and may function as a shared memory accessible by multiple sub-cores. Geometry / fixed function pipeline 237 may be included in fixed function block 230 in place of geometry / fixed function pipeline 231 and may include the same or similar logic units.

[0089] In one embodiment, graphics processor core 219 includes additional fixed function logic 238, which may include various fixed function acceleration logic for use by graphics processor core 219. In one embodiment, additional fixed function logic 238 includes an additional geometry pipeline for use with position-only shading. In position-only shading, there are two geometry pipelines, the geometry / fixed function pipeline 238, the full geometry pipeline in 231, and the culling pipeline, which is an additional geometry pipeline that may be included in the additional fixed function logic 238. In one embodiment, the culling pipeline is a reduced functionality version of the full geometry pipeline. The full pipeline and the culling pipeline can run different instances of the same application, with each instance having a separate context. Position-only shading can hide lengthy culling runs of discarded triangles, allowing shading to complete sooner in some instances. For example, in one embodiment, the culling pipeline logic in the additional fixed function logic 238 can execute position shaders in parallel with the main application, and the culling pipeline generally produces significant results faster than the full pipeline because it only fetches and shades position attributes of vertices without rasterizing and rendering pixels to a frame buffer. The culling pipeline can use the significant results produced to calculate visibility information for all triangles, regardless of whether those triangles have been culled or not. The full pipeline (sometimes referred to as a replay pipeline in this example) can use the visibility information to skip culled triangles and shade only visible triangles that are ultimately passed to the rasterization phase.

[0090] In one embodiment, the additional fixed function logic 238 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations that include optimizations for machine learning training or inference.

[0091] Included within each graphics sub-core 221A-221F is a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. The graphics sub-cores 221A-221F include a number of EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD / IC) logic 223A-223F, 3D (e.g., texture) samplers 225A-225F, media samplers 206A-206F, shader processors 227A-227F, and shared local memories (SLMs) 228A-228F. Each of the EU arrays 222A-222F, 224A-224F includes multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations in service of graphics, media, or compute operations, including graphics, media, or compute shader programs. The TD / IC logic 223A-223F performs local thread dispatch and thread control operations for the execution units in the sub-cores and facilitates communication between threads running on the execution units of the sub-cores. The 3D samplers 225A-225F can read textures or other 3D graphics related data into memory. The 3D samplers can read texture data differently based on the configured sample state and the texture format associated with a given texture. The media samplers 206A-206F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each of the graphics sub-cores 221A-221F can alternatively include an integrated 3D and media sampler. Threads executing in execution units within each sub-core 221A-221F can use the shared local memory 228A-228F within each sub-core, allowing threads executing within a thread group to execute using a common pool of on-chip memory.

[0092] 2C illustrates a graphics processing unit (GPU) 239 that includes a dedicated set of graphics processing resources arranged into multi-core groups 240A-240N. Although details of only a single multi-core group 240A are provided, it will be understood that the other multi-core groups 240B-240N may include the same or similar sets of graphics processing resources.

[0093] As shown, multicore group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. Scheduler / dispatcher 241 schedules and dispatches graphics threads for execution on the various cores 243, 244, 245. A set of register files 242 store operand values ​​used by cores 243, 244, 245 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

[0094] One or more combined level 1 (L1) cache and shared memory units 247 store graphics data, such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multicore group 240A. One or more texture units 247 may also be used to perform texturing operations, such as texture mapping and sampling. A level 2 (L2) cache 253, shared by all or a subset of the multicore groups 240A-240N, stores graphics data and / or instructions for multiple simultaneous graphics threads. As shown, the L2 cache 253 may be shared across multiple multicore groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to memory 249, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0095] Input / output (I / O) circuitry 250 couples GPU 239 to one or more I / O devices 252, such as a digital signal processor (DSP), a network controller, or a user input device. An on-chip interconnect may be used to couple I / O device 252 to GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of I / O circuitry 250 directly couple I / O device 252 to system memory 249. In one embodiment, IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, I / O device 252, CPU(s) 246, and GPU(s) 239 may share the same virtual address space.

[0096] In one implementation, IOMMU 251 supports virtualization. In this case, it may manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables (e.g., in system memory 249) for mapping guest / graphics physical addresses to system / host physical addresses. The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out upon context switch (e.g., so that a new context is provided access to the associated set of page tables). Although not shown in FIG. 2C, each of cores 243, 244, 245 and / or multicore groups 240A-240N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical, guest physical to host physical, and guest virtual to host physical translations.

[0097] In one embodiment, CPU 246, GPU 239, and I / O devices 252 are integrated onto a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated onto the same chip or may be coupled to memory controller 248 via an off-chip interface. In one implementation, memory 249 comprises GDDR6 memory that shares the same virtual address space as other physical system level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0098] In one embodiment, tensor cores 244 include multiple execution units specifically designed to perform matrix operations, which are fundamental computational operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for training and inference of neural networks. Tensor cores 244 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32-bit), half-precision floating point (e.g., 16-bit), integer word (16-bit), byte (8-bit), and half-byte (4-bit). In one embodiment, the neural network implementation extracts features of each rendered scene and potentially combines details from multiple frames to construct a high-quality final image.

[0099] In a deep learning implementation, parallel matrix multiplication operations may be scheduled to run on tensor cores 244. Specifically, training a neural network requires a significant number of matrix dot product operations. To process the inner product formulation of N×N×N matrix multiplication, tensor cores 244 may include at least N dot product processing elements. Before the matrix multiplication begins, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded each of the N cycles. In each cycle, there are N dot products to be processed.

[0100] Matrix elements may be stored with different precisions depending on the particular implementation, such as 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes are specified for tensor cores 244 so that the most efficient precision is used for different workloads (e.g., inference workloads that can tolerate quantization into bytes and half-bytes).

[0101] In one embodiment, ray tracing core 245 accelerates ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. Specifically, ray tracing core 245 includes ray traversal / intersection circuitry for performing ray traversal using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 245 may also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar arrangement). In one implementation, ray tracing core 245 performs traversal and intersection operations, at least some of which may be executed on tensor core 244, in coordination with the image denoising techniques described herein. For example, in one embodiment, tensor core 244 implements a deep learning neural network to perform denoising of frames generated by ray tracing core 245. However, the CPU(s) 246, graphics core 243, and / or ray tracing core 245 may also implement all or part of the denoising and / or deep learning algorithms.

[0102] Additionally, as discussed above, GPU 239 may employ a distributed approach to denoising in a computing device coupled to other computing devices via a network or high speed interconnect. In this embodiment, the interconnected computing devices share neural network learning / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0103] In one embodiment, the ray tracing core 245 handles all BVH traversal and ray primitive intersections, preventing the graphics core 243 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing ray and triangle intersection tests (e.g., intersection of traversed rays). Thus, in one embodiment, the multi-core group 240A can simply launch ray probes, and the ray tracing cores 245 independently perform ray traversal and intersections and return hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. While the ray tracing core 245 performs traversal and intersection operations, the other cores 243, 244 are freed to perform other graphics or computational work.

[0104] In one embodiment, each ray tracing core 245 includes a traversal unit for performing BVH test operations and an intersection unit for performing ray primitive intersection tests. The intersection unit generates a "hit," "no hit," or "multiple hits" response that it provides to the appropriate thread. During traversal and intersection operations, the execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed to perform other forms of graphics work.

[0105] In one particular embodiment described below, a hybrid rasterization / ray tracing approach is used in which work is distributed between the graphics core 243 and the ray tracing core 245.

[0106] In one embodiment, the ray tracing core 245 (and / or other cores 243, 244) includes hardware support for a ray tracing instruction set, such as Microsoft's DirectX Raytracing (DXR), including the DispatchRays command, as well as ray generation, nearest hit, any hit, and miss shaders that can assign a unique set of shaders and textures per object. Another ray tracing platform that may be supported by the ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, it should be noted that the principles underlying the present invention are not limited to any particular ray tracing ISA.

[0107] In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes instructions / functions for ray generation, nearest hit, arbitrary hit, ray primitive intersection, per-primitive and hierarchical bounding box construction, miss, access, and exception. More specifically, one embodiment includes ray tracing instructions for performing the following functions: Ray generation - Ray generation instructions may execute per pixel, sample, or other user-defined work allocation. Nearest hit - Nearest hit instructions may execute to find the nearest intersection of a ray with a primitive in the scene. Arbitrary hit - Any hit instructions identify multiple intersections between rays and primitives in the scene, and potentially identify a new nearest intersection. Intersection - Intersection instructions perform ray primitive intersection tests and output the results. Per-primitive bounding box construction - This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure). Miss - indicates that the ray missed all geometry in the scene or a specified region of the scene. Visit - indicates the child volumes that the ray traversed. Exceptions - contains exception handlers of various types (e.g. called for various error conditions).

[0108] 2D is a block diagram of a general purpose graphics processing unit (GPGPU) 270 that can be configured as a graphics processor and / or computational accelerator, according to embodiments described herein. GPGPU 270 can be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and / or memory buses. In one embodiment, memory 271 is a system memory that can be shared with one or more CPUs 246, and memory 272 is a device memory dedicated to GPGPU 270. In one embodiment, components within GPGPU 270 and device memory 272 can be mapped to memory addresses accessible to one or more CPUs 246. Access to memories 271 and 272 can be facilitated via memory controller 268. In one embodiment, memory controller 268 can include an internal direct memory access (DMA) controller 269 or can otherwise include logic for performing operations performed by a DMA controller.

[0109] The GPGPU 270 includes multiple cache memories, including an L2 cache 253, an L1 cache 254, an instruction cache 255, and a shared memory 256, at least some of which may also be partitioned as cache memories. The GPGPU 270 also includes multiple computation units 260A-260N. Each computation unit 260A-260N includes a set of vector registers 261, scalar registers 262, a vector logic unit 263, and a scalar logic unit 264. The computation units 260A-260N may also include a local shared memory 265 and a program counter 266. The computation units 260A-260N may be coupled with a constant cache 267, which may be used to store constant data, which is data that does not change during the execution of a kernel or shader program executing on the GPGPU 270. In one embodiment, the constant cache 267 is a scalar data cache, and the cached data may be fetched directly into the scalar registers 262.

[0110] In operation, one or more CPUs 246 can write commands to registers or memory in GPGPU 270 that are mapped into an accessible address space. Command processor 257 can read commands from registers or memory and determine how those commands are to be processed within GPGPU 270. Thread dispatcher 258 can then be used to dispatch threads to computation units 260A-260N to execute those commands. Each computation unit 260A-260N can execute threads independently of the other computation units. Additionally, each computation unit 260A-260N can be independently configured for conditional computation and can conditionally output computation results to memory. Command processor 257 can interrupt one or more CPUs 246 upon completion of a submitted command.

[0111] 3A-3C show block diagrams of additional graphics processor and computation accelerator architectures provided by embodiments described herein. Elements of FIGs. 3A-3C having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to, but not limited to, that described elsewhere herein.

[0112] 3A is a block diagram of a graphics processor 300, which may be a separate graphics processing unit or may be a graphics processor integrated with multiple processing cores, or other semiconductor devices such as, but not limited to, a memory device or a network interface. In some embodiments, the graphics processor communicates with registers on the graphics processor via a memory-mapped I / O interface and with commands placed in the processor memory. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or an interface to system memory.

[0113] In some embodiments, the graphics processor 300 also includes a display controller 302 for driving display output data to a display device 318. The display controller 302 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device 318 can be an internal or external display device. In one embodiment, the display device 318 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9, ​​and SoCiety of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

[0114] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a computation engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0115] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable fixed-function elements that perform various tasks within the elements and / or spawn execution threads in 3D / media subsystem 315. While 3D pipeline 312 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 that is used specifically to perform media operations such as video post-processing and image enhancement.

[0116] In some embodiments, the media pipeline 316 includes fixed function or programmable logic units for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, on behalf of the video codec engine 306. In some embodiments, the media pipeline 316 further includes a thread generation unit for generating threads for execution on the 3D / media subsystem 315. The generated threads perform computations for the media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0117] In some embodiments, the 3D / Media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / Media subsystem 315, which includes thread dispatch logic for arbitrating the various requests and dispatching to available thread execution resources. The execution resources include an array of graphics execution units for processing the 3D and media threads. In some embodiments, the 3D / Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0118] FIG. 3B illustrates a graphics processor 320 having a tile architecture according to an embodiment described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A in the graphics engine tiles 310A-310D. Each graphics engine tile 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D can also be connected to a memory module or memory device 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D can use any graphics memory technology. For example, the memory devices 326A-326D can be graphics double data rate (GDDR) memory. In one embodiment, the memory devices 326A-326D are high bandwidth memory (HBM) modules that can be on-die with the respective graphics engine tiles 310A-310D. In one embodiment, memory devices 326A-326D are memory devices that can be stacked on top of respective graphics engine tiles 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D resides on a separate chiplet that is coupled to a base die or base substrate, as described in further detail in Figures 11B-11D.

[0119] The graphics processing engine cluster 322 may be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 may enable communication between the graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engines 304 may be used to move data between the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 may also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable connection with an external display device 318. The graphics processor may also be configured as a graphics or computation accelerator. In an accelerator configuration, the display controller 302 and the display device 318 may be omitted.

[0120] Graphics processor 320 may connect to a host system via host interface 328. Host interface 328 may enable communication between graphics processor 320, system memory, and / or other system components. Host interface 328 may be, for example, a PCI Express bus or another type of host system interface.

[0121] FIG. 3C illustrates a computation accelerator 330 according to an embodiment described herein. The computation accelerator 330 may include architectural similarities to the graphics processor 320 of FIG. 3B and is optimized for computation acceleration. The computation engine cluster 332 may include a set of computation engine tiles 340A-340D that include execution logic optimized for parallel or vector-based general-purpose computation operations. In some embodiments, the computation engine tiles 340A-340D do not include fixed-function graphics processing logic, but in one embodiment, one or more of the computation engine tiles 340A-340D may include logic for performing media acceleration. The computation engine tiles 340A-340D may be connected to memories 326A-326D via memory interconnects 325A-325D. The memories 326A-326D and memory interconnects 325A-325D may be of similar technology as the graphics processor 320 or may be of different technology. The graphics compute engine tiles 340A-340D may also be interconnected via a set of tile interconnects 323A-323F, which may connect and / or interconnect with the fabric interconnect 324. In one embodiment, the compute accelerator 330 includes a large L3 cache 336, which may be configured as a device-wide cache. The compute accelerator 330 may also be connected to a host processor and memory via a host interface 328, in a manner similar to the graphics processor 320 of FIG. 3B. Graphics Processing Engine

[0122] FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor, according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A and may represent the graphics engine tiles 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, including, but not limited to, 3D pipeline 312 and media pipeline 316 of FIG. 3A are shown. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, in at least one embodiment, a separate media and / or image processor is coupled to the GPE 410.

[0123] In some embodiments, the GPE 410 is coupled to or includes a command streamer 403, which provides a command stream to the 3D pipeline 312 and / or the media pipeline 316. In some embodiments, the command streamer 403 is coupled to a memory, which may be a system memory or one or more internal and shared cache memories. In some embodiments, the command streamer 403 receives commands from the memory and sends the commands to the 3D pipeline 312 and / or the media pipeline 316. The commands are instructions fetched from a ring buffer, which stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may further include a batch command buffer, which stores a batch of multiple commands. The commands for the 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 312 and / or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process commands and data by executing operations through logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, the graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core(s) 415A, graphics core(s) 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources including general-purpose and graphics-specific execution logic for performing graphics and computation operations, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0124] In various embodiments, the 3D pipeline 312 can include fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. The general-purpose execution logic (e.g., execution units) within the graphics core(s) 415A-414B of the graphics core array 414 includes support for a variety of 3D API shader languages ​​and can execute multiple concurrent threads of execution associated with multiple shaders.

[0125] In some embodiments, the graphics core array 414 includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution unit includes general purpose logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic can perform processing operations in parallel or in combination with the general purpose logic within the processor core(s) 107 of FIG. 1 or cores 202A-202N as in FIG. 2A.

[0126] Output data generated by threads executing on the graphics core array 414 can output data to memory in a unified return buffer (URB) 418. The URB 418 can store data for multiple threads. In some embodiments, the URB 418 can be used to transmit data between different threads executing on the graphics core array 414. In some embodiments, the URB 418 can further be used for synchronization between threads on the graphics core array and fixed function logic in the shared function logic 420.

[0127] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of GPE 410. In one embodiment, the execution resources are dynamically scalable such that they can be enabled or disabled as needed.

[0128] The graphics score array 414 couples to shared functionality logic 420 that includes multiple resources shared among the graphics scores in the graphics score array. The shared functionality in the shared functionality logic 420 is a hardware logic unit that provides specialized supplemental functionality to the graphics score array 414. In various embodiments, the shared functionality logic 420 includes, but is not limited to, sampler 421, computation 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 in the shared functionality logic 420.

[0129] Shared functionality is implemented at least when the demand for a given specialized functionality is insufficient for inclusion within the graphics core array 414. Instead, a single instantiation of that specialized functionality is implemented as a standalone entity within the shared functionality logic 420 and shared among the execution resources within the graphics core array 414. The exact set of functionality shared among and included within the graphics core array 414 varies by embodiment. In some embodiments, certain shared functionality within the shared functionality logic 420 that is used extensively by the graphics core array 414 may be included within the shared functionality logic 416 within the graphics core array 414. In various embodiments, the shared functionality logic 416 within the graphics core array 414 may include some or all of the logic within the shared functionality logic 420. In one embodiment, all logic elements within the shared functionality logic 420 may be duplicated within the shared functionality logic 416 of the graphics core array 414. In one embodiment, the shared functionality logic 416 within the graphics core array 414 is selected and the shared functionality logic 420 is excluded. Execution Unit

[0130] 5A-5B illustrate thread execution logic 500 including an array of processing elements for use in a graphics processor core according to embodiments described herein. Elements of FIG. 5A-5B having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, including, but not limited to, FIG. 5A-5B illustrate an overview of thread execution logic 500, which may represent the hardware logic shown in each of sub-cores 221A-221F of FIG. 2B. FIG. 5A illustrates an execution unit in a general-purpose graphics processor, and FIG. 5B illustrates an execution unit that may be used in a computational accelerator.

[0131] As shown in FIG. 5A, in some embodiments, the thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including multiple execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D-508N-1 and 508N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect fabric that links each component. In some embodiments, the thread execution logic 500 includes one or more connections to a memory, such as a system memory or a cache memory, via one or more of the instruction cache 506, the data port 514, the sampler 510, and the execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a stand-alone, programmable, general-purpose computational unit capable of executing multiple simultaneous hardware threads, processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of individual execution units.

[0132] In some embodiments, the execution units 508A-508N are primarily used to execute shader programs. The shader processor 502 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 504. In one embodiment, the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution units within the execution units 508A-508N. For example, the geometry pipeline can dispatch vertex shaders, tessellation shaders, or geometry shaders to thread execution logic for processing. In some embodiments, the thread dispatcher 504 can also handle run-time thread creation requests from running shader programs.

[0133] In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute shaders, media shaders). Each of the execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operation allows for an efficient execution environment despite higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is issued multiple times per clock to a pipeline capable of integer, single precision, double precision floating point operations, SIMD branch functions, logical operations, transcendental operations, and other operations. While waiting for data from either memory or a shared function, dependency logic within the execution units 508A-508N causes the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, the execution unit may execute operations of another type of shader program, including a pixel shader, a fragment shader, or a different vertex shader. Various embodiments may apply to the use of execution through the use of single instruction multithreading (SIMT) as an alternative to or in addition to the use of SIMD. References to SIMD cores or operations may also apply to SIMT or to SIMD in combination with SIMT.

[0134] Each execution unit of execution units 508A-508N operates on an array of data elements. The number of data elements is the "execution size" or number of channels for an instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) of a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating point data types.

[0135] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution unit processes the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 54-bit packed data elements (quadword (QW) sized data elements), eight separate 32-bit packed data elements (doubleword (DW) sized data elements), sixteen separate 16-bit packed data elements (word (W) sized data elements), or 32 separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0136] In one embodiment, one or more execution units may be combined with fused execution units 509A-509N having thread control logic (507A-507N) common to the fused EUs. Multiple EUs may be fused into an EU group. Each EU of the fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group may vary depending on the embodiment. Furthermore, various SIMD widths may be executed per EU, such as SIMD8, SIMD16, SIMD32, etc. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, fused execution unit 509A includes a first EU 508A, a second EU 508B, and thread control logic 507A common to the first EU 508A and the second EU 508B. The thread control logic 507A controls the threads executed in the fused graphics execution unit 509A and enables each EU in the fused execution units 509A-509N to execute using a common instruction pointer register.

[0137] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included to cache thread data during thread execution. Threads executing on the execution logic 500 may also store explicitly managed data in the shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 510 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0138] During execution, the graphics and media pipelines send thread start requests to the thread execution logic 500 via thread generation and dispatch logic. Once a group of geometry objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) in the shader processor 502 is invoked to further compute output information so that the results are written to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic in the shader processor 502 then executes pixel or fragment shader programs provided by an application programming interface (API). To execute the shader programs, the shader processor 502 dispatches threads to the execution units (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses texture sampling logic in the sampler 510 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data either compute pixel color data for each geometry fragment or discard one or more pixels from further processing.

[0139] In some embodiments, the data port 514 provides a memory access mechanism for the thread execution logic 500 to output processed data to memory for further processing in the graphics processor output pipeline. In some embodiments, the data port 514 includes or is coupled to one or more cache memories (e.g., data cache 512) to cache data for memory access via the data port.

[0140] In one embodiment, the execution logic 500 may also include a ray tracer 505 that may provide ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be similar to or different from the ray tracing instruction set supported by the ray tracing core 245 of FIG. 2C.

[0141] 5B illustrates exemplary internal details of execution unit 508, according to an embodiment. GSU 508 may include an instruction fetch unit 537, a general register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD floating point units (FPUs) 534, and, in one embodiment, a set of dedicated integer SIMD ALUs 535. GRF 524 and ARF 526 include a general register file and a set of architectural register files associated with each concurrent hardware thread that may be active in GSU 508. In one embodiment, per-thread architectural state is maintained in ARF 526, and data used during thread execution is stored in GRF 524. Execution state of each thread, including each thread's instruction pointer, may be held in thread-specific registers in ARF 526.

[0142] In one embodiment, the graphics execution unit 508 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). The architecture has a modular configuration that can be tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, and the resources of the execution unit are divided across the logic used to execute multiple simultaneous threads. The number of logical threads that can be executed by the graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0143] In one embodiment, the graphics execution unit 508 can simultaneously issue multiple instructions, each of which can be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch the instruction to either the send unit 530, the branch unit 532, or the SIMD FPU(s) 534 for execution. Each execution thread can access 128 general purpose registers in the GRF 524, each of which can store 32 bytes accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread can access 4K bytes in the GRF 524, although the embodiment is not so limited and more or less register resources can be provided in other embodiments. In one embodiment, the graphics execution unit 508 is divided into seven hardware threads that can independently perform computational operations, although the number of threads per execution unit can also vary according to the embodiment. For example, in one embodiment, a maximum of 16 hardware threads are supported. In an embodiment in which the seven threads can access 4K bytes, the GRF 524 can store a total of 28 kilobytes. With 16 threads each having access to 4K bytes, the GRF524 can store a total of 64K bytes. Flexible addressing modes allow registers to be addressed together, effectively building wide registers or representing strided rectangular block data structures.

[0144] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed by a message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

[0145] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating point units (FPU(s)) 534 for performing floating point operations. In one embodiment, the FPU(s) 534 also support integer calculations. In one embodiment, the FPU(s) 534 can SIMD execute up to M 32-bit floating point (or integer) operations or SIMD execute up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPU(s) provides extended math capabilities to support high throughput transcendental math functions and double precision 54-bit floating point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present and may be specifically optimized to perform operations related to machine learning calculations.

[0146] In one embodiment, an array of multiple instances of the graphics execution unit 508 can be instantiated in a graphics sub-core group (e.g., a sub-slice). For scalability, the product architect can select the exact number of execution units per sub-core group. In one embodiment, the execution unit 508 can execute instructions across multiple execution channels. In a further embodiment, each thread executing on the graphics execution unit 508 executes on a different channel.

[0147] FIG. 6 illustrates an additional execution unit 600, according to one embodiment. The execution unit 600 may be, for example, but not limited to, a compute-optimized execution unit for use in the compute engine tiles 340A-340D, as in FIG. 3C. A variation of the execution unit 600 may also be used in the graphics engine tiles 310A-310D, as in FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604. The execution unit 600 further includes a register file 606 that stores registers that can be allocated to hardware threads within the execution unit. The execution unit 600 further includes a send unit 607 and a branch unit 608. In one embodiment, the send unit 607 and the branch unit 608 may operate similarly to the send unit 530 and the branch unit 532 of the graphics execution unit 508 of FIG. 5B.

[0148] Execution unit 600 also includes a computation unit 610 that includes multiple different types of functional units. In one embodiment, computation unit 610 includes an ALU unit 611 that includes an array of arithmetic logic units. ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. The integer and floating point operations may be performed simultaneously. Computation unit 610 can also include a systolic array 612, and computation unit 613. Systolic array 612 includes a wide W and deep D network of data processing units that can be used to perform vector or other data parallel operations in a systolic manner. In one embodiment, systolic array 612 can be configured to perform matrix operations, such as matrix dot product operations. In one embodiment, systolic array 612 supports 16-bit floating point operations, as well as 8-bit and 4-bit integer operations. In one embodiment, systolic array 612 can be configured to accelerate machine learning operations. In such an embodiment, systolic array 612 may be configured to support the bfloat 16-bit floating point format. In one embodiment, a computation unit 613 may be included to perform a particular subset of computation operations therefrom in a more efficient and lower power manner than ALU unit 611. Computation unit 613 may include a variation of computation logic that may be found in the shared function logic of a graphics processing engine provided by other embodiments (e.g., computation logic 422 of shared function logic 420 of FIG. 4). In one embodiment, computation unit 613 may be configured to perform 32-bit and 64-bit floating point operations.

[0149] The thread control unit 601 includes logic for controlling the execution of threads in the execution units. The thread control unit 601 may include thread arbitration logic for starting, stopping, and pre-empting the execution of threads in the execution units 600. The thread state unit 602 may be used to store thread states for threads assigned to execute on the execution units 600. Storing thread states within the execution units 600 allows for rapid pre-emption of threads when they become blocked or idle. The instruction fetch / pre-fetch unit 603 may fetch instructions from an instruction cache of a higher level of execution logic (e.g., instruction cache 506 as in FIG. 5A). The instruction fetch / pre-fetch unit 603 may also issue pre-fetch requests for instructions to be loaded into the instruction cache based on an analysis of currently executing threads. The instruction decode unit 604 may be used to decode instructions to be executed by the computation units. In one embodiment, the instruction decode unit 604 may be used as a secondary decoder to decode complex instructions into constituent micro-operations.

[0150] The execution unit 600 further includes a register file 606 that may be used by hardware threads executing on the execution unit 600. The registers in the register file 606 may be divided across logic used to execute multiple simultaneous threads within the computational units 610 of the execution unit 600. The number of logical threads that may be executed by the graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads may be assigned to each hardware thread. The size of the register file 606 may vary by embodiment based on the number of hardware threads supported. In one embodiment, register renaming may be used to dynamically assign registers to hardware threads.

[0151] 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. The solid lined boxes indicate components that are typically included in an execution unit instruction, while the dashed lines include components that are optional or included in only a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated is a macro-instruction, in that it is an instruction that is supplied to an execution unit, as opposed to a micro-operation that results from an instruction decode after the instruction has been processed.

[0152] In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format 710. A 64-bit compressed instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 730. The native instructions available in the 64-bit format 730 vary depending on the embodiment. In some embodiments, the instruction is partially compressed using a set of index values ​​in the index field 713. The execution unit hardware looks up a set of compression tables based on the index values ​​and uses the compression table outputs to reconstruct the native instruction in the 128-bit instruction format 710. Instructions of other sizes and formats may be used.

[0153] For each format, the instruction opcode 712 defines the operation that the execution unit performs. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture or image element. By default, the execution unit executes each instruction across all data channels of an operand. In some embodiments, the instruction control field 714 allows control over certain execution options, such as channel selection (e.g., assert) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710, the execution size field 716 limits the number of data channels that are executed in parallel. In some embodiments, the execution size field 716 is not available in the 64-bit compact instruction format 730.

[0154] Some execution unit instructions have up to three operands, including two source operands src0 720, src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions may have a third source operand (e.g., SRC2 724), and the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0155] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether a direct or indirect register addressing mode is used. When using the direct register addressing mode, the register addresses of one or more operands are provided directly by bits of the instruction.

[0156] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment of the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction can use byte-aligned addressing for source and destination operands, and in a second mode, the instruction can use 16-byte aligned addressing for all source and destination operands.

[0157] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. If the direct register addressing mode is used, bits of the instruction directly provide the register address of one or more operands. If the indirect register addressing mode is used, the register address of one or more operands may be calculated based on an address register value and an address immediate field of the instruction.

[0158] In some embodiments, instructions are grouped based on opcode 712 bit fields to simplify opcode decode 740. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode groupings shown are merely examples. In some embodiments, the move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares the five most significant bits (MSBs), with move (mov) instructions being of the form 0000xxxxb and logic instructions being of the form 0001xxxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions of the form 0010xxxxb (e.g., 0x20). The other instruction group 746 includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the format of 0011xxxxb (e.g., 0x30). The parallel computation instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the format of 0100xxxxb (e.g., 0x40). The parallel computation group 748 performs arithmetic operations in parallel across data channels. The vector computation group 750 includes arithmetic instructions (e.g., dp4) in the format of 0101xxxxb (e.g., 0x50). The vector computation group performs arithmetic operations such as dot product calculations of vector operands. In one embodiment, the illustrated opcode decode 740 can be used to determine which portion of the execution unit to use to execute the decoded instruction. For example, some instructions can be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), can be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic. Graphics Pipeline

[0159] Figure 8 is a block diagram of another embodiment of a graphics processor 800. Elements of Figure 8 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to, but not limited to, that described elsewhere herein.

[0160] In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by command streamer 803, which supplies instructions to individual components of geometry pipeline 820 or media pipeline 830.

[0161] In some embodiments, command streamer 803 directs the operation of vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides the vertex data to vertex shader 807, which performs coordinate space transformations and lighting operations for each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

[0162] In some embodiments, the execution units 852A-852B are an array of vector processors with an instruction set for performing graphics and media operations. In some embodiments, the execution units 852A-852B have an associated L1 cache 851 that is local to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

[0163] In some embodiments, the geometry pipeline 820 includes tessellation components for performing hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operations. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellator 813 operates at the direction of the hull shader 811 and includes special purpose logic for generating a set of detailed geometry objects based on a coarse geometry model provided as input to the geometry pipeline 820. In some embodiments, the tessellation components (e.g., the hull shader 811, the tessellator 813, and the domain shader 817) can be bypassed if tessellation is not used.

[0164] In some embodiments, a complete geometry object may be processed by the geometry shader 819 via one or more threads dispatched to execution units 852A-852B, or may proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometry objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. The geometry shader 819 receives input from the vertex shader 807 if tessellation is disabled. In some embodiments, the geometry shader 819 is programmable by the geometry shader program to perform geometry tessellation if the tessellation unit is disabled.

[0165] A clipper 829 processes the vertex data before rasterization. The clipper 829 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 in the rendering output pipeline 870 dispatches pixel shaders to convert geometry objects into per-pixel representations. In some embodiments, pixel shader logic is included in the thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access unrasterized vertex data via the stream-out unit 823.

[0166] The graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the major components of the processor. In some embodiments, the execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via data port 856 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, the sampler 854, caches 851, 858, and the execution units 852A-852B each have a separate memory access path. In one embodiment, the texture cache 858 may also be configured as a sampler cache.

[0167] In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. In some embodiments, an associated rendering cache 878 and depth cache 879 are also available. A pixel manipulation component 877 performs pixel-based operations on the data, although in some instances pixel operations associated with 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 841 or substituted by the display controller 843 using overlay display planes at display time. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing sharing of data without using main system memory.

[0168] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command streamer 803. In some embodiments, the media pipeline 830 includes a separate command streamer. In some embodiments, the video front end 834 processes the media commands before sending the commands to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function that generates threads for dispatching to the thread execution logic 850 via the thread dispatcher 831.

[0169] In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples to the graphics processor via ring interconnect 802 or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 includes special purpose logic that can operate independently of the 3D pipeline. In some embodiments, display controller 843 couples to a display device (not shown), which may be a system integrated display device, such as a laptop computer, or an external display device connected via a display device connector.

[0170] In some embodiments, the geometry pipeline 820 and the media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for all of the Khronos Group's Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulcan Graphics and Computing APIs. In some embodiments, support may also be provided for Microsoft Corporation's Direct3D library. In some embodiments, combinations of these libraries may be supported. Support may also be provided for the open source computer vision library (OpenCV). Future APIs with compatible 3D pipelines are also supported if a mapping can be created from the future API's pipeline to the graphics processor's pipeline. Graphics Pipeline Programming

[0171] Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to one embodiment. The solid lined boxes in Figure 9A indicate components that are typically included in a graphics command, while the dashed lines include components that are optional or included in only a subset of the graphics commands. The example graphics processor command format 900 of Figure 9A includes data fields to identify the client 902, the command operation code (opcode) 904, and the data 906 of the command. Sub-opcodes 905 and command size 908 are also included in some commands.

[0172] In some embodiments, the client 902 specifies a client unit of the graphics device that will process the command data. In some embodiments, the graphics processor command parser inspects the client field of each command to condition further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the command. When a command is received by a client unit, the client unit reads the opcode 904 and, if present, the sub-opcode 905 to determine the operation to perform. The client unit executes the command using the information in the data field 906. For some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands based on the command opcode. In some embodiments, the commands are aligned via multiples of double words. Other command formats may also be used.

[0173] The flow diagram of Figure 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses versions of the command sequence shown to set up, execute, and terminate a series of graphics operations. The sample command sequence is shown and described for illustrative purposes only, as embodiments are not limited to these particular commands or this command sequence. Additionally, commands may be issued as a batch of commands in a command sequence such that the graphics processor processes the sequence of commands at least partially concurrently.

[0174] In some embodiments, the graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipelines to complete any commands currently pending in the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. The pipeline flush is performed to cause the active graphics pipelines to complete any pending commands. In response to the pipeline flush, the graphics processor's command parser pauses command processing until the active drawing engines complete pending operations and the associated read caches are invalidated. Optionally, any data in the rendering cache that is marked as "dirty" may be flushed to memory. In some embodiments, the pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0175] In some embodiments, the pipeline select command 913 is used when a command sequence requests the graphics processor to explicitly switch pipelines. In some embodiments, the pipeline select command 913 is only needed once within an execution context before issuing a pipeline command unless the context issues commands for both pipelines. In some embodiments, a pipeline flush command 912 is needed immediately before a pipeline switch via the pipeline select command 913.

[0176] In some embodiments, pipeline control commands 914 are used to configure the graphics pipeline for operation and to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and to clear data from one or more cache memories in the active pipeline before processing a batch of commands.

[0177] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for a respective pipeline to write data to. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers to which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0178] The remaining commands in the command sequence depend on the active pipeline for the operation. Based on the pipeline decision 920, the command sequence is tailored for the 3D pipeline 922, beginning with a 3D pipeline state 930, or the media pipeline 924, beginning with a media pipeline state 940.

[0179] Commands for configuring the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are configured before 3D primitive commands are processed. The values ​​of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if those elements are not used.

[0180] In some embodiments, 3D primitive 932 commands are used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters passed to the graphics processor via 3D primitive 932 commands are forwarded to a vertex fetch function of the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 932 commands are used to perform vertex operations on the 3D primitives via vertex shaders. To process the vertex shaders, the 3D pipeline 922 dispatches shader execution threads to the graphics processor execution units.

[0181] In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing of the 3D primitives. Once the operations are complete, the resulting geometry objects are rasterized and the pixel engine colors the resulting pixels. Additional commands that control pixel shading and pixel backend operations may also be included in these operations.

[0182] In some embodiments, the graphics processor command sequence 910 follows the path of the media pipeline 924 when performing media operations. In general, the particular use and manner of programming for the media pipeline 924 depends on the media or computational operations being performed. Certain media decode operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline may also be bypassed, and media decoding may be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to rendering graphics primitives.

[0183] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands to configure the media pipeline state 940 is dispatched or placed in a command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 include data to configure the media pipeline elements used to process the media object. This includes data to configure the video decode and video encode logic in the media pipeline, such as the encode or decode format. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0184] In some embodiments, the media object command 942 provides a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains the video data to be processed. In some embodiments, all media pipeline state must be valid before issuing the media object command 942. Once the pipeline state is configured and the media object command 942 is queued, the media pipeline 924 is triggered via an execute command 944 or an equivalent execute event (e.g., a register write). The output from the media pipeline 924 can then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a similar manner to media operations. Graphics Software Architecture

[0185] 10 illustrates an exemplary graphics software architecture for a data processing system 1000 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor core(s) 1034. The graphics application 1010 and the operating system 1020 each execute within the system memory 1050 of the data processing system.

[0186] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be a high-level shader language such as Direct3D High Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 that are defined by vertex data.

[0187] In some embodiments, the operating system 1020 is a Microsoft Windows operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system that uses a variant of the Linux kernel. The operating system 1020 can support a graphics API 1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. If the Direct3D API is used, the operating system 1020 compiles any shader instructions 1012 in HLSL into a low-level shader language using a front-end shader compiler 1024. The compilation can be a just-in-time (JIT) compilation, or the application can perform shader pre-compilation. In some embodiments, the high-level shaders are compiled into low-level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate format, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0188] In some embodiments, the user mode graphics driver 1026 includes a back-end shader compiler 1027 for converting the shader instructions 1012 into a hardware-specific representation. When the OpenGL API is being used, the shader instructions 1012 in the GLSL high-level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 communicates with a kernel mode graphics driver 1029 using operating system kernel mode functions 1028. In some embodiments, the kernel mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions. IP Core Implementation

[0189] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions that represent various logic within a processor. When read by a machine, the instructions may cause the machine to create logic for performing the techniques described herein. Such representations, known as "IP cores," are reusable units of logic for an integrated circuit that may be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be provided to various customers or manufacturing facilities, which load the hardware model into a manufacturing machine that produces the integrated circuit. The integrated circuit may be manufactured such that the circuit performs the operations described in connection with any of the embodiments described herein.

[0190] FIG. 11A is a block diagram illustrating an IP core development system 1100 that may be used to fabricate an integrated circuit for performing operations according to one embodiment. The IP core development system 1100 may be used to generate modular, reusable designs that may be incorporated into a larger design or used to build an entire integrated circuit (e.g., an SoC integrated circuit). The design facility 1130 may generate a software simulation 1110 of the IP core design in a high-level programming language (e.g., C / C). The software simulation 1110 may be used to design, test, and verify the operation of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and / or timing simulation. A register transfer level (RTL) design 1115 may then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the operation of the integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is executed using the modeled digital signals. In addition to the RTL design 1115, lower level designs at the logic or transistor level may also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

[0191] The RTL design 1115 or equivalent may be further synthesized by a design facility into a hardware model 1120, which may be a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the design of the IP core. The IP core design may be stored using a non-volatile memory 1140 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for distribution to a third-party manufacturing facility 1165. Alternatively, the IP core design may be transmitted via a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 1165 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0192] 11B illustrates a cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processors or accelerator devices described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 coupled to a substrate 1180. The logic 1172, 1174 may be at least partially implemented in configurable logic or fixed function logic hardware and may include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic 1172, 1174 may be implemented in a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180 and may include, but is not limited to, interconnects such as bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1170 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 for routing electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0193] In some embodiments, the units of logic 1172, 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a high density interconnect structure that provides paths for electrical signals. The bridge 1182 may include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing features may be formed on the bridge substrate to provide chip-to-chip connections between the logic 1172, 1174.

[0194] Although two units of logic 1172, 1174 and bridge 1182 are shown, the embodiments described herein may include more or fewer logic units on one or more dies. If logic is included in a single die, bridge 1182 may be omitted, and thus one or more dies may be connected by zero or more bridges. Alternatively, multiple dies or units of logic may be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges may be interconnected in other possible configurations, including three-dimensional configurations.

[0195] FIG. 11C illustrates a package assembly 1190 including multiple units of hardware logic chiplets connected to a substrate 1180 (e.g., a base die). The graphics processing units, parallel processors, and / or computational accelerators described herein can be constructed from various silicon chiplets fabricated separately. In this context, a chiplet is an at least partially packaged integrated circuit that includes units of separate logic that can be assembled into a larger package with other chiplets. A set of various chiplets with different IP core logic can be assembled into one device. Furthermore, chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP cores can be fabricated using different process technologies and configured during fabrication, which avoids the complexities of integrating multiple IPs into the same fabrication process, especially in large SoCs with multiple flavors of IP. Enabling the use of multiple process technologies reduces time to market and provides a cost-effective way to create multiple product SKUs. Furthermore, the decomposed IP is suitable to be independently power-gated, allowing components not being used in a given workload to be powered off, reducing overall power consumption.

[0196] The hardware logic chiplets can include special purpose hardware logic chiplets 1172, logic or I / O chiplets 1174, and / or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I / O chiplets 1174 can be at least partially implemented in configurable logic or fixed function logic hardware and can include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplets 1175 can be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0197] Each chiplet may be fabricated as a separate semiconductor die and coupled to the substrate 1180 via interconnect structures 1173. The interconnect structures 1173 may be configured to route electrical signals between the various chiplets and logic in the substrate 1180. The interconnect structures 1173 may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect structures 1173 may be configured to route electrical signals such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic, I / O, and memory chiplets.

[0198] In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1190 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 for routing electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0199] In some embodiments, the logic or I / O chiplets 1174 and the memory chiplets 1175 can be electrically coupled through a bridge 1187 configured to route electrical signals between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 can be a high density interconnect structure that provides a path for the electrical signals. The bridge 1187 can include a bridge substrate constructed from glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide chip-to-chip connections between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 can also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 1187 is an embedded multi-die interconnect bridge (EMIB) in some embodiments. In some embodiments, the bridge 1187 can simply be a direct connection from one chiplet to another.

[0200] Substrate 1180 can include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. Fabric 1185 can be embedded within substrate 1180 to enable communication between various logic chiplets and logic 1191, 1193 within substrate 1180. In one embodiment, I / O 1191, fabric 1185, cache, bridges, and other hardware logic 1193 can be integrated into a base die that is layered on top of substrate 1180.

[0201] In various embodiments, the package assembly 1190 can include a fewer or greater number of components and chiplets interconnected by the fabric 1185 or one or more bridges 1187. The chiplets in the package assembly 1190 can be arranged in a 3D or 2.5D arrangement. In general, the bridge structures 1187 can be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. The fabric 1185 can be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, the cache memory 1192 in the substrate can function as a global cache for the package assembly 1190, as part of a distributed global cache, or as a dedicated cache for the fabric 1185.

[0202] 11D illustrates a package assembly 1194 including a replaceable chiplet 1195, according to one embodiment. The replaceable chiplet 1195 can be assembled into a standardized slot on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to other bridge interconnects described herein, for example, an EMIB. Memory chiplets can also connect to logic or I / O chiplets via a bridge interconnect. I / O and logic chiplets can communicate via an interconnect fabric. Each base chiplet can support one or more slots of a standardized format for either logic, I / O, or memory / cache.

[0203] In one embodiment, the SRAM and power delivery circuitry can be fabricated in one or more of the base chiplets 1196, 1198, which can be fabricated using a different process technology than the replaceable chiplets 1195 stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 can be fabricated using a larger process technology, while the replaceable chiplets can be fabricated using a smaller process technology. One or more of the replaceable chiplets 1195 can be memory (e.g., DRAM) chiplets. Different memory densities for the package assembly 1194 can be selected based on the power and / or performance targets of the product using the package assembly 1194. Additionally, logic chiplets with different numbers of types of functional units when assembled can be selected based on the power and / or performance targets of the product. Additionally, chiplets containing different types of IP logic cores can be inserted into the replaceable chiplet slots, allowing for the design of hybrid processors where IP blocks of different technologies can be mixed and matched. Exemplary System-on-Chip Integrated Circuit

[0204] 12-14 illustrate an exemplary integrated circuit and associated graphics processor that may be manufactured using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0205] 12 is a block diagram illustrating an example system-on-chip integrated circuit 1200 that may be manufactured using one or more IP cores, according to one embodiment. The example integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may further include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller 1236. 2 S / I 2 The integrated circuit may further include peripheral or bus logic including a C controller 1240. Additionally, the integrated circuit may include a display device 1245 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including a flash memory and a flash memory controller. Memory interfacing may be provided via a memory controller 1265 for accessing SDRAM or SRAM memory devices. Some integrated circuits further include an embedded security engine 1270.

[0206] 13-14 are block diagrams illustrating an example graphics processor for use within an SoC according to embodiments described herein. FIG. 13 illustrates an example graphics processor 1310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to one embodiment. FIG. 13 illustrates an additional example graphics processor 1340 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to one embodiment. The graphics processor 1310 of FIG. 13 is an example of a low-power graphics processor core. The graphics processor 1340 of FIG. 13 is an example of a higher performance graphics processor core. Each of the graphics processors 1310, 1340 may be a variation of the graphics processor 1210 of FIG. 12.

[0207] As shown in FIG. 13, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D-1315N-1, and 1315N). The graphics processor 1310 can execute different shader programs through separate logic such that the vertex processor 1305 is optimized to perform operations for a vertex shader program while the one or more fragment processors 1315A-1315N execute fragment (e.g., pixel) shading operations for a fragment shader program or a pixel shader program. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processor(s) 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on a display device. In one embodiment, the fragment processor(s) 1315A-1315N are optimized for executing fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs as provided in the Direct3D API.

[0208] The graphics processor 1310 further includes one or more memory management units (MMUs) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. The one or more MMU(s) 1320A-1320B provide virtual to physical address mapping for the graphics processor 1310, including the vertex processor 1305 and / or fragment processor(s) 1315A-1315N, which may reference vertices or image / texture data stored in memory in addition to vertices or image / texture data stored in the one or more caches 1325A-1325B. In one embodiment, one or more MMU(s) 1320A-1320B may synchronize with other MMUs in the system, including one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 of FIG. 12, such that each processor 1205-1220 can participate in a shared or unified virtual memory system. One or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interface with other IP cores in the SoC via an internal bus of the SoC or via a direct connection, according to an embodiment.

[0209] As shown in Figure 14, the graphics processor 1340 includes one or more MMU(s) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of the graphics processor 1310 of Figure 13. The graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F-1355N-1, and 1355N), which provide a unified shader core architecture in which a single core or type or cores can execute all types of programmable shader code, including shader program code implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary depending on the embodiment and implementation. Additionally, graphics processor 1340 includes an inter-core task manager 1345, which functions as a thread dispatcher that dispatches execution threads to one or more shader cores 1355A-1355N, and a tiling unit 1358 that accelerates tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize internal cache usage.

[0210] Figure 15 shows an implementation of initial training. A machine learning engine 1500 (e.g., a CNN) receives a region of NxN pixels as high sample count image data 1702 with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive ID, and albedo, and generates the final pixel color. Representative training data is generated using one frame's worth of low sample count inputs 1501. The network is trained on these inputs, and the machine learning engine 1500 generates a set of "ideal" weights 1505 that are then used at run time to denoise the low sample count images.

[0211] To improve upon the above techniques, the denoising phase is augmented to generate new training data for every frame or every subset of frames (e.g., every N frames, where N=2, 3, 4, 10, 25, etc.). Specifically, as shown in Figure 16, one or more regions in each frame are selected, referred to herein as "new reference regions" 1602, that are rendered at high sample counts into a separate high sample count buffer 1604. A low sample count buffer 1603 stores the low sample count input frame 1601 (including a region 1604 of low samples that corresponds to the new reference region 1602).

[0212] The location of the new reference region 1602 may be selected randomly, or the location of the new reference region 1602 may be adjusted in a pre-specified manner for each new frame (e.g., confined to a specified region in the center of the frame, with a pre-defined movement of the region between frames, etc.).

[0213] Regardless of how the new reference regions are selected, the new reference regions are used by the machine learning engine 1600 to continually improve and update the trained weights 1605 used for denoising. Specifically, the reference pixel color from each new reference region 1602 and the noisy reference pixel input from the corresponding low sample count region 1607 are rendered. Supplemental training is then performed on the machine learning engine 1600 using the high sample count reference region 1602 and the corresponding low sample count region 1607. In contrast to the initial training, this training is performed continuously for each new reference region 1602 during execution, thereby ensuring that the machine learning engine 1600 is trained accurately. For example, per-pixel data channels (e.g., pixel color, depth, normal, normal deviation, etc.) may be evaluated, and the per-pixel data channels are used by the machine learning engine 1600 to adjust the trained weights 1605. As in the training case (FIG. 15), the machine learning engine 1600 is trained towards a set of ideal weights 1605 to remove noise from low sample count input frames 1601, generating denoised frames 1620. However, the trained weights 1605 are continually updated based on new image characteristics of new types of low sample count input frames 1601.

[0214] The retraining operations performed by the machine learning engine 1600 may run simultaneously in a background process on a graphics processor unit (GPU) or host processor. A rendering loop, which may be implemented as a driver component and / or a GPU hardware component, may continually generate new training data (e.g., in the form of new reference regions 1602) that it places in a queue. A background training process running on the GPU or host processor may continually read new training data from this queue and retrain and update the machine learning engine 1600 with new weights 1605 at appropriate intervals.

[0215] 17 shows an example of such an implementation in which a background training process 1700 is implemented by a host CPU 1710. Specifically, the background training process 1700 uses new reference regions 1602 of high sample counts and corresponding regions 1604 of low samples to continually update the trained weights 1605, thereby updating the machine learning engine 1600.

[0216] As shown in FIG. 18A, in a non-limiting example of a multiplayer online game, different host machines 1820-1822 separately generate reference regions that background training processes 1700A-C send to a server 1800 (e.g., a game server, etc.). The server 1800 then runs training on the machine learning engine 1810 using the new reference regions received from each of the hosts 1821-1822 and updates the weights 1805 as described above. The server 1800 sends these weights 1805 to the host machine 1820, which stores the weights 1605A-C, thereby updating the individual machine learning engines (not shown). Because the server 1800 can be provided with a large number of reference regions in a short period of time, it can efficiently and accurately update the weights for any given application (e.g., an online game) being run by a user.

[0217] As shown in FIG. 18B, different host machines may generate new trained weights (e.g., based on training / reference domains 1602 as described above) and share the new trained weights with a server 1800 (e.g., a game server, etc.), or alternatively, may use a peer-to-peer sharing protocol. A machine learning management component 1810 on the server uses the new weights received from each of the host machines to generate a set of combined weights 1805. The combined weights 1805 may be, for example, an average generated from the new weights, and may be continually updated, as described herein. Once generated, copies of the combined weights 1605A-C may be sent to and stored in each of the host machines 1820-1821, which may then use the combined weights described herein to perform denoising operations.

[0218] The semi-closed loop update mechanism can also be used by hardware manufacturers. For example, the reference network can be included as part of the driver distributed by the hardware manufacturer. As the driver uses the techniques described herein to generate new training data and continually sends these back to the hardware manufacturer, the hardware manufacturer uses this information to continue to improve the machine learning implementation for the next driver update.

[0219] In an exemplary implementation (e.g., batch movie rendering on a render farm), the renderer sends newly generated training regions to a dedicated server or database (within the studio's render farm) that aggregates this data over time from multiple rendering nodes. A separate process on a separate machine continuously improves the studio's dedicated denoising network, and new rendering jobs always use the most recently trained network.

[0220] The machine learning method is illustrated in Figure 19. The method may be implemented in the architectures described herein, but is not limited to any particular system or graphics processing architecture.

[0221] At 1901, as part of an initial training stage, low sample count and high sample count image data are generated for a number of image frames. At 1902, a machine learning denoising engine is trained using the high / low sample count image data. For example, a set of convolutional neural network weights associated with pixel features may be updated following the training. However, any machine learning architecture may be used.

[0222] At run-time, at 1903, image frames with low sample counts are generated along with at least one reference region with high sample counts. At 1904, the reference regions with high sample counts are used by the machine learning engine and / or separate training logic (e.g., background training module 1700) to continually improve the training of the machine learning engine. For example, the reference regions with high sample counts may be used in combination with corresponding portions of the image with low sample counts to continue to teach the machine learning engine 1904 how to most effectively perform denoising. In a CNN implementation, for example, this may include updating weights associated with the CNN.

[0223] The above-mentioned variations may implement a method for configuring a feedback loop to a machine learning engine, an entity for generating training data, a method for feeding back the training data to the training engine, and a method for providing an improved network to a rendering engine. Additionally, while the above-mentioned example performs continuous training using a single reference region, any number of reference regions may be used. Additionally, as previously mentioned, the reference regions may be of different sizes, may be used in different numbers of image frames, and may be placed at different locations within the image frames using different techniques (e.g., random, following a predetermined pattern, etc.).

[0224] Additionally, although a convolutional neural network (CNN) is described as one example of a machine learning engine 1600, the principles underlying the present invention may be implemented using any form of machine learning engine that can continually improve its results using new training data. By way of example and not limitation, other machine learning implementations include group methods of data processing (GMDH), long short-term memory, deep reservoir computing, deep belief networks, tensor deep stacking networks, and deep predictive coding networks, to name a few. For efficient variance noise removal Apparatus and method

[0225] As mentioned above, denoising has become a key feature for real-time ray tracing with smooth and noise-free images. Rendering can occur across a distributed system on multiple devices, but so far all existing denoising frameworks run on a single instance on a single machine. When rendering occurs across multiple devices, the devices may not have access to all the rendered pixels to compute the denoised portions of the image.

[0226] A distributed denoising algorithm is presented that works with both artificial intelligence (AI) and non-AI based denoising techniques. Regions of the image are either already distributed across nodes from a distributed rendering operation, or are split and distributed from a single framebuffer. Ghost regions of neighboring regions needed to compute sufficient denoising are collected from neighboring nodes as needed, and the resulting tiles are composited into the final image. Distributed Processing

[0227] Figure 20 shows multiple nodes 2021-2023 performing rendering. Although only three nodes are shown for simplicity, the principles underlying the invention are not limited to any particular number of nodes. Indeed, a single node may be used to implement a particular embodiment of the invention.

[0228] Each of the nodes 2021-2023 renders a portion of the image, resulting in regions 2011-2013 in this example. Although rectangular regions 2011-2013 are shown in FIG. 20, regions of any shape may be used and any device may process any number of regions. The regions required by a node to perform a sufficiently smooth denoising operation are called ghost regions 2011-2013. In other words, the ghost regions 2001-2003 represent the total data required to perform denoising at a particular level of quality. Reducing the quality level reduces the size of the ghost regions and therefore the amount of data required, while increasing the quality level increases the ghost regions and the corresponding required data.

[0229] If a node, such as node 2021, has a local copy of the portion of ghost region 2001 required to denoise its region 2011 at a particular level of quality, the node obtains the necessary data from one or more "neighboring" nodes, such as node 2022, which owns a portion of ghost region 2001 as shown. Similarly, if node 2022 has a local copy of the portion of ghost region 2002 required to denoise its region 2012 at a particular level of quality, node 2022 obtains the necessary ghost region data 2032 from node 2021. The obtainment may be performed over a bus, an interconnect, a high-speed memory fabric, a network (e.g., fast Ethernet), or it may be an on-chip interconnect in a multi-core chip (e.g., used to render large images with either extreme resolution or time variation) that can distribute rendering work across multiple cores. Each node 2021-2023 may comprise an individual execution unit or a particular set of execution units within a graphics processor.

[0230] The specific amount of data transmitted depends on the denoising technique being used. Additionally, the data from the ghost regions may include any data necessary to improve denoising of the respective regions. For example, the ghost region data may include image color / wavelength, brightness / alpha data, and / or normals. However, the principles underlying the present invention are not limited to any particular set of ghost region data. Further details

[0231] For slow networks or interconnects, compression of this data can be utilized using existing general purpose lossless or lossy compression. Examples include, but are not limited to, zlib, gzip, and LZMA (Lempel-Ziv-Markov chain algorithm). Further content-specific compression can be used by noting that deltas of ray hit information between frames are very sparse, and if a node already has a delta collected from the previous frame, then it only needs to send samples that contribute to that delta. These can be selectively pushed to the node i that collects those samples, or node i can request samples from other nodes. Lossless compression is used for certain types of data and program code, while lossy compression is used for other types of data.

[0232] FIG. 21 shows additional details of the interactions between the nodes 2021-2022. Each node 2021-2022 includes ray tracing rendering circuitry 2081-2082 for rendering the respective image regions 2011-2012 and ghost regions 2001-2002. The denoisers 2100-2111 perform denoising operations on the regions 2011-2012 for which each node 2021-2022 is responsible for rendering and denoising, respectively. For example, the denoisers 2021-2022 may include circuitry, software, or any combination thereof for generating the denoised regions 2121-2122, respectively. As discussed above, when generating the denoised regions, the denoisers 2021-2022 may need to rely on data in ghost regions owned by different nodes (e.g., the denoiser 2100 may need data from the ghost region 2002 owned by the node 2022).

[0233] Thus, the denoisers 2100-2111 may generate denoised regions 2121-2122 using data from the regions 2011-2012 and the ghost regions 2001-2002, at least some of which may be received from another node. The region data managers 2101-2102 may manage data transfers from the ghost regions 2001-2002 as described herein. The compressor / decompressor units 2131-2132 may perform compression and decompression of ghost region data exchanged between the nodes 2021-2022, respectively.

[0234] For example, the region data manager 2101 of node 2021, in response to a request from node 2022, may send data from the ghost region 2001 to a compressor / decompressor 2131, which compresses the data to generate compressed data 2106 that is sent to node 2022, thereby reducing the bandwidth of an interconnect, network, bus, or other data communication link. The compressor / decompressor 2132 of node 2022 then decompresses the compressed data 2106, and the denoiser 2111 uses the decompressed ghost data to generate a denoised region 2012 of higher quality than would be possible with data from region 2012 alone. The region data manager 2102 may store the decompressed data from the ghost region 2001 in a cache, memory, register file, or other storage for use by the denoiser 2111 when generating the denoised region 2122. A similar set of operations may be performed to provide data from the ghost region 2002 to a denoiser 2100 on node 2021, which uses that data in combination with data from region 2011 to generate a higher quality denoised region 2121. Retrieving or Rendering Data

[0235] If connections between devices such as nodes 2021-2022 are slow (i.e., below a threshold latency and / or threshold bandwidth), it may be faster to render the ghost region locally than to request results from other devices. This can be determined at runtime by tracking the network transaction speed and a linear extrapolated rendering time for the ghost region size. If it is faster to render the entire ghost region, multiple devices may end up rendering the same portion of the image. The resolution of the rendered portion of the ghost region may be adjusted based on the variance of the base region and the determined degree of blurring. load balancing

[0236] Static and / or dynamic load balancing schemes may be used to distribute the processing load among the various nodes 2021-2023. In the case of dynamic load balancing, the variance determined by the denoising filter may drive the amount of samples used to render certain regions of the scene, such that low variance and blurry regions of the image require fewer samples, although more time is required for denoising. The particular regions assigned to a particular node may be dynamically adjusted based on data from the previous frame, or may be dynamically communicated across devices at render time, such that all devices have the same amount of work.

[0237] FIG. 22 illustrates how the monitors 2201-2202 running on the respective nodes 2021-2022 collect performance metric data including, but not limited to, the time taken to transmit data over the network interfaces 2211-2212, the time taken to denoise the regions (with and without ghost region data), and the time taken to render each region / ghost region. The monitors 2201-2202 report these performance metrics to the manager or load balancing node 2201, which analyzes the data to identify the current workload of each node 2021-2022 and potentially determine a more efficient mode of processing the various denoising regions 2121-2122. The manager node 2201 then distributes new workloads of new regions to the nodes 2021-2022 according to the detected load. For example, the manager node 2201 may send more work to nodes that are not highly loaded and / or reallocate work from nodes that are overloaded. Additionally, the load balancing node 2201 may send reconfiguration commands to adjust the particular way in which rendering and / or denoising is performed by each node (some examples of which are described above). Determining the ghost area

[0238] The size and shape of the ghost regions 2001-2002 may be determined based on a denoising algorithm implemented by the denoisers 2100-2111. The respective sizes may then be dynamically changed based on the detected variance of the samples to be denoised. A learning algorithm used for the AI ​​denoising itself may be used to determine the appropriate region size, or in other cases, such as double-sided blurring, a pre-defined filter width determines the size of the ghost regions 2001-2002. In an example implementation using a learning algorithm, the machine learning engine may run on the manager node 2201 and / or parts of the machine learning may run on each of the individual nodes 2021-2023 (see, e.g., Figures 18A-18B and related text above). Acquiring the final image

[0239] The final image may be generated by collecting the rendered and denoised regions from each of the nodes 2021-2023 without the need for ghost regions or normals. In FIG. 22, for example, the denoised regions 2121-2122 are sent to a region processor 2280 of the manager node 2201 which combines the regions to generate a final denoised image 2290, which is then displayed on the display 2290. The region processor 2280 may combine the regions using various 2D compositing techniques. Although shown as separate components, the region processor 2280 and the denoised image 2290 may be integrated into the display 2290. The various nodes 2021-2022 transmit the denoised regions 2121-2122 using direct transmission techniques, potentially using various lossy or lossless compression of the region data.

[0240] As gaming moves to the cloud, AI denoising remains a costly operation. Therefore, to achieve real-time frame rates for traditional games or virtual reality (VR) that require higher frame rates, it may be necessary to distribute the denoising process across multiple nodes. Also, movie studios often render on large render farms that can be leveraged to speed up denoising.

[0241] An exemplary method for performing distributed rendering and denoising is shown in Figure 23. The method may be implemented within the context of the system architectures described above, but is not limited to any particular system architecture.

[0242] At 2301, graphics work is dispatched to multiple nodes that perform ray tracing operations to render regions of an image frame. Each node may already have the necessary data to perform the operations in memory. For example, two or more nodes may share a common memory, or data from a previous ray tracing operation may already be stored in the node's local memory. Alternatively, or in addition, specific data may be sent to each node.

[0243] At 2302, the "ghost region" (i.e., an acceptable level of performance) required for a particular level of denoising is determined. The ghost region consists of any data required to perform the particular level of denoising, including data owned by one or more other nodes.

[0244] Data relating to the ghost regions (or portions thereof) is exchanged between the nodes at 2303. At 2304, each node performs denoising on its respective regions (e.g., using the exchanged data) and combines the results at 2305 to generate a final denoised image frame.

[0245] A manager node or primary node, such as that shown in Figure 22, may dispatch work to the nodes and then combine the work performed by the nodes to generate the final image frame. A peer-based architecture can be used where the nodes are peers that exchange data to render and denoise the final image frame.

[0246] The nodes described herein (e.g., nodes 2021-2023) may be graphics processing computing systems interconnected via a high-speed network. Alternatively, the nodes may be individual processing elements coupled to a high-speed memory fabric. All nodes may share a common virtual memory space and / or a common physical memory. Alternatively, the nodes may be a combination of CPU and GPU. For example, the manager node 2201 described above may be a CPU and / or software running on a CPU, and the nodes 2021-2022 may be a GPU and / or software running on a GPU. Various different types of nodes may be used while still adhering to the principles underlying the present invention. Neural network implementation example

[0247] There are many types of neural networks, and a simple type of neural network is a feedforward network. A feedforward network may be implemented as an acyclic graph with nodes arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer converts the inputs received by the input layer into a representation useful for generating outputs at the output layer. The network nodes are fully connected via edges to nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes in the input layer of a feedforward network is propagated (i.e., "feed forward") to the nodes in the output layer via an activation function that calculates the state of the nodes in each successive layer in the network based on the coefficients ("weights") associated with each of the edges connecting each layer. Depending on the particular model represented by the algorithm being executed, the output from a neural network algorithm can take a variety of forms.

[0248] Before a machine learning algorithm is used to model a particular problem, the algorithm is trained using a training dataset. Training a neural network involves selecting a network topology, using a set of training data that represents the problem being modeled by the network, and adjusting the weights until the network model performs with minimal error for all instances in the training dataset. For example, during the supervised learning training process of a neural network, outputs generated by the network in response to inputs that represent instances in the training dataset are compared to the "correct" labeled outputs for that instance, an error signal representing the difference between the outputs and the labeled outputs is calculated, and the weights associated with the connections are adjusted to minimize that error as the error signal is propagated backwards through the layers of the network. The network is considered "trained" when the error for each output generated from an instance in the training dataset is minimized.

[0249] The accuracy of machine learning algorithms can be greatly affected by the quality of the data sets used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on traditional general-purpose processors. Thus, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the calculations performed in adjusting the coefficients of the neural network naturally lend themselves to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to take advantage of the parallel processing hardware within general-purpose graphics processing devices.

[0250] FIG. 24 is a generalized diagram of a machine learning software stack 2400. A machine learning application 2402 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 2402 can include training and inference functions for the neural network and / or specialized software that can be used to train the neural network prior to deployment. The machine learning application 2402 can implement any type of machine intelligence, including, but not limited to, image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0251] Hardware acceleration of the machine learning application 2402 can be enabled through the machine learning framework 2404. The machine learning framework 2404 can be implemented on hardware described herein, such as the processing system 100 including the processors and components described herein. Elements in FIG. 24 having the same or similar names as elements in any other figure herein can describe the same elements in the other figures, can operate or function in a similar manner, can include the same components, and can be linked to other entities as described elsewhere herein, including, but not limited to, the other figures. The machine learning framework 2404 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 2404, developers of machine learning algorithms would need to create and optimize the primary computational logic associated with the machine learning algorithm and reoptimize the computational logic as new parallel processors are developed. Instead, machine learning applications can be configured to perform the required computations using primitives provided by the machine learning framework 2404. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed during the training of convolutional neural networks (CNNs). The machine learning framework 2404 may also provide primitives for implementing basic linear algebra subprograms performed by many machine learning algorithms, such as matrix and vector operations.

[0252] The machine learning framework 2404 can process input data received from the machine learning application 2402 and generate appropriate inputs to the computation framework 2406. The computation framework 2406 can abstract the underlying instructions provided to the GPGPU driver 2408 to enable the machine learning framework 2404 to take advantage of hardware acceleration via the GPGPU hardware 2410 without requiring the machine learning framework 2404 to have detailed knowledge of the architecture of the GPGPU hardware 2410. Additionally, the computation framework 2406 can enable hardware acceleration of the machine learning framework 2404 across different types and generations of GPGPU hardware 2410.

[0253] GPGPU Machine Learning Acceleration

[0254] FIG. 25 illustrates a multi-GPU computing system 2500, which may be a variation of the processing system 100. Thus, disclosure of any feature in combination with the processing system 100 herein also discloses, but is not limited to, the corresponding combination with the multi-GPU computing system 2500. Elements of FIG. 25 having the same or similar names as elements of any other figure herein may describe the same elements in the other figures, may operate or function in a similar manner as such, may include the same components, and may be linked to other entities as described elsewhere herein, including, but not limited to, the same elements in the other figures. The multi-GPU computing system 2500 may include a processor 2502 coupled to a number of GPGPUs 2506A-D via a host interface switch 2504. The host interface switch 2504 may be, for example, a PCI Express switch device that couples the processor 2502 to a PCI Express bus through which the processor 2502 can communicate with the set of GPGPUs 2506A-D. Each of the multiple GPGPUs 2506A-D may be an instance of a GPGPU as described above. The GPGPUs 2506A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2516. High-speed GPU-to-GPU links can be connected to each GPGPU 2506A-D via a dedicated GPU link. The P2P GPU links 2516 allow direct communication between each of the GPGPUs 2506A-D without requiring communication via the host interface bus to which the processor 2502 is connected. For inter-GPU traffic sent to the P2P GPU links, the host interface bus can still be used for system memory access or for communication with other instances of the multi-GPU computing system 2500, for example, via one or more network devices. Instead of connecting the GPGPUs 2506A-D to the processor 2502 via the host interface switch 2504, the processor 2502 can include direct support for the P2P GPU links 2516 and can thus be directly connected to the GPGPUs 2506A-D.

[0255] Implementing machine learning neural networks

[0256] The computing architecture described herein can be configured to perform a type of parallel processing that is particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is well known in the art, there are various types of implementations of neural networks used in machine learning. One exemplary type of neural network is the feedforward network, as mentioned above.

[0257] A second exemplary type of neural network is the convolutional neural network (CNN). CNNs are specialized feed-forward neural networks for processing data with a known grid-like topology, such as image data. Thus, CNNs are commonly used for computer vision and image recognition applications, but may also be used for other types of pattern recognition, such as speech and language processing. The nodes of a CNN input layer are organized into sets of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes of successive layers of the network. Computation for a CNN involves applying a convolution computation operation to each filter to generate the output of that filter. Convolution is a special kind of computation operation performed by two functions to generate a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution may be called the input, and the second function may be called the convolution kernel. The output may be called a feature map. For example, the input to a convolutional layer may be a multidimensional array of data that defines the various color components of the input image. The convolution kernel can be a multi-dimensional array of parameters, which are adapted by a neural network training process.

[0258] Recurrent neural networks (RNNs) are a family of feed-forward neural networks that contain feedback connections between layers. RNNs allow for the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN contains cycles. At least a portion of the output data from an RNN is used as feedback to process subsequent inputs in the sequence, so the cycle represents the influence that the current value of a variable has on its own value in the future. This feature makes RNNs particularly useful for language processing, as it enhances the mutable nature that linguistic data can consist of.

[0259] The figures set forth below provide examples of feedforward, CNN, and RNN networks, and illustrate the general process for training and deploying each of these types of networks. It will be understood that these descriptions are exemplary and non-limiting, and that the illustrated concepts are applicable to deep neural networks and machine learning techniques in general.

[0260] The exemplary neural networks described above can be used to perform deep learning, which is machine learning using deep neural networks. Deep neural networks used in deep learning are artificial neural networks that are composed of multiple hidden layers, as opposed to shallow neural networks that contain only a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network allow for multi-stage pattern recognition and reduce output error compared to shallow machine learning techniques.

[0261] A deep neural network used in deep learning typically includes a front-end network for performing feature recognition coupled to a back-end network representing a computational model that can perform operations (e.g., object classification, speech recognition, etc.) based on feature representations provided to the model. Deep learning allows machine learning to be performed without the need to perform feature engineering manually on the model. Instead, a deep neural network can learn features based on statistical structures or correlations in the input data. The learned features can be provided to a computational model that can map the detected features to an output. The computational model used in the network is generally specialized for the particular task to be performed, and different models are used to perform different tasks.

[0262] Once a neural network is constructed, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights in the model to reduce the network's output error. Backpropagation of error is a common method used to train neural networks. Input vectors are presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then propagated backwards until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from these errors and update the neural network weights using algorithms such as the stochastic gradient descent algorithm.

[0263] 26-27 show an example of a convolutional neural network. FIG. 26 shows various layers within a CNN. As shown in FIG. 26, an exemplary CNN used to model image processing can receive an input 2602 describing the red, green, and blue (RGB) components of an input image. The input 2602 can be processed by multiple convolutional layers (e.g., convolutional layer 2604, convolutional layer 2606). The output from the multiple convolutional layers can optionally be processed by a set of fully connected layers 2608. The neurons in the fully connected layers are connected to all activations of the previous layer, as previously described for feedforward networks. The output from the fully connected layers 2608 can be used to generate an output result from the network. The activations in the fully connected layers 2608 can be calculated using matrix multiplication instead of convolutions. Not all CNN implementations utilize fully connected layers. For example, in some implementations, the convolutional layers 2606 can generate the output of the CNN.

[0264] Convolutional layers are sparsely connected, which differs from traditional neural network configurations found in the fully connected layer 2608. Traditional neural network layers are fully connected, such that every output unit interacts with every input unit. However, as shown in the figure, convolutional layers are sparsely connected because the output of the convolution of the field (instead of the respective state values ​​of each node in the field) is input to the nodes of the next layer. The kernels associated with a convolutional layer perform the convolution operation, and the output is sent to the next layer. The dimensionality reduction performed within the convolutional layers is one aspect that allows CNNs to scale to process large images.

[0265] FIG. 27 illustrates exemplary computational stages within a convolutional layer of a CNN. An input to the convolutional layer 2712 of a CNN can be processed in three stages in the convolutional layer 2714. The three stages can include a convolution stage 2716, a detector stage 2718, and a pooling stage 2720. The convolutional layer 2714 can then output data to a successive convolutional layer. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer to generate, for example, a classification value for the input to the CNN.

[0266] The convolution stage 2716 performs several convolutions in parallel to generate a set of linear activations. The convolution stage 2716 can include an affine transformation, which is any transformation that can be specified as a linear transformation and a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) that is connected to a particular region in the input, which can be determined as a local region associated with the neuron. The neuron calculates a dot product between the weight of the neuron and the region of the local input to which the neuron is connected. The output from the convolution stage 2716 defines a set of linear activations that are processed by successive stages of the convolution layer 2714.

[0267] The linear activations may be processed by a detector stage 2718. In the detector stage 2718, each linear activation is processed by a nonlinear activation function. The nonlinear activation function enhances the nonlinear characteristics of the entire network without affecting the receptive fields of the convolutional layers. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x)=max(0,x) such that the activations are thresholded at zero.

[0268] The pooling stage 2720 uses a pooling function that replaces the output of the convolutional layer 2706 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance to the neural network so that small translations to the input do not change the pooled output. Invariance to local transformations can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 2720, including max pooling, average pooling, and l2-norm pooling. Furthermore, some CNN implementations do not include a pooling stage. Instead, such implementations substitute and add a convolution stage with an increased stride compared to the previous convolution stage.

[0269] The output from the convolutional layer 2714 may then be processed by the next layer 2722, which may be either an additional convolutional layer or a fully connected layer 2708. For example, the first convolutional layer 2704 in FIG. 27 may output to a second convolutional layer 2706, which may output to the first layer of a fully connected layer 2808.

[0270] FIG. 28 illustrates an exemplary recurrent neural network 2800. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be constructed in a variety of ways, using a variety of functions. The use of RNNs generally revolves around using computational models to predict the future based on a series of previous inputs. For example, RNNs can be used to perform statistical language modeling to predict the next word given a previous word sequence. The illustrated RNN 2800 can be described as having an input layer 2802 that receives input vectors, a hidden layer 2804 to implement a recurrent function, a feedback mechanism 2805 to allow "memory" of the previous state, and an output layer 2806 to output the results. The RNN 2800 operates based on time steps. The state of the RNN at a given time step is influenced based on the previous time step via the feedback mechanism 2805. For a given time step, the state of the hidden layer 2804 is defined by the previous state and the input at the current time step. An initial input (x1) at a first time step may be processed by the hidden layer 2804. A second input (x2) may be processed by the hidden layer 2804 using state information determined during processing of the initial input (x1). A given state may be calculated as s_t=f(Ux_t+Ws_(t-1)), where U and W are parameter matrices. The function f is typically a nonlinearity such as a variant of the hyperbolic tangent function (Tanh) or the rectifier function f(x)=max(0,x). However, the particular computational function used in the hidden layer 2804 may vary depending on the details of a particular implementation of the RNN 2800.

[0271] In addition to the basic CNN and RNN networks described, variants of these networks may be enabled. One example of an RNN variant is the long short-term memory (LSTM) RNN. LSTM RNNs can learn long-term dependencies that may be necessary to process longer sequences of language. A variant of CNN is the convolutional deep belief network, which has a similar structure to a CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network that consists of multiple layers of probabilistic (random) variables. DBNs can be trained layer-by-layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining the optimal initial weight set for the neural network.

[0272] FIG. 29 illustrates the training and deployment of deep neural networks. Once a given network is structured for a task, the neural network is trained using a training dataset 2902. Various training frameworks 2904 have been developed to allow hardware acceleration of the training process. For example, the machine learning frameworks described above can be configured as training frameworks. The training frameworks 2904 hook into an untrained neural network 2906 and allow the untrained neural net to be trained using parallel processing resources as described herein to generate a trained neural net 2908.

[0273] To begin the training process, initial weights can be selected randomly or by pre-training using a deep belief network. Training cycles are then performed in either a supervised or unsupervised manner.

[0274] Supervised learning is a learning method in which training is performed as a mediated operation, such as when a training data set 2902 includes pairs of inputs and desired outputs of the inputs, or when a training data set includes inputs with known outputs and the output of the neural network is evaluated manually. The network processes the inputs and compares the results and the resulting outputs to a set of expected or desired outputs. Errors are then propagated through the system. The training framework 2904 can be adjusted to adjust the weights that control the untrained neural network 2906. The training framework 2904 can provide tools to monitor how well the untrained neural network 2906 is converging towards a model suitable for generating correct answers based on known input data. The training process is iterative as the weights of the network are adjusted to adjust the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural net 2908. The trained neural network 2908 can then be deployed to implement any number of machine learning operations.

[0275] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, in the case of unsupervised learning, a training dataset 2902 includes input data without any associated output data. The untrained neural network 2906 can learn groupings within the unlabeled inputs and determine how individual inputs relate to the entire dataset. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 2907 that can perform operations useful for reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which can identify data points within an input dataset that deviate from normal patterns in the data.

[0276] Variations of supervised and unsupervised training may also be used. Semi-supervised learning is an approach in which the training data set 2902 contains a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variation of supervised learning in which input data is continually used to further train the model. Incremental learning allows the trained neural network 2908 to adapt to new data 2912 without forgetting the knowledge instilled in the network during initial training.

[0277] The training process, especially of deep neural networks, whether supervised or unsupervised, can be too computationally intensive for a single computation node. Instead of using a single computation node, a distributed network of computation nodes can be used to accelerate the training process.

[0278] 30A is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes, such as those described above, to perform supervised or unsupervised training of neural networks. Each distributed computing node may include one or more host processors and one or more general-purpose processing nodes, such as a highly parallel general-purpose graphics processing unit. As shown, distributed learning can perform model parallelism 3002, data parallelism 3004, or a combination of model parallelism and data parallelism.

[0279] In model parallelism 3002, different computational nodes in a distributed system can perform training computations on different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Advantages of model parallelism include its ability to scale, especially for large models. Partitioning the computations associated with different layers of a neural network enables the training of very large neural networks where the weights of all layers do not fit into the memory of a single computational node. In some examples, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0280] In data parallelism 3004, different nodes of the distributed network have a complete instance of the model, with each node receiving a different portion of the data. The results from the different nodes are then combined. Various approaches to data parallelism are possible, but all data parallel training approaches require techniques to combine results and synchronize model parameters between each node. Exemplary approaches to combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transferring parameters from nodes to a parameter server, updates to the model are transferred. Additionally, update-based data parallelism can be performed in a distributed manner where updates are compressed and transferred between nodes.

[0281] The combination of model and data parallelism 3006 can be implemented, for example, in a distributed system where each compute node contains multiple GPUs. Each node can have a complete instance of the model, and separate GPUs within each node are used to train different parts of the model.

[0282] Distributed training incurs increased overhead compared to training on a single machine, but the parallel processors and GPGPUs described herein can implement various techniques to reduce the overhead of distributed training, including techniques that enable high-bandwidth inter-GPU data transfers and accelerated remote data synchronization, respectively. Example Machine Learning Applications

[0283] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Computer vision applications range from replicating human visual capabilities, such as recognizing faces, to creating new categories of visual capabilities. For example, computer vision applications can be configured to recognize sound waves from vibrations induced in objects displayed in a video. Parallel processor-accelerated machine learning makes it possible to train computer vision applications using much larger training datasets than previous training datasets, and allows inference systems to be deployed using low-power parallel processors.

[0284] Machine learning accelerated on parallel processors has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein enable rapid training of increasingly complex neural networks used in autonomous driving solutions and enable deployment of low-power inference processors on mobile platforms suitable for integration into autonomous vehicles.

[0285] Deep neural networks accelerated on parallel processors have enabled a machine learning approach to automatic speech recognition (ASR). ASR involves the creation of a function that calculates the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled the replacement of hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0286] Machine learning accelerated by parallel processors can also be used to accelerate natural language processing. Automated learning procedures can utilize statistical inference algorithms to create models that are robust to erroneous or unfamiliar input. Exemplary natural language processor applications include automatic machine translation between human languages.

[0287] Parallel processing platforms used for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallelized and include optimizations to accelerate multi-GPU single-node training and multi-node, multi-GPU training. Exemplary parallel processors suitable for training include the highly parallel general-purpose graphics processing units and / or multi-GPU computing systems described herein. In contrast, deployed machine learning platforms generally include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0288] FIG. 30B illustrates an exemplary inference system-on-chip (SoC) 3100 suitable for performing inference using the trained model. Elements of FIG. 30B having the same or similar names as elements of any other figure herein may describe the same elements in the other figures, may operate or function in a similar manner as such, may include the same components, and may be linked to other entities as described elsewhere herein, including, but not limited to, the other figures. The SOC 3100 may integrate processing components including a media processor 3102, a vision processor 3104, a GPGPU 3106, and a multi-core processor 3108. The SOC 3100 may further include an on-chip memory 3105 that may enable a shared on-chip data pool accessible by each processing component. Optimizing the processing components for low-power operation allows for deployment in a variety of machine learning platforms, such as autonomous cars and autonomous robots. For example, one implementation of the SOC 3100 may be used as part of the main control system of an autonomous vehicle. When the SOC3100 is configured for use in an autonomous vehicle, the SOC will be designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0289] In operation, the media processor 3102 and the vision processor 3104 can work in concert to accelerate computer vision operations. The media processor 3102 can enable low latency decoding of multiple high resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 3105. The vision processor 3104 can then analyze the decoded video and perform pre-processing operations on frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the vision processor 3104 can accelerate the convolution operations of a CNN used to perform image recognition on high resolution video data, with the back-end model computations being performed by the GPGPU 3106.

[0290] The multi-core processor 3108 may include control logic to assist in ordering and synchronizing data transfer and shared memory operations performed by the media processor 3102 and the vision processor 3104. The multi-core processor 3108 may also function as an application processor for executing software applications that can utilize the inference computation capabilities of the GPGPU 3106. For example, at least a portion of the navigation and driving logic may be implemented in software that runs on the multi-core processor 3108. Such software may issue computational workloads directly to the GPGPU 3106 or may issue computational workloads to the multi-core processor 3108, which may offload at least a portion of their operations to the GPGPU 3106.

[0291] The GPGPU3106 can include processing clusters such as low power configurations of processing clusters DPLAB06A-DPLAB06H within the highly parallel general purpose graphics processing unit DPLAB00. The processing clusters within the GPGPU3106 can support instructions specifically optimized for performing inference calculations on trained neural networks. For example, the GPGPU3106 can support instructions for performing low precision calculations such as 8-bit and 4-bit integer vector operations. Ray Tracing Architecture

[0292] In one implementation, a graphics processor includes circuitry and / or program code for performing real-time ray tracing. A dedicated set of ray tracing cores may be included in the graphics processor to perform various ray tracing operations described herein, including ray traversal and / or ray intersection operations. In addition to the ray tracing cores, multiple sets of graphics processing cores for performing programmable shading operations and multiple sets of tensor cores for performing matrix operations on tensor data may also be included.

[0293] FIG. 31 illustrates one exemplary portion of such a graphics processing unit (GPU) 3105 including a dedicated set of graphics processing resources arranged in multi-core groups 3100A-N. The graphics processing unit (GPU) 3105 may be a variation of the graphics processor 300, the GPGPU 1340, and / or any other graphics processor described herein. Thus, the disclosure of any feature for a graphics processor also discloses, but is not limited to, the corresponding combination with the GPU 3105. Additionally, elements of FIG. 31 having the same or similar names as elements of any other figure herein may describe the same elements in the other figures, may operate or function in a similar manner as such, may include the same components, and may be linked to other entities as described elsewhere herein. Although details of only a single multi-core group 3100A are provided, it will be understood that the other multi-core groups 3100B-N may comprise the same or similar sets of graphics processing resources.

[0294] As shown, multicore group 3100A may include a set of graphics cores 3130, a set of tensor cores 3140, and a set of ray tracing cores 3150. A scheduler / dispatcher 3110 schedules and dispatches graphics threads for execution on the various cores 3130, 3140, 3150. A set of register files 3120 store operand values ​​used by the cores 3130, 3140, 3150 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. The tile registers may be implemented as a combined set of vector registers.

[0295] One or more level 1 (L1) caches and texture units 3160 store graphics data, such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multicore group 3100A. A level 2 (L2) cache 3180, shared by all or a subset of the multicore groups 3100A-N, stores graphics data and / or instructions for multiple simultaneous graphics threads. As shown, the L2 cache 3180 may be shared across multiple multicore groups 3100A-N. One or more memory controllers 3170 couple the GPU 3105 to memory 3198, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0296] An input / output (IO) circuit 3195 couples the GPU 3105 to one or more IO devices 3195, such as a digital signal processor (DSP), a network controller, or a user input device. An on-chip interconnect may be used to couple the I / O device 3190 to the GPU 3105 and the memory 3198. One or more IO memory management units (IOMMUs) 3170 of the IO circuit 3195 directly couple the IO device 3190 to the system memory 3198. The IOMMU 3170 may manage multiple sets of page tables to map virtual addresses to physical addresses in the system memory 3198. Additionally, the IO device 3190, the CPU(s) 3199, and the GPU(s) 3105 may share the same virtual address space.

[0297] The IOMMU 3170 may also support virtualization. In this case, it may manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables (e.g., in system memory 3198) for mapping guest / graphics physical addresses to system / host physical addresses. The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out during a context switch (e.g., so that a new context is provided access to the associated set of page tables). Although not shown in FIG. 31, each of the cores 3130, 3140, 3150 and / or multicore groups 3100A-N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical, guest physical to host physical, and guest virtual to host physical translations.

[0298] The CPU 3199, GPU 3105, and IO devices 3190 may be integrated into a single semiconductor chip and / or chip package. The illustrated memory 3198 may be integrated on the same chip or may be coupled to the memory controller 3170 via an off-chip interface. In one implementation, the memory 3198 comprises GDDR6 memory that shares the same virtual address space with other physical system level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0299] Tensor cores 3140 may include multiple execution units specifically designed to perform matrix operations, which are fundamental computational operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for training and inference of neural networks. Tensor cores 3140 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32-bit), half-precision floating point (e.g., 16-bit), integer word (16-bit), byte (8-bit), and half-byte (4-bit). Neural network implementations may extract features of each rendered scene and potentially combine details from multiple frames to construct a high-quality final image.

[0300] In a deep learning implementation, parallel matrix multiplication operations may be scheduled to run on the tensor cores 3140. Specifically, training a neural network requires a significant number of matrix dot product operations. To process the inner product formulation of NxNxN matrix multiplication, the tensor cores 3140 may include at least N dot product processing elements. Before the matrix multiplication begins, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded each of the N cycles. In each cycle, there are N dot products to be processed.

[0301] Matrix elements may be stored with different precisions depending on the particular implementation, such as 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes are specified for tensor cores 3140 so that the most efficient precision is used for different workloads (e.g., inference workloads that can tolerate quantization into bytes and half-bytes).

[0302] The ray tracing core 3150 may be used to accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. Specifically, the ray tracing core 3150 may include ray traversal / intersection circuitry for performing ray traversal using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 3150 may also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar arrangement). In one implementation, the ray tracing core 3150 performs traversal and intersection operations, at least some of which may be executed on the tensor core 3140, in coordination with the image denoising techniques described herein. For example, the tensor core 3140 implements a deep learning neural network to perform denoising of frames generated by the ray tracing core 3150. However, the CPU(s) 3199, graphics core 3130, and / or ray tracing core 3150 may also implement all or part of the denoising and / or deep learning algorithms.

[0303] Additionally, as discussed above, the GPU 3105 may employ a distributed approach to denoising in a computing device coupled to other computing devices via a network or high-speed interconnect. The interconnected computing devices may further share neural network learning / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0304] The ray tracing core 3150 may handle all BVH traversal and ray primitive intersections, preventing the graphics core 3130 from being overloaded with thousands of instructions per ray. Each ray tracing core 3150 may include a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing ray and triangle intersection tests (e.g., intersection of traversed rays). Thus, the multi-core group 3100A may simply launch ray probes, and the ray tracing cores 3150 independently perform ray traversal and intersections and return hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. While the ray tracing core 3150 performs traversal and intersection operations, the other cores 3130, 3140 may be freed to perform other graphics or computational work.

[0305] Each ray tracing core 3150 may include a traversal unit for performing BVH test operations and an intersection unit for performing ray primitive intersection tests. The intersection unit may then generate a "hit," "no hit," or "multiple hits" response to provide to the appropriate thread. During traversal and intersection operations, the execution resources of other cores (e.g., graphics core 3130 and tensor core 3140) may be freed up to perform other forms of graphics work.

[0306] A hybrid rasterization / ray tracing approach may also be used, in which work is distributed between the graphics core 3130 and the ray tracing core 3150.

[0307] The ray tracing core 3150 (and / or other cores 3130, 3140) may include hardware support for a ray tracing instruction set such as Microsoft's DirectX Raytracing (DXR), including the DispatchRays command, as well as ray generation, nearest hit, any hit, and miss shaders that can assign a unique set of shaders and textures per object. Another ray tracing platform that may be supported by the ray tracing core 3150, graphics core 3130, and tensor core 3140 is Vulkan 1.1.85. However, it should be noted that the principles underlying the present invention are not limited to any particular ray tracing ISA.

[0308] In general, the various cores 3150, 3140, 3130 may support a ray tracing instruction set that includes instructions / functions for ray generation, nearest hit, any hit, ray primitive intersection, per-primitive and hierarchical bounding box construction, miss, access, and exception. More specifically, the ray tracing instructions may include instructions for performing the following functions:

[0309] Ray Generation - Ray generation instructions may be performed per pixel, sample, or other user-defined work allocation.

[0310] Nearest Hit - The nearest hit command can be executed to find the nearest intersection point of a ray with a primitive in the scene.

[0311] Any Hit - The any hit command identifies multiple intersection points between rays and primitives in the scene, and potentially identifies a new closest intersection point.

[0312] Intersection - The intersection command performs a ray primitive intersection test and outputs the result.

[0313] Build Per-Primitive Bounding Box - This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other accelerated data structure).

[0314] Miss - indicates that the ray missed all geometry in the scene or a specified region of the scene.

[0315] Visit - Describes the child volume that the ray traverses.

[0316] Exceptions - Contains exception handlers of various types (e.g., called for various error conditions). Hierarchical Beam Tracing

[0317] Bounding volume hierarchies are commonly used to improve the efficiency of performing operations on graphics primitives and other graphics objects. A BVH is a hierarchical tree structure built on a set of geometric objects. At the top of the tree structure is a root node that encloses all geometric objects in a given scene. Individual geometric objects are enclosed within bounding volumes that form leaf nodes of the tree. These nodes are then grouped into small sets and enclosed within larger bounding volumes. These are then grouped and enclosed recursively within other larger bounding volumes, eventually resulting in a tree structure with a single bounding volume at the top of the tree, represented by the root node. Bounding volume hierarchies are used to efficiently support various operations on sets of geometric objects, such as collision detection, primitive culling, and ray traversal / intersection operations used in ray tracing.

[0318] In a ray tracing architecture, rays traverse the BVH to determine ray primitive intersections. For example, if a ray does not pass through the root node of the BVH, the ray does not intersect with any of the primitives enclosed by the BVH, and no further processing is required for the ray with respect to this set of primitives. If a ray passes through the first child node of the BVH, but not through the second child node, the ray does not need to be tested against any primitives enclosed by the second child node. In this way, the BVH provides an efficient mechanism for testing ray primitive intersections.

[0319] A group of consecutive rays, called a "beam," may be tested against the BVH rather than individual rays. FIG. 32 shows an example beam 3201 outlined by four different rays. Any ray that intersects with a patch 3200 defined by the four rays is considered to be in the same beam. Although the beam 3201 in FIG. 32 is defined by a rectangular arrangement of rays, beams may be defined in a variety of other ways while still adhering to the principles underlying the present invention (e.g., circle, ellipse, etc.).

[0320] FIG. 33 illustrates how the ray tracing engine 3310 of the GPU 3320 implements the beam tracing techniques described herein. Specifically, the ray generation circuit 3304 generates multiple rays on which traversal and intersection operations are to be performed. However, rather than performing traversal and intersection operations on individual rays, the traversal and intersection operations are performed using a hierarchy of beams 3307 generated by the beam hierarchy construction circuit 3305. The beam hierarchy is similar to a bounding volume hierarchy (BVH). For example, FIG. 34 provides an example of a primary beam 3400 that may be subdivided into multiple different components. Specifically, the primary beam 3400 may be divided into quadrants 3401-3404, each of which may itself be divided into sub-quadrant such as sub-quadrant A-D within the quadrant 3404. The primary beam may be subdivided in various ways. For example, the primary beam may be divided into halves (rather than quadrants), each half may be divided into halves, and so on. Regardless of how the subdivision is performed, a hierarchical structure is generated in a manner similar to a BVH, for example with a root node representing the primary beam 3400, first level child nodes each represented by a quadrant 3401-3404, second level child nodes for each sub-quadrant A-D, etc.

[0321] Once the beam hierarchy 3307 is constructed, the traversal / intersection circuit 3306 may perform traversal / intersection operations using the beam hierarchy 3307 and the BVH 3308. Specifically, it may test the beam against the BVH and cull portions of the beam that do not intersect with any portion of the BVH. Using the data shown in FIG. 34, for example, if a sub-beam associated with sub-regions 3402 and 3403 does not intersect with the BVH or a particular branch of the BVH, the sub-beam may be culled with respect to the BVH or branch. The remaining portions 3401, 3404 may be tested against the BVH by performing a depth-first search or other search algorithm.

[0322] The method for ray tracing is shown in Figure 35. The method may be implemented within the context of the graphics processing architectures described above, but is not limited to any particular system architecture.

[0323] At 3500, a primary beam with multiple rays is constructed, and at 3501, the beam is subdivided and a hierarchical data structure is generated to create a beam hierarchy. Operations 3500-3501 may be performed as a single integrated operation to construct a beam hierarchy from multiple rays. At 3502, the beam hierarchy is used with the BVH to cull rays (from the beam hierarchy) and / or nodes / primitives from the BVH. At 3503, intersections of the ray primitives are determined against the remaining rays and primitives. Lossy and Lossless Packet Compression in Distributed Ray Tracing Systems

[0324] Ray tracing operations may be distributed across multiple computational nodes coupled over a network. Figure 36, for example, shows a ray tracing cluster 3600 including multiple ray tracing nodes 3610-3613 performing ray tracing operations in parallel and potentially combining the results at one of the nodes. In the illustrated architecture, the ray tracing nodes 3610-3613 are communicatively coupled to a client-side ray tracing application 3630 via a gateway.

[0325] One problem with a distributed architecture is that a large amount of packetized data must be transmitted between each of the ray tracing nodes 3610-3613. Both lossless and lossy compression techniques can be used to reduce the data transmitted between the ray tracing nodes 3610-3613.

[0326] To implement lossless compression, rather than sending packets filled with the results of a particular type of operation, they send data or commands that allow the receiving node to reconstruct the results. For example, stochastically sampled area lights and ambient occlusion (AO) operations do not necessarily require a direction. Thus, the sending node can simply send a random seed, which is then used by the receiving node to perform the random sampling. For example, if a scene is distributed across nodes 3610-3612, to sample light 1 at points p1-p3, only the light ID and the origin need to be sent to nodes 3610-3612. Each node may then independently sample the light probabilistically. The random seed may be generated by the receiving node. Similarly, for a primary ray hit point, ambient occlusion (AO) and soft shadow sampling can be computed on nodes 3610-3612 without waiting for the point of origin for successive frames. Furthermore, if a set of rays is known to be directed to the same point light source, an instruction identifying the light source may be sent to the receiving node, which applies the instruction to the set of rays. As another example, if there are N ambient occlusion rays sent to a single point, a command may be sent to generate N samples from this point.

[0327] Various additional techniques may be applied to the lossy compression. For example, using a quantization factor, all coordinate values ​​related to the BVH, primitives, and rays may be quantized. Additionally, 32-bit floating point values ​​used for data such as BVH nodes and primitives may be converted to 8-bit integer values. In an exemplary implementation, the boundaries of the ray packets are stored with full precision, but the individual ray points P1-P3 are transmitted as indexed offsets to the boundaries. Similarly, multiple local coordinate systems may be generated that use 8-bit integer values ​​as local coordinates. The location of the origin of each of these local coordinate systems may be encoded using full precision (e.g., 32-bit floating point) values, effectively connecting the global and local coordinate systems.

[0328] Below is an example of lossless compression: Below is an example of a ray data format used internally by ray tracing programs: struct Ray { uint32 pixId; uint32 materialID; uint32 instanceID; uint64 primitiveID; uint32 geometryID; uint32 lightID; float origin[3]; float direction[3]; float t0; float t; float time; float normal[3]; / / used for geometry intersections float u; float v; float wavelength; float phase; / / Interferometry float refractedOffset; / / Schlieren-esque float amplitude; float weight; };

[0329] Instead of sending the raw data for every generated node, this data can be compressed by grouping values ​​and creating implicit rays with applicable metadata where possible.

[0330] Ray data combining and grouping flags can be used for general data or masks with modifiers. struct RayPacket { uint32 size; uint32 flags; list <ray>rays; }Example: RayPacket.rays=ray_1~ray_256 All origins are shared

[0331] All ray data is packed except that only a single origin is stored across all rays. RayPacket.flags is set to RAYPACKET_COMMON_ORIGIN. When a RayPacket is unpacked upon receipt, the origin is filled in from a single origin value. The origin is only shared among several rays.

[0332] All ray data is packed, except for rays that share an origin. For each group of unique shared origins, an operator is packed that identifies the operation (shared origin), stores the origin, and masks which rays share information. Such operations can be performed on any value that is shared between nodes, such as material IDs, primitive IDs, origins, orientations, normals, etc. struct RayOperation { uint8 operationID; void*value; uint64 mask; } Implicit Ray Sending

[0333] In many cases, ray data can be derived at the receiver using minimal meta-information used to generate the ray data. A very common example is generating multiple secondary rays to probabilistically sample an area. Instead of the sender generating and sending secondary rays and the receiver manipulating them, the sender can send a command that a ray should be generated using the dependency information, and the ray is generated at the receiver. If the sender needs to generate a ray first to determine which receiver to send it to, they can generate the ray and send a random seed to regenerate the exact same ray.

[0334] For example, to sample hit points with 64 shadow rays sampling an area light source, all 64 rays intersect with the same area of ​​computation N4. A RayPacket with a common origin and normal is created. More data can be sent if the receiver wishes to shade the resulting pixel contribution, but for this example we will assume we only want to return whether the ray hits another node's data. A RayOperation is created for the shadow ray generation operation and is assigned the value of the lightID to be sampled and a random seed. When N4 receives the ray packet, it generates fully populated ray data by filling all rays with the shared origin data, setting the direction based on the lightID probabilistically sampled with the random seed, and generating the same rays as the original sender generated. When results are returned, only the binary results of all rays need to be returned, allowing rays to be passed through a mask.

[0335] In this example, sending 64 rays of the origin uses 104 bytes * 64 rays = 6656 bytes. If the return rays were also sent in raw form, this would also double to 13312 bytes. Using lossless compression, where only the common ray origin, normal, and ray generation operations are sent, with seeds and IDs, only 29 bytes would be sent, and 8 bytes returned for the intersected masks. This results in a data compression ratio of about 360:1 that needs to be sent over the network. This does not include the overhead for processing the messages themselves, which would need to be identified somehow, but that is up to the implementation. Other operations may be done to recalculate the ray origin and direction from pixelD of the primary ray, to recalculate pixelID based on ranges in the ray packet, and many other possible implementations for recalculating values. Similar operations can be used for any single ray or group of rays sent, including shadows, reflections, refractions, ambient occlusion, intersections, volume intersections, shading, and bounce reflections in path tracing.

[0336] FIG. 37 shows additional details regarding two ray tracing nodes 3710-3711 performing compression and decompression of ray tracing packets. Specifically, when the first ray tracing engine 3730 is ready to send data to the second ray tracing engine 3731, the ray compression circuit 3720 performs lossy and / or lossless compression of the ray tracing data as described herein (e.g., converting 32-bit values ​​to 8-bit values, substituting instructions for reconstructing the data with the raw data, etc.). The compressed ray packet 3701 is transmitted over a local network (e.g., a 10 Gb / s, 100 Gb / s Ethernet network) from the network interface 3725 to the network interface 3726. The ray decompression circuit then decompresses the ray packet as needed. For example, it may execute commands (e.g., perform random sampling of lighting operations using a random seed) to reconstruct the ray tracing data. The ray tracing engine 3731 then performs ray tracing operations using the received data.

[0337] In the reverse direction, the ray compression circuit 3741 compresses the ray data, the network interface 3726 transmits the compressed ray data over the network (e.g., using the techniques described herein), the ray decompression circuit 3740 decompresses the ray data as necessary, and the ray tracing engine 3730 uses the data in ray tracing operations. Although shown as separate units in Figure 37, the ray decompression circuits 3740-3741 may be integrated within the ray tracing engines 3730-3731, respectively. For example, to the extent that the compressed ray data includes commands for reconstructing the ray data, these commands may be executed by the respective ray tracing engines 3730-3731.

[0338] 38, the ray compression circuit 3720 may include a lossy compression circuit 3801 for performing the lossy compression techniques described herein (e.g., converting 32-bit floating point coordinates to 8-bit integer coordinates), and a lossless compression circuit 3803 for performing the lossless compression techniques (e.g., sending commands and data to enable the ray recompression circuit 3821 to reconstruct the data). The ray decompression circuit 3721 includes a lossy decompression circuit 3802 and a lossless decompression circuit 3804 for performing lossless decompression.

[0339] Another exemplary method is shown in Figure 39. The method may be implemented in a ray tracing architecture or other architectures described herein, but is not limited to any particular architecture.

[0340] At 3900, ray data is received from a first ray tracing node to be transmitted to a second ray tracing node. At 3901, a lossy compression circuit performs lossy compression on the first ray tracing data, and at 3902, a lossless compression circuit performs lossless compression on the second ray tracing data. At 3903, the compressed ray tracing data is transmitted to the second ray tracing node. At 3904, a lossy / lossless decompression circuit performs lossy / lossless decompression of the ray tracing data, and at 3905, the second ray tracing node performs a ray tracing operation using the decompressed data. Hardware-equipped graphics processor Accelerated Hybrid Ray Tracing

[0341] Next, a hybrid rendering pipeline is presented that performs rasterization in the graphics core 3130 and ray tracing operations in the ray tracing core 3150, the graphics core 3130, and / or the CPU 3199 core. For example, rasterization and depth testing may be performed in the graphics core 3130 instead of the primary ray casting stage. The ray tracing core 3150 may then generate secondary rays for reflection, refraction, and shadowing of rays. Furthermore, certain regions of the scene (e.g., based on material property thresholds such as high reflectivity levels) are selected on which the ray tracing core 3150 performs ray tracing operations, while other regions of the scene are rasterized and rendered on the graphics core 3130. This hybrid implementation may be used for real-time ray tracing applications where latency is a critical issue.

[0342] The ray traversal architecture described below may use existing single instruction multiple data (SIMD) and / or single instruction multiple thread (SIMT) graphics processors to perform programmable shading and control of ray traversal, while accelerating critical functions such as BVH traversal and / or intersection using dedicated hardware. SIMD occupancy of incoherent paths may be improved by regrouping shaders generated at specific points during traversal and before shading. This is achieved using dedicated hardware that dynamically reorders shaders on-chip. Recursion is managed by splitting the function into continuations. Continuations are executed when returning and regrouping continuations before execution to improve SIMD occupancy.

[0343] Programmable control of ray traversal / intersection is achieved by decomposing traversal functionality into inner traversals, which can be implemented as fixed-function hardware, and outer traversals, which run on the GPU processor and allow programmable control via user-defined traversal shaders. The cost of transferring traversal contexts between hardware and software is reduced by conservatively truncating inner traversal state during the transition between inner and outer traversals.

[0344] Programmable control of ray tracing can be expressed through various shader types, which are listed in Table A below. There can be multiple shaders per type. For example, each material can have a different hit shader. [Table A] [Table 1]

[0345] Recursive ray tracing may begin with an API function that instructs the graphics processor to launch a set of primary shaders or intersection circuits that can generate ray-scene intersections of a primary ray. This generates other shaders, such as traversal, hit, and miss shaders. A shader that generates child shaders can also receive return values ​​from the child shaders. A callable shader is a generic function that can be generated directly by another shader and can also return values ​​to the calling shader.

[0346] Figure 40 shows a graphics processing architecture including shader execution circuitry 4000 and fixed function circuitry 4010. The general-purpose execution hardware subsystem includes multiple single instruction multiple data (SIMD) and / or single instruction multiple thread (SIMT) cores / execution units (EUs) 4001 (i.e., each core may include multiple execution units), one or more samplers 4002, and a level 1 (L1) cache 4003 or other form of local memory. The fixed function hardware subsystem 4010 includes a message unit 4004, a scheduler 4007, a ray-BVH traversal / intersection circuitry 4005, a reordering circuitry 4008, and a local L1 cache 4006.

[0347] In operation, the primary dispatcher 4009 dispatches a set of primary rays to the scheduler 4007, which schedules work to shaders executing on the SIMD / SIMT core / EU 4001. The SIMD core / EU 4001 may be the ray tracing core 3150 and / or the graphics core 3130 described above. Executing the primary shader generates additional work to execute (e.g., performed by one or more child shaders and / or fixed function hardware). The message unit 4004 distributes the work generated by the SIMD core / EU 4001 to the scheduler 4007, accessing the free stack pool, the reordering circuit 4008, or the ray-BVH intersection circuit 4005 as needed. If additional work is sent to the scheduler 4007, it is scheduled for processing on the SIMD / SIMT core / EU 4001. Prior to scheduling, the sorting circuit 4008 may sort the rays into groups or bins (e.g., grouping rays with similar characteristics) as described herein. The ray-BVH intersection circuit 4005 performs intersection testing of the rays with the BVH volumes. For example, the ray-BVH intersection circuit 4005 may compare the ray coordinates with each level of the BVH to identify volumes that intersect with the ray.

[0348] Shaders can be referenced using a shader record, a user-allocated structure that contains a pointer to an entry function, vendor-specific metadata, and global arguments for the shader to be executed by the SIMD core / EU4001. Each running instance of a shader is associated with a call stack that can be used to store arguments passed between parent and child shaders. The call stack can also store references to continuation functions that are executed when the call returns.

[0349] FIG. 41 shows an example set of allocated stacks 4101 including a primary shader stack, a hit shader stack, a traversal shader stack, a continuation function stack, and a ray-BVH intersection stack (which may be implemented by fixed function hardware 4010 as described). A new shader invocation may implement a new stack from a free stack pool 4102. Call stacks, e.g., stacks constituted by the set of allocated stacks, may be cached in local L1 caches 4003, 4006 to reduce access latency.

[0350] There may be a finite number of call stacks, each with a fixed maximum size "Sstack" allocated in a contiguous region of memory. Thus, the base address of a stack can be calculated directly from the stack index (SID) as base address = SID * Sstack. Stack IDs may be allocated and deallocated by the scheduler 4007 when scheduling work to a SIMD core / EU 4001.

[0351] The primary dispatcher 4009 may comprise a graphics processor command processor that dispatches primary shaders in response to dispatch commands from a host (e.g., a CPU). The scheduler 4007 may receive these dispatch requests and launch the primary shaders on the SIMD processor threads if it can allocate a stack ID for each SIMD lane. The stack IDs may be allocated from a free stack pool 4102 that is initialized at the start of a dispatch command.

[0352] An executing shader can spawn child shaders by sending a spawn message to the message unit 4004. This command contains the stack ID associated with the shader and also contains pointers to the child shader records for each active SIMD lane. A parent shader can only issue this message once for an active lane. After sending spawn messages to all relevant lanes, the parent shader can exit.

[0353] Shaders executing on SIMD cores / EUs 4001 can also generate fixed function tasks such as ray-BVH intersection using generate messages with shader record pointers reserved for fixed function hardware. As described above, message unit 4004 sends generated ray-BVH intersection work to fixed function ray-BVH intersection circuit 4005 and callable shaders directly to reordering circuit 4008. Reordering circuit may group shaders by shader record pointers to derive SIMD batches with similar characteristics. Thus, stack IDs from different parent shaders can be grouped by reordering circuit 4008 in the same batch. Reordering circuit 4008 sends the grouped batches to scheduler 4007, which accesses shader records from graphics memory 2511 or last level cache (LLC) 4020 and launches shaders on processor threads.

[0354] Continuations may be treated as callable shaders and may be referenced via shader records. When a child shader is generated and returns a value to a parent shader, a pointer to the continuation shader record may be pushed onto the call stack 4101. When the child shader returns, the continuation shader record may then be popped from the call stack 4101 and the continuation shader may be generated. Optionally, the generated continuation may pass through a reordering unit in the same way as a callable shader and be launched on a processor thread.

[0355] As shown in FIG. 42, the reordering circuit 4008 groups tasks generated by shader record pointers 4201A, 4201B, 4201n to create a SIMD batch for shading. The stack IDs or context IDs in the reordered batch can be grouped from various dispatches and various input SIMD lanes. The grouping circuit 4210 can perform the reordering using a content addressable memory (CAM) structure 4201 that includes multiple entries with each entry identified by a tag 4201. As previously mentioned, the tag 4201 can be a corresponding shader record pointer 4201A, 4201B, 4201n. The CAM structure 4201 can store a limited number of tags (e.g., 32, 64, 128, etc.) associated with an incomplete SIMD batch that corresponds to a shader record pointer.

[0356] For incoming generate commands, each SIMD lane has a corresponding stack ID (represented as 16 context IDs 0-15 in each CAM entry) and shader record pointer 4201A-B, ...n (which acts as a tag value). Grouping circuit 4210 may compare the shader record pointer of each lane to tags 4201 in CAM structure 4201 to find a matching batch. If a matching batch is found, the stack ID / context ID may be added to the batch. If not, a new entry with a new shader record pointer tag may be created and the old entry with the incomplete batch may be deleted.

[0357] A running shader can deallocate its call stack when it becomes empty by sending a deallocate message to the message unit, which relays the deallocate message to the scheduler, which returns the stack ID / context ID of the active SIMD lane to the free pool.

[0358] A hybrid approach to ray traversal operations is presented, using a combination of fixed-function ray traversal and software ray traversal, thus providing the flexibility of software traversal while maintaining the efficiency of fixed-function traversal. Figure 43 shows an acceleration structure that may be used for hybrid traversal. This is a two-level tree with a single top-level BVH 4300 and multiple bottom-level BVHs 4301 and 4302. Graphical elements are shown on the right, showing an inner traversal path 4303, an outer traversal path 4304, a traversal node 4305, a leaf node with a triangle 4306, and a leaf node with a custom primitive 4307.

[0359] A leaf node with a triangle 4306 in the top-level BVH 4300 can reference a triangle, an intersection shader record for a custom primitive, or a traversal shader record. A leaf node with a triangle 4306 in a bottom-level BVH 4301-4302 can only reference triangle and intersection shader records for custom primitives. The type of reference is encoded in the leaf node 4306. An internal traversal 4303 refers to a traversal within each BVH 4300-4302. Internal traversal operations include computing ray-BVH intersections, while traversals 4300-4302 that cross the BVH structure are known as external traversals. Internal traversal operations can be implemented efficiently in fixed-function hardware, while external traversal operations can be performed with acceptable performance in programmable shaders. Thus, internal traversal operations may be performed using fixed function circuitry 4010, and external traversal operations may be performed using shader execution circuitry 4000, which includes a SIMD / SIMT core / EU 4001 for executing programmable shaders.

[0360] Note that for simplicity, the SIMD / SIMT core / EU 4001 may be referred to herein simply as a "core," "SIMD core," "EU," or "SIMD processor." Similarly, the ray-BVH traversal / intersection circuit 4005 may be referred to simply as a "traversal unit," "traversal / intersection unit," or "traversal / intersection circuit." When alternative terminology is used, the particular names used to designate the respective circuits / logic do not change the underlying function that the circuits / logic perform, as described herein.

[0361] Additionally, although shown as a single component in FIG. 40 for purposes of illustration, the traversal / intersection unit 4005 may include a separate traversal unit and a separate intersection unit, each of which may be implemented with the circuitry and / or logic described herein.

[0362] When a ray intersects a traversal node during an inner traversal, a traversal shader may be generated. The reordering circuit 4008 may group these shaders by shader record pointers 4201A-B, n to create a SIMD batch that is launched by the scheduler 4007 for SIMD execution on the graphics SIMD core / EU 4001. The traversal shader may modify the traversal in several ways, allowing for a wide range of applications. For example, the traversal shader may select a BVH at a coarser level of detail (LOD) or transform the ray to allow for rigid body transformations. The traversal shader may then generate an inner traversal of the selected BVH.

[0363] Inner traversals compute ray-BVH intersections by traversing the BVH and computing the intersection of the ray box and the ray triangle. Inner traversals are generated in the same way as shaders, by sending messages to a message circuit 4004 which relays the corresponding generation messages to a ray-BVH intersection circuit 4005 which computes the ray-BVH intersections.

[0364] The stack for the internal traversal may be stored locally in the fixed function circuitry 4010 (e.g., in the L1 cache 4006). When the ray intersects with a leaf node corresponding to a traversal or intersection shader, the internal traversal may terminate and the internal stack may be truncated. The truncated stack, along with a pointer to the ray and the BVH, may be written to memory at a location specified by the calling shader, and then the corresponding traversal or intersection shader may be generated. If the ray intersects with any triangle during the internal traversal, the corresponding hit information may be provided as an input argument to these shaders, as shown in the code below. These generated shaders may be grouped by the reordering circuitry 4008 to create a SIMD batch for execution. struct HitInfo { float barycentrics[2]; float tmax; boolinnerTravComplete; uint primID; uintgeomID; ShaderRecord*leafShaderRecord; }

[0365] Truncating the internal traversal stack reduces memory spill costs. In the technique described in Restart Trail for Stackless BVH Traversal, High Performance Graphics (2010), pp. 107-111, for truncating the stack to a small number of entries at the top of the stack, a 42-bit restart trail and a 6-bit depth value may be applied. The restart trail indicates branches already taken in the BVH, and the depth value indicates the depth of the traversal corresponding to the last stack entry. This is enough information to resume the internal traversal at a later time.

[0366] The inner traversal is complete when the inner stack is empty and there are no more BVH nodes to test. In this case, if the outer stack is not empty, an outer stack handler is spawned which pops the top of the outer stack and resumes the traversal.

[0367] The outer traversal can execute a main traversal state machine and can be implemented in program code executed by the shader execution circuitry 4000. An inner traversal query can be generated under the following conditions: (1) when a new ray is generated by a hit shader or a primary shader, (2) when a traversal shader selects a BVH for traversal, and (3) when an outer stack handler resumes inner traversal for a BVH.

[0368] As shown in Figure 44, before the inner traversal is generated, space is allocated for the fixed function circuit 4010 on the call stack 4405 to store a truncated inner stack 4410. The offsets 4403-4404 to the top of the call stack and the inner stack are maintained in a traversal state 4400 that is also stored in memory 2511. The traversal state 4400 also includes hit information for rays in world space 4401 and object space 4402, as well as the nearest intersecting primitives.

[0369] The traversal shaders, intersection shaders, and outer stack handlers are all generated by the ray-BVH intersection circuit 4005. The traversal shaders are allocated on the call stack 4405 before starting a new inner traversal for the second level BVH. The outer stack handlers are the shaders responsible for updating the hit information and resuming any pending inner traversal tasks. The outer stack handlers are also responsible for generating hit or miss shaders when the traversal is complete. If there are no pending inner traversal queries to generate, the traversal is completed. Once the traversal is complete and an intersection is found, a hit shader is generated, otherwise a miss shader is generated.

[0370] Although the hybrid traversal scheme described above uses a two-level BVH hierarchy, any number of BVH levels may be implemented with corresponding changes to the implementation of outer traversal.

[0371] Additionally, although a fixed function circuit 4010 for performing ray-BVH intersection is described above, other system components may also be implemented in the fixed function circuit. For example, the external stack handler described above may be an internal (user invisible) shader that may potentially be implemented in the fixed function BVH traversal / intersection circuit 4005. This implementation may be used to reduce the number of dispatched shader stages and round trips between the fixed function intersection hardware 4005 and the processor.

[0372] The examples described herein enable programmable shading and ray traversal control using user-defined functions that can run with greater SIMD efficiency on existing and future GPU processors. Programmable control of ray traversal enables several key features, such as procedural instancing, probabilistic level-of-detail selection, custom primitive intersections, and deferred BVH updates.

[0373] A programmable multiple instruction multiple data (MIMD) ray tracing architecture is also provided that supports speculative execution of hit and intersection shaders. Specifically, the architecture focuses on reducing the scheduling and communication overhead between the programmable SIMD / SIMT core / execution units 4001 described above with respect to FIG. 40 and the fixed-function MIMD traversal / intersection units 4005 in a hybrid ray tracing architecture. The multiple speculative execution schemes of hit and intersection shaders described below can be dispatched in a single batch from the traversal hardware, avoiding multiple traversal and shading round trips. Dedicated circuitry for implementing these techniques may be used.

[0374] Embodiments of the present invention are particularly beneficial in use cases where execution of multiple hit or intersection shaders is desired from a ray traversal query that imposes significant overhead if implemented without dedicated hardware support. These include, but are not limited to, nearest k hit queries (which invoke a hit shader for the k nearest intersections) and multiple programmable intersection shaders.

[0375] The techniques described herein may be implemented as extensions to the architecture shown in Figure 40 (and described with respect to Figures 40-44). Specifically, this embodiment of the invention is built on an architecture with extensions to improve performance for the use cases described above.

[0376] The performance limitation of the hybrid ray tracing traversal architecture is the overhead of launching traversal queries from the execution units and invoking programmable shaders from the ray tracing hardware. When multiple hit or intersection shaders are invoked during the traversal of the same ray, this overhead generates "execution round trips" between the programmable cores 4001 and the traversal / intersection units 4005. This also puts additional pressure on the reordering units 4008, which must extract SIMD / SIMT coherence from the individual shader invocations.

[0377] Several aspects of ray tracing require programmable control that can be expressed in terms of various shader types (i.e., primary, hit, any hit, miss, intersection, traversal, and callable) listed in Table A above. There can be multiple shaders for each type. For example, each material can have a different hit shader. Several of these shader types are defined in the current Microsoft® Ray Tracing API.

[0378] As a brief explanation, recursive ray tracing begins with an API function that instructs the GPU to launch a set of primary shaders capable of generating ray scene intersections (implemented in hardware and / or software) for a primary ray. This may generate other shaders, such as traversal, hit or miss shaders. A shader that generates child shaders can also receive return values ​​from that shader. A callable shader is a generic function that can be generated directly by another shader and can also return values ​​to the calling shader.

[0379] Ray traversal computes ray scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH). Recent research has shown that the efficiency of computing ray scene intersections can be improved by orders of magnitude using techniques suitable for fixed-function hardware, such as low-precision arithmetic, BVH compression, per-ray state machines, dedicated intersection pipelines and custom caches.

[0380] The architecture shown in FIG. 40 comprises a system in which an array of SIMD / SIMT cores / execution units 4001 interact with a fixed-function ray tracing / intersection unit 4005 to perform programmable ray tracing. Programmable shaders are mapped to SIMD / SIMT threads on the execution units / cores 4001 where SIMD / SIMT utilization, execution, and data coherence are critical for optimal performance. Ray queries often break coherence for a variety of reasons, including: Traversal Difference: The duration of BVH traversal is -Very different between rays which prioritizes asynchronous ray processing. · Execution divergence: Rays generated from different lanes of the same SIMD / SIMT thread may invoke different shaders. · Differences in data access: for example rays hitting different surfaces will sample different BVH nodes, primitives and shaders will access different textures. There are many other scenarios where data access differences can occur.

[0381] The SIMD / SIMT core / execution unit 4001 may be a variation of a core / execution unit described herein, including the graphics core(s) 415A-415B, shader core 1355A-N, graphics core 3130, graphics execution unit 608, execution units 852A-B, or any other core / execution unit described herein. The SIMD / SIMT core / execution unit 4001 may be used in place of the graphics core(s) 415A-415B, shader core 1355A-N, graphics core 3130, graphics execution unit 608, execution units 852A-B, or any other core / execution unit described herein. Thus, disclosure of any feature described herein in combination with graphics core(s) 415A-415B, shader cores 1355A-N, graphics core 3130, graphics execution unit 608, execution units 852A-B, or any other core / execution unit also discloses a corresponding combination with, but is not limited to, SIMD / SIMT core / execution unit 4001 of FIG. 40.

[0382] The fixed-function ray tracing / intersection unit 4005 may overcome the first two challenges by processing each ray individually and out of order. However, this splits the SIMD / SIMT groups. The reordering unit 4008 is therefore responsible for forming new coherent SIMD / SIMT groups of shader invocations that are dispatched back to the execution units.

[0383] The advantages of such an architecture compared to pure software-based ray tracing implemented directly in a SIMD / SIMT processor are easily seen. However, there is overhead associated with messaging between the SIMD / SIMT core / execution units 4001 (sometimes referred to herein simply as SIMD / SIMT processors or cores / EUs) and the MIMD traversal / intersection unit 4005. Additionally, the reordering unit 4008 may not extract full SIMD / SIMT utilization from incoherent shader invocations.

[0384] Use cases can be identified where shader invocations may be particularly frequent during traversal. Extensions are described for a hybrid MIMD ray tracing processor to significantly reduce communication overhead between the cores / EUs 4001 and the traversal / intersection unit 4005. This can be particularly beneficial when finding k-nearest intersections and implementing programmable intersection shaders. However, it should be noted that the techniques described herein are not limited to any particular processing scenario.

[0385] Below is an overview of the high level cost of a ray tracing context switch between the Core / EU 4001 and the Fixed Function Traversal / Intersection Unit 4005. Most of the performance overhead is caused by these two context switches every time a shader invocation is required during a single ray traversal.

[0386] Each SIMD / SIMT lane that fires a ray generates a generate message to the traversal / intersection unit 4005 associated with the BVH to be traversed. The data (ray traversal context) is relayed to the traversal / intersection unit 4005 via the generate message and (cached) memory. When the traversal / intersection unit 4005 is ready to allocate a new hardware thread for the generate message, it loads the traversal state and performs the traversal on the BVH. There is also some setup cost that needs to be performed before the first traversal step of the BVH.

[0387] Figure 45 shows the operational flow of a programmable ray tracing pipeline. The shaded elements, including traversal 4502 and intersection 4503, may be implemented in fixed function circuitry, while the remaining elements may be implemented using programmable cores / execution units.

[0388] The primary ray shader 4501 submits work to a traversal circuit at 4502 which traverses the current ray(s) through the BVH (or other acceleration structure). Upon reaching a leaf node, the traversal circuit calls the intersection circuit at 4503, which upon identifying a ray triangle intersection calls any hit shaders at 4504 (which can return a result to the traversal circuit as shown).

[0389] Alternatively, the traversal may terminate before reaching a leaf node and at 4507 the closest hit shader may be called (if a hit is recorded) or at 4506 the miss shader may be called (in the case of a miss).

[0390] An intersection shader may be invoked if the traversal circuitry reaches a custom primitive leaf node, as shown at 4505. The custom primitive may be any non-triangular primitive, such as a polygon or polyhedron (e.g., a tetrahedron, voxel, hexahedron, wedge, pyramid, or other "unstructured" volume). The intersection shader 4505 identifies any intersection between a ray and the custom primitive to any hit shader 4504 that implements any hit processing.

[0391] When the hardware traversal 4502 reaches a programmable stage, the traversal / intersection unit 4005 may generate shader dispatch messages to the associated shaders 4505-4507, corresponding to a single SIMD lane of the execution unit(s) used to execute the shaders. Because dispatches occur in any ray order and diverge in the programs being invoked, the reordering unit 4008 may accumulate multiple dispatch invocations to extract a coherent SIMD batch. The updated traversal state and optional shader arguments may be written to memory 2511 by the traversal / intersection unit 4005.

[0392] For the k-nearest intersection problem, a closest hit shader 4507 is run for the first k intersections. In traditional methods, this means terminating the ray traversal upon finding the closest intersection, invoking the hit shader, and spawning a new ray from the hit shader to find the next closest intersection (because the ray origin is offset, the same intersection will never occur twice). It is easy to see that this implementation requires the generation of k rays for a single ray. Another implementation works with an arbitrary hit shader 4504 that is invoked for every intersection and maintains a global list of closest intersections, using an insertion reordering operation. The main problem with this approach is that there is no upper bound on arbitrary hit shader invocations.

[0393] As mentioned above, the intersection shader 4505 may be invoked on non-triangle (custom) primitives. Depending on the outcome of the intersection test and the traversal state (pending node and primitive intersections), traversal of the same ray may continue after the execution of the intersection shader 4505. Thus, finding the closest hit may require several round trips to the execution units.

[0394] By modifying the traversal hardware and shader scheduling model, we can also focus on reducing SIMD-MIMD context switches for intersection shaders 4505 and hit shaders 4504, 4507. First, the ray traversal circuitry 4005 delays shader invocations by accumulating multiple potential invocations and dispatching them in larger batches. Additionally, certain invocations that are found to be unnecessary can be culled at this stage. Additionally, the shader scheduler 4007 can aggregate multiple shader invocations from the same traversal context into a single SIMD batch, resulting in a single ray generation message. In one exemplary implementation, the traversal hardware 4005 pauses the traversal thread and waits for the results of multiple shader invocations. This mode of operation is referred to herein as "speculative" shader execution, as it allows for the dispatch of multiple shaders, some of which may not be invoked when using sequential invocations.

[0395] FIG. 46A illustrates an example where a traversal operation encounters multiple custom primitives 4650 in a subtree, and FIG. 46B illustrates how to resolve this with three intersection dispatch cycles C1-C3. In particular, the scheduler 4007 may require three cycles to send work to the SIMD processor 4001, and the traversal circuitry 4005 may require three cycles to provide the results to the reordering unit 4008. The traversal state 4601 required by the traversal circuitry 4005 may be stored in a memory, such as a local cache (e.g., an L1 cache and / or an L2 cache). A. Deferred ray tracing shader invocation

[0396] The way in which the hardware traversal state 4601 is managed can also be modified to allow for the accumulation of multiple potential intersections or hit invocations in the list. At a given time during the traversal, each entry in the list can be used to generate a shader invocation. For example, the kth closest intersection can be accumulated on the traversal hardware 4005 and / or in the traversal state 4601 in memory, and a hit shader can be invoked for each element when the traversal is complete. In the case of a hit shader, multiple potential intersections can be accumulated for a subtree in the BVH.

[0397] For the k-nearest use case, the advantage of this approach is that all hit shaders are called from the same traversal thread during a single traversal operation on the traversal circuitry 4005, instead of k-1 round trips and k-1 new ray generation messages to the SIMD core / EU 4001. A potential implementation challenge is that it is not trivial to guarantee the order of execution of hit shaders (in a standard "round trip" approach, the hit shader of the closest intersection is guaranteed to be executed first, etc.). This may be addressed by either synchronization or relaxing the ordering of hit shaders.

[0398] For the intersection shader use case, the traversal circuit 4005 does not know in advance whether a given shader will return a positive intersection test. However, multiple intersection shaders can be speculatively executed, and if at least one shader returns a positive hit result, the hit results are merged into a global neighborhood hit. A particular implementation needs to find an optimal number of delayed intersection tests to reduce the number of dispatch calls while avoiding calling too many redundant intersection shaders. B. Aggregation of shader invocations from the traversal circuit

[0399] When dispatching multiple shaders from the same ray generation on the traversal circuit 4005, branches may be created in the flow of the ray traversal algorithm. This can be problematic for intersection shaders, since the remaining BVH traversal depends on the results of all dispatched intersection tests. This means that synchronous operations are required to wait for the results of the shader invocations, which can be difficult on asynchronous hardware.

[0400] Two points for merging the results of shader invocations can be the SIMD processor 4001 and the traversal circuitry 4005. With respect to the SIMD processor 4001, multiple shaders can use standard programming models to synchronize and aggregate their results. One relatively simple way to do this is to use global atomics and aggregate the results into a shared data structure in memory that can store multiple shader intersection results. The last shader can then resolve the data structure and call back to the traversal circuitry 4005 to continue the traversal.

[0401] A more efficient approach may also be implemented that restricts execution of multiple shader invocations to lanes of the same SIMD thread on the SIMD processor 4001. Intersection tests are then reduced locally using SIMD / SIMT reduce operations (rather than relying on global atomics). This implementation may rely on new circuitry in the reordering unit 4008 to keep small batches of shader invocations in the same SIMD batch.

[0402] Execution of the traversal thread may further be suspended on the traversal circuitry 4005. Using a traditional execution model, when a shader is dispatched during traversal, the traversal thread is terminated and the ray traversal state is saved to memory to allow other ray generation commands to be executed while the execution unit 4001 processes the shader. If the traversal thread is simply suspended, there is no need to store the traversal state and the result of each shader can be waited for individually. This implementation may include circuitry to avoid deadlocks and provide sufficient hardware utilization.

[0403] Figures 47-48 show an example of a delay model for invoking a single shader invocation on a SIMD core / execution unit 4001 with three shaders 4701. Save, all intersection tests are evaluated within the same SIMD / SIMT group. Therefore, the closest intersection can be calculated on the programmable core / execution unit 4001 as well.

[0404] As discussed above, all or part of the aggregation and / or delay of shaders may be performed by the traversal / intersection circuitry 4005 and / or the core / EU scheduler 4007. Figure 47 illustrates how a shader delay / aggregation circuitry 4706 in the scheduler 4007 may delay scheduling of shaders associated with a particular SIMD / SIMT thread / lane until a specified trigger event occurs. Upon detecting the trigger event, the scheduler 4007 dispatches the multiple aggregated shaders in a single SIMD / SIMT batch to the core / EU 4001.

[0405] 48 illustrates how a shader delay / aggregation circuit 4805 in the traversal / intersection circuit 4005 can delay scheduling of shaders associated with a particular SIMD thread / lane until a specified trigger event occurs. Upon detecting the trigger event, the traversal / intersection circuit 4005 sends the aggregated shaders in a single SIMD / SIMT batch to the reordering unit 4008.

[0406] However, it should be noted that the shader delay and aggregation techniques may be implemented in various other components, such as reordering unit 4008, or may be distributed across multiple components. For example, to ensure that shaders for a SIMD thread are efficiently scheduled on core / EU 4001, traversal / intersection circuit 4005 may perform a first set of shader aggregation operations and scheduler 4007 may perform a second set of shader aggregation operations.

[0407] The "trigger event" that causes the aggregated shaders to be dispatched to a core / EU may be a processing event, such as a particular number of accumulated shaders or a minimum latency associated with a particular thread. Alternatively, or in addition, the trigger event may be a temporal event, such as a particular duration from the latency of a first shader or a particular number of processor cycles. Other variables, such as the current workload on the core / EU 4001 and traversal / intersection unit 4005, may also be evaluated by the scheduler 4007 to determine when to dispatch a SIMD / SIMT batch of shaders.

[0408] Different embodiments of the invention may be implemented using different combinations of the above approaches, based on the requirements of the particular system architecture and application used. Ray Tracing Instructions

[0409] The ray tracing instructions described below are included in an instruction set architecture (ISA) supporting the CPU 3199 and / or GPU 3105. When executed by the CPU, single instruction multiple data (SIMD) instructions may utilize vector / packed source and destination registers to perform the described operations and may be decoded and executed by the CPU core. When executed by the GPU 3105, the instructions may be executed by the graphics core 3130. For example, any of the execution units (EUs) 4001 described above may execute the instructions. Alternatively, or in addition, the instructions may be executed by execution circuitry on the ray tracing core 3150 and / or tensor core tensor core 3140.

[0410] Figure 49 illustrates an architecture for executing the ray tracing instructions described below. The illustrated architecture may be integrated into one or more of the cores 3130, 3140, 3150 described above (see, e.g., Figure 31 and associated text), or may be included in a different processor architecture.

[0411] In operation, the instruction fetch unit 4903 fetches ray tracing instructions 4900 from memory 3198 and the decoder 4995 decodes the instructions. In one implementation, the decoder 4995 decodes the instructions to generate executable operations (e.g., micro-operations or UOPs in a microcoded core). Alternatively, some or all of the ray tracing instructions 4900 may be executed without decoding, and thus the decoder 4904 is not required.

[0412] In either implementation, the scheduler / dispatcher 4905 schedules and dispatches instructions (or operations) across a set of functional units (FUs) 4910-4912. The illustrated implementation includes a vector FU 4910 for executing single instruction, multiple data (SIMD) instructions that operate simultaneously on multiple packed data elements stored in vector registers 4915, and a scalar FU 4911 for operating on scalar values ​​stored in one or more scalar registers 4916. An optional ray tracing FU 4912 may operate on packed data values ​​stored in the vector registers 4915 and / or scalar values ​​stored in the scalar registers 4916. In an implementation without a dedicated FU 4912, the vector FU 4910 and, possibly, the scalar FU 4911 may execute ray tracing instructions described below.

[0413] The various FUs 4910-4912 access ray tracing data 4902 (e.g., traversal / intersection data) required to execute the ray tracing instructions 4900 from vector registers 4915, scalar registers 4916, and / or a local cache subsystem 4908 (e.g., an L1 cache). The FUs 4910-4912 may also perform accesses to memory 3198 via load and store operations, and the cache subsystem 4908 may operate independently to cache data locally.

[0414] Ray tracing instructions may be used to improve performance of ray traversal / intersection and BVH builds, but may also be applied to other areas such as high performance computing (HPC) and general purpose GPU (GPGPU) implementations.

[0415] In the following description, the term doubleword may be abbreviated as dw and unsigned byte may be abbreviated as ub. Additionally, the source and destination registers referenced below (e.g., src0, src1, dest, etc.) may refer to vector registers 4915 or, in some cases, a combination of vector registers 4915 and scalar registers 4916. Typically, vector registers 4915 are used when a source or destination value used by an instruction contains packed data elements (e.g., when the source or destination stores N data elements). Other values ​​may use scalar registers 4916 or vector registers 4915. inverse quantization

[0416] An example of a dequantize instruction "dequantizes" a previously quantized value. As an example, in a ray tracing implementation, a particular BVH subtree may be quantized to reduce storage and bandwidth requirements. The dequantize instruction may take the form dequantize dest src0 src1 src2, where source register src0 stores N unsigned bytes, source register src1 stores one unsigned byte, source register src2 stores one floating point value, and destination register dest stores N floating point values. All of these registers may be vector registers 4915. Alternatively, src0 and dest may be vector registers 4915 and src1 and src2 may be scalar registers 4916.

[0417] The following code sequence defines one particular implementation of the dequantize instruction. for(int i=0;i <SIMD_WIDTH){ if(execMask[i]) { dst[i]=src2[i]+ldexp(convert_to_float(src0[i]),src1); } } In this example, ldexp multiplies a double-precision floating-point value by the specified integer power of 2 (i.e., ldexp(x,exp)=x*2 exp In the above code, if the execution mask value associated with the current SIMD data element (execMask[i]) is set to 1, the SIMD data element at position i in src0 is converted to a floating-point value and multiplied by an integer power (2 src1 value ) and this value is added to the corresponding SIMD data element of src2. Selective minimum or maximum

[0418] The selective min or max instruction may perform a min or max operation per lane (i.e., return the minimum or maximum of a set of values) as indicated by the bits of a bit mask. The bit mask may utilize vector registers 4915, scalar registers 4916, or a separate set of mask registers (not shown). The following code sequence defines one particular implementation of the min / max instruction: sel_min_max dest src0 src1 src2, where src0 stores N doublewords, src1 stores N doublewords, src2 stores one doubleword, and the destination register stores N doublewords.

[0419] The following code sequence defines one particular implementation of the selective min / max command: for(int i=0;i <SIMD_WIDTH){ if(execMask[i]) { dst[i]=(1< <i)&src2?min(src0[i],src1[i]):max(src0[i],src1[i]); } } In this example, (1<<i) and the value of src2 (shift 1 to the left by i bits and perform an AND operation with src2) are used to select the minimum value of the i-th data element of src0 and src1 or the maximum value of the i-th data element of src0 and src1. This operation is performed on the i-th data element only if the execution mask value (execMask[i]) associated with the current SIMD data element is set to 1. Shuffle index instruction

[0420] The shuffle index instruction can copy any set of input lanes to the output lanes. When the SIMD width is 32, this instruction can be executed with a lower throughput. The format of this instruction is as follows: shuffle_index dest src0 src1 <optional flag>, where src0 stores N doublewords, src1 stores N unsigned bytes (i.e., index values), and dest stores N doublewords.

[0421] The following code sequence defines one specific implementation of the shuffle index instruction. for(int i = 0; i < SIMD_WIDTH){ uint8_t srcLane = src1.index[i]; if(execMask[i]){ bool invalidLane = srcLane < 0 || srcLane >= SIMD_WIDTH ||!execMask[srcLaneMod]; if(FLAG){ invalidLane |= flag[srcLaneMod]; } if(invalidLane){ dst[i] = src0[i]; } else{ dst[i] = src0[srcLane]; } } }

[0422] In the code above, the index of src1 identifies the current lane. If the i-th value of the execution mask is set to 1, a check is performed to ensure the source lane is within the range of 0 to the SIMD width. If so, a flag is set (srcLaneMod) and the destination data element i is set equal to data element i of src0. If the lane is within range (i.e., valid), the index value from src1 (srcLane0) is used as an index into src0 (dst[i] = src0[srcLane]). Instant Shuffle Up / Dn / XOR Instructions

[0423] The immediate shuffle instruction may shuffle the input data elements / lanes based on the immediate of the instruction. The immediate may specify to shift the input lanes by 1, 2, 4, 8, or 16 positions based on the value of the immediate. Optionally, an additional scalar source register may be specified as a fill value. If the source lane index is invalid, the fill value (if provided) is stored in the destination data element location. If no fill value is specified, the data element locations are all set to zero.

[0424] The flags register may be used as a source mask. If the flag bit for a source lane is set to 1, the source lane may be marked as invalid and the instruction may proceed.

[0425] Below are examples of various implementations of the instantaneous shuffle command. shuffle_ <up dn xor>_<1 / 2 / 4 / 8 / 16>dest src0<optional src1><optional flag> shuffle_ <up dn xor>_<1 / 2 / 4 / 8 / 16>dest src0<optional src1><optional flag> In this implementation, src0 contains N doublewords, src1 contains one doubleword for the fill value (if there is one), and dest contains N doublewords containing the result.

[0426] The following code sequence defines one particular implementation of an immediate shuffle instruction. for(int i=0;i <SIMD_WIDTH){ int8_t srcLane; switch(SHUFFLE_TYPE) { case UP: srcLane=i-SHIFT; case DN: srcLane=i+SHIFT; case XOR: srcLane=i^SHIFT; } if(execMask[i]) { bool invalidLane=srcLane<0||srcLane>=SIMD_WIDTH||!execMask[srcLane]; if(FLAG) { invalidLane |=flag[srcLane]; } if(invalidLane) { if(SRC1) dst[i] = src1; else dst[i]=0; } else { dst[i] = src0[srcLane]; } } }

[0427] Here, the input data elements / lanes are shifted by 1, 2, 4, 8, or 16 positions based on the immediate value. Register src1 is an additional scalar source register used as a fill value to be stored in the destination data element location if the source lane index is invalid. If no fill value is provided and the source lane index is invalid, the destination data element location is set to 0. The flag register (FLAG) is used as a source mask. If the flag bit for a source lane is set to 1, the source lane is marked as invalid and the instruction proceeds as described above. Indirect Shuffle Up / Dn / XOR Instructions

[0428] An indirect shuffle instruction has a source operand (src1) that controls the mapping from the source lane to the destination lane. An indirect shuffle instruction may take the following forms: shuffle_ <up dn xor>dest src0 src1<optional flag> Here, src0 stores N doublewords, src1 stores 1 doubleword, and dest stores N doublewords.

[0429] The following code sequence defines one particular implementation of an immediate shuffle instruction. for(int i=0;i <SIMD_WIDTH){ int8_t srcLane; switch(SHUFFLE_TYPE) { case UP: srcLane=i-src1; case DN: srcLane=i+src1; case XOR: srcLane = i^src1; } if(execMask[i]) { bool invalidLane=srcLane<0||srcLane>=SIMD_WIDTH||!execMask[srcLane]; if(FLAG) { invalidLane |=flag[srcLane]; } if(invalidLane) { dst[i]=0; } else { dst[i] = src0[srcLane]; } } }

[0430] Thus, the indirect shuffle instruction operates similarly to the immediate shuffle instruction described above, except that the mapping from source lanes to destination lanes is controlled by the source register src1 rather than immediate.

[0431] Cross lane min / max instructions may be supported for floating point and integer data types. Cross lane min instructions may take the form lane_mindest src0 and cross lane max instructions may take the form lane_max dest src0, where src0 stores N double words and dest stores 1 double word.

[0432] As an example, the following code sequence defines one particular implementation of a cross lane minimum: dst = src[0]; for(int i=1;i <SIMD_WIDTH){ if(execMask[i]) { dst = min(dst,src[i]); } }In this example, the doubleword value of data element position i in the source register is compared to the data element in the destination register, and the minimum of the two values ​​is copied to the destination register. The cross lane max instructions operate in essentially the same way, the only difference being that the maximum value of the data element in position i and the destination value are selected. Cross lane min / max index instructions

[0433] A cross lane minimum index instruction may take the form lane_min_indexdest src0, and a cross lane maximum index instruction may take the form lane_max_index dest src0, where src0 stores N doublewords and dest stores 1 doubleword.

[0434] As an example, the following code sequence defines one particular implementation of a cross lane minimum index instruction: dst_index=0; tmp=src[0] for(int i=1;i <SIMD_WIDTH){ if(src[i] <tmp&&execMask[i]) { tmp = src[i]; dst_index=i; } } In this example, the destination index is incremented from 0 to the SIMD width across the destination register. If the execution mask bit is set, the data element at position i of the source register is copied to a temporary location (tmp) and the destination index is set to position i of the data element. Cross-lane sorting network instructions

[0435] The cross lane sorting network instruction may sort all N input elements in either ascending (sortnet_min) or descending (sortnet_max) order using N wide (stable) sorting networks. Min / max versions of the instruction may take the form sortnet_min destsrc0 and sortnet_maxdestsrc0, respectively. In one implementation, src0 and dest store N double words. A min / max sort is performed on the N double words of src0, and the ascending elements (for the minimum) or descending elements (for the maximum) are stored in dest in their respective sorted order. An example of a code sequence defining the instruction is as follows: dst=apply_N_wide_sorting_network_min / max(src0). Crosslane sorting network index instructions

[0436] The cross lane sorting network index instruction may sort all N input elements using N wide (stable) sorting networks, but returns a permutation index in either ascending (sortnet_min) or descending (sortnet_max) order. Min / max versions of the instruction may take the form sortnet_min_index destsrc0 and sortnet_max_indexdest src0, where src0 and dest each store N double words. An example of a code sequence defining the instruction is dst=apply_N_wide_sorting_network_min / max_index(src0).

[0437] A method for executing any of the above instructions is illustrated in Figure 50. The method may be implemented in the particular processor architectures discussed above, but is not limited to any particular processor or system architecture.

[0438] At 5001, instructions of a primary graphics thread are executed in a processor core, which may include, for example, any of the cores described above (e.g., graphics core 3130). When ray tracing work arrives in the primary graphics thread determined at 5002, the ray tracing instructions are offloaded to a ray tracing execution circuit, which may be in the form of a functional unit (FU) as described above with respect to FIG. 49, or may be in a dedicated ray tracing core 3150 as described with respect to FIG.

[0439] At 5003, the ray tracing instructions are decoded and fetched from memory, and at 5005, the instructions are decoded into executable operations (e.g., in embodiments requiring a decoder). At 5004, the ray tracing instructions are scheduled and dispatched for execution by the ray tracing circuitry. At 5005, the ray tracing instructions are executed by the ray tracing circuitry. For example, the instructions may be dispatched and executed on the FUs (e.g., the vector FU 4910, the ray tracing FU 4912, etc.) mentioned above and / or the graphics core 3130 or the ray tracing core 3150.

[0440] Upon completion of execution of the ray tracing instructions, the results are stored (e.g., stored in memory 3198) at 5006 and the primary graphics thread is notified at 5007. At 5008, the ray tracing results are processed within the context of the primary thread (e.g., read from memory and integrated into the graphics rendering results).

[0441] In embodiments, the terms "engine" or "module" or "logic" may refer to, be a part of, or include an application specific integrated circuit (ASIC), electronic circuitry, a processor (shared, dedicated, or group) executing one or more software or firmware programs, and / or memory (shared, dedicated, or group), combinatorial logic circuitry, and / or other suitable components that provide the described functionality. In embodiments, the engine, module, or logic may be implemented in firmware, hardware, software, or any combination of firmware, hardware, and software. Apparatus and method for asynchronous ray tracing - Patents.com

[0442] An embodiment of the present invention includes a combination of fixed-function acceleration circuitry and general-purpose processing circuitry for performing ray tracing. For example, certain operations related to ray traversal and intersection testing of bounding volume hierarchies (BVHs) may be performed by the fixed-function acceleration circuitry, while multiple execution circuits execute various forms of ray tracing shaders (e.g., any hit shader, intersection shader, miss shader, etc.). One embodiment includes dual high-bandwidth storage banks including multiple entries for storing rays and corresponding dual stacks for storing BVH nodes. In this embodiment, the traversal circuitry alternates between the dual ray banks and stacks to process rays at each clock cycle. Additionally, one embodiment includes priority selection circuitry / logic that distinguishes between interior nodes, non-interior nodes, and primitives and uses this information to intelligently prioritize processing of BVH nodes and primitives bounded by BVH nodes.

[0443] One particular embodiment uses a short stack to store a limited number of BVH nodes during a traversal operation to reduce the high-speed memory required for traversal. This embodiment includes stack management circuitry / logic for efficiently pushing and popping entries to and from the short stack to ensure that required BVH nodes are available. Additionally, traversal operations are tracked by performing updates to a tracking data structure. When the traversal circuitry / logic is paused, it references the tracking data structure to start the traversal operation at the same location in the BVH where it was interrupted, and tracks the tracking data held in the data structure so that the traversal circuitry / logic can be restarted.

[0444] FIG. 51 illustrates an embodiment including a shader execution circuitry 4000 for executing shader program code and processing associated ray tracing data 4902 (e.g., BVH node data and ray data), a ray tracing acceleration circuitry 5110 for performing traversal and intersection operations, and a memory 3198 for storing program code and associated data processed by the RT acceleration circuitry 5110 and the shader execution circuitry 4000.

[0445] In one embodiment, the shader execution circuitry 4000 includes multiple cores / execution units 4001 that execute shader program code to perform various forms of data parallel operations. For example, in one embodiment, the cores / execution units 4001 can execute a single instruction across multiple lanes, where each instance of the instruction operates on data stored in a different lane. For example, in a SIMT implementation, each instance of the instruction is associated with a different thread. During execution, the L1 cache stores certain ray tracing data (e.g., recently accessed data or frequently accessed data) for efficient access.

[0446] The set of primary rays may be dispatched to a scheduler 4007, which schedules work to shaders executed by the core / EU 4001. The core / EU 4001 may be a ray tracing core 3150, a graphics core 3130, a CPU core 3199, or other type of circuitry capable of executing shader program code. One or more primary ray shaders 5101 process the primary rays and generate additional work to be executed by the ray tracing acceleration circuitry 5110 and / or the core / EU 4001 (e.g., executed by one or more child shaders). The new work generated by the primary ray shader 5101 or other shaders executed by the core / EU 4001 may be distributed to a sorting circuitry 4008, which sorts the rays into groups or bins (e.g., grouping rays with similar characteristics) as described herein. The scheduler 4007 then schedules the new work on the core / EU 4001.

[0447] Other shaders that may be executed include any hit shader 4514 and nearest hit shader 4507, which process hit results (e.g., identify any hits or nearby hits, respectively, for a given ray) as described above. Miss shader 4506 processes ray misses (e.g., when a ray does not intersect with a node / primitive). As described above, various shaders can be referenced using a shader record, which may include one or more pointers, vendor-specific metadata, and global arguments. In one embodiment, the shader record is identified by a shader record identifier (SRI). In one embodiment, each execution instance of a shader is associated with a call stack 5203, which stores arguments passed between parent and child shaders. The call stack 5121 may also store a reference to a continuing function that is executed when the call returns.

[0448] The ray traversal circuitry 5102 traverses each ray through the nodes of the BVH and works down the hierarchy of the BVH (e.g., through parent, child, and leaf nodes) to identify the nodes / primitives traversed by the ray. The ray-BVH intersection circuitry 5103 performs intersection tests of rays, determines hit points on primitives, and generates results in response to hits. The traversal circuitry 5102 and intersection circuitry 5103 may obtain work from one or more call stacks 5121. Within the ray tracing acceleration circuitry 5110, the call stacks 5121 and associated ray tracing data 4902 may be stored in a local ray tracing cache (RTC) 5107 or other local storage device for efficient access by the traversal circuitry 5102 and intersection circuitry 5103. One particular embodiment described below includes a high-bandwidth ray bank (see, e.g., FIG. 52A).

[0449] The ray tracing acceleration circuit 5110 may be a variation of the various traversal / intersection circuits described herein, including the ray-BVH traversal / intersection circuit 4005, the traversal circuit 4502 and the intersection circuit 4503, and the ray tracing core 3150. The ray tracing acceleration circuit 5110 may be used in place of the ray-BVH traversal / intersection circuit 4005, the traversal circuit 4502 and the intersection circuit 4503, and the ray tracing core 3150 or any other circuit / logic for processing and / or performing traversal / intersection of the BVH stack. Thus, the disclosure of any feature in combination with the ray-BVH traversal / intersection circuit 4005, the traversal circuit 4502 and the intersection circuit 4503, and the ray tracing core 3150 described herein also discloses, but is not limited to, the corresponding combination with the ray tracing acceleration circuit 5110.

[0450] Referring to FIG. 52A, one embodiment of the ray traversal circuit 5102 includes first and second ray storage banks 5201 and 5202, respectively, each bank including multiple entries for storing a corresponding number of incident rays 5206 loaded from memory. The corresponding first and second stacks 5203 and 5204 each include selected BVH node data 5290-5291 read from memory and stored locally for processing. As described herein, in one embodiment, the stacks 5203-5204 are "short" stacks including a limited number of entries (e.g., six entries in one embodiment) for storing BVH node data. Although shown separately from the ray banks 5201-5202, the stacks 5203-5204 may also be maintained within the corresponding ray banks 5201-5202. Alternatively, the stacks 5203-5204 may be stored in separate local memories or caches.

[0451] One embodiment of the traversal processing circuitry 5210 alternates (e.g., in a ping-pong fashion) between the two banks 5201-5202 and the stacks 5203-5204 when selecting the next ray and node to process. For example, the traversal processing circuitry 5210 may select a new ray / BVH node from an alternate ray bank / stack at each clock cycle, thereby ensuring highly efficient operation. However, it should be noted that this particular arrangement is not required to adhere to the principles underlying the present invention.

[0452] In one embodiment, the ray allocator 5205 balances the input of incident rays 5206 to the first and second memory banks 5201-5202, respectively, based on the current relative values ​​of a set of bank allocation counters 5220. In one embodiment, the bank allocation counters 5220 maintain a count of the number of untraversed rays in each of the first and second memory banks 5201-5202. For example, the first bank allocation counter may be incremented when the ray allocator 5205 adds a new ray to the first bank 5201, and decremented when a ray is processed from the first bank 5201. Similarly, the second bank allocation counter may be incremented when the ray allocator 5205 adds a new ray to the second bank 5201, and decremented when a ray is processed from the second bank 5201.

[0453] In one embodiment, the ray allocator 5205 allocates the current ray to the bank associated with the smaller counter value. If the two counters are equal, the ray allocator 5205 may select either bank or may select a different bank than the one selected the last time the counters were equal. In one embodiment, each ray is stored in one entry in one of the banks 5201-5202, with each bank containing 32 entries for storing up to 32 rays. However, the principles underlying the invention are not limited to these details.

[0454] FIG. 52B illustrates four processes 5251-5254 that execute in one embodiment to manage ray storage banks 5201-5202 and stacks 5203-5204. In one embodiment, the four processes 5251-5254 are different implementations or configurations of a common set of program code (sometimes referred to herein as "TraceRay"). An initial process 5251 may execute to read a ray 5261 and perform a new top-down traversal of the BVH, starting from the root node. The Alloc function modifies control bits and initiates a corresponding read request to the ray tracing stack. Specifically, to allocate a new entry, Alloc sets the valid (VLD) bit and resets the invalid ready (Evict_Rdy) bit. In the bank entry for the ray, the data present (DP) bit and the dirty bit are reset. The DP bit of the corresponding stack entry is set. For the corresponding Hitinfo, the DP bit is set and the dirty bit is reset. The DP bit associated with the node data and the DP bit in the Shader Record Identifier (SRI) are reset.

[0455] An instance process 5252 performs a traversal within one of the nodes of the BVH (other than the root node) and reads the ray and the prior commit hit 5262. In one embodiment, when one of the hit shaders identifies a hit between a ray and a primitive, a commit process 5253 executes to commit the result and reads the ray, the potential hit, and the stack 5263. Alternatively, a continue process 5254 executes to continue traversing the ray and reads the ray, the commit hit, and the stack 5264.

[0456] In various situations, the traversal circuitry 5002 must pause the traversal operation and save the current ray and associated BVH nodes, such as when a shader is required to perform a set of operations. For example, when a non-opaque object is hit, or when a procedural texture is hit, the traversal circuitry 5002 saves the stacks 5203-5204 to memory and executes the necessary shaders. When the shaders have completed processing the hit (or other data), the traversal circuitry 5002 restores the state of the ray banks 5201-5202 and stacks 5203-5204 from memory.

[0457] In one embodiment, the traversal / stack tracker 5248 continuously monitors the traversal and stack operations and stores restart data in the tracking array 5249. For example, if the traversal circuit 5002 has already traversed nodes N, N0, N1, N2, and N00 and produced results, the traversal / stack tracker 5248 updates the tracking array to indicate that traversal of these nodes is complete and / or to indicate the next node to be processed from the stack. When the traversal circuit 5002 is restarted, it may read the restart data from the tracking array 5249 and resume the traversal without re-traversing any of the BVH nodes (and without wasting cycles), and thus at the correct stage. The restart data stored in the tracking array 5249 may also be referred to as the "restart trail" or "RST".

[0458] As shown in FIG. 52B, the various TraceRay processes 5251-5254 manage allocations to and from ray storage banks 5201-5202 through one or more functions. As shown in the initial process 5251, the Alloc function sets the valid bit (VLD) in the storage bank entry (indicating that the entry contains a valid ray) and resets the ready to delete flag (Rst) (indicating that the ray data should not be deleted). The Ray function stores the ray in the selected entry and resets the data present (DP) bit (indicating that ray data is stored in the entry) and the dirty bit (indicating that the data has not been modified). Upon reading a ray from a storage bank, the stack function sets the DP bit and retrieves the associated BVH node from the stack (e.g., the root node in the case of the initial process 5251, or another node in the case of the instance process 5252). The HitInfo function resets the dirty bit and sets the DP bit for the initial process 5251 or resets the DP bit for all other functions. In one embodiment, Hitinfo generates data reflecting a ray hit. The Node function resets the DP bit and the SRI (Shader Record Identifier) ​​DP, which is the DP of the shader record identifier. One embodiment performs a Kernel Start Pointer (KSP) lookup to ensure that the KSP is not equal to zero. If so, different processing is implemented for non-opaque quads.

[0459] In one embodiment, when a ray entry is allocated in one of the storage banks 5201-5202, a fetch is performed to obtain the node data (and potentially other data) from a stack associated with the ray. In one embodiment, a stack is maintained for each ray that contains a working set of data for the current node that the ray traverses.

[0460] When moving to the next level in the BVH (e.g., when a ray is determined to intersect with a parent node), the child nodes are reordered and pushed onto the stack 5203-5204. The child nodes are popped off the stack in order and processed individually to identify the child nodes that the ray traversed (the traversal "hits"). In one embodiment, the stack is stored in memory or a local cache / storage whenever there is a handoff between the RT acceleration circuitry 5110 and the shaders 4504, 4506, 4507, 5101, 5105.

[0461] When a leaf node containing a quad or triangle (or other primitive type) is identified by the traversal circuit 5102, the traversal circuit 5102 passes this information to the intersection circuit 5103, which performs an intersection test with the quad or triangle, respectively. If the primitive is not a quad or triangle, in one implementation, the traversal circuit terminates the traversal and returns control to the nearest hit shader 4507 (if a hit is found) or miss shader 4506 (if a hit is not found). In implementations in which the intersection circuit 5103 is designed to perform intersections for various primitives (e.g., lines, arcs, circles, etc.) in addition to quads and triangles, the traversal circuit 5102 forwards leaf nodes for these primitives to the intersection circuit 5103.

[0462] In one embodiment, when a hardware or software component generates a read request to memory 3198 or a cache, a 16-bit tag is used to provide information about the data type and the requestor. For example, a 2-bit code may specify whether the request is for a ray, stack data, hit data, node data from the BVH, or other type of data. Once the ray, stack, and Hitinfo are returned from memory, the ray traverses one or more BVH nodes and intersection testing is performed as described above.

[0463] One or more stacks 5203-5204 and rays 5206 are loaded from memory at various stages of processing. For example, the initial process 5251 and / or the instance process 5252 may request to load a new BVH for traversal. In these situations, the stacks 5203-5204 may be initialized to the top node (or "root" node) of the BVH. In the case of a ray continuation 5254 in the BVH, the stacks 5203-5204 may be loaded from memory and unrolled. Once the stacks 5203-5204 are prepared, the node data is fetched from the stacks (an operation sometimes referred to below as Proc_Node_Fetch).

[0464] In one embodiment, node data is fetched by initiating parallel requests to two non-internal (NI) nodes and two internal nodes. Figure 53 illustrates one such embodiment in which NI node priority selection logic (PRISEL) 5311 requests a dual NI node, a first NI node 5301 from bank 0 and a second NI node 5302 from bank 1. At the same time, internal node PRISEL logic 5312 requests a dual internal node, a first node 5303 from bank 0 and a second node 5304 from bank 1.

[0465] In one embodiment, the NI node priority selection logic (PRISEL) 5311 prioritizes one of the first NI node 5301 and the second NI node 5302 and stores the prioritized results in a ray tracing cache (RTC). Similarly, the internal node PRISEL logic 5312 requests dual internal nodes and selects prioritized results from the first internal node 5303 and the second internal node 5304.

[0466] Each instance of priority selection logic 5311-5312 prioritizes one of the non-internal BVH nodes 5301-5302 and one of the internal BVH nodes 5303-5304 from different banks, if possible. In one embodiment, only one request is selected from each bank (e.g., one of requests 5302 and 5304, and one of requests 5301 and 5303). The initiation of these requests may also reset the stack data present (DP) bit, as shown, so that this entry is not retrieved in response to a node fetch operation. In one embodiment, for an instance fetch operation, the data present (DP) bit for a ray is reset when the instance request is sent and is eventually set when the ray is transformed after the node fetch. Apparatus and method for low delay sorting operations - Patents.com

[0467] As discussed above, data reordering is used in many graphics pipeline stages to improve efficiency. For example, graphics primitives such as triangles and quads may be reordered based on relative depth to cull hidden primitives (e.g., those obscured by other primitives in the current view). As discussed above with respect to Figures 31, 40, 45, and 51, in a ray tracing system, the reordering circuitry / logic 4008 reorders child nodes of a bounding volume hierarchy (BVH) based on the relative distance of the child nodes from the ray origin (or other specified set of coordinates). Rays may also be reordered to improve efficiency. For example, in some implementations, rays are reordered and / or grouped based on similarity (e.g., based on coordinates, bidirectional reflectance distribution function (BRDF), etc.) so that rays with similar characteristics can be processed together. Thus, although the embodiments of the invention described below focus on reordering child nodes of a BVH, the principles underlying the invention are not limited to this particular implementation.

[0468] In one embodiment, reordering the set of child BVH nodes is accomplished using a series of comparison operations. In one particular implementation, a "greater than or equal to" ("GTE" or "GEQ") comparison operation is used, although other comparison operations may also be used (e.g., less than, less than or equal, etc.). These operations may be performed in a systolic network with or without floating-point arithmetic.

[0469] Given N numbers to be sorted, in one embodiment of the present invention, the fewest levels of logic are used to determine the order of sorting. Figure 54 shows one embodiment of sorting circuit / logic 5408 in which comparison circuit 5402 compares each number in a set of N numbers to every other number in the set and arranges the results in an N x N comparison result matrix 5420. To perform all comparisons in parallel, one implementation of comparison circuit 5402 includes N*(N-1) / 2 comparators configured to perform simultaneous comparisons of input values, which may be floating point, integer, or any other data type.

[0470] FIG. 55 illustrates a comparison result matrix 5420 that stores the results of comparisons between four numbers, A, B, C, and D. In one embodiment, each row of the comparison result matrix 5420 is associated with a different number in the set and includes one bit for each comparison with another number in the set. For example, matrix element AgteB is set to value 1 if A is greater than or equal to B, and AgteB is set to 1 if A is less than or equal to B. Other bit values ​​are similarly set based on the results of the corresponding comparisons. The comparison results are stored in the comparison result matrix 5420, as shown, with the diagonal columns set to 0 and the bottom left of the diagonal column mirroring the top right. Thus, using four input values ​​(A-D), a 4×4 comparison result matrix 5420 is generated, but only six comparison operations are required (i.e., AgteB, AgteC, AgteD, BgteC, BgteD, and CgteD from the top right and vice versa at the bottom left).

[0471] Returning to FIG. 54, a set of adders 5430 sums each row of the matrix in parallel. The sums are guaranteed to be unique for each row and range from 0 to (N-1). The ordering circuit / logic 5440 then generates an index onto the sums to return a sorted order of the child BVH nodes 5450. For example, if the sum of row 0 associated with number A is 0, then A is the smallest number (e.g., representing the smallest distance in one embodiment), but if the sum of row 0 is 3, then A is the largest number (representing the largest distance). The ordering circuit / logic 5440 then orders the associated child BVH nodes associated with the remaining numbers B-D based on the sum values ​​associated with the child BVH nodes.

[0472] The structure of the comparison result matrix 5420 ensures that if two numbers are the same, if either number is treated as greater than or equal to any number that follows it, the latter will not be treated as greater than or equal to the former in subsequent rows of the matrix. This arrangement ensures stable sorting. Furthermore, the above approach does not increase the level of logic in the comparison and matrix generation operations, no matter how many input numbers are used.

[0473] The sorting circuit / logic 5408 may be the sorting circuit / logic 4008 described above with additional sorting functionality as described herein. The comparator 5410, adder 5430, and ordering circuit / logic 5440 may be implemented in program code executed by the core / EU 4001 described above, which may be the ray tracing core 3150, the graphics core 3130, the CPU core 3199, or other type of circuitry capable of executing shader program code. In one embodiment, the comparator 5410 comprises a systolic-like network or other type of data parallel processing circuitry including multiple functional units (FUs) performing parallel operations. For example, the FUs may perform all the comparison operations necessary to generate the comparison result matrix 5420 in parallel (e.g., each FU performs a comparison of a pair of numbers). Similarly, the adder 5430 may be implemented with another set of FUs (or the same set) that add the values ​​of each row in parallel. Alternatively, or in addition, one or more of the comparator 5410, the adder 5430, and the ordering circuit / logic 5440 are implemented as fixed function circuitry or via a combination of fixed function circuitry and FUs executing program code.

[0474] A method according to one embodiment of the present invention is illustrated in Figure 56. The method may be implemented within the context of the processor and system architectures described above, but is not limited to any particular system architecture.

[0475] At 5601, N input values ​​are sent for sorting. As described above, the N input values ​​may be associated with various types of data structures, such as BVH nodes (e.g., child nodes with the same parent node), rays, primitives, etc.

[0476] At 5602, each input value is compared to every other input value to generate N*(N-1) / 2 comparison results. As mentioned above, in one embodiment, the comparisons are performed in parallel by N*(N-1) / 2 comparators.

[0477] At 5603, a result matrix is ​​generated having a row for each input value. Each row of the result matrix includes a number of bits indicating the result of a comparison with the other input value. As described above, the result matrix is ​​arranged in an inverse mirror pattern, with a first region (e.g., top right of FIG. 55) storing bits indicating the results of the N*(N-1) / 2 comparisons, and a second region opposite the first region (e.g., bottom left of FIG. 55) storing bits indicating the inverse of the N*(N-1) / 2 comparison results.

[0478] At 5605, the bits of each row are added to generate N unique result values ​​(one for each row) associated with the N input values.

[0479] At 5606, the N input values ​​and / or any associated data structures (e.g., BVH nodes) are ordered based on the result values. For example, an index to the result values ​​may be generated to return a sorted order of the input values ​​and associated data structures.

[0480] At 5607, the associated data structures and / or input values ​​are stored in sorted order. For example, if the data structures include BVH child nodes and the input values ​​are distance values, the child BVH nodes may be pushed onto the stack in sorted order, with the child BVH node with the smallest distance value at the top of the stack and the child BVH node with the largest distance value at the top of the stack.

[0481] Working Example

[0482] The following are exemplary implementations of different embodiments of the present invention.

[0483] Example 1 the processor comprises an input circuit for receiving a set of N input values ​​to be sorted into a sorted order; a comparison circuit for comparing each input value in parallel with every other input value to generate at least N*(N-1) / 2 comparison result values; a matrix generation circuit and / or logic for generating a result matrix having a row associated with each input value, wherein a plurality of bits in each row include a comparison result value indicative of a result of the comparison with the other input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values ​​and a second region of the result matrix opposite the first region storing a second set of bits including the inverses of the N*(N-1) / 2 comparison result values; a parallel addition circuit for performing parallel addition of the bits in each row to generate N unique result values; and a sorting circuit for indexing the N unique result values ​​to return the sorted order.

[0484] Example 2 The processor of embodiment 1, wherein the comparison circuit comprises N*(N-1) / 2 comparators for performing N*(N-1) / 2 parallel comparisons to generate at least N*(N-1) / 2 comparison result values.

[0485] Example 3 The processor of example 2, wherein the N*(N-1) / 2 comparisons include greater than or equal to comparisons, and each comparison result value includes a bit that is set to 1 if the first input value is greater than or equal to the second input value, and is set to 0 if the first input value is less than or equal to the second input value.

[0486] Example 4 2. The processor of claim 1, wherein each of the N input values ​​includes a distance value associated with N bounding volume hierarchy (BVH) nodes, and a sorting circuit generates a sorted order of the BVH nodes based on the comparison result values.

[0487] Example 5 5. The processor of embodiment 4, further comprising stack management circuitry and / or logic for pushing the N BVH nodes onto the stack in a sorted order.

[0488] Example 6 11. The processor of claim 1, wherein a first region of the result matrix includes an upper right region, a second region of the result matrix includes a lower left region, and the first region and the second region of the result matrix are separated by bit positions of a series of diagonal columns in the matrix connecting the upper left corner of the result matrix and the lower right corner of the result matrix.

[0489] Example 7 11. The processor of claim 1, wherein a first region of the result matrix includes an upper left region, a second region of the result matrix includes a lower right region, and the first region and the second region of the result matrix are separated by a set of bit positions of a diagonal column in the matrix connecting the lower left corner of the result matrix and the upper right corner of the result matrix.

[0490] Example 8 The processor of Example 1, wherein the value of N for a set of N input values ​​is variable up to a threshold, the comparison circuit generates a comparison result value, and the matrix generation circuit generates a result matrix in the same number of processor cycles regardless of the value of N up to the threshold.

[0491] Example 9 The method comprises receiving a set of N input values ​​to be sorted into a sorted order; comparing each input value in parallel with every other input value to generate at least N*(N-1) / 2 comparison result values; generating a result matrix having a row associated with each input value, where a plurality of bits in each row include comparison result values ​​indicative of a result of the comparison with the other input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values ​​and a second region of the result matrix opposite the first region storing a second set of bits including reciprocals of the N*(N-1) / 2 comparison result values; performing parallel addition of the bits in each row to generate N unique result values; and indexing the N unique result values ​​to return the sorted order.

[0492] Example 10 10. The method of example 9, wherein N*(N-1) / 2 parallel comparisons are performed by N*(N-1) / 2 comparators to generate at least N*(N-1) / 2 comparison result values.

[0493] Example 11 11. The method of example 10, wherein the N*(N-1) / 2 comparisons include greater than or equal to comparisons (GTEs), and each comparison result value includes a bit that is set to 1 if the first input value is greater than or equal to the second input value, and is set to 0 if the first input value is less than or equal to the second input value.

[0494] Example 12 10. The method of example 9, wherein each of the N input values ​​includes distance values ​​associated with N bounding volume hierarchy (BVH) nodes, and a sorted order of the BVH nodes is generated based on the comparison result values.

[0495] Example 13 13. The method of example 12, further comprising pushing the N BVH nodes onto a stack in a sorted order.

[0496] Example 14 10. The method of example 9, wherein the first region of the result matrix comprises an upper right region, the second region of the result matrix comprises a lower left region, and the first region and the second region of the result matrix are separated by bit positions of a series of diagonal columns in the matrix connecting the upper left ...

Claims

1. 1. A processor comprising: an input circuit for receiving a set of N input values ​​to be sorted into a sorted order, said set of N input values ​​being obtained from a graphics pipeline stage; a comparison circuit for comparing each input value with every other input value in parallel to generate at least N*(N-1) / 2 comparison result values; a matrix generator circuit and / or logic for generating a result matrix having a row associated with each input value, a plurality of bits in each row including a comparison result value indicative of a result of a comparison with the other input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values, and a second region of the result matrix opposite the first region storing a second set of bits including logical inverses of the N*(N-1) / 2 comparison result values; a parallel summation circuit for performing parallel summation of the plurality of bits in each row to generate N unique result values; and a sorting circuit that indexes the N unique result values ​​and returns the sorted order to the graphics pipeline stages.

2. 2. The processor of claim 1, wherein the comparison circuitry comprises N*(N-1) / 2 comparators for performing N*(N-1) / 2 parallel comparisons to generate at least the N*(N-1) / 2 comparison result values.

3. 3. The processor of claim 2, wherein the N*(N-1) / 2 comparisons include greater than or equal to comparisons, and each comparison result value includes a bit that is set to 1 if a first input value is greater than or equal to a second input value and is set to 0 if the first input value is less than or equal to the second input value.

4. 4. The processor of claim 1, wherein each of the N input values ​​comprises a distance value associated with N bounding volume hierarchy nodes (BVH nodes), and the sorting circuitry generates a sorted order of the BVH nodes based on the comparison result values.

5. A processor, comprising: an input circuit for receiving a set of N input values ​​to be sorted into a sorted order; a comparison circuit for comparing each input value with every other input value in parallel to generate at least N*(N-1) / 2 comparison result values; a matrix generator circuit and / or logic for generating a result matrix having a row associated with each input value, a plurality of bits in each row including a comparison result value indicative of a result of a comparison with the other input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values, and a second region of the result matrix opposite the first region storing a second set of bits including logical inverses of the N*(N-1) / 2 comparison result values; a parallel summation circuit for performing parallel summation of the plurality of bits in each row to generate N unique result values; a sorting circuit that indexes the N unique result values ​​to return the sorted order; A processor, wherein each of the N input values ​​comprises a distance value associated with N bounding volume hierarchy nodes (BVH nodes), and the sorting circuitry generates a sorted order of the BVH nodes based on the comparison result values.

6. The processor of claim 4 or 5, further comprising stack management circuitry and / or logic for pushing the N BVH nodes onto a stack in the sorted order.

7. 2. The processor of claim 1, wherein the first region of the result matrix comprises an upper right region, the second region of the result matrix comprises a lower left region, and the first and second regions of the result matrix are separated by bit positions of a series of diagonal columns in the result matrix connecting an upper left corner of the result matrix and a lower right corner of the result matrix.

8. 2. The processor of claim 1, wherein the first region of the result matrix comprises an upper left region, the second region of the result matrix comprises a lower right region, and the first and second regions of the result matrix are separated by bit positions of a series of diagonal columns in the result matrix connecting a lower left corner of the result matrix and an upper right corner of the result matrix.

9. 9. The processor of claim 1, wherein the value of N for the set of N input values ​​is variable up to a threshold, the comparison circuit generates the comparison result values, and the matrix generation circuit generates the result matrix in the same number of processor cycles regardless of the value of N up to the threshold.

10. A processor-implemented method comprising: receiving a set of N input values ​​to be sorted into a sorted order, said set of N input values ​​being obtained from a graphics pipeline stage; comparing each input value in parallel with every other input value to generate at least N*(N-1) / 2 comparison result values; generating a result matrix having a row associated with each input value, a plurality of bits in each row including a comparison result value indicative of a result of a comparison with the other input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values, and a second region of the result matrix opposite the first region storing a second set of bits including logical inverses of the N*(N-1) / 2 comparison result values; performing parallel addition of the plurality of bits for each row to generate N unique result values; and indexing the N unique result values ​​to return the sorted order to the graphics pipeline stage.

11. 11. The method of claim 10, wherein the N*(N-1) / 2 parallel comparisons are performed by N*(N-1) / 2 comparators to generate at least the N*(N-1) / 2 comparison result values.

12. 12. The method of claim 11, wherein the N*(N-1) / 2 comparisons include greater than or equal to comparisons (GTE), and each comparison result value includes a bit that is set to 1 if a first input value is greater than or equal to a second input value and is set to 0 if the first input value is less than or equal to the second input value.

13. 13. The method of claim 10, wherein each of the N input values ​​comprises a distance value associated with N bounding volume hierarchy nodes (BVH nodes), and a sorted order of the BVH nodes is generated based on the comparison result values.

14. A processor-implemented method comprising: receiving a set of N input values ​​to be sorted into a sorted order; comparing each input value in parallel with every other input value to generate at least N*(N-1) / 2 comparison result values; generating a result matrix having a row associated with each input value, a plurality of bits in each row including a comparison result value indicative of a result of a comparison with the other input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values, and a second region of the result matrix opposite the first region storing a second set of bits including logical inverses of the N*(N-1) / 2 comparison result values; performing parallel addition of the plurality of bits for each row to generate N unique result values; and indexing the N unique result values ​​to return the sorted order; A method, wherein each of the N input values ​​comprises distance values ​​associated with N bounding volume hierarchy nodes (BVH nodes), and a sorted order of the BVH nodes is generated based on the comparison result values.

15. The method of claim 13 or 14, further comprising pushing the N BVH nodes onto a stack in the sorted order.

16. 11. The method of claim 10, wherein the first region of the result matrix comprises an upper right region, the second region of the result matrix comprises a lower left region, and the first and second regions of the result matrix are separated by bit positions of a series of diagonal columns in the result matrix connecting an upper left corner of the result matrix and a lower right corner of the result matrix.

17. 11. The method of claim 10, wherein the first region of the result matrix comprises an upper left region, the second region of the result matrix comprises a lower right region, and the first and second regions of the result matrix are separated by bit positions of a series of diagonal columns in the result matrix connecting the lower left corner of the result matrix and the upper right corner of the result matrix.

18. 18. A method according to any one of claims 10 to 17, wherein the value of N for the set of N input values ​​is variable up to a threshold value, and wherein the comparison result values ​​and the result matrix are generated in the same number of processor cycles regardless of the value of N up to the threshold value.

19. A program, an operation of receiving a set of N input values ​​to be sorted into a sorted order, where the set of N input values ​​are obtained from a graphics pipeline stage; comparing each input value in parallel with every other input value to generate at least N*(N-1) / 2 comparison result values; an operation of generating a result matrix having a row associated with each input value, a plurality of bits in each row including a comparison result value indicative of a result of a comparison with the other input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values, and a second region of the result matrix opposite the first region storing a second set of bits including logical inverses of the N*(N-1) / 2 comparison result values; performing parallel addition of the bits of each row to generate N unique result values; indexing the N unique result values ​​to return the sorted order to the graphics pipeline stages; A program that causes a processor to execute the following:

20. 20. The program of claim 19, wherein the N*(N-1) / 2 parallel comparisons are performed by N*(N-1) / 2 comparators to generate the at least N*(N-1) / 2 comparison result values.

21. 21. The program of claim 20, wherein the N*(N-1) / 2 comparisons include greater than or equal to comparisons (GTE), and each comparison result value includes a bit that is set to 1 if a first input value is greater than or equal to a second input value and is set to 0 if the first input value is less than or equal to the second input value.

22. 22. The program of claim 19, wherein each of the N input values ​​comprises a distance value associated with N bounding volume hierarchy nodes (BVH nodes), and a sorted order of the BVH nodes is generated based on the comparison result values.

23. A program comprising: receiving a set of N input values ​​to be sorted into a sorted order; comparing each input value in parallel with every other input value to generate at least N*(N-1) / 2 comparison result values; an operation of generating a result matrix having a row associated with each input value, a plurality of bits in each row including a comparison result value indicative of a result of a comparison with the other input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values, and a second region of the result matrix opposite the first region storing a second set of bits including logical inverses of the N*(N-1) / 2 comparison result values; performing parallel addition of the bits of each row to generate N unique result values; indexing the N unique result values ​​to return the sorted order; to a processor, each of the N input values ​​includes distance values ​​associated with N bounding volume hierarchy nodes (BVH nodes), and a sorted order of the BVH nodes is generated based on the comparison result values. program.

24. 24. The program of claim 22 or 23, further causing the processor to execute an operation of pushing the N BVH nodes onto a stack in the sorted order.

25. 20. The program of claim 19, wherein the first region of the result matrix comprises an upper right region, the second region of the result matrix comprises a lower left region, and the first and second regions of the result matrix are separated by bit positions of a series of diagonal columns in the result matrix connecting an upper left corner of the result matrix and a lower right corner of the result matrix.

26. 20. The program of claim 19, wherein the first region of the result matrix comprises an upper left region, the second region of the result matrix comprises a lower right region, and the first and second regions of the result matrix are separated by bit positions of a series of diagonal columns in the result matrix connecting a lower left corner of the result matrix and an upper right corner of the result matrix.

27. 27. The program of claim 19, wherein the value of N for a set of N input values ​​is variable up to a threshold, and the comparison result values ​​and the result matrix are generated in the same number of processor cycles regardless of the value of N up to the threshold.

28. 1. An apparatus comprising: means for receiving a set of N input values ​​to be sorted into a sorted order, where the set of N input values ​​are obtained from a graphics pipeline stage; means for comparing, in parallel, each input value with every other input value to generate at least N*(N-1) / 2 comparison result values; means for generating a result matrix having a row associated with each input value, a plurality of bits in each row including a comparison result value indicative of a result of a comparison with another input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values, and a second region of the result matrix opposite the first region storing a second set of bits including logical inverses of the N*(N-1) / 2 comparison result values; means for performing parallel addition of the plurality of bits for each row to generate N unique result values; and means for indexing the N unique result values ​​to return the sorted order to the graphics pipeline stages.

29. An apparatus comprising: means for receiving a set of N input values ​​to be sorted into a sorted order; means for comparing, in parallel, each input value with every other input value to generate at least N*(N-1) / 2 comparison result values; means for generating a result matrix having a row associated with each input value, a plurality of bits in each row including a comparison result value indicative of a result of a comparison with another input value, a first region of the result matrix storing a first set of bits including the N*(N-1) / 2 comparison result values, and a second region of the result matrix opposite the first region storing a second set of bits including logical inverses of the N*(N-1) / 2 comparison result values; means for performing parallel addition of the plurality of bits for each row to generate N unique result values; means for indexing the N unique result values ​​to return the sorted order; An apparatus, wherein each of the N input values ​​comprises distance values ​​associated with N bounding volume hierarchy nodes (BVH nodes), and a sorted order of the BVH nodes is generated based on the comparison result values.

30. A computer readable medium storing a program according to any one of claims 19 to 27.

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