Bendable silicon heterojunction solar cell with high photoelectric conversion efficiency and its manufacturing method

Abstract

To provide a bendable silicon heterojunction solar cell having high photoelectric conversion efficiency and a method for manufacturing the same. The present invention comprises a silicon-based layer 1, on the front side of which a hydrogenated amorphous silicon oxide layer 2, a hydrogenated amorphous silicon layer 3, an n-type hydrogenated nanocrystalline silicon oxide layer 4 and a transparent conductive oxide layer 6 are sequentially deposited, and on the rear side of the silicon-based layer 1, a hydrogenated amorphous silicon oxide layer 2, a hydrogenated amorphous silicon layer 3, a p-type hydrogenated nanocrystalline silicon layer 5 and a transparent conductive oxide layer 6 are sequentially deposited, and a metal electrode 7 is printed on the transparent conductive oxide layer 6.

Description

[Technical field]

[0001] The present invention relates to a bendable silicon heterojunction solar cell having high photoelectric conversion efficiency, and further to a method for manufacturing said silicon heterojunction solar cell. [Background technology]

[0002] Due to the increasing demand for energy and the urgent need for environmentally friendly energy, solar energy has been attracting attention as a renewable energy source. However, conventional crystalline silicon solar cells are limited in their energy conversion efficiency, cost, and inflexibility, which has limited their application fields.

[0003] To improve the efficiency and reduce the cost of solar cells, researchers have begun to look at the potential of crystalline silicon heterojunction solar cells. Such solar cells use crystalline silicon (c-Si) as the base material and introduce amorphous silicon at its surface or interface to form a heterojunction, which improves the light absorption and carrier separation efficiency of the cell.

[0004] Conventional c-Si solar cells account for more than 95% of the solar cell market, and their wafer thickness is usually 150-180μm. This thickness cannot be applied in extreme use environments (satellites, spacecraft, drones, etc.), so there are higher requirements for weight reduction and flexibility of solar cells. At present, making the thickness of c-Si wafers much thinner than typical c-Si solar cells and incorporating the advantages of "thin film solar cells" into c-Si solar cells is a hotspot direction. However, the power conversion efficiency of thin c-Si solar cells (55-130μm) has been maintained within the range of 23.27-24.70% for several decades. Summary of the Invention [Problem to be solved by the invention]

[0005] OBJECT OF THEINVENTION: The object of the present invention is to provide a silicon heterojunction solar cell that is bendable (thickness less than 130 μm) and has high photoelectric conversion efficiency, and another object of the present invention is to provide a method for manufacturing said silicon heterojunction solar cell. [Means for solving the problem]

[0006] Technical solution: The present invention provides a bendable silicon heterojunction solar cell with high photoelectric conversion efficiency, which includes a silicon base layer, on the front side of the silicon base layer, a hydrogenated amorphous silicon oxide layer, a hydrogenated amorphous silicon layer, an n-type hydrogenated nanocrystalline silicon oxide layer and a transparent conductive oxide layer are sequentially deposited; on the rear side of the silicon base layer, a hydrogenated amorphous silicon oxide layer, a hydrogenated amorphous silicon layer, a p-type hydrogenated nanocrystalline silicon layer and a transparent conductive oxide layer are sequentially deposited; and a metal electrode is printed on the transparent conductive oxide layer.

[0007] The metal electrodes silk-printed on the front and back transparent conductive oxide layers of the silicon-based layer are both in the form of gate lines, or the metal electrodes silk-printed on the front transparent conductive oxide layer of the silicon-based layer are in the form of gate lines, and the metal electrodes on the back transparent conductive oxide layer of the silicon-based layer are in the form of full-coverage metal electrodes.

[0008] The silicon base layer is n-type single crystal silicon, has a textured surface, and is less than 130 μm thick.

[0009] The hydrogenated amorphous silicon oxide layer has a thickness of less than 0.5 nm, an oxygen atomic content of 8-12 at.%, and a hydrogen content of 22-30 at.%, while the hydrogenated amorphous silicon layer has a thickness of 4-5 nm and a hydrogen content of 18-25 at.%.

[0010] The n-type hydrogenated nanocrystalline silicon oxygen layer has a thickness of 12-18 nm and a crystalline volume fraction of 40-46%, and the p-type hydrogenated nanocrystalline silicon layer has a thickness of 20-25 nm and a crystalline volume fraction of 60-66%.

[0011] The transparent conductive oxide layer is cerium-doped indium oxide with a thickness of 70 nm, the metal electrode is a silver electrode, and in the case of a double-sided battery, the front and back sides both use a gate line type with a width of 16 to 18 μm, and in the case of a single-sided battery, the front side uses a gate line type, and the back side of the battery uses a full-covered metal electrode, that is, the entire back side is filled with silver paste.

[0012] The method for producing the silicon heterojunction solar cell includes the steps of: (1) thinning and texturing a silicon base layer; (2) forming a passivation layer by sequential plasma enhanced chemical vapor deposition of a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on the silicon base layer, in which the present invention uses a combination of an ultra-thin hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer to effectively reduce the adverse effect of the passivation layer on the cell conductivity, and can effectively protect the integrity and flatness of the passivation layer through process control, thereby having a good passivation effect; (3) using a mixture gas of CO2 and H2 to perform plasma pretreatment on the passivation layer to realize nanocrystal seeding on the shallow surface of the passivation layer (3), where the mixture gas is used to perform plasma pretreatment, so that nanocrystals can be seeded on the surface of the passivation layer and the subsequent doped contact layer can grow vertically, which improves the conductivity of the battery and inhibits the reverse epitaxial growth of the seed layer, ensures the integrity of the passivation layer, and avoids destroying the passivation effect; (4) vertically growing a phosphorus-doped n-type nanocrystalline silicon oxide layer with a crystalline volume fraction of 40-46% on the nanocrystalline seeds of the passivation layer under a high hydrogen-silane gas flow ratio (i.e., converting a certain ratio of amorphous silicon into nanocrystalline silicon), and further increasing the hydrogen-silane gas flow ratio to vertically grow a boron-doped p-type nanocrystalline silicon layer with a crystalline volume fraction of 60-66% on the nanocrystalline seeds of the backside passivation layer; (5) depositing cerium-doped indium oxide as a transparent conductive oxide layer, and contactless laser transfer printing metal electrodes onto the transparent conductive oxide layer.

[0013] In step (2), during the process of successively depositing a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on the silicon base layer, the gas resistance sensor monitors the gas resistance in the working chamber in real time, and a density of 18-19 particles / cm on the surface of the sample table is obtained. 2 A diode is provided (as a voltage sensor for feeding back the impact strength of the plasma on the battery surface), and the resistance sensor transmits the collected gas resistance value and the voltage value of each point on the battery surface detected by the diode to the smart terminal of the system, and the smart terminal controls the opening degree of different gas intake valves to switch gas and adjust the gas flow rate, so that the change value of the battery surface impact voltage is less than ±0.5% of the initial battery surface voltage value. During the gas switching or gas flow rate adjustment process, the gas resistance in the working chamber can be kept constant, thereby realizing low damage to the passivation layer surface and avoiding the destruction of the passivation effect.

[0014] In the specific process of successively depositing the hydrogenated amorphous silicon oxide layer and the hydrogenated amorphous silicon layer, silane (SiH4) and CO2 are used as source gases at 190°C with a CO2:SiH4 gas flow ratio of 0.1-0.2:1 to grow an ultra-thin (<0.5 nm) hydrogenated amorphous silicon oxide layer having a thickness of 2-3 atomic layers that can resist epitaxial growth on both sides (front and back) of the silicon base layer, and when transferring from the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer, CO2 is replaced by H2 and the H2:SiH4 gas flow ratio is adjusted to 18-20:1, thereby making the plasma change voltage <±0.5%, and another layer without epitaxial hydrogenated amorphous silicon is deposited on the hydrogenated amorphous silicon oxide quasi-monolayer. The present invention can realize the sequential deposition of a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on a silicon base layer, i.e., a natural interface transition from the first passivation layer to the second passivation layer can be realized, and the fine amorphous layer can be protected from plasma damage during the entire passivation process, especially the ultra-thin hydrogenated amorphous silicon oxide layer, thereby effectively improving the epitaxial growth prevention ability, and the passivation layer obtained by the method of the present invention has a perfect surface, as shown in FIG. 3, which greatly improves the photoelectric conversion efficiency of the cell of the present invention.

[0015] In step (4), a phosphorus-doped n-type nanocrystalline silicon oxygen layer is vertically grown on the nanocrystalline seeds of the backside passivation layer (hydrogenated amorphous silicon layer) with a H2:SiH4:PH3 gas flow ratio of 720-780:5:0.1 and a CO2:SiH4 gas flow ratio of 0.5±0.2, and the inhalation of CO2 is blocked, and the hydrogen silane gas flow ratio is further increased until the H2:SiH4:B2H6 gas flow ratio is 2500-2900:5:0.1, and a boron-doped p-type nanocrystalline silicon layer is vertically grown on the nanocrystalline seeds of the backside passivation layer. Effect of the Invention

[0016] Beneficial Effects: Compared with the prior art, the present invention has the following significant advantages: The present invention can fabricate silicon heterojunction solar cells with photoelectric conversion efficiencies higher than 26% at thicknesses of 55-130 μm, and obtain photoelectric conversion efficiencies of 26.06%, 26.19%, 26.50%, 26.56% and 26.79% at thicknesses of 57, 74, 84, 106 and 125 μm, respectively; the open circuit voltage of the 57 μm-thick cell reaches 761 mV, which is the highest value among current c-Si solar cells; and the power-to-weight ratio of the 57 μm-thick cell is 1.9 W g -1 , the highest level for c-Si solar cells. The thinner cells also offer a significant improvement in flexibility, allowing the cell's radius of curvature to reach 19.6 mm (57 μm), opening up new possibilities for drones, spacecraft and other applications that require extreme weight and flexibility. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a structural schematic diagram of a double-sided silicon heterojunction solar cell of the present invention. [Diagram 2] FIG. 1 is a structural schematic diagram of a single-sided silicon heterojunction solar cell of the present invention. [Diagram 3] 1 is a high-resolution transmission electron microscope photograph of a cross section of the silicon heterojunction solar cell of Example 1. [Figure 4] (a) is an atomic force micrograph and roughness of a passivation layer obtained by conventional discontinuous plasma-enhanced chemical vapor deposition, and (b) is an atomic force micrograph and roughness of a passivation layer obtained by low-damage continuous plasma-enhanced chemical vapor deposition employed in Example 1. [Diagram 5] 1 shows the relationship between the thickness and main performance of the silicon heterojunction solar cell of the present invention. [Figure 6] 4 shows the anti-potential decay performance and anti-light decay performance of the silicon heterojunction solar cell of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Example 1 As shown in FIG. 1, the bendable silicon heterojunction solar cell with high photoelectric conversion efficiency of the present invention includes a silicon base layer 1, on the front side of which a hydrogenated amorphous silicon oxide layer 2, a hydrogenated amorphous silicon layer 3, an n-type hydrogenated nanocrystalline silicon oxide layer 4 and a transparent conductive oxide layer 6 are sequentially deposited; on the rear side of the silicon base layer 1, a hydrogenated amorphous silicon oxide layer 2, a hydrogenated amorphous silicon layer 3, a p-type hydrogenated nanocrystalline silicon layer 5 and a transparent conductive oxide layer 6 are sequentially deposited; and on the transparent conductive oxide layer 6, a metal electrode 7 is printed; and the metal electrodes 7 printed on the transparent conductive oxide layers 6 on the front and rear sides of the silicon base layer 1 are both in the form of gate lines.

[0019] The silicon base layer 1 is n-type single crystal silicon, the surface of which is textured and has a thickness of 57 μm; the hydrogenated amorphous silicon oxide layer 2 is less than 0.5 nm thick, has an oxygen atomic content of 10 at.%, and has a hydrogen content of 26.3 at.%; the hydrogenated amorphous silicon layer 3 is 4.5 nm thick and has a hydrogen content of 19.2 at.%; the n-type hydrogenated nanocrystalline silicon oxygen layer 4 is 15 nm thick and has a crystalline volume fraction of 43.7%; the p-type hydrogenated nanocrystalline silicon layer 5 is 22 nm thick and has a crystalline volume fraction of 63.4%; the transparent conductive oxide layer 6 is cerium-doped indium oxide and has a thickness of 70 nm; the metal electrode 7 is a silver electrode, and the width of the silver electrode in the form of a gate line is 18 μm.

[0020] The fabrication method of the silicon heterojunction solar cell described above included the following steps.

[0021] (1) The silicon base layer is thinned and textured. Specifically, the silicon wafer is selected as n-type Czochralski c-Si single crystal silicon with a thickness of 150 μm and M6 size (166 × 166 mm ± 0.25), with a (100) orientation and a resistivity of 1 to 3 Ω·cm. The silicon wafer is immersed in a KOH solution with a mass fraction of 10% for about 1200 s isotropic chemical etching to thin the wafer thickness. The silicon wafer is textured in a KOH solution with an additive added to form a square pyramid with an exposed (111) crystal plane of 3 to 9 μm in size on the wafer surface. Then, chemical etching is performed in a HF solution with a mass fraction of 1 to 2% to remove the natural SiO on the wafer surface. x The film was removed and the average thickness of each wafer group was measured by the cup method with an accuracy of ±0.5 μm.

[0022] (2) depositing a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on a silicon-based layer in succession to form a passivation layer; specifically, using a radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) (13.56MHz) system at 190°C, using SiH4 and CO2 as source gases with a CO2:SiH4 gas flow ratio of 0.15:1 to grow an ultra-thin (<0.5nm) hydrogenated amorphous silicon oxide layer with a thickness of 2-3 atomic layers, which can resist epitaxial growth, on both sides (front and back) of the silicon-based layer; when transferring from the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer and depositing, CO2 is switched to H2 and the H2:SiH4 gas flow ratio is adjusted to 19:1, thereby making the plasma change voltage <±0.5%, and depositing another layer without epitaxial hydrogenated amorphous silicon on the hydrogenated amorphous silicon oxide quasi-monolayer; During the process of successively depositing a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on a silicon base layer, the gas resistance sensor monitors the gas resistance in the working chamber in real time and deposits a density of 18-19 particles / cm on the cell surface to detect the impulse voltage on the cell surface. 2A diode (a voltage sensor for feeding back the impact strength (impact voltage) of the battery surface plasma) is provided, and the resistance sensor transmits the collected gas resistance value and the impact voltage value of each point on the battery surface detected by the diode to the smart terminal of the system. The smart terminal switches the gases by controlling the opening of each gas inlet pipe valve and adjusts the inlet flow rate of each gas, so that the change in the battery surface impact voltage is smaller than ±0.5% of the initial battery surface voltage value.

[0023] (3) Using a mixture of CO2 and H2 gas to perform plasma pretreatment on the passivation layer, nanocrystals are seeded on the surface of the passivation layer. Specifically, a doped contact layer is fabricated by a self-restoring nanocrystal seeding and vertical growth induction (NSVGI) method, and a plasma pretreatment of a mixture of CO2 and H2 gas (CO2:H2 flow rate ratio is 1:20, treatment time is 20-50 s) is performed on the surface of the hydrogenated amorphous silicon layer by a very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD) method (40.68 MHz) to seed nanocrystal seeds and maintain the hydrogen content in the passivation layer, thereby maintaining the optimal passivation effect of the passivation layer, and limiting the nanocrystal seeding to the surface of the passivation layer, which can induce the vertical growth of the subsequent doped nanocrystal junction, without destroying the passivation effect of the passivation layer.

[0024] (4) A 15 nm thick phosphorus-doped n-type nanocrystalline silicon oxygen layer (n) was deposited on the nanocrystalline seeds of the passivation layer with a gas flow ratio of H2:SiH4:PH3 of 750:5:0.1 and a gas flow ratio of CO2:SiH4 of 0.5±0.2. + :nc-SiO x A boron-doped p-type nanocrystalline silicon layer (pNc) with a crystal volume fraction of 63.4% and a thickness of 22 nm was grown vertically as an electron collecting layer, with a crystal volume fraction of 43.7%. The optical band gap at this crystallinity was optimal. For the back junction, the inhalation of CO2 was blocked, and the hydrogen-silane gas flow ratio was further increased until the H2:SiH4:B2H6 gas flow ratio was 2700:5:0.1. A boron-doped p-type nanocrystalline silicon layer (pNc) with a crystal volume fraction of 63.4% and a thickness of 22 nm was grown on the nanocrystalline seeds of the back passivation layer. + :nc-Si:H) was grown vertically, and n+ :nc-SiO x :H and p + The nc-Si:H contacts were grown in the same chamber at a substrate temperature of 170 °C, and the fill factor and conversion efficiency of the cells could be improved by optimizing the crystalline volume fraction of the doped contact layer.

[0025] (5) Using a 2.8 wt.% Ce-doped indium oxide (In2O3) target, a 70 nm cerium-doped indium oxide layer was deposited on both sides in a low-damage reactive plasma deposition (RPD) sputtering tool with high-purity argon (Ar) as the sputtering gas at a substrate temperature of 100°C. During the RPD process, the ion bombardment voltage was less than 30 eV to avoid damaging the nanocrystalline junctions and passivation layer. A silver gate line with a line width of 18 μm was transferred and printed by non-contact laser, and the aspect ratio was optimized to be 0.7.

[0026] (6) Using a thermal evaporation device, a 80 nm thick magnesium fluoride (MgF2) layer was coated on the front side of the battery, or a 80 nm thick MgF2 layer was simultaneously coated on both the front and back sides of the battery using a thermal evaporation device. Both of these two methods were usable.

[0027] (7) The current-voltage (JV) curve test was conducted under AM1.5 light spectrum, and the photoelectric conversion efficiency was found to be 26.06%.

[0028] By adjusting only the etching time and not changing other process parameters, the manufacturing process of Example 1 can be used to obtain cells with thicknesses of 74, 84, 106 and 125 μm. JV curve tests were performed under AM1.5 light spectrum for the cells with thicknesses of 74, 84, 106 and 125 μm, and the photoelectric conversion efficiencies were 26.19%, 26.50%, 26.56% and 26.79%, respectively.

[0029] FIG. 3 is a high-resolution transmission electron micrograph of the cross section of the battery, in which it can be observed that there is no epitaxial growth in the passivation layer, and nanocrystals have grown vertically on the doped contact layer; FIG. 4(a) shows that with discontinuous plasma, the passivation layer has many through holes and is highly damaged; FIG. 4(b) shows that with continuous plasma, the passivation layer is completely smooth and has little damage; FIG. 5 shows the performance parameters of batteries with different thicknesses (57-125 μm) produced by the method of the present invention, and it was found that the batteries obtained by the method of the present invention have good conversion efficiency, fill factor, open circuit voltage, and short circuit current.

[0030] FIG. 6 shows batteries of different thicknesses (57 to 125 μm) manufactured by the method of the present invention, all of which had reliable weather resistance.

[0031] Example 2 As shown in FIG. 2, the bendable silicon heterojunction solar cell with high photoelectric conversion efficiency of the present invention includes a silicon base layer 1, on the front side of the silicon base layer 1, a hydrogenated amorphous silicon oxide layer 2, a hydrogenated amorphous silicon layer 3, an n-type hydrogenated nanocrystalline silicon oxide layer 4 and a transparent conductive oxide layer 6 are sequentially deposited; on the rear side of the silicon base layer 1, a hydrogenated amorphous silicon oxide layer 2, a hydrogenated amorphous silicon layer 3, a p-type hydrogenated nanocrystalline silicon layer 5 and a transparent conductive oxide layer 6 are sequentially deposited; a metal electrode 7 is printed on the transparent conductive oxide layer 6, and the metal electrode 7 printed on the transparent conductive oxide layer 6 on the front side of the silicon base layer 1 is in the form of a gate line, and the entire surface of the transparent conductive oxide layer 6 on the rear side of the silicon base layer 1 is covered with the metal electrode.

[0032] The silicon base layer 1 is n-type single crystal silicon, the surface is textured and has a thickness of 57 μm, the hydrogenated amorphous silicon oxide layer 2 is less than 0.5 nm thick, has an oxygen atomic content of 10 at.%, and a hydrogen content of 26.3 at.%, the hydrogenated amorphous silicon layer 3 is 4.5 nm thick and has a hydrogen content of 19.2 at.%, the n-type hydrogenated nanocrystalline silicon oxygen layer 4 is 15 nm thick and has a crystalline volume fraction of 43.7%, the p-type hydrogenated nanocrystalline silicon layer 5 is 22 nm thick and has a crystalline volume fraction of 63.4%, the transparent conductive oxide layer 6 is cerium-doped indium oxide and has a thickness of 70 nm, the metal electrode 7 is a silver electrode, and the width of the silver electrode in the form of a gate line on the front side of the battery is 18 μm, and the back side of the battery is fully coated, i.e. the entire back side is filled with silver paste.

[0033] The fabrication method of the silicon heterojunction solar cell described above included the following steps.

[0034] (1) The silicon base layer is thinned and textured. Specifically, the silicon wafer is selected as n-type Czochralski c-Si single crystal silicon with a thickness of 150 μm and M6 size (166 × 166 mm ± 0.25), with a (100) orientation and a resistivity of 1 to 3 Ω·cm. The silicon wafer is immersed in a KOH solution with a mass fraction of 10% for about 1200 s isotropic chemical etching to thin the wafer thickness. The silicon wafer is textured in a KOH solution with an additive added to form a square pyramid with an exposed (111) crystal plane of 3 to 9 μm in size on the wafer surface. Then, chemical etching is performed in a HF solution with a mass fraction of 1 to 2% to remove the natural SiO on the wafer surface. x The film was removed and the average thickness of each wafer group was measured by the cup method with an accuracy of ±0.5 μm.

[0035] (2) Sequentially depositing a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on a silicon-based layer to form a passivation layer, specifically, using an RF-PECVD (13.56MHz) system at 190°C, using SiH4 and CO2 as source gases with a CO2:SiH4 gas flow ratio of 0.15:1 to grow an ultra-thin (<0.5nm) hydrogenated amorphous silicon oxide layer with a thickness of 2-3 atomic layers that can resist epitaxial growth on both sides (front and back) of the silicon-based layer, and when transferring from the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer and depositing, CO2 is switched to H2 and the H2:SiH4 gas flow ratio is adjusted to 19:1, thereby making the plasma change voltage <±0.5%, and depositing another layer without epitaxial hydrogenated amorphous silicon on the hydrogenated amorphous silicon oxide quasi-monolayer; During the process of successively depositing a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on a silicon base layer, the gas resistance sensor monitors the gas resistance in the working chamber in real time and deposits a density of 18-19 particles / cm on the cell surface to detect the impulse voltage on the cell surface. 2 A diode (a voltage sensor for feeding back the impact strength (impact voltage) of the battery surface plasma) is provided, and the resistance sensor transmits the collected gas resistance value and the impact voltage value of each point on the battery surface detected by the diode to the smart terminal of the system. The smart terminal switches the gases by controlling the opening of each gas inlet pipe valve and adjusts the inlet flow rate of each gas, so that the change in the battery surface impact voltage is smaller than ±0.5% of the initial battery surface voltage value.

[0036] (3) Using a mixture of CO2 and H2 gas, plasma pretreatment is performed on the passivation layer to realize the seeding of nanocrystals on the surface of the passivation layer. Specifically, a doped contact layer is fabricated by the NSVGI method, and the hydrogenated amorphous silicon layer surface is pretreated with a mixture of CO2 and H2 gas (CO2:H2 flow rate ratio is 1:20, and the treatment time is 20-50 s) by the VHF-PECVD method (40.68 MHz), so as to seed nanocrystal seeds and maintain the hydrogen content in the passivation layer, thereby maintaining the optimal passivation effect of the passivation layer, and limiting the seeding of nanocrystals to the surface of the passivation layer, which can induce the vertical growth of the subsequent doped nanocrystal junction, without destroying the passivation effect of the passivation layer.

[0037] (4) A 15 nm thick phosphorus-doped n film was deposited on the nanocrystalline seeds of the passivation layer with a H2:SiH4:PH3 gas flow ratio of 750:5:0.1 and a CO2:SiH4 gas flow ratio of 0.5±0.2. + :nc-SiO x The :H layer was grown vertically as an electron collecting layer, with a crystalline volume fraction of 43.7%. The optical band gap at this crystallinity was optimal. For the back junction, the inhalation of CO2 was blocked, and the hydrogen-silane gas flow ratio was further increased until the H2:SiH4:B2H6 gas flow ratio was 2700:5:0.1. A boron-doped pN with a crystalline volume fraction of 63.4% and a thickness of 22 nm was grown on the nanocrystalline seeds of the back passivation layer. + nc-Si:H is grown vertically and n + :nc-SiO x :H and p + The nc-Si:H contacts were grown in the same chamber at a substrate temperature of 170 °C, and the fill factor and conversion efficiency of the cells could be improved by optimizing the crystalline volume fraction of the doped contact layer.

[0038] (5) Using a 2.8 wt.% Ce-doped In2O3 target, a 70 nm cerium-doped indium oxide layer was deposited on both sides in a low-damage RPD sputtering tool with high-purity Ar as the sputtering gas at a substrate temperature of 100°C. During the RPD process, the ion impact voltage was less than 30 eV to avoid damaging the nanocrystalline junctions and passivation layer. A silver gate line with a line width of 18 μm was transferred and printed by non-contact laser on the front side of the battery with an aspect ratio optimized to 0.7. The entire back side of the battery was filled with silver paste.

[0039] (6) Using a thermal evaporation device to coat a 80 nm thick MgF2 layer on the front side of the battery, or using a thermal evaporation device to simultaneously coat 80 nm thick MgF2 layers on the front and back sides of the battery, both of which could be used.

[0040] (7) A JV curve test was conducted under AM1.5 light spectrum, and the photoelectric conversion efficiency was found to be 26.11%.

Claims

1. A bendable silicon heterojunction solar cell having high photoelectric conversion efficiency, comprising a silicon base layer (1), a hydrogenated amorphous silicon oxide layer (2), a hydrogenated amorphous silicon layer (3), an n-type hydrogenated nanocrystalline silicon oxide layer (4) and a transparent conductive oxide layer (6) are sequentially deposited on the front surface of the silicon base layer (1), a hydrogenated amorphous silicon oxide layer (2), a hydrogenated amorphous silicon layer (3), a p-type hydrogenated nanocrystalline silicon layer (5) and a transparent conductive oxide layer (6) are sequentially deposited on the rear surface of the silicon base layer (1), and a metal electrode (7) is printed on the transparent conductive oxide layer (6); The silicon base layer (1) is n-type single crystal silicon, has a textured surface, and has a thickness of less than 130 μm; The hydrogenated amorphous silicon oxide layer (2) has a thickness of less than 0.5 nm, an oxygen atomic content of 8-12 at. %, and a hydrogen content of 22-30 at. %, and the hydrogenated amorphous silicon layer (3) has a thickness of 4-5 nm and a hydrogen content of 18-25 at. %, The n-type hydrogenated nanocrystalline silicon oxygen layer (4) has a thickness of 12-18 nm and a crystalline volume fraction of 40-46%, and the p-type hydrogenated nanocrystalline silicon layer (5) has a thickness of 20-25 nm and a crystalline volume fraction of 60-66%, The photoelectric conversion efficiency is higher than 26%. A bendable silicon heterojunction solar cell comprising:

2. The bendable silicon heterojunction solar cell according to claim 1, characterized in that the metal electrodes (7) transferred by non-contact laser on the transparent conductive oxide layer (6) on the front and back sides of the silicon base layer (1) are both in the form of gate lines, or the metal electrodes (7) transferred by non-contact laser on the transparent conductive oxide layer (6) on the front side of the silicon base layer (1) are in the form of gate lines, and the metal electrodes on the transparent conductive oxide layer (6) on the back side of the silicon base layer (1) are full-coverage metal electrodes.

3. 2. The bendable silicon heterojunction solar cell of claim 1, characterized in that the transparent conductive oxide layer (6) is cerium doped indium oxide, the metal electrode (7) is a silver electrode, and the width of the silver electrode using the gate line format is 16-18 μm.

4. (1) thinning and texturing a silicon base layer; (2) successively depositing a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on the silicon-based layer to form a composite passivation layer; (3) Carbon dioxide (CO ２ ) and hydrogen gas (H ２ ) performing a plasma pretreatment on the passivation layers on both sides using a gas mixture of 0.1% to 1.0% to achieve nanocrystalline seeding of the shallow surface of the passivation layer; (4) vertically growing a phosphorus-doped n-type nanocrystalline silicon oxide layer with a crystalline volume fraction of 40-46% on the nanocrystalline seeded front passivation layer under a high hydrogen-silane gas flow ratio, and further increasing the hydrogen-silane gas flow ratio to vertically grow a boron-doped p-type nanocrystalline silicon layer with a crystalline volume fraction of 60-66% on the nanocrystalline seeded backside passivation layer; (5) depositing cerium-doped indium oxide as a transparent conductive oxide layer, and contactless laser transfer printing metal electrodes onto the transparent conductive oxide layer.

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