Substrate for semiconductor device

Abstract

To provide a substrate for a semiconductor device capable of inhibiting the wetting spread of solder and other bonding materials even when recesses are formed in the copper plate.SOLUTION: A substrate for a semiconductor device according to the present invention has an insulating plate having first and second surfaces, a first copper plate bonded to the first surface of the insulating plate to form a conductive pattern, and a second copper plate bonded to the second surface of the insulating plate, and a plurality of recesses are formed in at least one of the first and second copper plates, and a diameter D1 of an opening of each recess is smaller than the maximum diameter D2 inside than the opening of the recess.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a substrate for a semiconductor device. [Background technology]

[0002] As a substrate for a semiconductor device used in a power transistor module or the like, a DBOC substrate (Direct Bonding of Copper Substrate) is known, which has a copper plate on the surface of an insulating plate such as a ceramic sintered body. In addition, a recessed portion, for example, as shown in Patent Document 1, can be formed on the periphery of the copper plate. With this, even if thermal stress due to temperature changes in the semiconductor device acts on the insulating plate, the thermal stress generated on the periphery of the copper plate can be alleviated by the multiple recessed portions. As a result, it is possible to prevent cracking of the insulating plate and peeling of the copper plate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 167509 Summary of the Invention [Problem to be solved by the invention]

[0004] However, although forming a recess can alleviate the thermal stress occurring at the periphery of the copper plate as described above, there is a risk that the recess may hinder the wetting and spreading of a bonding material such as solder on the main surface of the copper plate. The present invention has been made to solve the above problem, and aims to provide a substrate for a semiconductor device that can suppress the inhibition of the wetting and spreading of a bonding material such as solder even if a recess is formed in the copper plate. [Means for solving the problem]

[0005] The substrate for a semiconductor device of the present invention comprises an insulating plate having a first surface and a second surface, a first copper plate joined to the first surface of the insulating plate for forming a conductive pattern, and a second copper plate joined to the second surface of the insulating plate, wherein a plurality of recesses are formed in at least one of the first copper plate and the second copper plate, and a diameter D1 of an opening of each of the recesses is smaller than a maximum diameter D2 inside the opening of the recess.

[0006] In the above substrate for a semiconductor device, an edge of the first copper plate or the second copper plate corresponding to an opening edge of the recess can be formed to protrude radially inward from the opening and to have an arc-shaped cross section.

[0007] In the above substrate for a semiconductor device, the edge portion may have a radius of curvature of 2.0 μm or more.

[0008] In the substrate for a semiconductor device, the ratio of the maximum diameter D2 to the diameter D1 can be set to 1.08 or more.

[0009] In the substrate for a semiconductor device, the recessed portion may be formed so as not to reach the insulating plate.

[0010] In the substrate for a semiconductor device, a plurality of the recesses can be formed along the periphery of at least one of the first copper plate and the second copper plate.

[0011] In the substrate for a semiconductor device, a plurality of the recesses can be formed near the center of the first copper plate.

[0012] In the substrate for a semiconductor device, a plurality of the recesses can be formed in both the first copper plate and the second copper plate. Effect of the Invention

[0013] According to the present invention, even if a recess is formed in a copper plate, it is possible to suppress the inhibition of the wetting and spreading of a bonding material such as solder. [Brief description of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view showing one embodiment of a semiconductor device having a substrate for a semiconductor device according to the present invention. [Diagram 2] FIG. 2 is a plan view of a substrate for a semiconductor device. [Diagram 3] FIG. 2 is an enlarged cross-sectional view of a substrate for a semiconductor device. [Figure 4] FIG. 11 is a cross-sectional view showing another example of a recess. [Figure 5A] FIG. 3 is a cross-sectional view of a recess in the first embodiment. [Figure 5B] 4 is an enlarged cross-sectional view of an edge of a recess in Example 1. FIG. [Figure 6A] FIG. 11 is a cross-sectional view of a recess in Example 3. [Figure 6B] FIG. 11 is an enlarged cross-sectional view of an edge of a recess in Example 3. [Figure 7A] FIG. 11 is a cross-sectional view of a recess in Example 4. [Figure 7B] FIG. 11 is an enlarged cross-sectional view of the edge of a recess in Example 4. [Figure 8A] FIG. 13 is a cross-sectional view of a recess in Example 6. [Figure 8B] FIG. 13 is an enlarged cross-sectional view of the edge of a recess in Example 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a substrate for a semiconductor device according to the present invention will now be described with reference to the drawings, in which: Fig. 1 is a cross-sectional view of a semiconductor device having a substrate for a semiconductor device according to this embodiment.

[0016] <1. Overview of semiconductor device> The semiconductor device according to this embodiment is used as a power module in various electronic devices such as automobiles, air conditioners, industrial robots, commercial elevators, household microwave ovens, IH electric rice cookers, power generation (wind power generation, solar power generation, fuel cells, etc.), electric railways, and UPS (uninterruptible power supplies).

[0017] As shown in FIG. 1, the semiconductor device 1 according to this embodiment includes a substrate 2 for a semiconductor device, a first bonding material 5, a second bonding material 5′, a semiconductor chip 6, bonding wires 7, and a heat sink 8. The substrate 2 is a substrate for a semiconductor device.

[0018] The substrate 2 for a semiconductor device is a so-called DBOC substrate (Direct Bonding of Copper Substrate) and comprises a plate-shaped insulating plate 3 which is an insulator, a first copper plate 4 bonded to its first surface (upper surface), and a second copper plate 4' bonded to its second surface (lower surface).

[0019] The insulating plate 3 is made of ceramics having excellent thermal conductivity, such as aluminum oxide, aluminum nitride, silicon nitride, etc. The thickness of the insulating plate 3 is, for example, preferably 0.25 to 0.635 mm, and more preferably 0.25 to 0.38 mm.

[0020] A transmission circuit such as a conductive pattern is formed on the first copper plate 4. On the other hand, the second copper plate 4' is formed in a flat plate shape. The thickness of these copper plates 4, 4' is preferably, for example, 0.1 to 2.0 mm, and more preferably 0.2 to 0.4 mm. If the copper plates 4, 4' are thick, the heat dissipation of the semiconductor device substrate 2 is improved, but on the other hand, the thermal stress increases, which may reduce reliability. Therefore, the thickness of the copper plates 4, 4' is set depending on the application of the semiconductor device 1, the mechanical strength of the insulating plate 3, and the like. In addition, a recess is formed in the second copper plate 4' as described later.

[0021] A semiconductor chip 6 is bonded to the upper surface of the substrate 2 for a semiconductor device, i.e., to a part of the upper surface of the first copper plate 4, via a first bonding material 5. In addition, the semiconductor chip 6 and the first copper plate 4 are connected by bonding wires 7.

[0022] On the other hand, a heat sink 8 is bonded to the lower surface of the substrate 2 for a semiconductor device, i.e., the lower surface of the second copper plate 4', via a second bonding material 5'. The heat sink 8 is a known material and can be made of a metal such as copper.

[0023] The bonding materials 5, 5' can be formed of solder, silver solder, etc. When the bonding materials 5, 5' are solder, for example, lead-free solder containing at least one of the following alloys as a main component: an alloy of tin-silver-copper, an alloy of tin-zinc-bismuth, an alloy of tin-copper, and an alloy of tin-silver-indium-bismuth can be used.

[0024] <2. Recesses formed on the second copper plate> As described above, the second copper plate 4' has recesses formed therein. This will be described in detail. FIG. 2 is a plan view of the substrate for a semiconductor device as viewed from the second copper plate, and FIG. 3 is an enlarged cross-sectional view of FIG. 2. As shown in FIGS. 2 and 3, the second copper plate 4' has a plurality of recesses 9 formed along the periphery of the second copper plate 4' at predetermined intervals. Each recess 9 is formed in a hemispherical shape, and the planar shape of the opening is formed in a circular shape. The above-mentioned second bonding material 5' flows into each recess 9.

[0025] Each recess 9 is circular in plan view, and Figure 3 is a cross-sectional view in the thickness direction of the second copper plate 4', passing through the center of the circle. The diameter of the opening of each recess 9, which is circular in plan view, is represented by D1. Each recess 9 is a cavity inside the second copper plate 4' that is close to a sphere. Therefore, the cross-sectional shape of each recess 9 is a shape in which a part of a circle has been cut out, as shown in Figure 3. Of the dimensions of each recess 9 in the direction perpendicular to the thickness direction of the second copper plate 4', the maximum dimension is represented by D2. Furthermore, of the dimensions of each recess 9 in the thickness direction of the second copper plate 4', the maximum dimension is represented by D3. D3 is the depth dimension of each recess 9.

[0026] The diameter D1 of the opening of each recess 9 is smaller than the maximum diameter D2 inside the opening. Therefore, an edge 91 of the second copper plate 4' corresponding to the opening edge of each recess 9 protrudes radially inward from the opening. In this embodiment, the tip of this edge 91 is formed to have an arc-shaped cross section.

[0027] The diameter D1 of each recess 9 is preferably 300 to 700 μm, and more preferably 400 to 600 μm. The maximum diameter D2 is preferably 320 to 700 μm, and more preferably 450 to 700 μm. The ratio of the maximum diameter D2 to the diameter D1 is preferably 1.05 to 1.20, and more preferably 1.08 to 1.15.

[0028] The depth D3 of the recesses 9 is smaller than the thickness of the second copper plate 4' and is preferably 100 to 400 μm, and more preferably 250 to 390 μm. The ratio of the depth D3 of the recesses 9 to the diameter D1 of the recesses 9 is preferably 0.5 to 0.8, and more preferably 0.6 to 0.8.

[0029] The radius of curvature of the cross section of the edge 91 of the second copper plate 4' is preferably 1.5 to 10.0 μm, and more preferably 2.0 to 8.0 μm. However, the cross section of the edge 91 does not necessarily have to be an arc, and may be formed at an acute angle.

[0030] If the interval W of the recesses 9 is too narrow, the second bonding material 5' will not spread well, whereas if the interval W is too large, the stress relaxation effect of the recesses may not be obtained. Therefore, the interval W of the recesses 9 is preferably 0.1 to 0.5 mm, and more preferably 0.15 to 0.3 mm.

[0031] <3. Method for manufacturing substrate for semiconductor device> Next, an example of a method for manufacturing the substrate 2 for a semiconductor device described above will be described. First, a laminate is formed in which the first and second copper plates 4, 4' are arranged on the upper and lower surfaces of the insulating plate 3. Here, the surface of each copper plate used is oxidized. Next, this laminate is heated for about 10 minutes under a nitrogen atmosphere condition at 1065°C to 1083°C. As a result, a Cu-O eutectic liquid phase is generated at the interface where the insulating plate 3 and the first and second copper plates 4, 4' are bonded, and each surface of the insulating plate 3 becomes wet. Next, the laminate is cooled to solidify the Cu-O eutectic liquid phase, and the first and second copper plates 4, 4' are bonded to the insulating plate 3. The first and second copper plates 4, 4' may be bonded to the insulating plate 3 in a vacuum using a brazing material containing an active metal such as titanium.

[0032] Next, recesses 9 are formed in the second copper plate 4'. First, a mask layer having circular through holes formed therein corresponding to the recesses 9 of the second copper plate 4' is laminated on the second copper plate 4'. The inner diameter of these through holes is smaller than the diameter D1 of the opening of the recesses 9, and can be, for example, 35 to 55% of the diameter D1. Then, etching is performed at an etching speed of 0.5 to 5 m / min to form the recesses 9.

[0033] The transmission circuit formed on the first copper plate 4 can be formed by, for example, a subtractive method or an additive method.

[0034] <4. Features> According to the above embodiment, the following effects can be obtained. (1) Even if thermal stress due to temperature changes in the semiconductor device 1 acts on the substrate 2 for a semiconductor device, the thermal stress occurring on the periphery of the second copper plate 4' can be alleviated by the multiple recesses 9. As a result, cracks in the substrate 2 for a semiconductor device and peeling off of the second copper plate 4' can be prevented.

[0035] (2) Since the diameter D1 of the opening of the recess 9 is smaller than the maximum diameter D2 inside the recess 9, the area of ​​the main surface of the second copper plate 4' can be increased while forming the recess 9. This reduces the inhibition of the spreading of the bonding material 5', such as solder, that has flowed over the flat main surface of the second copper plate 4' by the recess 9. As a result, the formation of cavities in the bonding material 5' between the second copper plate 4' and the heat sink 8 is suppressed, and the heat generated in the semiconductor chip 6 can be effectively transferred to the heat sink 8.

[0036] (3) Since the edge 91 of the second copper plate 4' at the opening edge of the recess 9 protrudes radially inward, the volume of the second copper plate 4' increases by the amount of the protrusion, thereby improving the heat dissipation of the substrate 2 for a semiconductor device.

[0037] (4) Since the cross-sectional shape of the edge 91 of the second copper plate 4' at the opening edge is arc-shaped, the second bonding material 5' can be smoothly guided from the main surface of the second copper plate 4' into the recess 9, and the second bonding material 5' easily flows into the recess 9. In particular, the larger the radius of curvature of the edge 91, the easier it is for the second bonding material 5' to flow. This makes it possible to prevent voids from being formed in the recess 9. This makes it possible to prevent partial discharges in the voids and also to prevent a decrease in heat dissipation caused by the voids.

[0038] <5. Modifications> Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and various modifications are possible without departing from the spirit of the present invention. The following modifications can be combined as appropriate.

[0039] (1) In the above embodiment, one row of recesses 9 is formed along the periphery of the second copper plate 4', but two or more rows may also be formed.

[0040] (2) In the above embodiment, the recesses 9 are formed only in the second copper plate 4', but the recesses 9 can also be formed in the first copper plate 4. In this case, like the second copper plate 4', one or more rows of recesses 9 can be formed along the periphery of the first copper plate 4. Also, the recesses 9 can be formed near the center of the first copper plate 4. The recesses 9 can be used, for example, to position the semiconductor chip 6.

[0041] (3) The shape of the opening of the recess 9 is not particularly limited, and in addition to the circle as described above, it can be an ellipse, a rectangle with rounded corners, or the like. In this case, the diameter D1 of the opening can be the maximum diameter. The maximum diameter can be set to the diameter equivalent to a circumscribing circle for the shape of the opening. The cross-sectional shape of the recess 9 can be a part of an ellipse, in addition to being a part of a substantially circle.

[0042] (4) In the above embodiment, the recess 9 is formed in the second copper plate 4' and does not reach the insulating plate 3. However, for example, as shown in FIG. 4, the recess 9 may penetrate the second copper plate 4' and reach the insulating plate 3. In this case, the thermal stress relaxation effect of the recess 9 is enhanced. On the other hand, compared to when the recess 9 reaches the insulating plate 3, the volume of the second copper plate 4' is relatively larger when the recess 9 does not reach the insulating plate 3. This improves heat dissipation. Furthermore, since the volume of the recess 9 is reduced, the formation of voids due to insufficient flow of the second bonding material 5' can be suppressed. EXAMPLES

[0043] Examples of the present invention will be described below, but the present invention is not limited to the following examples.

[0044] An insulating plate of alumina having a thickness of 0.32 mm was prepared. Then, a copper plate having a thickness of 0.4 mm and an oxidized surface was placed on both sides of the insulating plate, and the copper plate was bonded to the insulating plate by heating for about 10 minutes under a nitrogen atmosphere at 1070°C. A recess was formed along the periphery of one of the copper plates of the substrate for semiconductor device thus obtained, and the substrate for semiconductor device according to Examples 1 to 6 was obtained.

[0045] The recesses were formed by etching. The diameter of the through holes formed in the mask for the recesses and the etching speed are as shown in Table 1 below. The copper plate surface of the assembly consisting of an insulating plate and a copper plate is masked with an etching resist or dry film, and the unmasked parts of the copper plate are chemically etched to form a circuit pattern of the desired shape. The etching speed indicates the speed at which the assembly is passed through an etching area approximately 5m long. In the etching area, an etching solution is sprayed toward the assembly, and the copper plate is etched. [Table 1] By such etching, in Examples 1 to 6, recesses as shown in Table 2 below were formed. Among these, the recess in Example 6 penetrated the copper plate and reached the insulating plate. In this way, the substrates for semiconductor devices according to Examples 1 to 6 were obtained. Note that the edge length in Table 2 below refers to the length of the portion protruding beyond the maximum diameter D2 of the recess, and is calculated by (D2-D1) / 2. [Table 2]

[0046] Moreover, cross-sectional shapes and enlarged views of the edges of the recesses formed in Examples 1, 3, 4, and 6 are shown in Figs. 5 to 8, respectively.

[0047] As described above, in all of Examples 1 to 6, a recess in which the maximum diameter D2 is larger than the diameter D1 of the opening can be formed. Therefore, the area of ​​the main surface of the copper plate can be increased while forming the recess. Therefore, for example, when a heat sink is bonded to a copper plate by a bonding material, the wetting and spreading of the bonding material that has flowed over the main surface of the flat copper plate can be prevented from being hindered by the recess. In addition, the volume of the copper plate increases, so that the heat dissipation can be improved. Furthermore, the cross section of the edge of each recess is formed in an arc shape. Therefore, it is possible to easily move the bonding material from the main surface of the copper plate toward the inside of the recess. [Explanation of symbols]

[0048] 2...Substrate for semiconductor device 3...Insulating plate 4,4'...Copper plate 9…Recess 91…Edge

Claims

1. A substrate for a semiconductor device configured so that a semiconductor chip and a heat sink are bonded to each other via a bonding material, an insulating plate having a first surface and a second surface; a first copper plate bonded to the first surface of the insulating plate for forming a conductive pattern; a second copper plate joined to the second surface of the insulating plate; Equipped with At least one of the first copper plate and the second copper plate has a plurality of recesses formed on a surface opposite to the insulating plate, The semiconductor chip is bonded to the first copper plate via the bonding material, The heat sink is bonded to the second copper plate via the bonding material, A diameter D1 of the opening of each recess is smaller than a maximum diameter D2 inside the opening of the recess, A substrate for a semiconductor device, wherein an edge portion of the first copper plate or the second copper plate corresponding to an opening edge portion of the recess protrudes radially inward from the opening and is formed to have an arc-shaped cross section.

2. A substrate for a semiconductor device configured so that a semiconductor chip and a heat sink are bonded to each other via a bonding material, an insulating plate having a first surface and a second surface; a first copper plate bonded to the first surface of the insulating plate for forming a conductive pattern; a second copper plate joined to the second surface of the insulating plate; Equipped with At least one of the first copper plate and the second copper plate has a plurality of recesses formed on a surface opposite to the insulating plate, The semiconductor chip is bonded to the first copper plate via the bonding material, The heat sink is bonded to the second copper plate via the bonding material, A diameter D1 of the opening of each recess is smaller than a maximum diameter D2 inside the opening of the recess, A substrate for a semiconductor device, wherein a plurality of the recesses are formed near the center of the first copper plate.

3. A substrate for a semiconductor device configured so that a semiconductor chip and a heat sink are bonded to each other via a bonding material, an insulating plate having a first surface and a second surface; a first copper plate bonded to the first surface of the insulating plate for forming a conductive pattern; a second copper plate joined to the second surface of the insulating plate; Equipped with A plurality of recesses are formed on the first copper plate and the second copper plate on a surface opposite to the insulating plate, The semiconductor chip is bonded to the first copper plate via the bonding material, The heat sink is bonded to the second copper plate via the bonding material, A diameter D1 of the opening of each recess is smaller than a maximum diameter D2 inside the opening of the recess, A substrate for a semiconductor device, wherein at least some of the recesses formed in the first copper plate are used for positioning the semiconductor chip.

4. A substrate for a semiconductor device configured so that a semiconductor chip and a heat sink are bonded to each other via a bonding material, comprising: an insulating plate having a first surface and a second surface; a first copper plate bonded to the first surface of the insulating plate for forming a conductive pattern; a second copper plate joined to the second surface of the insulating plate; Equipped with The second copper plate has a plurality of recesses formed on a surface opposite to the insulating plate, The semiconductor chip is bonded to the first copper plate via the bonding material, The heat sink is bonded to the second copper plate via the bonding material, a diameter D1 of an opening of each of the recesses is smaller than a maximum diameter D2 inside the opening of the recess.

5. 2. The substrate for a semiconductor device according to claim 1, wherein the edge portion has a radius of curvature of 2.0 [mu]m or more.

6. 6. The substrate for a semiconductor device according to claim 1, wherein a ratio of said maximum diameter D2 to said diameter D1 is 1.08 or more.

7. 7. The substrate for a semiconductor device according to claim 1, wherein the recess does not reach the insulating plate.

8. 8. The substrate for a semiconductor device according to claim 1, wherein a plurality of said recesses are formed along a periphery of at least one of said first copper plate and said second copper plate.

9. 9. The substrate for a semiconductor device according to claim 1, wherein a plurality of said recesses are formed in both said first copper plate and said second copper plate.

10. 9. The substrate for a semiconductor device according to claim 1, wherein a plurality of said recesses are formed in at least said second copper plate out of said first copper plate and said second copper plate.

11. 11. The substrate for a semiconductor device according to claim 1, wherein the diameter D1 is 300 to 700 μm.

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