Current Regulator System

Abstract

An example power supply system 100 includes a switching voltage regulator 102 including at least one switch 104 configured to conduct an input current in response to a switching signal to generate an output voltage based on an input voltage. The system 100 also includes a current regulator 106 configured to generate a current sample voltage based on the amplitude of the input current relative to a reference current defining a maximum average amplitude set point for the input current to set a switching time defining a switching period of the at least one switch 104. The system 100 also includes a switch controller 110 configured to provide a switching signal to control the at least one switch 104 based on the amplitude of the output voltage relative to the reference voltage and based on the switching time.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This description relates generally to electronic circuits, and more particularly to current regulator systems. [Background technology]

[0002] Power supply circuits can be implemented in a variety of different ways. Examples of power supply circuits include synchronous rectifier power converters, asynchronous rectifier power converters, resonant power converters, and any of a variety of other types of switching power converters. Thus, a typical power supply circuit may activate one or more switches to convert an input voltage to an output voltage. Power supply circuits are typically implemented in wireless electronic devices. As a result, the input voltage is typically provided by a battery. Thus, the operating life of the battery is typically limited by the amplitude of the input current provided from the input voltage to generate the output voltage in the power supply circuit. For example, in a switching power supply circuit that provides power through an inductor, the operating life of the battery may be based on the average amplitude of the input current over an operating cycle of the switching power supply circuit. Summary of the Invention

[0003] An exemplary circuit includes a switching voltage regulator having a first input, a second input, and an output. The first input is coupled to a source of input current. A current regulator has an input, a first output, and a second output. The input is coupled to the source of input current. The current regulator provides a comparison signal at the first output having a logic state responsive to a current sampling voltage. The current regulator provides a reference current at the second output proportional to a maximum average amplitude set point of the input current over a switching period of the switching voltage regulator. A switch controller has a first input, a second input, a third input, and an output, the first input is coupled to the first output of the current regulator circuit. The second input is coupled to the output of the switching voltage regulator and the third input is adapted to be coupled to a reference voltage source. The output is coupled to the second input of the switching voltage regulator.

[0004] An example of a power supply system includes a switching voltage regulator including at least one switch configured to conduct an input current to generate an output voltage based on an input voltage in response to a switching signal, the system also includes a current regulator configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current defining a maximum average amplitude set point of the input current to set a switching time defining a switching period of the at least one switch, the system also includes a switch controller configured to provide a switching signal to control the at least one switch based on the amplitude of the output voltage relative to the reference voltage and based on the switching time.

[0005] An example of an integrated circuit (IC) includes a switching voltage regulator including at least one switch configured to conduct an input current to generate an output voltage based on an input voltage in response to a switching signal. The IC also includes a current regulator configured to generate a current sample voltage across a sampling capacitor. The current sample voltage may be based on an amplitude of the input current relative to a reference current set at a first external pin to set a switching time defining a switching period of the at least one switch, the reference current being proportional to a maximum average amplitude set point of the input current. The IC includes an input pin adapted to couple to a source of the reference current. The IC further includes a switch controller configured to provide a switching signal for controlling the at least one switch based on the switching time and based on an amplitude of the output voltage relative to a reference voltage set at a second external pin. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of an example of a power supply system.

[0007] [Diagram 2]FIG. 2 is an example of a schematic electrical circuit diagram of a power supply circuit.

[0008] [Diagram 3] FIG. 1 is an example of a timing diagram.

[0009] [Figure 4] 1 is another example of a timing diagram.

[0010] [Diagram 5] FIG. 2 is an example of a schematic electrical diagram of current flow in a power supply circuit.

[0011] [Figure 6] 2 is another example of a schematic electrical diagram of current flow in a power supply circuit.

[0012] [Figure 7] 1 is another example of a schematic electrical circuit diagram of a power supply circuit.

[0013] [Figure 8] 2 is another example of a schematic electrical diagram of current flow in a power supply circuit.

[0014] [Figure 9] 2 is another example of a schematic electrical diagram of current flow in a power supply circuit.

[0015] [Figure 10] 2 is another example of a schematic electrical diagram of current flow in a power supply circuit.

[0016] [Figure 11] 2 is another example of a schematic electrical diagram of current flow in a power supply circuit.

[0017] [Figure 12] 2 is another example of a schematic electrical diagram of current flow in a power supply circuit.

[0018] [Figure 13]2 is another example of a schematic electrical diagram of current flow in a power supply circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The present description relates generally to electronic circuits, and more particularly to a current regulator system. The current regulator system may be included in a power supply system, such as a switching power supply system. The power supply system may also include a switching voltage regulator including at least one switch controlled by a switch signal to provide an input current from an input voltage through an inductor and generate an output voltage. The power supply system further includes a switch controller configured to generate the switch signal based on, for example, an output voltage relative to a reference voltage and relative to a current sampling voltage having an amplitude related to a switching time of the switching voltage regulator, to adjust the amplitude of the input current.

[0020] As an example, the input voltage is provided from a battery. As such, the current regulator system may be configured to adjust the amplitude of the input current to mitigate current draw from the battery and therefore extend the operating life of the battery. The current regulator system may include a sampling capacitor configured to generate a current sampling voltage based on the sampling current. The sampling current may be based on the input current and a charging current related to a reference current. As an example, the charging current is generated based on the input current and is proportional to the input current. As another example, the charging current is a current having a fixed amplitude that is estimated to be proportional to the input current. The reference current may have an amplitude proportional to a maximum average amplitude set point of the input current over a switching period.

[0021] The current sampling voltage may have an amplitude based on the amplitude of the charging current minus the reference current during a first switching phase of the switching voltage regulator. For example, the reference current is arranged to flow from the sampling capacitor. Thus, during the first switching phase of the switching voltage regulator, the amplitude of the current sampling voltage may increase. During a second switching phase of the switching voltage regulator, the amplitude of the current sampling voltage may be based only on the reference current, so that during the second switching phase of the switching voltage regulator, the amplitude of the current sampling voltage may decrease. The duration of time from the start of charging the sampling capacitor in the first sampling phase to the end of discharging the sampling capacitor in the second sampling phase (e.g., between approximately zero equal charges) may define the switching time of the switching voltage regulator. Thus, the switch controller may monitor the amplitude of the current sampling voltage to switch between the switching phases of the switching voltage regulator and thus adjust the amplitude of the output voltage and the input current.

[0022] 1 is an example block diagram of a power supply system 100. Power supply system 100 may be implemented in any of a variety of wireless electronic devices, such as a laptop computer, a tablet computer, a smartphone, or any of a variety of other electronic devices. Power supply system 100 receives an input voltage V IN to output voltage V OUT As an example, the input voltage V IN is provided from the battery. As described herein, the power supply system 100 operates by integrating an input current I IN to provide regulation of the input current I IN , thereby extending the operating life of a battery. As an example, power supply system 100 may be fabricated on or as part of an integrated circuit (IC).

[0023] The power supply system 100 includes at least one switch 104 controlled by at least one respective switching signal, shown in the example of FIG. 1 as signal SS, and configured to receive an input voltage V IN Based on the output voltage V OUT As an example, the switching voltage regulator 102 may operate as a buck regulator or a boost regulator and / or in both buck and boost modes to generate an output voltage V OUT For example, switch 104 may include a high-side switch (e.g., a p-channel field effect transistor (PFET)) and a low-side transistor (e.g., an n-channel field effect transistor (NFET)) that are alternately activated to provide current through an inductor to generate an output voltage V at the output of switching voltage regulator 102. OUT As described herein, activation of the switch 104 may be defined by switching phases, such as a first switching phase and a second switching phase, that define a change in current through the inductor and collectively define a switching period of the switching voltage regulator 102.

[0024] The power supply system 100 also receives an input current I IN As mentioned above, the input current I IN is the input current I IN In the example of FIG. 1, the current regulator system 106 regulates the input current I over a switching period. IN The power supply system 100 includes a reference current generator 108 configured to generate a reference current having an amplitude proportional to a maximum average amplitude set point of the reference current generator 108. As an example, the reference current generator 108 is set (e.g., as a resistor to ground) at an external pin of an associated IC in which the power supply system 100 is fabricated.

[0025] The current regulator system 106 regulates the input current I INBased on the charging current associated with SMPL In one example, the charging current may include a sampling capacitor configured to generate an input current I IN is generated based on the input current I IN As another example, the charging current is a current having a fixed amplitude that is assumed to be proportional to the input current. For example, the charging current and the reference current are each a current proportional to the input current I IN , so that the reference current is proportional to the input current I IN is proportional to the maximum average amplitude set point.

[0026] As an example, the current sampling voltage V SMPL has an amplitude based on the amplitude of the charging current minus the reference current during a first switching phase of the switching voltage regulator 102 as defined by the switching signal SS. For example, the reference current flows from the sampling capacitor to subtract current from the charging current provided to the sampling capacitor. Thus, during a first switching phase of the switching voltage regulator 102, the current sampling voltage V SMPL The amplitude of may increase, and the input current I IN During the second switching phase of the switching voltage regulator 102, the current sampling voltage V SMPL The amplitude of the current sampling voltage V may be based on the reference current, but not on the charging current. For example, the switching signal SS may include a signal that operates a switch to control the charging current being provided to the sampling capacitor. Thus, during the second switching phase of the switching voltage regulator 102, the amplitude of the current sampling voltage V SMPL The amplitude of the input current I IN The target adjustment amplitude may be proportional to the target amplitude of the

[0027] For example, the current regulator system 106 may be configured to regulate the current sampling voltage V SMPLThe sampling comparator includes a sampling comparator configured to identify a near-zero volt amplitude of the current sampling voltage V across the sampling capacitor at the beginning and end of a given switching period of the switching voltage regulator 102. As explained herein, the term "approximately" may include some deviation (e.g., + / - 5%) from the exact value. Thus, the sampling comparator determines the magnitude of the current sampling voltage V across the sampling capacitor at the beginning and end of a given switching period of the switching voltage regulator 102. SMPL In the example of Figure 1, the output of the sampling comparator is shown as comparison signal CMP1.

[0028] The power supply system 100 further includes a switch controller 110. The switch controller 110 is configured to provide a switching signal SS in response to the comparison signal CMP1. For example, the sampling comparator may be SMPL , to switch from the second switching phase of the switching voltage regulator 102 to the first switching phase of the switching voltage regulator 102, and thus to the next switching period of the switching voltage regulator 102. The next switching period also monitors the amplitude of the reference voltage V REF Output voltage V OUT As an example, the reference voltage V REF can be set (e.g., as a fixed voltage source) at an external pin of the associated IC in which the power supply system 100 is fabricated. Thus, the switch controller 110 controls the current sampling voltage V SMPL For example, the switch controller 110 may also control the switching time of the switching voltage regulator 102 based on the magnitude of the current sampling voltage V SMPL and the reference voltage V REF Output voltage V OUT The state machine is configured to generate a switching signal SS based on the amplitude of the input signal, etc.

[0029] The switch controller 110 outputs the current sampling voltage V SMPLAs a result of controlling the switching period of the switching voltage regulator 102 based on IN The amplitude of the current sampling voltage V in the first switching phase may be adjusted to reduce power consumption from an associated battery, thereby extending the operating life of the battery. For example, implementing the reference current generator 108 to draw a reference current from a sampling capacitor and adjusting the amplitude of the current sampling voltage V in the first switching phase may be implemented. SMPL The starting amplitude of the current sampling voltage V SMPL By providing a switching period transition over a time period approximately equal to the final amplitude of the input current I IN Therefore, the power supply system 100 can reduce the average amplitude of the input voltage V IN In addition, as described in more detail herein, power supply system 100 may operate with any of a variety of waveforms for the current through the inductor of switching voltage regulator 102.

[0030] 2 is an example of a schematic electrical diagram of a power supply circuit 200. The power supply circuit 200 may be implemented in any of a variety of wireless electronic devices, such as a laptop computer, a tablet computer, a smart phone, or any of a variety of other electronic devices. The power supply circuit 200 receives an input voltage V IN to output voltage V OUT The power supply circuit 200 may be the power supply system 100 in the example of Fig. 1. Therefore, in the following description of the example of Fig. 2, reference is made to the example of Fig. 1.

[0031] The power supply circuit 200 includes a switching voltage regulator 202. The switching voltage regulator 202 includes a high-side switch designated as PFET P1, a low-side switch designated as NFET N1, a first output switch designated as NFET N2, and a second output switch designated as NFET N3. PFET P1 is coupled to an input voltage V INat its source and the switching node 204 at its drain, and NFET N1 interconnects the switching node 204 at its drain and the low voltage rail at its source, which is shown as ground in the example of FIG. OUT at its drain and the switching node 206 at its source, and NFET N3 interconnects the switching node 206 at its drain and the low voltage rail at its source. An inductor L1 interconnects the switching nodes 204 and 206 and flows a current I L is configured to conduct

[0032] PFET P1 is controlled by switching signal IN1, NFET N1 is controlled by switching signal IN2, NFET N2 is controlled by switching signal OUT1, and NFET N3 is controlled by switching signal OUT2. The sequential activation of FETs P1, N1, N2, and N3 results in a current I flowing through inductor L1 during switching phases defined by switching signals IN1, IN2, OUT1, and OUT2, respectively. L For example, activation of PFET P1 and NFET N3 is based on switching signals IN1 and OUT2 during the first switching phase relative to the input voltage V IN The input current I IN , so that during the first switching phase of the switching voltage regulator 202, the current I L is the input current I IN During a second switching phase of switching voltage regulator 202, switching signals IN2 and OUT1 deactivate PFET P1 and NFET N3 and activate NFET N1 and NFET N2 to cause a current I L is conducted from the low voltage rail through inductor L1.

[0033] Figure 3 shows an example of a timing diagram, which shows the inductor current I plotted as a function of time for a converter operating in buck mode. L 3 is a first timing diagram 302 showing the inductor current I plotted as a function of time for a converter operating in boost mode. L and a second timing diagram 304 showing the inductor current I L may be the current through inductor L1 of switching voltage regulator 202 in the example of Figure 2. Therefore, in the following description of the example of Figure 3, reference is made to the example of Figure 2. For simplicity, the transition times of timing diagrams 302 and 304 are aligned. However, the transition times may differ between the buck mode and the boost mode.

[0034] In the first timing diagram 302, the switching voltage regulator 202 begins a first switching phase at time T0. At time T0, PFET P1 and NFET N3 are activated by switching signals IN1 and OUT2, respectively. Thus, the input current I IN is the input voltage V IN From this, the current I L As a result, the current I L is an amplitude greater than or equal to zero L0 from the amplitude of I at time T1 L1 At time T1, NFET N3 is deactivated by switching signal OUT2, and NFET N2 is activated by switching signal OUT1. Therefore, the input current I IN is the input voltage V IN Then, it flows through PFET P1, through inductor L1 as current IL, and through NFET N2. Therefore, in the example of FIG. 3, the current I L is the amplitude I L1 from amplitude I L2t, and is therefore shown as an increase with a less steep slope than between times T0 and T1.

[0035] The switching voltage regulator 202 switches from the first switching phase to the second switching phase at time T2. At time T2, PFET P1 is deactivated, NFET N1 is activated, and NFET N2 remains activated by switching signals IN1 and IN2, respectively. Thus, the input current I IN stops, and the current I L flows from the low voltage rail, through NFET N1, through inductor L1, and through NFET N2. Thus, in the example of FIG. 3, the current I L At time T3, the amplitude I L2 from amplitude I L3 and amplitude I L3 is the amplitude I L1 At time T3, NFET N2 is deactivated by switching signal OUT1, and NFET N3 is activated by switching signal OUT2. Therefore, the current I L flows from the low voltage rail, through NFET N1, through inductor L1, and through NFET N3. Thus, in the example of FIG. 3, the current I L At time T4, the amplitude I L3 from the initial amplitude I L0 The second switching phase ends at time T4. The first and second switching phases may define a switching period, such that in the example of FIG. 3, the next switching period is shown as beginning at time T4. For example, the current I L Idle times during which V remains zero may occur during switching periods, such as during deactivation of power supply circuit 200 or during a discontinuous mode of operation of power supply circuit 200.

[0036] The second timing diagram 304 may be arranged similarly to the first timing diagram 302 and may define a boost mode of operation of the power supply circuit 200. As an example, the boost mode of operation may vary the current I based on a change in the topology of the power supply circuit 200.L Accordingly, the second timing diagram 304 is illustrated to illustrate that the operating principles of the power supply circuit 200, as described herein, are applicable to any of a variety of inductor current waveforms.

[0037] Referring back to the example of FIG. 2, the power supply circuit 200 receives an input current I IN As mentioned above, the input current I IN can be drawn from the battery, so that the input current I IN 2, the current regulator system 208 is coupled to the switching node 204 via a first switch SW1 controlled by a switching signal S1 and coupled to the input voltage V via a second switch SW2 controlled by a switching signal S2. IN The transconductance amplifier 210 also receives an input voltage V via a third switch SW3 controlled by a switching signal S3. IN , and has a second input coupled to a third switching node 212. The third switching node 212 is coupled to an input voltage V through a PFET P2. IN As an example, PFET P2 is a replica switch with respect to PFET P1, so that PFET P2 has a channel width that is scaled down by a factor of K relative to PFET P1. In the example of FIG. 2, PFET P2 is activated by switching signal IN1, so that PFET P2 is activated simultaneously with PFET P1 to drive input current I IN Charging current I with amplitude approximately equal to the amplitude of CH (e.g., I CH =I IN / K).

[0038] The transconductance amplifier 210 supplies a charging current I to the sampling node 214 via a switch SW4 controlled by a switching signal S4. CH , which is configured to generate a signal CT that is provided to PFET P3 to provide a sampling capacitor C S A switch SW4, controlled by a switching signal S5, interconnects the sampling node 214 and the node 220. The sampling node 214 and the node 220 are also coupled by a switch SW5, controlled by a switching signal S5. A voltage source 218 provides an offset voltage VOFF to the node 220. A switch SW6, controlled by a switching signal S6, also interconnects the sampling node 214 and the node 216, and a switch SW7, controlled by a switching signal S7, interconnects the nodes 216 and 220.

[0039] The current regulator system 208 also includes a current source 222 coupled to the sampling node 214 via a switch SW8 controlled by a switching signal S8. The current source 222 may be the reference current generator 108 in the example of FIG. 1. For example, the current source 222 is provided (e.g., as a resistor to ground) at an external pin of the associated IC in which the power supply circuit 200 is fabricated. Thus, when the switch SW8 is closed, the current source 222 draws current from the sampling node 214, and thus the sampling capacitor C S From the reference current I REF For example, the offset voltage V OFF (For example, about 350 mV) is the reference current I REF As mentioned above, the reference current I REF is the input current I over the switching period of the switching voltage regulator 202. IN For example, the input current I IN Reference current I for maximum average amplitude set point REF The proportionality of is the coefficient of K, and therefore the charging current I CH As an example, the reference current I REFhas an amplitude expressed as: I REF =I TAR / K expression 1 Here, I TAR is the input current I over the switching period of the switching voltage regulator 202. IN is the maximum average amplitude set point.

[0040] The current regulator system 208 also includes a sampling comparator 224 having inputs at nodes 216 and 220. Thus, the sampling comparator 224 detects when the switch SW6 is closed (e.g., when the offset voltage V OFF Based on the common-mode behavior defined by SMPL The sampling comparator 224 is configured to monitor the sampling voltage V SMPL The first comparison signal CMP1 may be generated in response to determining that has an amplitude of approximately zero.

[0041] The power supply circuit 200 further includes a switch controller 226. The switch controller 226 includes a state machine 228. The first comparison signal CMP1 is provided to the state machine 228, which also receives a second comparison signal CMP2 from a reference comparator 230. In the example of FIG. 2, the reference comparator 230 controls the output voltage V OUT A fixed reference voltage V REF Based on the comparison signals CMP1 and CMP2, state machine 228 may generate switching signals IN, OUT, and S that are provided to respective PFETs P1-P3, NFETs N1-N3, and switches SW1-SW8. Thus, state machine 228 may define the first and second switching phases of switching voltage regulator 202, and thus the switching period of switching voltage regulator 202. State machine 228 also provides control for operating switches SW1-SW8 to regulate input current I IN In order to regulate the amplitude of the current regulator system 208, operation of the current regulator system 208 may be provided during each of the first and second switching phases.

[0042] The example power supply circuit 200 may be configured differently than that shown in the example of Figure 2. For example, the switching voltage regulator 202 is not limited to the arrangement of the high-side and low-side switches P1, N1, N2, and N3. As an example, PFET P1, and by extension, replica PFET P2, may instead be arranged as an n-channel transistor.

[0043] The operation of the power supply circuit 200 is shown in further detail in Figures 4-6. Figure 4 is another example of a timing diagram. The timing diagram shows the inductor current I plotted as a function of time for a converter operating in buck mode. L 3. The first timing diagram 402 is thus the same as the first timing diagram 302 in the example of FIG. 3. A second timing diagram 404 shows the sampled voltage V plotted as a function of time. SMPL Figure 5 is an example of a schematic electrical circuit diagram 500 of current flow within power supply circuit 200 in a first switching phase of switching voltage regulator 202, and Figure 6 is an example of a schematic electrical circuit diagram 600 of current flow within power supply circuit 200 in a second switching phase of switching voltage regulator 202. Therefore, in the following description, reference will be made to the examples of Figures 4 to 6.

[0044] In the first timing diagram 402, the switching voltage regulator 202 begins a first switching phase at time T0. At time T0, PFET P1 and NFET N3 are activated by switching signals IN1 and OUT2, respectively. Also, referring to the example of FIG. 5, switches SW1, SW4, SW7, and SW8 are closed by switching signals S1, S4, S7, and S8, respectively. Thus, the input current I IN is the input voltage V IN Then, it flows through PFET P1, through inductor L1 as current IL, and through NFET N3. Therefore, in the example of FIG. 4, current I L I L0 from the amplitude of I L1This is shown as an increase to

[0045] At time T1, NFET N3 is deactivated by switching signal OUT2, and NFET N2 is activated by switching signal OUT1. Therefore, the input current I IN is the input voltage V IN From this, the current I L As a result, the current I L continues to increase in amplitude from time T1 to time T2 during the first switching phase of switching voltage regulator 202. And, with further reference to the example of FIG. 5, during the first switching phase defined between time T0 and time T2, the input current I IN is based on matched PFETs P1 and P2 that are simultaneously activated by switching signal IN1. CH through replica PFET P2 by CH is the input current I IN has a scaled amplitude approximately equal to the amplitude of I divided by the channel width scale factor K (e.g., I CH =I IN / K).

[0046] Due to the closure of switch SW1, transconductance amplifier 210 receives approximately equal voltages at each of its inputs at switching node 204 and node 212 due to the high gain of transconductance amplifier 210. Transconductance amplifier 210 flows a current I L (For example, the input current I during the first switching phase of switching voltage regulator 202 IN ) as an absolute value rather than a relative value, and may be configured as a high bandwidth transconductance amplifier 210 to track the slope of the current I LThe transconductance amplifier 210 may be configured with a low offset to measure V. The low offset may be implemented, for example, by providing trimming, calibration, or chopping of the transconductance amplifier 210, or by providing auto-zero techniques using switches SW2 and SW3, as described in detail herein.

[0047] The transconductance amplifier 210 provides a control signal CT to the PFET P3 to regulate the charging current I CH through PFET P3 and through switch SW4 to the sampling node 214. Based on the closure of switch SW8, the charging current I CH is provided to the sampling node 214, while the reference current I REF flows out of the sampling node 214. As a result, the sampling capacitor C S Sampling current I via SMPL Therefore, the current I SMPL is the charging current I CH From the reference current I REF Therefore, the sampling current I SMPL is the sampling capacitor C S starts charging and the sampling voltage V SMPL During the first switching phase of the switching voltage regulator 202, because switch SW6 is open and switch SW7 is closed, the sampling comparator 224 increases the amplitude of the sampling voltage V SMPL Therefore, the first comparison signal CMP1 is asserted in a logic high state.

[0048] Referring back to FIG. 4, switching voltage regulator 202 switches from the first switching phase to the second switching phase at time T2. At time T2, PFET P1 is deactivated, NFET N1 is activated, and NFET N2 remains activated by switching signals IN1 and IN2, respectively. Also referring to the example of FIG. 6, switches SW1, SW4, and SW7 are opened by switching signals S1, S4, and S7, respectively, and switches SW2, SW3, and SW6 are closed by switching signals S2, S3, and S6, respectively. Switch SW8 remains closed during the second switching phase of switching voltage regulator 202. Thus, the input current I IN stops, and the current I L flows from the low voltage rail, through NFET N1, through inductor L1, and through NFET N2. Thus, in the example of FIG. 4, the current I L At time T3, the amplitude I L2 from amplitude I L3 At time T3, NFET N2 is deactivated by switching signal OUT1 and NFET N3 is activated by switching signal OUT2. Thus, the current I L flows from the low voltage rail, through NFET N1, through inductor L1, and through NFET N3. Thus, in the example of FIG. 4, the current I L is the amplitude I at time T4 L3 from the initial amplitude I L0 This is shown as a decrease to

[0049] Referring to the example of FIG. 6, in the second switching phase of the switching voltage regulator 202, both PFETs P1 and P2 are deactivated, thereby decreasing the input current I IN The flow of the charging current I CH The switches SW2 and SW3 are closed to provide nulling of the transconductance amplifier 210. The charging current I CH stops flowing, so the charging current I CHis no longer provided to the sampling node 214. However, switch SW8 is still closed in the second switching phase of switching voltage regulator 202, resulting in the reference current I REF continues, sampling capacitor C S The result is a sampling voltage V SMPL decreases during the second switching phase of switching voltage regulator 202, beginning at time T2.

[0050] Due to switch SW6 being closed, the sampling comparator 224 detects the sampling voltage V SMPL is compared to the voltage at node 220, thus monitoring the voltage across the sampling capacitor Cs. SMPL has an amplitude of approximately zero, and therefore the sampling capacitor C S In response to the sampling voltage V having approximately zero charge, the sampling comparator 224 may deassert the first comparison signal CMP1. As described herein, the sampling voltage V SMPL The zero amplitude of is the offset voltage V OFF The sampling voltage V SMPL Based on the sampling capacitor C S The sampling voltage V SMPL The zero amplitude of the sampling voltage V is also based on the sampling capacitor Cs. SMPL , so that the inverting input of the sampling comparator 224 may point to approximately the negative amplitude of the sampling voltage V SMPL has a voltage swing greater than

[0051] In response to the deassertion of the first comparison signal CMP1 and in response to a logic low swing of the second comparison signal CMP2 as provided by the reference comparator 230 (e.g., the reference voltage V REF is the output voltage V OUTIn response to the input current I being greater than 1, the state machine 228 may change the state of the switching signals IN, OUT, and S. Thus, the state machine 228 may switch the switching voltage regulator 202 from the second switching phase to the first switching phase, and thus the start of the next switching period. Thus, the state machine 228 may change the state of the switching signals IN, OUT, and S. IN To adjust the amplitude of REF Input current I IN Based on the amplitude of the sampling voltage V SMPL ) may dictate the duration of the switching period of switching voltage regulator 202.

[0052] As an example, upon completion of the switching period, state machine 228 implements an idle (e.g., sleep) mode for power supply circuit 200, such as based on a deactivated mode for power supply circuit 200 or a discontinuous operation mode for switching voltage regulator 202. For example, during the idle mode, switch SW8 de-energizes sampling capacitor C S From the reference voltage I REF , and switches SW2 and SW3 may remain closed to provide nulling of the transconductance amplifier 210, and switch SW5 may be opened by switching signal S8 to decouple the sampling capacitor C S , and switch SW6 may remain closed to latch the first comparison signal CMP1 provided by the sampling comparator 224. The state machine 228 may then wait for a change in state of the second comparison signal CMP2 to begin the next switching period.

[0053] The power supply circuit 200 supplies a reference current I REF Input current I IN Based on the amplitude of the sampling voltage V SMPL Because the power supply circuit 200 provides switching times based on the input current I in a manner that is more effective than input current regulation in typical power supply circuits. INFor example, as described above, the current regulation of power supply circuit 200 may be limited to a triangular inductor current waveform with an initial zero amplitude, as opposed to being limited to a triangular inductor current waveform with an initial zero amplitude, as is the case for typical power supply circuits. L The more complex waveform of the inductor current I L The power supply circuit 200 also implements a step-down converter 204 for a non-zero initial amplitude of the input current I during each cycle of the switching voltage regulator 202. IN and therefore the inductor current I L This is in contrast to regulating the input current based on a fixed peak current amplitude estimate provided in a typical power supply circuit. Furthermore, a typical power supply circuit requires multiple capacitors to compare multiple charges (e.g., the charge delivered from the input and the charge of the desired average input current) to perform input current regulation. Power supply circuit 200 uses a single capacitor (e.g., sampling capacitor C) for current control. S ), which may provide a more compact circuit and eliminate the requirement for matching between two or more capacitors. Thus, the input current regulation provided by power supply circuit 200 may be substantially more efficient than the input current regulation of typical power supply circuits.

[0054] 7 is another example of a schematic electrical diagram of a power supply circuit 700. The power supply circuit 700 may be implemented in any of a variety of wireless electronic devices, such as a laptop computer, a tablet computer, a smart phone, or any of a variety of other electronic devices. The power supply circuit 700 receives an input voltage V IN to output voltage V OUTThe power supply circuit 700 may be the power supply system 100 in the example of FIG. 1. Accordingly, the description of the example of FIG. 7 also refers to FIG. 1. The power supply circuit 700 in the example of FIG. 7 is provided as another example of a current control technique that implements an open-loop topology (described in further detail herein) for the transconductance amplifier, as opposed to a closed-loop topology for the transconductance amplifier 210 in the example of FIG. 2. Thus, the power supply circuit 700 does not necessarily require stability compensation, and as a result, the inductor current I L Supports high gradients of

[0055] The power supply circuit 700 includes a switching voltage regulator 702. The switching voltage regulator 702 includes a high-side switch designated as PFET P1, a low-side switch designated as NFET N1, a first output switch designated as NFET N2, and a second output switch designated as NFET N3. PFET P1 is coupled to an input voltage V IN at its source and the switching node 704 at its drain, and NFET N1 interconnects the switching node 704 at its drain and the low voltage rail at its source shown in the example of FIG. OUT at its drain and a switching node 706 at its source, and an NFET N3 interconnects the switching node 706 at its drain and the low voltage rail at its source. An inductor L1 interconnects the switching nodes 704 and 706 and a current I L is configured to conduct

[0056] PFET P1 is controlled by switching signal IN1, NFET N1 is controlled by switching signal IN2, NFET N2 is controlled by switching signal OUT1, and NFET N3 is controlled by switching signal OUT2. The sequential activation of FETs P1, N1, N2, and N3 results in a current I through inductor L1 during switching phases defined by switching signals IN1, IN2, OUT1, and OUT2, respectively. L For example, activation of PFET P1 is based on switching signal IN1 during the first switching phase by decreasing input voltage V IN to the switching node 704. IN and thus the current I L represents the input current I during the first switching phase of the switching voltage regulator 702. IN During a second switching phase of switching voltage regulator 702, PFET P1 is deactivated by switching signal IN2 and NFET N1 is activated to supply current I L from the low voltage rail through inductor L1. Thus, switching voltage regulator 702 operates substantially similarly to switching voltage regulator 202 in the example of FIG.

[0057] The power supply circuit 700 also receives an input current I IN 7, the current regulator system 708 is coupled to the switching node 704 via a first switch SW1 controlled by a switching signal S1, and coupled to the input voltage V via a second switch SW2 controlled by a switching signal S2. IN The first transconductance amplifier 710 also includes a first input coupled to an input voltage V IN The current regulator system 708 also has a second input coupled to a node 714 and receives an input voltage V through a switch SW3 controlled by a switching signal S3.IN The first and second transconductance amplifiers 710 and 712 may be fabricated substantially similarly and therefore may have substantially equal transconductance (GM) coefficients. The second transconductance amplifier 712 also receives an input voltage V IN Node 714 is coupled to the input voltage V through a PFET P2. IN As an example, PFET P2 is a replica switch with respect to PFET P1, so that PFET P2 has a channel width that is scaled down by a factor of K relative to PFET P1.

[0058] In the example of FIG. 7, PFET P2 is activated by switching signal IN1, which results in PFET P2 being activated simultaneously with PFET P1, and the reference current I generated by current source 716. REF via switch SW4, which is controlled by switching signal S4. Current source 716 may be reference current generator 108 in the example of FIG. 1. For example, current source 716 is provided (e.g., as a resistor to ground) at an external pin of the associated IC in which power supply circuit 700 is fabricated. Thus, when switch SW4 is closed, current source 716 conducts reference current I REF is the input voltage V IN 1 through PFET P2. As described above, the reference current I REF is the input current I of the switching voltage regulator 702 IN For example, the input current I IN The maximum average amplitude set point (I TAR (expressed as) REF The proportionality of is similarly scaled by a factor of K, as provided in Equation 1 above.

[0059] The first transconductance amplifier 710 provides a charging current I to a sampling node 718 via a switch SW5 controlled by a switching signal S5. CHFor example, the charging current I CH The amplitude of is expressed as follows: I CH =GM×I IN ×R DSON formula 2 where GM is the transconductance of the first transconductance amplifier 710 and R DSON is the activation resistance of PFET P1. The second transconductance amplifier 712 also provides a current I through a diode-connected NFET N4 via a switch SW6 controlled by a switching signal S6. R As an example, in the example of FIG. 7, the amplitude of the current I R is expressed as follows: I R =GM×I TAR ×K×R DSON formula 3 Here, GM is the transconductance of the second transconductance amplifier 712, which is approximately equal to the transconductance of the first transconductance amplifier 710. K×R DSON is the activation resistance of PFET P2, approximately equal to K times the activation resistance of PFET P1.

[0060] Diode-connected NFET N4 has its gate and drain coupled to sample-and-hold capacitor C1 and the gate of NFET N5 through switch SW7 controlled by switching signal S7. NFETs N4 and N5 are thus arranged as a current mirror, whereby when switch SW7 is closed to charge capacitor C1, a current I R is provided to capacitor C1. The voltage V1 on capacitor C1 thus provides an activation voltage for NFET N5, causing a current I R Therefore, NFET N5 mirrors the current I R Conduction is performed.

[0061] Similar to the power supply circuit 200, the sampling node 718 is coupled to a sampling capacitor Cs and a sampling voltage V SMPLを Sampling capacitor C S interconnects sampling node 718 and node 720. Sampling node 718 and node 720 are also coupled by switch SW8, which is controlled by switching signal S8. A voltage source 722 supplies an offset voltage V OFF A switch SW9 controlled by a switching signal S9 interconnects the sampling node 718 and the node 724, and provides a switching signal S 10 Switch controlled by SW 10 interconnects nodes 720 and 724. In the example of FIG. 7, NFET N5 is coupled at its drain to the sampling node 718. Thus, NFET N5 couples the drain of the sampling node 718 and, therefore, the sampling capacitor C S From the above, the current I R For example, the offset voltage V OFF (For example, about 350 mV) is the current I R Provides sufficient headroom for

[0062] The current regulator system 708 includes a sampling comparator 726 having inputs at nodes 724 and 720. Thus, the sampling comparator 726 detects when the switch SW9 is closed (e.g., when the offset voltage V OFF based on the common-mode behavior defined by), and the sampling capacitor C S The upper sampling voltage V SMPL The sampling comparator 726 is configured to monitor the sampling voltage V SMPL has an amplitude of approximately zero.

[0063] The power supply circuit 700 further includes a switch controller 728 that includes a state machine 730. The first comparison signal CMP1 is provided to the state machine 730, which also receives a second comparison signal CMP2 from a reference comparator 732. In the example of FIG. OUT A fixed reference voltage V REF Based on the comparison signals CMP1 and CMP2, the state machine 730 controls the respective PFETs P1-P3, NFETs N1-N3, and switches SW1-SW 10 The state machine 730 may generate switching signals IN, OUT, and S that are provided to the switching voltage regulator 702. Thus, the state machine 730 may define the first and second switching phases of the switching voltage regulator 702, and thus the switching period of the switching voltage regulator 702. The state machine 730 also controls the switches SW1-SW 10 to provide a control for operating the input current I IN In order to regulate the amplitude of the current regulator system 708 during each of the first and second switching phases, operation of the current regulator system 708 may be provided.

[0064] The power supply circuit 700 is not limited to the example shown in Figure 7. For example, the switching voltage regulator 702 is not limited to the arrangement of the high-side and low-side switches P1, N1, N2, and N3. As an example, PFET P1, and by extension the replica PFET P2, are instead arranged as n-channel transistors.

[0065] The operation of the power supply circuit 700 is shown in further detail in Figures 4, 8 and 9. Figure 8 is another example of a schematic electrical circuit diagram 800 of the current flow in the power supply circuit 700 in a first switching phase of the switching voltage regulator 702, and Figure 9 is another example of a schematic electrical circuit diagram 900 of the current flow in the power supply circuit 700 in a second switching phase of the switching voltage regulator 702. Therefore, the following description also refers to the examples of Figures 4, 8 and 9.

[0066] In the first timing diagram 402, the switching voltage regulator 702 begins a first switching phase at time T0. At time T0, PFET P1 and NFET N3 are activated by switching signals IN1 and OUT2, respectively. Also, referring to the example of FIG. 8, switches SW1, SW4, SW5, SW6, SW7, and SW 10 are switching signals S1, S4, S5, S6, S7, and S 10 Therefore, the input current I IN is the input voltage V IN From this, the current I L As a result, the current I L is the amplitude I L0 from amplitude I L1 This is shown as an increase to

[0067] At time T1, NFET N3 is deactivated by switching signal OUT2, and NFET N2 is activated by switching signal OUT1. Therefore, the input current I IN is the input voltage V IN From this, the current I L As a result, the current I L continues to increase in amplitude from time T1 to time T2 during the first switching phase of switching voltage regulator 702. And, with further reference to the example of FIG. 8, during the first switching phase defined between time T0 and time T2, the input current I IN The first transconductance amplifier 710 receives the input current I IN Based on the closure of switch SW1, a charging current I having an amplitude defined by Equation 2 above is generated. CHSimilarly, the second transconductance amplifier 712 generates a current I based on the reference current and having a magnitude defined by Equation 3 above based on the closure of switch SW4. R Generate.

[0068] Based on the closure of switch SW5, the charging current I CH is provided from the first transconductance amplifier 710 to the sampling node 718. Based on the closure of the switch SW6, the current I R is provided from the second transconductance amplifier 712 through NFET N4. R charges the capacitor C1, providing a voltage V1 at the gate of the NFET N5, and a current I R is mirrored from NFET N4 to NFET N5. As a result, the sampling capacitor C S Sampling current I via SMPL is provided. The current I SMPL Therefore, the charging current I CH from current I R Therefore, the sampling current I SMPL is the sampling capacitor C S starts charging and the sampling voltage V SMPL During the first switching phase of the switching voltage regulator 702, switch SW9 is open and switch SW 10 is closed, the sampling comparator 726 detects the sampling voltage V SMPL Therefore, the first comparison signal CMP1 is asserted in a logic high state.

[0069] 4, switching voltage regulator 702 switches from a first switching phase to a second switching phase at time T2. At time T2, PFET P1 is deactivated, NFET N1 is activated, and NFET N2 remains activated by switching signals IN1 and IN2, respectively. Also, referring to the example of FIG. 9, switches SW1, SW4, SW5, SW6, SW7, and SW 10 are switching signals S1, S4, S5, S6, S7, and S 10 The input current I is opened by switching signals S1, S2, S3, and S9, respectively, and the switches SW2, SW3, and SW9 are closed by switching signals S2, S3, and S9, respectively. IN stops, and the current I L flows from the low voltage rail, through NFET N1, through inductor L1, and through NFET N2. So, in the example of Figure 4, the current I L At time T3, the amplitude I L2 from amplitude I L3 At time T3, NFET N2 is deactivated by switching signal OUT1 and NFET N3 is activated by switching signal OUT2. Thus, the current I L flows from the low voltage rail, through NFET N1, through inductor L1, and through NFET N3. So, in the example of Figure 4, the current I L At time T4, the amplitude I L3 From the early I L0 This is shown as a decrease to

[0070] Referring to the example of FIG. 9, in the second switching phase of the switching voltage regulator 702, PFETs P1 and P2 are both deactivated, thereby decreasing the input current I IN , and by extension the reference current I REF The flow of the charging current I stops. The switches SW2 and SW3 are closed to provide nulling of the first and second transconductance amplifiers 710 and 712. CHstops flowing from the first transconductance amplifier 710, so that the charging current I CH is not provided to the sampling node 718. Similarly, the current I R stops flowing from the second transconductance amplifier 712. However, the sampled voltage V1 across the capacitor C1 continues to provide activation of the NFET N5 in the second switching phase of the switching voltage regulator 702, resulting in a current I R is the sampling capacitor C S The result is a sampling voltage V SMPLは , decreasing during the second switching phase of switching voltage regulator 702, beginning at time T2.

[0071] Due to the closure of switch SW9, the sampling comparator 726 detects the sampling voltage V SMPL is compared to the voltage at node 720, thus monitoring the voltage across the sampling capacitor C. SMPL has an amplitude of approximately zero, and therefore the sampling capacitor C S In response to V having approximately zero charge, the sampling comparator 726 may deassert the first comparison signal CMP1. In response to the deassertion of the first comparison signal CMP1 and in response to a logic low amplitude of the second comparison signal CMP2 as provided by the reference comparator 732 (e.g., the reference voltage V REF is the output voltage V OUT In response to the reference current I being greater than 1, the state machine 730 may change the state of the switching signals IN, OUT, and S. Thus, the state machine 730 may switch the switching voltage regulator 702 from the second switching phase to the first switching phase, and thus the start of the next switching period. Thus, the state machine 730 may change the state of the reference current I REF Input current I IN Based on the amplitude of the sampling voltage V SMPL, based on which the input current I IN The amplitude of the signal may be adjusted.

[0072] Similar to above, upon completion of the switching period, state machine 730 may implement an idle (e.g., sleep) mode for power supply circuit 700 based on a deactivated mode for power supply circuit 700 or a discontinuous operation mode for switching voltage regulator 702, etc. For example, during the idle mode, switches SW2 and SW3 remain closed to provide zeroing of transconductance amplifiers 710 and 712, and switch SW8 is closed by switching signal S8 to load sampling capacitor C S , and switch SW9 remains closed, providing a zeroing of sampling comparator 726. State machine 730 may then wait for a change in state of the second comparison signal CMP2 to begin the next switching period.

[0073] 10 is another example of a schematic electrical diagram illustrating current flow in a power supply circuit 1000. The power supply circuit 1000 may be implemented in any of a variety of wireless electronic devices, such as a laptop computer, a tablet computer, a smart phone, or any of a variety of other electronic devices. The power supply circuit 1000 receives an input voltage V IN to output voltage V OUT The power supply circuit 1000 may be the power supply system 100 in the example of FIG. 1. Therefore, the description of FIG. 10 also refers to FIG. 1. The power supply circuit 1000 in the example of FIG. 10 is configured to generate an inductor current I L 10 provides another example of a current regulation technique that implements estimates for the peak and valley amplitudes of the inductor current I L The estimates for the peak and valley amplitudes of are given by the operating mode of the power supply circuit 1000, the input voltage V IN and the output voltage V OUT The amplitude of the input signal may be calculated in any of a variety of ways, such as the relative amplitude of the input signal, duty cycle, factory test / calibration, or any of a variety of methods.

[0074] The power supply circuit 1000 includes a switching voltage regulator 1002. The switching voltage regulator 1002 includes a high-side switch designated as PFET P1, a low-side switch designated as NFET N1, a first output switch designated as NFET N2, and a second output switch designated as NFET N3. PFET P1 is coupled to an input voltage V IN 10 at its source and a switching node 1004 at its drain, and NFET N1 interconnects the switching node 1004 at its drain and the low voltage rail at its source, which is shown as ground in the example of FIG. OUT at its drain and the switching node 1006 at its source, and NFET N3 interconnects the switching node 1006 at its drain and the low voltage rail at its source. An inductor L1 interconnects the switching nodes 1004 and 1006 and flows a current I L is configured to conduct

[0075] PFET P1 is controlled by switching signal IN1, NFET N1 is controlled by switching signal IN2, NFET N2 is controlled by switching signal OUT1, and NFET N3 is controlled by switching signal OUT2. The sequential activation of FETs P1, N1, N2, and N3 results in a current I through inductor L1 during switching phases defined by switching signals IN1, IN2, OUT1, and OUT2, respectively. L For example, activation of PFET P1 provides an input current I IN During the first switching phase, the input voltage V IN to the switching node 1004, resulting in a current I L During the first switching phase of the switching voltage regulator 1002, the input current I INDuring a second switching phase of switching voltage regulator 1002, switching signal IN2 deactivates PFET P1 and activates NFET N1 to allow a current I L from the low voltage rail through inductor L1. Thus, switching voltage regulator 1002 operates substantially similarly to switching voltage regulator 202 in the example of FIG.

[0076] The power supply circuit 1000 also receives an input current I IN 10, the current regulator system 1008 includes a first current source 1010 generating a first current I1, a second current source 1012 generating a second current I2, and a third current source 1014 generating a third current I3. As an example, as described in more detail herein, the combination of currents I1, I2, and I3 may form a charging current I CH The first current source 1010 is connected to the input voltage V IN , and a switch SW1 controlled by a switching signal S1. A second current source 1012 is connected to the input voltage V IN , and a switch SW2 controlled by a switching signal S2. A third current source 1014 interconnects the input voltage V IN , and a switch SW3 controlled by a first switching signal S3. The parallel arrangement of current source 1010 and switch SW1, current source 1012 and switch SW2, and current source 1014 and switch SW3 is arranged in series with a switch SW4 controlled by a switching signal S4.

[0077] The switch SW4 is coupled to the sampling node 1016. A sampling capacitor Cs interconnects the sampling node 1016 and a node 1018. The sampling node 1016 and the node 1018 are also coupled to a switch SW5 that is controlled by a switching signal S5. A voltage source 1020 supplies an offset voltage V OFFto node 1018. Also, a switch SW6 controlled by a switching signal S6 interconnects the sampling node 1016 and a node 1022, and a switch SW7 controlled by a switching signal S7 interconnects the nodes 1018 and 1022.

[0078] The current regulator system 1008 also includes a current source 1024 coupled to the sampling node 1016 via a switch SW8 controlled by a switching signal S8. The current source 1024 may be the reference current generator 108 in the example of FIG. 1. For example, the current source 1024 is provided (e.g., as a resistor to ground) at an external pin of the associated IC from which the power supply circuit 1000 is fabricated. Thus, when the switch SW8 is closed, the current source 1024 draws current from the sampling node 1016, and thus the sampling capacitor C S From the reference current I REF For example, the offset voltage V OFF (For example, about 350 mV) is the reference current I REF As mentioned above, the reference current I REF is the input current I of the switching voltage regulator 1002. IN For example, the input current I IN The maximum average amplitude set point (I TAR (expressed as) REF is similarly scaled by a factor K, as provided in Equation 1 above. The current regulator system 1008 also includes a current source 1026 coupled to the sampling node 1016 via a switch SW9 controlled by a switching signal S9. The current source 1026 generates a current I3 approximately equal to the current I3 generated by the current source 1014 described above.

[0079] The switching voltage regulator 1008 includes a sampling comparator 1028 having inputs at nodes 1018 and 1022. The sampling comparator 1028 thus outputs a comparator voltage (e.g., an offset voltage V OFFWhen switch SW6 is closed, the sampling capacitor C S The upper sampling voltage V SMPL The sampling comparator 1028 is configured to monitor the sampling voltage V SMPL has an amplitude of approximately zero, the first comparison signal CMP1 may be generated.

[0080] The power supply circuit 1000 further includes a switch controller 1030 that includes a state machine 1032. The first comparison signal CMP1 is provided to the state machine 1032, which also receives a second comparison signal CMP2 from a reference comparator 1034. In the example of FIG. OUT is the reference voltage V REF Based on the comparison signals CMP1 and CMP2, the state machine 1032 may generate switching signals IN, OUT, and S that are provided to each PFET P1, NFETs N1-N3, and switches SW1-SW9, respectively. Thus, the state machine 1032 may define the first and second switching phases of the switching voltage regulator 1002, and thus the switching period of the switching voltage regulator 1002. The state machine 1032 also provides controls for operating the switches SW1-SW9 to regulate the input current I IN In order to regulate the amplitude of the current regulator system 1008, operation of the current regulator system 1008 may be provided in each of the first and second switching phases.

[0081] Power supply circuit 1000 is not limited to the circuit shown in Figure 10. For example, switching voltage regulator 1002 is not limited to the arrangement of high-side and low-side switches P1, N1, N2, and N3. As an example, PFET P1 is instead arranged as an n-channel transistor.

[0082] The operation of the power supply circuit 1000 is shown in further detail in Figure 4 and Figures 11 to 13. Figure 11 is another example of a schematic electrical circuit diagram 1100 of the current flow in the power supply circuit 1000 in a first switching phase of the switching voltage regulator 1002, Figure 12 is another example of a schematic electrical circuit diagram 1200 of the current flow in the power supply circuit 1000 in a first switching phase of the switching voltage regulator 1002, and Figure 13 is another example of a schematic electrical circuit diagram 1300 of the current flow in the power supply circuit 1000 in a second switching phase of the switching voltage regulator 1002. Therefore, the description of Figure 11 will also refer to Figures 4 and 11 to 13.

[0083] In the first timing diagram 402, the switching voltage regulator 1002 begins a first switching phase at time T0. At time T0, PFET P1 and NFET N3 are activated by switching signals IN1 and OUT2, respectively. Thus, the input current I IN is the input voltage V IN From this, the current I L As a result, the current I L I L0 from the amplitude of I L1 This is shown as an increase to

[0084] 11 , switches SW1, SW4, SW7, and SW8 are closed by switching signals S1, S4, S7, and S8, respectively, from time T0 to time T1. Thus, from time T0 to T1, current I1 flows from current source 1010 through closed switches SW1 and SW4 to sampling node 1016. While current I1 is provided to sampling node 1016, a reference current I REF flows out of the sampling node 1016. As a result, the sampling capacitor C S Sampling current I via SMPL is provided. The current I SMPLTherefore, the current I1 is converted to the reference current I REF Therefore, the sampling current I SMPL is the sampling capacitor C S starts charging, and the sampling voltage V SMPLの During the first switching phase of the switching voltage regulator 1002, switch SW6 is open and switch SW7 is closed, so that the sampling comparator 1028 detects the sampling voltage V SMPL Therefore, the first comparison signal CMP1 is asserted at a logic high state.

[0085] Referring to the example of FIG. 4, at time T4, NFET N3 is deactivated by switching signal OUT2, and NFET N2 is activated by switching signal OUT1. Therefore, the input current I IN is the input voltage V IN From this, the current I L As a result, the current I L continues to increase in amplitude from time T4 to time T2 during the first switching phase of switching voltage regulator 1002. Also, referring to the example of Figure 12, switch SW1 is opened by switching signal S1, switches SW4, SW7, and SW8 remain closed, switch SW2 is closed by switching signal S2, and one of switches SW3 and SW9 is closed by a respective one of switching signals S3 and S9 depending on the operating mode of switching voltage regulator 1002.

[0086] For example, for buck mode operation of timing diagram 402 (and timing diagram 302 in the example of FIG. 3), switch SW3 is closed. However, for boost mode operation shown in timing diagram 304 in the example of FIG. 3, switch SW9 is closed instead. Thus, in a buck mode of operation, the amplitude of current I3 is added to the amplitude of current I2 at sampling node 1016, or in a boost mode of operation, the amplitude of current I3 is subtracted from the amplitude of current I2. Although the example of FIG. 12 shows an example where both switches SW3 and SW9 are closed simultaneously, at a given time, only one of switches SW3 and SW9 is closed depending on the mode of operation of switching voltage regulator 1002. Thus, current I1 is the charging current I provided to sampling node 1016 from time T0 to time T1. CH and the combination (addition or subtraction) of currents I2 and I3 may be the charging current I provided to sampling node 1016 from time T1 to time T2. CH It could be.

[0087] Based on the closure of the switch SW, the charging current I CH is provided to the sampling node 1016 during the first switching phase of the switching voltage regulator 1002. The charging current I CH is provided to the sampling node 1016 based on the closure of the switch SW8, while the reference current I REF flows out of the sampling node 1016. As a result, the sampling capacitor C S Through, the sampling current I SMPL is provided. The current I SMPL Therefore, the charging current I CH From the reference current I REF Therefore, the sampling current I SMPL is the sampling capacitor C S starts charging and the sampling voltage V SMPLDuring the first switching phase of the switching voltage regulator 1002, because switch SW6 is open and switch SW7 is closed, the sampling comparator 1028 increases the amplitude of the sampling voltage V SMPL Therefore, the first comparison signal CMP1 is asserted at a logic high state.

[0088] Referring back to FIG. 4, switching voltage regulator 1002 switches from the first switching phase to the second switching phase at time T2. At time T2, PFET P1 is deactivated, NFET N1 is activated, and NFET N2 remains activated by switching signals IN1 and IN2, respectively. Also, referring to the example of FIG. 13, switches SW2, SW3, SW9, SW4, and SW7 are opened by switching signals S1, S3, S9, S4, and S7, respectively, and switch SW6 is closed by switching signal S6. Switch SW8 remains closed during the second switching phase of switching voltage regulator 1002. Thus, current I IN stops, and the current I L flows from the low voltage rail, through NFET N1, through inductor L1, and through NFET N2. Thus, in the example of FIG. 4, the current I L At time T3, the amplitude I L2 from amplitude I L3 At time T3, NFET N2 is deactivated by switching signal OUT1 and NFET N3 is activated by switching signal OUT2. Thus, the current I L flows from the low voltage rail, through NFET N1, through inductor L1, and through NFET N3. Thus, in the example of FIG. 4, the current I L is the amplitude I at time T4 L3 from the initial amplitude I L0 This is shown as a decrease to

[0089] 13, in the second switching phase of the switching voltage regulator 1002, the currents I1, I2, and I3 stop. Therefore, the charging current I CH stops flowing to the sampling node 1016. However, the reference current I REF continues to flow from the sampling node 1016 to the sampling capacitor C S The result is a sampling voltage V SMPL decreases during the second switching phase of switching voltage regulator 1002, beginning at time T2.

[0090] Closing switch SW6 causes sampling comparator 1028 to sample voltage V SMPL is compared to the voltage at node 1018, and thus the sampling capacitor C S The voltage across the sampling voltage V SMPL In response to the sampling capacitor Cs having a logic low amplitude, and therefore a logic low charge on the sampling capacitor Cs, the sampling comparator 1028 may deassert the first comparison signal CMP1. In response to the deassertion of the first comparison signal CMP1, and in response to a logic low amplitude of the second comparison signal CMP2, as provided by the reference comparator 1034 (e.g., the reference voltage V REF is the output voltage V OUT In response to the reference current I being greater than 1, the state machine 1032 may change the state of the switching signals IN, OUT, and S. Thus, the state machine 1032 may switch the switching voltage regulator 1002 from the second switching phase to the first switching phase, and thus the start of the next switching period. Thus, the state machine 1032 may change the state of the reference current I REF Input current I IN Based on the amplitude of the sampling voltage V SMPL ) to indicate the duration of the switching period of the switching voltage regulator 1002, and the input current I IN Adjust the amplitude of.

[0091] Similar to the above, upon completion of the switching period, the state machine 1032 may implement an idle (e.g., sleep) mode for the power supply circuit 1000, such as based on a deactivated mode for the power supply circuit 1000 or a discontinuous operation mode for the switching voltage regulator 1002. For example, during the idle mode, the switch SW8 is opened by the switching signal S8 to supply the reference current I REF , and switch SW5 is closed by switching signal S5 to provide zeroing of sampling capacitor Cs. Switch SW6 may remain closed to latch the first comparison signal CMP1 provided by sampling comparator 1028. State machine 1032 may then wait for a change in state of the second comparison signal CMP2 to begin the next switching period.

[0092] Therefore, in the examples of FIGS. 7 to 13, the reference current I REF Input current I IN Based on the amplitude of the sampling voltage V SMPL Based on the input current I IN Here, another example of a power supply circuit that can regulate the input current I is described. Thus, similar to power supply circuit 200, power supply circuits 700 and 1000 regulate the input current I in a manner that is more efficient than input current regulation in a typical power supply circuit. IN For example, as described above, the current regulation of power supply circuits 700 and 1000 is implemented for more complex waveforms of inductor current I L and for non-zero initial amplitudes of inductor current I L. Power supply circuit 700 also regulates input current I L during each cycle of switching voltage regulator 702 in an open-loop manner that obviates the need for bandwidth-limiting stability compensation. IN , and therefore the inductor current I L Alternatively, the power supply circuit 1000 may provide a real-time measurement of the amplitude of the input current I IN and provides a measure of the estimated amplitude of the input current I INThus, the input current regulation provided by power supply circuits 700 and 1000 can be substantially more effective than the input current regulation of typical power supply circuits.

[0093] As used herein, the term "couple" may encompass any connection, communication, or signal path that enables a functional relationship consistent with the description herein. For example, if device A generates a signal to control a control device B to perform an action, (a) in a first example, device A is directly coupled to device B, and (b) in a second example, device A is indirectly coupled to device B via an intermediate component C, whereby the intermediate component C does not substantially change the functional relationship between device A and device B, and thus device B is controlled by device A via the control signal generated by device A.

[0094] Also, in this description, devices that are "configured" to perform certain tasks or functions may be configured (e.g., programmed and / or hardwired) to perform those functions by a manufacturer at the time of manufacture and / or they may be configurable (or reconfigurable) by a user after manufacture to perform those functions and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the devices, or through the configuration and / or layout of the hardware components and interconnections of the devices, or through a combination thereof. Also, a circuit or device described as including certain components may instead be configured to couple to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be configured to couple to at least some of the passive elements and / or sources, thereby forming the described structure, either at the time of manufacture or at a time thereafter, e.g., by an end user and / or a third party.

[0095] Modifications are possible in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. 1. A circuit comprising: a switching voltage regulator having a first input coupled to a source of input current, a second input, and an output; a current regulator having an input coupled to a source of the input current, a first output, and a second output, the current regulator having an input for receiving a sampling current in a first switching phase of the switching voltage regulator responsive to a switching signal, the sampling capacitor charging in response to the sampling current to generate a current sampling voltage; providing a comparison signal at the first output having a logic state responsive to the current sampling voltage; providing a reference current to the second output proportional to a maximum average amplitude set point of the input current over a switching period of the switching voltage regulator; the current regulator configured as follows: a switch controller having a first input coupled to a first output of the current regulator circuit, a second input coupled to an output of the switching voltage regulator, a third input adapted to be coupled to a reference voltage source, and an output coupled to the second input of the switching voltage regulator, the switch controller being configured to provide the switching signal; Including, The circuit wherein the sampling current has an amplitude equal to a charging current flowing into the sampling capacitor minus the reference current flowing from the sampling capacitor.

2. 2. The circuit of claim 1, The circuit wherein the charging current has an amplitude responsive to the input current.

3. 3. The circuit of claim 2, the sampling capacitor discharging during a second switching phase of the switching voltage regulator in response to the reference current flowing from the sampling capacitor to reduce the current sampling voltage; The circuit, wherein the switch controller monitors the current sampling voltage and switches from the second switching phase to the first switching phase in response to the current sampling voltage having an amplitude of approximately zero.

4. 3. The circuit of claim 2, the current regulator further includes a first transconductance amplifier configured to monitor the input current to generate the charging current in response to the input current, the charging current having an amplitude that is scaled proportionally to the input current.

5. 5. The circuit of claim 4, The current regulator a second transconductance amplifier configured to generate the reference current; a current mirror configured to mirror the reference current through a transistor coupled to the sampling capacitor; The circuit further comprises:

6. 3. The circuit of claim 2, The circuit, wherein the current regulator is further configured to switch between a plurality of current sources configured to provide a respective plurality of currents to generate the charging current in response to at least one of a step-down and step-up operation of the switching voltage regulator.

7. 2. The circuit of claim 1, The switch controller, a sampling comparator having an input for receiving the current sampling voltage and an output for providing a first comparison signal; a reference comparator having a first input for receiving the output voltage, a second input for receiving a reference voltage, and an output for providing a second comparison signal; a state machine having a first input for receiving the first comparison signal, a second input for receiving the second comparison signal, a first output providing a switching signal provided from an output of the switch controller, and a second output providing a switch control signal; The circuit includes:

8. 8. The circuit of claim 7, the current regulator further having a second input for receiving the switch control signal; The circuit, wherein the switch control signal controls a switch to provide a current path for each of the input current and the reference current to generate the current sampling voltage in response to a switching phase defined by the state machine.

9. 1. A power supply system, comprising: a switching voltage regulator including at least one switch configured to conduct an input current to generate an output voltage in response to a switching signal and an input voltage; a current regulator including a sampling capacitor responsive to the switching signal to sample a sampling current in a first switching phase of the switching voltage regulator, the current regulator being configured to generate a current sampling voltage responsive to an amplitude of the input current relative to a reference current defining a maximum average amplitude set point of the input current to set a switching time defining a switching period of the at least one switch, the sampling current having an amplitude equal to a charging current flowing into the sampling capacitor minus the reference current flowing from the sampling capacitor; a switch controller configured to provide the switching signal to control the at least one switch in response to an amplitude of the output voltage relative to a reference voltage and in response to the switching time; , a power system.

10. 10. The power supply system of claim 9, The charging current has an amplitude responsive to the input current.

11. 11. The power supply system of claim 10, the sampling capacitor discharging during a second switching phase of the switching voltage regulator in response to the reference current flowing from the sampling capacitor to reduce the current sampling voltage; the switch controller monitors the current sampling voltage and switches from the second switching phase to the first switching phase in response to the current sampling voltage having a magnitude of approximately zero; The switching time has an equal duration to the first and second switching phases.

12. 11. The power supply system of claim 10, the current regulator further comprises a first transconductance amplifier configured to monitor the input current to generate the charging current in response to the input current, the charging current having an amplitude scaled proportionally to the input current.

13. 13. The power supply system of claim 12, The current regulator a second transconductance amplifier configured to generate the reference current; a current mirror configured to mirror the reference current through a transistor coupled to the sampling capacitor; The power system further comprises:

14. 11. The power supply system of claim 10, 11. The power supply system of claim 1, wherein the current regulator is further configured to switch between a plurality of current sources configured to provide respective plurality of currents to generate the charging current responsive to at least one of a step-down and step-up operation of the switching voltage regulator.

15. 1. An integrated circuit (IC), comprising: a switching voltage regulator including at least one switch configured to conduct an input current to generate an output voltage in response to a switching signal and an input voltage; a current regulator configured to generate a current sampling voltage across a sampling capacitor, the current sampling voltage being responsive to an amplitude of the input current relative to a reference current proportional to a maximum average amplitude set point of the input current to set a switching time defining a switching period of the at least one switch, the sampling capacitor integrating a sampling current in a first switching phase of the switching voltage regulator in response to the switching signal to generate the current sampling voltage, the sampling current having an amplitude equal to a charging current flowing into the sampling capacitor minus the reference current flowing out of the sampling capacitor; an input pin adapted to be coupled to a source of said reference current; a switch controller configured to provide the switching signal to control the at least one switch in response to the switching time and in response to an amplitude of the output voltage relative to a reference voltage; Including, IC.

16. 16. The IC of claim 15, The charging current has an amplitude responsive to the input current.

17. 17. The IC of claim 16, the sampling capacitor discharging during a second switching phase of the switching voltage regulator in response to the reference current flowing from the sampling capacitor to decrease the current sampling voltage; the switch controller monitors the current sampling voltage and switches from the second switching phase to the first switching phase in response to the current sampling voltage having a magnitude of approximately zero; The switching time has an equal duration to the first and second switching phases.

18. 17. The IC of claim 16, the current regulator includes a first transconductance amplifier configured to monitor the input current to generate the charging current in response to the input current, the charging current having an amplitude that is scaled proportionally to the input current.

19. 20. The IC of claim 18, The current regulator a second transconductance amplifier configured to generate the reference current; a current mirror configured to mirror the reference current through a transistor coupled to the sampling capacitor; The IC further comprises:

20. 17. The IC of claim 16, The current regulator is configured to switch between a plurality of current sources configured to provide respective plurality of currents to generate the charging current in response to at least one of a step-down and step-up operation of the switching voltage regulator.

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