Data transmission method, device, apparatus and system, and computer-readable storage medium

Abstract

This application discloses a data transmission method, an apparatus, a device and a system, and a computer-readable storage medium. The data transmission method includes: a first chip obtains first data obtained through coding using a first forward error correction FEC code type; a second FEC code type is determined based on a reference clock frequency of the first chip and an output rate corresponding to the first FEC code type; coding the first data based on the second FEC code type to obtain second data; and transmitting the second data. A third chip receives the second data and decodes the second data based on the second FEC code type to obtain decoded data. According to the method, the coding gain of the second data is high, and when transmitting data in a channel prone to bit errors, error correction can be effectively performed on the data in which bit errors occur, thereby improving data transmission quality.

Description

[Technical field]

[0001] This application claims priority to Chinese Patent Application No. 202110099748.1, entitled "CODING AND DECODING METHOD, DEVICE, AND SYSTEM," filed on January 25, 2021, which is incorporated herein by reference in its entirety. This application further claims priority to Chinese Patent Application No. 202110185631.5, entitled "DATA TRANSMISSION METHOD, APPARATUS, DEVICE, AND SYSTEM, AND READABLE STORAGE MEDIUM," filed on February 10, 2021, which is incorporated herein by reference in its entirety.

[0002] TECHNICAL FIELD Embodiments of this application relate to the field of communication technologies, and in particular to data transmission methods, devices, apparatus and systems, and computer-readable storage media. [Background technology]

[0003] Forward error correction (FEC) is a data coding method that improves data transmission speed and transmission distance in a channel by providing parity bits to the transmitted data. In the data transmission process, the transmitting end uses a specific FEC code type to code the original data and then sends the coded data to the receiving end, where the received data is decoded using the same FEC code type to obtain the original data. Summary of the Invention

[0004] This application provides a data transmission method, apparatus, device and system, as well as a computer-readable storage medium, for extending FEC code types to accommodate high-speed and / or long-distance data transmission.

[0005] According to a first aspect, a data transmission method is provided, the method including: obtaining first data obtained through coding by a first chip using a first forward error correction (FEC) code type, determining a second FEC code type based on a reference clock frequency of the first chip and an output rate corresponding to the first FEC code type, coding the first data based on the second FEC code type to obtain second data, and transmitting the second data.

[0006] In this method, a second FEC code type is determined based on a reference clock frequency of a first chip for transmitting data and an output rate corresponding to the first FEC code type, and the first data obtained by coding using the first FEC code type is re-coded using the second FEC code type to obtain the second data by concatenated coding. Therefore, the second data has a higher coding gain, and when transmitting data through a channel prone to bit errors, error correction can be effectively performed on the data in which bit errors occur, thereby improving the data transmission quality. Additionally, since the second data is data obtained by directly coding based on the first data, the implementation process of this method is simple, and the data transmission efficiency is improved.

[0007] In a possible implementation, the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, the codeword length of the second data, and the information length in the codeword of the second data satisfy an overhead proportionality relationship, and determining the second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type includes determining the second FEC code type based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportionality relationship. By determining the second FEC code type based on the overhead proportionality relationship, the overhead obtained through coding using the second FEC code type can be secured, and the data transmission performance is further improved.

[0008] In a possible implementation, the overhead proportionality includes:

number

[0009] where n is the codeword length of the second data, k is the information length in the codeword of the second data, v1 is the output rate corresponding to the first FEC code type, p is an adjustment parameter, f is the reference clock frequency of the first chip, and p is a positive integer.

[0010] In a possible implementation, the codeword length of the second data has an integer multiple relationship with the number of logical channels to which the second data is distributed, and the integer multiple relationship is taken into consideration when the second FEC code type is determined, so that the determined second FEC code type is more suitable for the transmission scenario, and the data transmission performance is improved.

[0011] In a possible implementation, the first chip coding the first data based on the second FEC code type to obtain the second data includes the first chip distributing the first data to obtain a plurality of first sub-data, and the first chip separately coding the plurality of first sub-data based on the second FEC code type to obtain a plurality of second sub-data. The first chip transmitting the second data includes the first chip transmitting the plurality of second sub-data.

[0012] In a possible implementation, the first chip distributing the first data to obtain the plurality of first sub-data may include distributing the first data through a physical coding sublayer PCS channel to obtain the plurality of first sub-data, or distributing the first data through a first physical medium connection sublayer PMA channel to obtain the plurality of first sub-data. data to obtain a plurality of first sub-data.

[0013] In a possible implementation, the first chip transmitting the second data includes the first chip distributing the second data to obtain a plurality of third sub-data and transmitting the plurality of third sub-data via a plurality of logical channels.

[0014] In a possible implementation, before determining the second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type, the method further includes the first chip performing auto-negotiation with a third chip receiving the data transmitted by the first chip, and in response to an auto-negotiation result indicating that concatenated coding is required, the first chip determining the second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type. 。 Auto-negotiation is used to determine whether to perform concatenated coding, which is more suitable for the actual scenario requirements. available This is possible and more preferable.

[0015] In possible implementations, the first data is data in the first chip, or the first data is data received by the first chip and transmitted by the second chip. The first data may be data in the first chip, or may be received data transmitted by another chip, so the data transmission scenario to which the method is applied is flexible.

[0016] According to a first aspect, a data transmission method is provided. The method includes: a third chip receives second data, the second data being data obtained by coding the first data using a second forward error correction FEC code type, and the first data being data obtained via coding using the first FEC code type. The third chip decodes the second data based on the second FEC code type to obtain decoded data. The second data is obtained via coding the first data using the second FEC code type, and the first data is obtained via coding using the first FEC code type. Thus, the second data received by the third chip has a higher coding gain and a higher error correction capability. By decoding the second data, the obtained decoded data has a higher accuracy.

[0017] In a possible implementation, the third chip decoding the second data based on the second FEC code type includes the third chip performing soft-decision decoding on the second data based on the second FEC code type.

[0018] In a possible implementation, after the third chip decodes the second data based on the second FEC code type to obtain the decoded data, the method further includes the third chip recoding the decoded data based on the third FEC code type and transmitting the recoded data. By recoding the decoded data based on the third FEC code type, the data transmission quality of the next link can be protected.

[0019] In a possible implementation, the third FEC code type is the second FEC code type.

[0020] According to a fourth aspect, a data transmission device is provided, the device including: an acquisition module configured to acquire first data, the first data being data acquired through coding using a first forward error correction (FEC) code type; a determination module configured to determine a second FEC code type based on a reference clock frequency of the first chip and an output rate corresponding to the first FEC code type; a coding module configured to code the first data based on the second FEC code type to acquire second data; and a transmission module configured to transmit the second data.

[0021] In a possible implementation, a reference clock frequency of the first chip, an output rate corresponding to the first FEC code type, a codeword length of the second data, and an information length in the codeword of the second data satisfy an overhead proportionality relationship, and the determination module is configured to determine the second FEC code type based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportionality relationship.

[0022] In a possible implementation, the overhead proportionality includes:

number

[0023] where n is the codeword length of the second data, k is the information length in the codeword of the second data, v1 is the output rate corresponding to the first FEC code type, p is an adjustment parameter, f is the reference clock frequency of the first chip, and p is a positive integer.

[0024] In a possible implementation, the codeword length of the second data is in an integer multiple relationship with the number of logical channels over which the second data is distributed.

[0025] In a possible implementation, the coding module is configured to distribute the first data to obtain a plurality of first sub-data and separately code the plurality of first sub-data based on a second FEC code type to obtain a plurality of second sub-data. The transmission module is configured to transmit the plurality of second sub-data.

[0026] In a possible implementation, the coding module distributes the first data through a physical coding sublayer PCS channel to obtain a plurality of first subdata, or distributes the first subdata through a physical medium connection sublayer PMA channel. data to obtain a plurality of first sub-data.

[0027] In a possible implementation, the transmission module is configured to distribute the second data to obtain a plurality of third sub-data and transmit the plurality of third sub-data via a plurality of logical channels.

[0028] In a possible implementation, the apparatus further includes an auto-negotiation module configured to perform auto-negotiation with a third chip receiving data transmitted by the first chip, and in response to an auto-negotiation result indicating that concatenated coding is required, the determination module determines a second FEC code type based on a reference clock frequency of the first chip and an output rate corresponding to the first FEC code type.

[0029] In a possible implementation, the first data is data within the first chip, or the first data is data received by the first chip and transmitted by the second chip.

[0030] According to a fourth aspect, there is provided a data transmission apparatus, the apparatus including: a receiving module configured to receive second data, the second data being data obtained by coding the first data using a second forward error correction FEC code type, the first data being data obtained via coding using the first FEC code type, and a decoding module configured to decode the second data based on the second FEC code type to obtain decoded data.

[0031] In a possible implementation, the decoding module is configured to perform soft-decision decoding on the second data based on the second FEC code type to obtain decoded data.

[0032] In a possible embodiment, the apparatus further includes a coding module configured to recode the decoded data based on a third FEC code type, and a transmission module configured to transmit the recoded data.

[0033] In a possible implementation, the third FEC code type is the second FEC code type.

[0034] According to a first aspect, there is provided a data transmission device, the device including a processor, the processor coupled to a memory, the memory storing at least one program instruction or code, the at least one program instruction or code being loaded and executed by the processor, such that the apparatus implements the data transmission method according to the first aspect or the second aspect.

[0035] According to a sixth aspect, there is provided a data transmission system, the system including a first data transmission device configured to perform a method according to the first aspect or any one of its possible implementations, and a second data transmission device configured to perform a method according to the second aspect or any one of its possible implementations.

[0036] According to a seventh aspect, there is provided a computer readable storage medium storing at least one program instruction or code which, when loaded and executed by a processor, enables the computer to implement the data transmission method according to the first or second aspect.

[0037] Another communication device is provided. The device includes a communication interface, a memory, and a processor. The memory and the processor communicate with each other using an internal connection path. The memory is configured to store the memory. The processor executes instructions stored in the memory to control the communication interface to receive data and to control the communication interface to transmit data. When the processor executes the instructions stored in the memory, the processor is capable of performing the method in the first aspect or any one of the possible implementations of the first aspect, or performing the method in the second aspect or any one of the possible implementations of the second aspect.

[0038] In an exemplary embodiment, there are one or more processors and one or more memories.

[0039] In an exemplary embodiment, the memory may be integrated with the processor or the memory may be disposed separately from the processor.

[0040] In a particular implementation process, the memory may be a non-transitory memory such as a read-only memory (ROM). The memory and the processor may be integrated into one chip or may be separately arranged on different chips. The type of memory and the manner in which the memory and the processor are arranged are not limited in this embodiment of this application.

[0041] A computer program product is provided, which comprises computer program code that, when executed on a computer, enables the computer to carry out a method according to the aforementioned aspects.

[0042] A chip is provided, the chip including a processor configured to retrieve from the memory and execute instructions stored in the memory, such that a device in which the chip is installed performs the method in the aforementioned aspect.

[0043] Another chip is provided. The chip includes an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected to each other using an internal connection path. The processor is configured to execute code in the memory. When the code is executed, the processor is configured to execute the method in the aforementioned aspect.

[0044] A device is provided, comprising a chip according to any one of the preceding solutions.

[0045] A device is provided, the device including the first chip in any one of the preceding solutions and / or the third chip in any one of the preceding solutions.

[0046] In the above embodiment, during soft decoding, first, calculate the reliability (also called reliability) of each bit in the received codeword based on the received quantized soft decision information to obtain a reliability sequence, select M lowest reliability bit positions from the reliability sequence, and for the M lowest reliability bit positions, sequentially try bitwise flips for all combinations of 0, 1, 2, ... and N (N <= M) bit positions to obtain multiple test codewords, then perform hard decision decoding error correction for each test codeword, calculate the Euclidean distance between the reliability sequence and all corrected test codewords, and select the corrected test codeword corresponding to the minimum distance as the final corrected codeword output. If there is no correctable codeword in the test codeword, the hard decision result corresponding to the original received codeword is used as the output codeword. [Brief description of the drawings]

[0047] [Figure 1] 1 is a schematic diagram of an implementation scenario of a data transmission method according to an embodiment of this application;

[0048] [Diagram 2] 1 is a flowchart of a data transmission method according to an embodiment of the present application.

[0049] [Diagram 3] FIG. 2 is a schematic diagram of coding first data based on a second FEC code type according to an embodiment of the present application;

[0050] [Figure 4] FIG. 2 is a schematic diagram of distributing first data according to an embodiment of the present application;

[0051] [Diagram 5] FIG. 2 is a schematic diagram of distributing first data over a PCS channel according to an embodiment of the present application;

[0052] [Figure 6] FIG. 2 is a schematic diagram of distributing second data according to an embodiment of the present application;

[0053] [Figure 7] FIG. 13 is another schematic diagram of distributing second data according to an embodiment of the present application;

[0054] [Figure 8] FIG. 2 is a schematic diagram of another implementation scenario of a data transmission method according to an embodiment of this application;

[0055] [Figure 9] 1 is a schematic diagram of the structure of a data transmission device according to an embodiment of this application;

[0056] [Figure 10] FIG. 2 is a schematic diagram of the structure of another data transmission device according to an embodiment of this application;

[0057] [Figure 11] FIG. 2 is a schematic diagram of the structure of a data transmission device according to an embodiment of this application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0058] The terms used in the implementation section of this application are only used to describe a specific embodiment of this application and are not intended to limit this application. Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

[0059] In the field of communication technology, coding data by FEC is an important technical measure to reduce the bit error rate in the data transmission process and further improve the data transmission quality. In scenarios where the link rate is improved and the channel is more difficult, FEC with higher coding gain may be required. For example, for 800 gigabit Ethernet (GE) / 1.6 terabit Ethernet (TE) Ethernet interfaces, 200G 4th generation pulse amplitude modulation (PAM 4) optical links, the higher the transmission speed, the stricter the requirements for the channel and bit error rate, and after the bit error rate before correction is improved, the stronger the FEC, the lower the bit error rate after correction can be suppressed. In this regard, an embodiment of this application provides a data transmission method. In this method, a second FEC code type is determined based on a reference clock frequency of a first chip for transmitting data and an output rate corresponding to the first FEC code type, and the first data obtained by coding using the first FEC code type is re-coded using the second FEC code type to obtain the second data by concatenated coding. Therefore, the second data has a higher coding gain, and when transmitting data in a channel prone to bit errors, error correction can be effectively performed on the data in which bit errors occur, thereby improving the data transmission quality. Additionally, since the second data is data obtained by directly coding based on the first data, the implementation process of this method is simple, and the data transmission efficiency is improved. Additionally, the process of concatenated coding may be performed under a specific trigger condition.For example, in this method, the chip performs auto-negotiation, and based on the auto-negotiation result indicating that concatenated coding is required, performs a process of determining a second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type, so that the chip can proactively determine whether it needs to perform concatenated coding, which is more flexible in coding data transmitted on different channels.

[0060] The method in the embodiment of this application is applicable to the current Ethernet interface or another scenario that needs to transmit data. The implementation scenario shown in FIG. 1 is used as an example. The implementation scenario includes multiple chips, and the chips can exchange information to implement data transmission. As shown in FIG. 1, the data transmission may be performed between a first chip 101 and a second chip 102, and between the first chip 101 and a third chip 103. The implementation scenario shown in FIG. 1 may include N chips, where N is a positive integer equal to or greater than 2. In FIG. 1, only three chips are used as an example for illustration.

[0061] Referring to the implementation scenario shown in FIG. 1, the data transmission method provided in the embodiment of this application is shown in FIG. 2, including but not limited to steps 201 to 206.

[0062] Step 201: A first chip obtains first data, where the first data is data obtained through coding using a first FEC code type.

[0063] In possible implementations, the first data is data in the first chip, or the first data is data received by the first chip and transmitted by the second chip. For example, the first chip codes the original data using a first FEC code type to obtain the first data, and the second chip codes the original data using a first FEC code type to obtain coded data. The second chip scrambles the coded data to form the first data, and the first chip receives the first data transmitted by the second chip. For example, the second chip transmits the first data to the first chip via a physical channel. Whether the first data is data in the first chip or data transmitted from the second chip, other processing may be performed on the first data in addition to coding using the first FEC. For example, the first data may be data sent by the second chip to the first chip using a physical medium attachment sublayer (PMA) and / or physical media dependent (PMD) interface, or the first data may be data passing through a PMA and / or physical coding sublayer (PCS) in the first chip. Additionally, the first data may alternatively be data on which other processing is performed. For example, the first data is data after interleaving and distribution is performed.

[0064] The first FEC code type is not limited in this embodiment of the application. In a possible implementation, the first FEC code type is any one of a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a fire code, a turbo code, a turbo product code (TPC), a staircase code, and a low-density parity-check (LDPC) code.

[0065] Additionally, the first chip may directly transmit the first data after receiving the first data. In order to improve data transmission quality, the first data may alternatively be recoded. The triggering manner of performing concatenated coding by the first chip is not limited in this embodiment of the application. In a possible embodiment, the first chip performs auto-negotiation with a third chip that receives the data transmitted by the first chip, and in response to an auto-negotiation result indicating that concatenated coding is required, the first chip determines a second FEC code type based on the reference clock frequency of the first chip and an output rate corresponding to the first FEC code type. The auto-negotiation process may be performed after the first data is received or before the method is performed. The opportunity for auto-negotiation is not limited in this embodiment of the application, and it is only required that the auto-negotiation is performed before the first data is transmitted.

[0066] Step 202: Determine a second FEC code type according to a reference clock frequency of a first chip and an output rate corresponding to the first FEC code type.

[0067] In a possible implementation, the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, the code word length of the second data, and the information length in the code word of the second data satisfy an overhead proportionality relationship. Determining the second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type includes determining the second FEC code type based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportionality relationship. The second FEC code type is determined based on the overhead proportionality relationship, so that the overhead obtained through coding using the second FEC code type can be secured, and the data transmission performance is further improved.

[0068] In a possible implementation, the overhead proportionality includes:

number

[0069] where n is the codeword length of the second data, k is the information length in the codeword of the second data, v1 is the output rate corresponding to the first FEC code type, p is an adjustment parameter, f is the reference clock frequency of the first chip, and p is a positive integer.

[0070] It should be noted that there are different combinations of n, k, and p as long as the aforementioned overhead proportionality relationship can be satisfied. For example, the adjustment parameter is a reference value, for example, the adjustment parameter is an integer multiple of 10 or an integer multiple of 20. Based on the reference value, a second FEC code type that satisfies the overhead proportionality relationship is determined.

[0071] For example, the first FEC code type is RS(544,514), the reference clock frequency of the first chip is 156.25 megahertz (MHz), and the output rate corresponding to the first FEC code type is 106.25 gigabits per second (Gbps). (=106250 Megabits per second (Mbps)) For example, tone When the integral parameter is 720, n=144 and k=136, or n=180 and k=170.

[0072] In a possible implementation, when the second FEC code type is determined based on an overhead proportionality relationship, the second FEC code type may be determined by reference to Table 1, where all code types in Table 1 are BCH codes. [Table 1]

[0073] In Table 1, n is the codeword length, k is the information length in the codeword, and m is the number of bits in the finite field or Galois field in which the code is located, GF(2 m ), and t is the error correction capability. For example, BCH(180,170,m=10,t=1) indicates that the codeword length of the BCH code type is 180 bits, the length includes 0 extended bits, the information length in the codeword is 170 bits, m=10, and the error correction capability is 1. eBCH(161+1,153,m=8,t=1) indicates that the BCH code type is a BCH code type including extended bits, the codeword length is 162 bits, the length includes 1 extended bit, m=8, and the error correction capability is 1. The principles of the other BCH code types in Table 1 are the same as those of the BCH code types mentioned above. The details will not be described again here.

[0074] In a possible implementation, the codeword length of the second data is in an integer multiple relationship with the number of logical channels through which the second data is distributed. The logical channel may be a PCS channel or an FEC channel. When the second FEC code type is determined, the integer multiple relationship is taken into account, so that the determined second FEC code type is more suitable for the transmission scenario, and the data transmission performance is improved. For example, when the number of logical channels through which the second data is distributed is 8, the codeword length of the second data is an integer multiple of 8. Of course, the number of logical channels may alternatively be 1, i.e., the second data is transmitted through one logical channel. Since the codeword length of the second data is a positive integer, the codeword length of the second data is also in an integer multiple relationship with the number of logical channels through which the second data is distributed.

[0075] The manner of determining the second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type includes, but is not limited to, the following three manners:

[0076] Scheme 1: The first chip first determines a first set based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportionality relationship, and the first set includes a plurality of FEC code types that satisfy the overhead proportionality relationship. Then, the second FEC code type is determined from the first set based on the integer multiple relationship between the codeword length and the logical channel during distribution.

[0077] Scheme 2: The first chip first determines a second set based on an integer multiple relationship between the second codeword length and the logical channel during distribution, and the second set includes a plurality of FEC code types that satisfy the integer multiple relationship. Then, the second FEC code type is determined from the second set based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type based on the overhead proportional relationship.

[0078] Method 3: The first chip first determines a first set based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportionality relationship, and the first set includes a plurality of FEC code types that satisfy the overhead proportionality relationship. Then, a second set is determined based on an integer multiple relationship between the codeword length and the logical channel being distributed, and the second set includes a plurality of FEC code types that satisfy the integer multiple relationship, and the second FEC code type is determined based on the first set and the second set. For example, the first chip determines the second FEC code type based on the intersection of the first set and the second set.

[0079] It should be noted that the second FEC code type may be any one of an RS code, a BCH code, a Fire code, a Turbo code, a Turbo product code, a Staircase code, or an LDPC code. The type of the second FEC code type is not limited in this embodiment of this application.

[0080] Step 203: The first chip codes the first data according to the second FEC code type to obtain second data.

[0081] In a possible implementation, if the first data is data in the first chip, the first chip may code the first data based on the second FEC code type to obtain the second data. If the first data is data received by the first chip and transmitted by the second chip, the first chip may directly code the data based on the second FEC code type to obtain the second data. The first chip may perform simple operations other than decoding on the received data, such as bit mux and bit demux.

[0082] For example, if the first data is one data, the first chip codes the first data based on the second FEC code type to obtain the second data, and the first data may be data directly received by the first chip, or may be data obtained by interleaving multiple sub-data distributed by the first chip. In this case, the first data is considered as a whole, and the first data is coded using the second FEC code type. Optionally, if there are multiple first data, for example multiple first data transmitted by the second chip, the first chip codes each first data separately based on the second FEC code type to obtain multiple second data. As shown in FIG. 3, the first chip receives third data through an Attachment Unit Interface (AUI), and processes the third data using a Physical Media Attachment Sublayer (PMA) to obtain multiple first data. The first chip codes the multiple first data separately to obtain multiple second data. The acquired multiple second data may be transmitted over multiple physical channels (physical channels 1-N in FIG. 5) and then transmitted to the outside using PMA, physical medium dependent (PMD), etc. In some embodiments, in FIG. 3, the second chip may be a physical layer (PHY) chip in a network device, e.g., a router or switch, and the first chip may be a chip in an optical module, or a clock data recovery (CDR) / retimer chip. The PHY chip may be a chip located on the board of the network device.The chip may be a central processing unit (CPU), a network processor (NP), a neural network processing unit (NPU), a field programmable gate array (FPGA), a programmable logic controller (PLC), etc., or any combination thereof.

[0083] In a possible implementation, the first chip coding the first data based on the second FEC code type to obtain the second data, whether one first data or multiple first data, includes the first chip distributing the first data to obtain multiple first sub-data, and the first chip separately coding the multiple first sub-data based on the second FEC code type to obtain multiple second sub-data. For example, the process may be as shown in FIG.

[0084] For example, the manner in which the first chip distributes the first data to obtain a plurality of first sub-data includes, but is not limited to, the following two manners.

[0085] Manner 1: The first chip distributes the first data through the logical channel to obtain a plurality of first sub-data.

[0086] For example, the first chip distributes the first data through N logical channels to obtain a plurality of first sub-data, where each logical channel is used to transmit one first sub-data, and the logical channel may be a PCS channel or an FEC channel. The first chip separately codes the plurality of first sub-data based on a second FEC code type to obtain a plurality of second sub-data. For example, the process may be as shown in FIG. 5. The obtained plurality of second sub-data may be separately transmitted to the outside using a PMA, a PMD, etc.

[0087] Method 2: The first chip distributes the first data through the PMA to obtain multiple first sub-data.

[0088] Step 204: The first chip transmits the second data.

[0089] The first chip transmits the second data through a logical channel, and the logical channel may be a PCS channel or an FEC channel. In possible implementations, for the number of data transmission channels, the first chip transmits the second data in the following two cases, including but not limited to:

[0090] Case 1: The number of channels is 1.

[0091] In case 1, the first chip transmits second data through the channel, and the second data may be one piece of data or may include multiple second sub-data.

[0092] Case 2: The number of channels is a positive integer greater than or equal to 2.

[0093] In case 2, the first chip distributes the second data to obtain multiple third sub-data, and transmits multiple third sub-data through multiple logical channels. For example, the first chip distributes the second data in a round-robin distribution. For example, as shown in FIG. 6, there are N logical channels, and N is a positive integer equal to or greater than 2. The first chip distributes the second data in a round-robin distribution to obtain N third sub-data, and transmits the N third sub-data through the N logical channels. For example, each of the N logical channels transmits one third sub-data correspondingly. The N third sub-data include, but are not limited to, being transmitted to the next chip through the PMA and the PMD.

[0094] For example, when the first data is one piece of data, after coding the first data using a second FEC code type to obtain the second data, the first chip distributes the second data to obtain a plurality of third sub-data, and transmits the plurality of third sub-data through a plurality of logical channels. When the first data is distributed as a plurality of first sub-data, any one of the plurality of first sub-data is coded using a second FEC code type to obtain the second sub-data, and the first chip distributes the plurality of second sub-data to obtain a plurality of third sub-data, and transmits the plurality of third sub-data through a plurality of logical channels. For example, the first chip distributes any one of the plurality of second sub-data in a round robin manner. Taking the system shown in FIG. 7 as an example, the plurality of second sub-data is obtained through coding using a second FEC code type. For each second sub-data, the first chip distributes the second sub-data to obtain N pieces of third sub-data (N is a positive integer equal to or greater than 2), and the multiple third sub-data are distributed through N logical channels, for example, each of the N logical channels transmits one piece of third sub-data correspondingly.

[0095] The above-mentioned steps 201 to 204 are all processes in which the first chip side performs data transmission. Hereinafter, the third chip side is used as an example to explain the data transmission method.

[0096] Step 205: The third chip receives second data, where the second data is data obtained by coding the first data using the second FEC code type, and the first data is data obtained via coding the first data using the first FEC code type.

[0097] In a possible implementation, the third chip receives the second data transmitted by the first chip via a logical channel.

[0098] Step 206: The third chip decodes the second data according to the second FEC code type to obtain decoded data.

[0099] The second data is obtained by coding the first data using a second FEC code type, and the first data is obtained by coding the first data using the first FEC code type. Thus, the second data received by the third chip has a higher coding gain and a higher error correction capability. By decoding the second data, the obtained decoded data has a higher accuracy.

[0100] In a possible implementation, the third chip performs auto-negotiation with the first chip transmitting the second data, and in response to an auto-negotiation result indicating a need to perform decoding, the third chip decodes the second data based on the second FEC code type to obtain decoded data.

[0101] The third chip decoding the second data based on the second FEC code type may include, but is not limited to, the third chip performing soft decision decoding on the second data based on the second FEC code type. For example, the third chip performing soft decision decoding on the second data based on the second FEC code type to obtain decoded data may include the third chip obtaining a first sequence of the second FEC code type based on the second data, the first sequence including a plurality of symbol elements. The third chip separately assigns a reliability metric to each of the plurality of symbol elements, the third chip determines at least one least reliable location based on the reliability metric, the third chip obtains an error pattern based on the at least one least reliable location, and corrects the first sequence based on the error pattern. The third chip obtains a first sequence based on the corrected first sequence. D The code is executed to obtain a first codeword set, and then the codewords in the first codeword set are mapped, and the third chip obtains the decoded data based on the mapping result.

[0102] In a possible implementation, after the third chip decodes the second data based on the second FEC code type to obtain the decoded data, the method further includes the third chip recoding the decoded data based on the third FEC code type and transmitting the recoded data. By recoding the decoded data based on the third FEC code type, the data transmission quality of the next link can be protected. The third FEC code type is not limited in this embodiment of this application. For example, the third FEC code type is a second FEC code type, and the second FEC code type may be the same as the second FEC code type for coding the second data, or may be another second FEC code type that satisfies the above-mentioned overhead proportionality relationship and the relationship that the codeword length is an integer multiple of the number of logical channels being distributed.

[0103] For example, as shown in Fig. 8, after the third chip decodes the second data based on the second FEC code type to obtain the decoded data, the third chip needs to send the decoded data to the fourth chip, and the fourth chip may process the received data as the processing manner of the first chip. For example, the decoded data is recoded according to the processing of steps 202 to 204 described above, and the recoded data is transmitted. Optionally, the fourth chip alternatively decodes the received data based on the first FEC code type to obtain the service data.

[0104] According to the method provided in this embodiment of the present application, a second FEC code type is determined based on a reference clock frequency of a first chip for transmitting data and an output rate corresponding to the first FEC code type, and the first data obtained by coding using the first FEC code type is re-coded using the second FEC code type to obtain the second data by concatenated coding, so that the second data has a higher coding gain and can effectively perform error correction on the data with bit errors when transmitting data through a channel prone to bit errors, thereby improving the data transmission quality.

[0105] Additionally, since the second data is obtained by directly coding the first data, the implementation process of the method is simple and the data transmission efficiency is improved.

[0106] Additionally, the method includes a process in which the chip performs auto-negotiation, and based on the auto-negotiation result indicating that concatenated coding is required, determines a second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type, so that the chip can proactively determine whether it needs to perform concatenated coding, which is more flexible in coding data transmitted on different channels.

[0107] An embodiment of this application further provides a data transmission device. FIG. 9 is a schematic diagram of the structure of a data transmission device according to an embodiment of this application. The data transmission device shown in FIG. 9 can perform all or part of the operations performed by the first chip based on the following multiple modules shown in FIG. 9. It should be understood that the device may include more additional modules than the modules shown, or may omit some of the modules shown. This is not limited in the embodiment of this application. As shown in FIG. 9, the device includes: an acquisition module 901 configured to acquire first data, where the first data is data acquired through coding using a first FEC code type; a determination module 902 configured to determine a second FEC code type based on a reference clock frequency of the first chip and an output rate corresponding to the first FEC code type; a coding module 903 configured to code the first data based on the second FEC code type to acquire second data; and a transmission module 904 configured to transmit the second data.

[0108] In a possible implementation, the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, the codeword length of the second data, and the information length in the codeword of the second data satisfy an overhead proportionality relationship, and the determination module 902 is configured to determine the second FEC code type based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportionality relationship.

[0109] In a possible implementation, the overhead proportionality includes:

number

[0110] where n is the codeword length of the second data, k is the information length in the codeword of the second data, v1 is the output rate corresponding to the first FEC code type, p is an adjustment parameter, f is the reference clock frequency of the first chip, and p is a positive integer.

[0111] In a possible implementation, the codeword length of the second data is in an integer multiple relationship with the number of logical channels over which the second data is distributed.

[0112] In a possible implementation, the coding module 903 is configured to distribute the first data to obtain a plurality of first sub-data and separately code the plurality of first sub-data based on a second FEC code type to obtain a plurality of second sub-data. The transmission module 904 is configured to transmit the plurality of second sub-data.

[0113] In a possible implementation, the coding module 903 distributes the first data over a PCS channel to obtain a plurality of first sub-data, or distributes the first data over a PMA channel to obtain a plurality of first sub-data. data to obtain a plurality of first sub-data.

[0114] In a possible implementation, the transmission module 904 is configured to distribute the second data to obtain a plurality of third sub-data, and transmit the plurality of third sub-data via a plurality of logical channels.

[0115] In a possible implementation, the apparatus further includes an auto-negotiation module configured to perform auto-negotiation with a third chip receiving data transmitted by the first chip, and in response to an auto-negotiation result indicating that concatenated coding is required, the determination module 902 performs a step of determining a second FEC code type based on a reference clock frequency of the first chip and an output rate corresponding to the first FEC code type.

[0116] In a possible implementation, the first data is data within the first chip, or the first data is data received by the first chip and transmitted by the second chip.

[0117] FIG. 10 is a schematic diagram of the structure of a data transmission device according to an embodiment of this application. The data transmission device shown in FIG. 10 can perform all or part of the operations performed by the third chip based on the following multiple modules shown in FIG. 10. It should be understood that the device may include more additional modules than the modules shown, or may omit some of the modules shown. This is not limited in the embodiment of this application. As shown in FIG. 10, the device includes a receiving module 1001 configured to receive second data, where the second data is data obtained through coding the first data using a second FEC code type, and a decoding module 1002 that decodes the second data based on the second FEC code type to obtain decoded data.

[0118] In a possible implementation, the decoding module 1002 is configured to perform soft-decision decoding on the second data based on the second FEC code type to obtain decoded data.

[0119] In a possible embodiment, the apparatus further includes a coding module configured to recode the decoded data based on a third FEC code type, and a transmission module configured to transmit the recoded data.

[0120] In a possible implementation, the third FEC code type is the first FEC code type or the second FEC code type.

[0121] When the device provided in FIG. 9 and FIG. 10 implements the functions of the device, the division into the above-mentioned functional modules is only used as an example for explanation. In actual applications, the above-mentioned functions may be assigned to different functional modules for implementation based on requirements. In other words, the internal structure of the device is divided into different functional modules to implement all or part of the functions described above. Additionally, the embodiments of the device and the method provided in the above embodiments are related to the same concept. For the specific implementation process of the device, please refer to the embodiment of the method. The details will not be described again here.

[0122] An embodiment of the present application provides a data transmission device, the device including a processor, the processor coupled to a memory, the memory storing at least one program instruction or code, the at least one program instruction or code being loaded and executed by the processor, such that the data transmission device implements a method in any of the above method embodiments.

[0123] Please refer to FIG. 11. FIG. 11 is a schematic diagram of the structure of a data transmission device 1100 according to an embodiment of this application. The data transmission device 1100 is a sender / receiver device. The data transmission device 1100 shown in FIG. 11 is configured to perform operations related to the data transmission method shown in FIG. 2. The data transmission device 1100 is, for example, a network device such as a switch, a router, or another device (for example, a server or a PC) including a chip-connected mode. The hardware structure of the data transmission device 1100 includes a communication interface 1101 and a processor 1102. Optionally, the communication interface 1101 and the processor 1102 are connected via a bus 1104. The communication interface 1101 is configured to obtain the first data and transmit the second data. The processor may store instructions or program codes and execute the functions performed by the first chip or the functions performed by the third chip by calling the instructions or program codes. Optionally, the network device further includes a memory 1103. The memory 1103 stores instructions or program codes. The processor 1102 is configured to call the instructions or program codes in the memory 1103, so that the network device executes the relevant processing steps of the first chip in the above-mentioned method embodiment. In a particular embodiment, the data transmission device 1100 in this embodiment of the present application may include the first chip in the above-mentioned method embodiment. The processor 1102 in the data transmission device 1100 reads the instructions or program codes in the memory 1103, so that the data transmission device 1100 shown in FIG. 11 can execute all or part of the operations executed by the first chip.

[0124] In a specific embodiment, the data transmission device 1100 in this embodiment of the present application includes the first chip in the above-mentioned method embodiment. The processor 1102 in the data transmission device 1100 reads instructions or program codes in the memory 1103, so that the data transmission device 1100 shown in FIG. 11 can perform all or part of the operations performed by the third chip.

[0125] For example, the processor 1102 may be, for example, a general purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits configured to implement the solutions of this application. For example, the processor 1102 may include an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The PLD may be, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor may implement or execute various exemplary logic blocks, modules, and circuits described in connection with the contents disclosed in the embodiments of the present invention. Alternatively, the processor may be a combination of processors that implement computing functions, including, for example, a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0126] Optionally, the data transmission device 1100 further includes a bus. The bus is configured to transfer information between components of the data transmission device 1100. The bus may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, etc. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used to represent a bus in FIG. 11, but this does not mean that there is only one bus or only one type of bus. In addition to being connected via a bus, the components of the data transmission device 1100 in FIG. 11 may be connected in other ways. In this embodiment of the present invention, the connection manner of the components is not limited.

[0127] For example, the memory 1103 may be a read-only memory (ROM), another type of static storage device capable of storing static information and instructions, a random access memory (RAM) or another type of dynamic storage device capable of storing information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM), or other compact disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile optical discs, Blu-ray discs, etc.), a disk storage medium or another magnetic storage device, or any other medium capable of carrying or storing program code contemplated in the form of instructions or data structures and accessible by a computer. However, the memory is not so limited. For example, the memory 1103 may exist independently and be connected to the processor 1102 via a bus. Alternatively, the memory 1103 may be integrated with the processor 1102.

[0128] The communication interface 1101 is any transceiver type device and is configured to communicate with another device or a communication network. The communication network may be an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The communication interface 1101 includes a wired communication interface and may further include a wireless communication interface. Specifically, the communication interface 1101 may be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. In this embodiment of the application, the communication interface 1101 may be used for the data transmission device 1100 to communicate with another device.

[0129] In a particular implementation, in one embodiment, the processor 1102 may include one or more CPUs. Each processor may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0130] In a particular embodiment, the data transmission device 1100 may include multiple processors. Each processor may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0131] In a particular implementation, in one embodiment, the data transmission device 1100 may alternatively include an output device and an input device. The output device may communicate with the processor 1102 and display information in a number of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED), a cathode ray tube (CRT) display device, or a projector. The input device may communicate with the processor 1102 and receive input by a user in a number of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensing device.

[0132] In some embodiments, the memory 1103 may be configured to store program code for performing the solutions of this application, and the processor 1102 may execute the program code stored in the memory 1303. In other words, the data transmission device 1100 may implement the data transmission method provided in the method embodiments using the processor 1102 and the program code in the memory 1103. The program code may include one or more software modules. Optionally, the processor 1102 may store program code or instructions for performing the solutions of this application.

[0133] In a particular embodiment, the data transmission device 1100 in this embodiment of the present application may include the first chip in the above-mentioned method embodiment. The processor 1102 in the data transmission device 1100 reads the program code in the memory 1102 or the program code or instructions stored in the processor 1102, so that the data transmission device 1100 shown in FIG. 11 can perform all or part of the operations performed by the first chip.

[0134] In a specific embodiment, the data transmission device 1100 in this embodiment of the present application includes a third chip in the above-mentioned method embodiment. The processor 1102 in the data transmission device 1100 reads the program code in the memory 1102 or the program code or instructions stored in the processor 1102, so that the data transmission device 1100 shown in FIG. 11 can perform all or part of the operations performed by the third chip.

[0135] The data transmission device 1100 may further correspond to the devices shown in Figures 9 and 10. Each functional module in the devices shown in Figures 9 and 10 is implemented using software in the data transmission device 1100. In other words, the functional modules included in the devices shown in Figures 9 and 10 are generated after the processor 1102 of the data transmission device 1100 reads the program code stored in the memory 1103.

[0136] The steps of the data transmission method shown in FIG. 2 may be completed using instructions in the form of integrated logic circuits or software in the processor of the data transmission device 1100. The steps of the method disclosed with reference to the embodiments of this application may be directly executed by a hardware processor, or may be executed using a combination of hardware and software modules in the processor. The software modules may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and performs the steps in the aforementioned method in combination with the hardware in the processor. To avoid repetition, the details will not be described again here.

[0137] An embodiment of the present application further provides a data transmission system, the system including a first optical transmission device and a second optical transmission device, the first data transmission device configured to perform the method performed by the first chip shown in FIG. 2, and the second data transmission device configured to perform the method performed by the third chip shown in FIG. 2.

[0138] For the functions of the first data transmission device and the second data transmission device in this system, please refer to the related description shown in Figure 2. The details will not be described again here.

[0139] It is noted that the processor may be a central processing unit (CPU), another general-purpose processor, a digital signal processing (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like. The general-purpose processor may be a microprocessor, any conventional processor. It is noted that the processor may be a processor supporting the advanced reduced instruction set computing machine (ARM) architecture.

[0140] Further, in any embodiment, the memory may include read-only memory and random access memory to provide instructions and data to the processor. The memory may further include non-volatile random access memory. For example, the memory may further store device type information.

[0141] The memory may be volatile or nonvolatile memory or may include both volatile and nonvolatile memory. The nonvolatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM) and is used as an external cache. For example, but not limited to, many forms of RAM may be used, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous dynamic random access memory (synchlink DRAM, SLDRAM), and direct rambus random access memory (DR RAM).

[0142] A computer-readable storage medium is further provided, which stores at least one program instruction or code, which, when loaded and executed by a processor, enables the computer to implement the data transmission method shown in FIG.

[0143] This application provides a computer program product, which when executed by a computer, enables the processor or computer to perform corresponding steps and / or procedures in the aforementioned method embodiments.

[0144] A chip is provided, the chip including a processor configured to retrieve from the memory and execute instructions stored in the memory, such that a device in which the chip is installed performs the method in the aforementioned aspect.

[0145] Another chip is provided. The chip includes an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected to each other using an internal connection path. The processor is configured to execute code in the memory. When the code is executed, the processor is configured to execute the method in the aforementioned aspect.

[0146] A device is provided, comprising a chip according to any one of the preceding solutions.

[0147] A device is provided, the device including the first chip in any one of the preceding solutions and / or the third chip in any one of the preceding solutions.

[0148] In some embodiments, in FIGS. 1-8, the second chip may be a physical layer (PHY) chip in a sending device, e.g., a router, switch, or server, and the first chip may be an interface of the sending device, e.g., a chip in an optical module, or a CDR / retimer chip. The third chip may be an interface of a receiving device, e.g., a chip in an optical module, or a CDR / retimer chip, and the fourth chip may be a physical layer (PHY) chip in the receiving device. The PHY chip may be a chip located on the board of a computing device, and the chip may be a CPU, a network processor (NP), a neural network processing unit (NPU), a field programmable gate array (FPGA), a programmable logic controller (PLC), or the like, or any combination thereof.

[0149] In some embodiments, the first chip communicates with the second chip using the AUI. In some embodiments, the third chip communicates with the fourth chip using the AUI.

[0150] In the above embodiment, during soft decoding, first, calculate the reliability (also called reliability) of each bit in the received codeword based on the received quantized soft decision information to obtain a reliability sequence, select M lowest reliability bit positions from the reliability sequence, and for the M lowest reliability bit positions, sequentially try bitwise flips for all combinations of 0, 1, 2, ... and N (N <= M) bit positions to obtain multiple test codewords, then perform hard decision decoding error correction for each test codeword, calculate the Euclidean distance between the reliability sequence and all corrected test codewords, and select the corrected test codeword corresponding to the minimum distance as the final corrected codeword output. If there is no correctable codeword in the test codeword, the hard decision result corresponding to the original received codeword is used as the output codeword.

[0151] All or part of the aforementioned embodiments may be implemented using software, hardware, firmware, or any combination thereof. When software is used to implement the aforementioned embodiments, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the procedures or functions according to this application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired (e.g., coaxial cable, optical fiber, or digital subscriber line) or wireless (e.g., infrared, radio, or microwave) manner. The computer-readable storage medium may be any available medium accessible by a computer, or a data storage device integrating one or more available media, such as a server or data center. The media available may be magnetic (e.g., floppy disk, hard disk, or magnetic tape), optical (e.g., DVD), or semiconductor (e.g., solid-state drive, SSD )) etc.

[0152] In the above specific implementation, the objectives, technical solutions and beneficial effects of this application are described in more detail. It should be understood that the above description is only a specific implementation of this application, and is not intended to limit the protection scope of this application. Any modifications, equivalent replacements or improvements made based on the technical solutions of this application shall be included in the protection scope of this application.

[0153] Those skilled in the art may recognize with reference to the embodiments disclosed in this specification that the method steps and modules may be implemented using software, hardware, firmware, or any combination thereof. In order to clearly explain the compatibility of hardware and software, the steps and configurations of each embodiment are generally described above based on functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but the implementation should not be considered to go beyond the scope of this application.

[0154] Those skilled in the art may understand that all or part of the steps of the embodiment may be implemented by hardware or a program that instructs related hardware. The program may be stored in a computer-readable storage medium. The storage medium may include a read-only memory, a magnetic disk, or an optical disk.

[0155] When software is used to implement the aforementioned embodiments, all or part of the embodiments may be implemented in the form of a computer program product. A computer program product includes one or more computer program instructions. For example, the methods in the embodiments of this application may be described in the context of machine-executable instructions. The machine-executable instructions are included in program modules that execute, for example, on a target real or virtual processor device. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., that perform particular tasks or implement particular abstract data structures. In various embodiments, the functionality of the program modules may be combined or split among the described program modules. The machine-executable instructions for the program modules may be executed in a local or distributed device. In a distributed device, the program modules may be located in both local and remote storage media.

[0156] The computer program code used to implement the methods in the embodiments of this application may be written in one or more programming languages. The computer program code may be provided to a processor of a general purpose computer, a special purpose computer, or another programmable data processing apparatus, so that when the program code is executed by the computer or another programmable data processing apparatus, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on the computer, partially on the computer, as a separate software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0157] In the context of the embodiments of this application, the computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. For example, the carrier may include a signal, a computer readable medium, etc.

[0158] For example, signals may include electrical, optical, radio, acoustic, or other forms of propagated signals such as carrier wave and infrared signals.

[0159] A machine-readable medium may be any tangible medium that contains or stores a program for use in or relating to an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More specific examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0160] For convenience and simplicity of description, the detailed work processes of the aforementioned systems, devices and modules may be referred to corresponding processes in the aforementioned method embodiments, which will be clearly understood by those skilled in the art, and the details will not be described herein.

[0161] In some embodiments provided in this application, it should be understood that the disclosed system, device, and method can be implemented in other ways. For example, the described device embodiment is merely an example. For example, the module division is merely a logical function division, and may be other divisions in actual implementation. For example, multiple modules or components may be combined or integrated into another system, and some features may be omitted or not implemented. Additionally, the shown or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces, and the indirect couplings or communication connections between devices or modules may be electrical, mechanical, or other forms of connection.

[0162] The modules described as separate parts may or may not be physically separate, and the parts shown as units may or may not be physical units, may be located in one location, or may be distributed across multiple network modules. Some or all of the modules may be selected based on actual requirements to achieve the objectives of the solutions in the embodiments of this application.

[0163] Additionally, the functional modules in the embodiments of this application may be integrated into one processor module, each module may exist physically alone, or two or more units may be integrated into one unit. The integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0164] When the integrated module is implemented in the form of a software function module and sold or used as an independent product, the integrated module may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of this application may be implemented essentially in the form of a software product, the part contributing to the related technology may be implemented in the form of a software product, or all or part of the technical solution may be implemented in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of this application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0165] In this application, the terms "first", "second", etc. are used to distinguish between the same or similar items whose effects and functions are essentially the same. It should be understood that there is no logical or time sequence dependency between "first", "second", and "nth", and the number and execution sequence are not limited. It should also be understood that the terms "first", "second", etc. are used in the following description to describe various elements, but these elements should not be limited by the terms. These terms are merely used to distinguish one element from another element. For example, without departing from the scope of the various examples, a first network device may be referred to as a second network device. Similarly, a second network device may be referred to as a first network device. Both the first network device and the second network device may be network devices, and in some cases, may be separate and distinct network devices.

[0166] It should be further understood that the sequence numbers of the processes do not mean the execution sequence in the embodiment of this application. The execution sequence of the processes should be determined based on the functions and internal logic of the processes, and should not be construed as any restriction on the implementation process of the embodiment of this application.

[0167] In this application, the term "at least one" means one or more, and the term "multiple" means two or more. For example, a plurality of second packets means two or more second messages. The terms "system" and "network" may be used interchangeably in this specification.

[0168] It should be understood that the terminology used in the description of the various examples in this specification is intended to describe particular examples only and is not intended to constitute a limitation. The singular terms "one" ("a" and "an") and "the" used in the description of the various examples and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0169] It will be further understood that as used in this specification, the term "comprising" (or "comprises", "including", "comprising" and / or "comprising") specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0170] It is further understood that the term "if" may be interpreted to mean "when" ("when" or "when"), "in response to determining," or "in response to detecting." Similarly, depending on the context, the phrases "when it is determined that" or "when (the stated condition or event) is detected" may be interpreted to mean "when it is determined that," "in response to determining," "when (the stated condition or event) is detected," or "in response to detecting (the stated condition or event)."

[0171] It should be understood that determining B based on A does not mean that B is determined based only on A, but that B may be determined based on A and / or other information.

[0172] It should be further understood that references throughout this specification to "one embodiment," "one embodiment," or "possible implementations" mean that a particular feature, structure, or characteristic associated with an embodiment or implementation is included in at least one embodiment of this application. Thus, the appearances of "in one embodiment," "in one embodiment," or "in a possible implementation" throughout this specification do not necessarily refer to the same embodiment. Additionally, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. 1. A data transmission method, comprising: acquiring, by a first chip, first data, the first data being data acquired via coding using a first forward error correction (FEC) code type; coding, by the first chip, the first data based on a second FEC code type to obtain second data, the second FEC code type being associated with a reference clock frequency of the first chip and an output rate corresponding to the first FEC code type; transmitting, by the first chip, the second data.

2. a reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, a codeword length of the second data, and an information length in the codeword of the second data satisfy an overhead proportional relationship; The method comprises: determining the second FEC code type based on a reference clock frequency of the first chip, an output rate corresponding to the first FEC code type, and the overhead proportionality; The overhead proportionality relationship is [0010] Including, 2. The method of claim 1, wherein n is a codeword length of the second data, k is an information length in a codeword of the second data, v1 is the output rate corresponding to the first FEC code type, p is an adjustment parameter, f is the reference clock frequency of the first chip, and p is a positive integer.

3. The method of claim 2 , wherein the codeword length of the second data is in an integer multiple relationship to the number of logical channels over which the second data is distributed.

4. Coding, by the first chip, the first data based on the second FEC code type to obtain second data, distributing, by the first chip, the first data to obtain a plurality of first sub-data, and separately coding, by the first chip, the plurality of first sub-data based on the second FEC code type to obtain a plurality of second sub-data; Transmitting, by the first chip, the second data, The method according to any one of claims 1 to 2, comprising transmitting the plurality of second sub-data by the first chip.

5. Distributing the first data by the first chip to obtain a plurality of first sub-data, Distributing, by the first chip, the first data through a physical coding sublayer (PCS) channel to obtain the plurality of first sub-data; or 5. The method of claim 4, further comprising: distributing, by the first chip, the first data through a physical medium attachment sublayer (PMA) channel to obtain the plurality of first sub-data.

6. Transmitting, by the first chip, second data, 3. The method according to claim 1, further comprising: distributing, by the first chip, the second data to obtain a plurality of third sub-data, and transmitting the plurality of third sub-data via a plurality of logical channels.

7. before determining the second FEC code type based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportionality; performing auto-negotiation by the first chip with a third chip that receives data transmitted by the first chip; 3. The method of claim 2, further comprising: in response to an auto-negotiation result indicating that concatenated coding is required, determining, by the first chip, the second FEC code type based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportionality.

8. The method according to any one of claims 1 to 2, wherein the first data is data within the first chip, or the first data is data received by the first chip and transmitted by a second chip.

9. A data transmission device applied to a first chip, comprising: a capture module configured to capture first data, the first data being data captured via coding using a first forward error correction (FEC) code type; a coding module configured to code the first data based on a second FEC code type to obtain second data, the second FEC code type being associated with a reference clock frequency of the first chip and an output rate corresponding to the first FEC code type; a transmission module configured to transmit the second data.

10. a reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, a codeword length of the second data, and an information length in the codeword of the second data satisfy an overhead proportional relationship; The apparatus further includes a determination module configured to determine the second FEC code type based on a reference clock frequency of the first chip, an output rate corresponding to the first FEC code type, and the overhead proportionality; The overhead proportionality relationship is [0025] Including, 10. The apparatus of claim 9, wherein n is a codeword length of the second data, k is an information length in a codeword of the second data, v1 is the output rate corresponding to the first FEC code type, p is an adjustment parameter, f is the reference clock frequency of the first chip, and p is a positive integer.

11. The apparatus of claim 10 , wherein the codeword length of the second data is in an integer multiple relationship to a number of logical channels over which the second data is distributed.

12. the coding module is configured to distribute the first data to obtain a plurality of first sub-data and separately code the plurality of first sub-data based on the second FEC code type to obtain a plurality of second sub-data; The apparatus according to any one of claims 9 to 10, wherein the transmission module is configured to transmit the plurality of second sub-data.

13. 13. The apparatus of claim 12, wherein the coding module is configured to distribute the first data over a physical coding sublayer (PCS) channel to obtain the plurality of first sub-data, or distribute the first data over a physical medium attachment sublayer (PMA) channel to obtain the plurality of first sub-data.

14. The apparatus according to any one of claims 9 to 10, wherein the transmission module is configured to distribute the second data to obtain a plurality of third sub-data, and transmit the plurality of third sub-data via a plurality of logical channels.

15. 11. The apparatus of claim 10, further comprising: an auto-negotiation module configured to perform auto-negotiation with a third chip that receives data transmitted by the first chip, and in response to an auto-negotiation result indicating that concatenated coding is required, the determination module determines the second FEC code type based on a reference clock frequency of the first chip, an output rate corresponding to the first FEC code type, and the overhead proportionality.

16. The apparatus of any one of claims 9 to 10, wherein the first data is data within the first chip, or the first data is data received by the first chip and transmitted by a second chip.

17. A data transmission system comprising a first data transmission device and a second data transmission device, the first data transmission device being configured to perform the method according to any one of claims 1 to 8.

18. A computer program comprising at least one program instruction or code, said program instruction or code being loaded and executed by a processor, causing the computer to implement the method according to any one of claims 1 to 8.

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