Current sensing circuit and DC / DC converter

Abstract

To provide a current sense circuit capable of widening an in-phase input range while reducing the size of a circuit scale, and a DC / DC converter.SOLUTION: Resistors R4 and R5 are connected in series between a junction point between an emitter of a transistor Q1 and a resistor R1 and a junction point between an emitter of a transistor Q2 and a resistor R2. A voltage V1 at a junction point between the resistor R4 and the resistor R5 and a predetermined voltage (V+-V2) are compared and when the junction point voltage V1 is higher than the predetermined voltage (V+-V2), a current I1 flows through transistors MP6 and MN5, a current M×I1 flows through a transistor MN4, and a current M×I1 / 2 flows from the resistor R1 and the resistor R2 toward a junction point between the resistors R4 and R5.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a current sensing circuit and a DC / DC converter. [Background technology]

[0002] As a current sense circuit that outputs a current detection signal Vis corresponding to a voltage drop occurring in a sense resistor Rs, for example, the one described in Patent Document 1 has been proposed. As shown in Fig. 5, the current sense circuit described in Patent Document 1 includes transistors Q11 to Q13 and resistors R11 to R15. The transistors Q11 to Q13 are configured by PNP transistors.

[0003] The base-emitter voltage V of transistor Q11 BEQ11 is the minimum operating voltage V BEQ11MIN It needs to be higher. V BEQ11 =VIN-(VR13+VR11)>V BEQ11MIN …(1) VIN: Input voltage applied to one end of the sense resistor Rs VR13: Voltage across resistor R13 VR11: Voltage across resistor R11

[0004] For this reason, the common-mode input voltage of the input voltage VIN is as shown in the following equation (2), and it cannot handle low input voltages VIN. VIN>VR13+VR11+V BEQ11MIN …(2)

[0005] That is, conventional current sense circuits have a problem in that the range of common-mode input voltage is narrow. Therefore, a technology has been proposed to widen the common-mode input range by providing an operational amplifier that is effective when the common-mode input range is low and an operational amplifier that is effective when the common-mode input range is high (Patent Document 2).

[0006] However, the technique of Patent Document 2 requires two operational amplifiers, which results in a large circuit scale and an increase in chip size. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Pat. No. 5,378,998 [Patent Document 2] JP 2018-179571 A Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a current sense circuit and a DC / DC converter that can widen the common-mode input range while reducing the circuit scale. [Means for solving the problem]

[0009] In order to achieve the above-mentioned object, a current sense circuit and a DC / DC converter according to the present invention are characterized by the following [1] to [6]. [1] A current sense circuit that outputs a current detection signal corresponding to a voltage drop occurring in a sense resistor, a first transistor having a collector-emitter connected between a power supply line to which a second input voltage is supplied and one end of the sense resistor; a second transistor having a collector-emitter connected between the power supply line and the other end of the sense resistor, a base connected to the base of the first transistor, and a base-collector connected thereto; a first resistor connected between one end of the sense resistor and the emitter of the first transistor; a second resistor connected between the other end of the sense resistor and the emitter of the second transistor, the second resistor having the same resistance as the first resistor; a third transistor having an emitter connected to the emitter of the second transistor and a base connected to the collector of the first transistor; a current detection signal generating circuit having a third resistor connected between the power supply line and the collector of the third transistor; a fourth resistor and a fifth resistor, each having the same resistance value, connected in series between a connection point between the emitter of the first transistor and the first resistor and a connection point between the emitter of the second transistor and the second resistor; a common-mode input range expanding circuit including a current supply circuit that compares a voltage corresponding to a first input voltage input to one end of the sense resistor with a predetermined voltage, and, when the voltage corresponding to the first input voltage is higher than the predetermined voltage, causes a current to flow from the one end of the sense resistor and the other end of the sense resistor toward a connection point of the fourth resistor and the fifth resistor. It is a current sensing circuit. [2] A current sense circuit according to [1], The current supply circuit includes: a comparison circuit including a fourth transistor and a fifth transistor whose sources are connected to each other, and a first current source that supplies a current to the fourth transistor and the fifth transistor, in which a voltage according to the first input voltage is supplied to a gate of the fourth transistor, and the predetermined voltage is supplied to a gate of the fifth transistor; a first current mirror circuit that outputs a current corresponding to a current flowing through the fifth transistor from a connection point between the fourth resistor and the fifth resistor. It is a current sensing circuit. [3] [1] or [2], wherein the current sense circuit is The voltage according to the first input voltage is a voltage at a junction between the fourth resistor and the fifth resistor. It is a current sensing circuit. [4] A current sense circuit according to any one of [1] to [3], The common mode input range expansion circuit comprises: The sixth transistor includes a plurality of sixth transistors that are diode-connected and connected in series with each other, and a second current source that supplies a current to the sixth transistors, and a voltage generating circuit that generates the predetermined voltage according to a voltage generated across the plurality of sixth transistors. It is a current sensing circuit. [5] A current sense circuit according to any one of [1] to [4], a third current source that supplies a constant current; a second current mirror circuit that copies the current of the third current source and supplies the copied current to the collectors of the first transistor and the second transistor, respectively; and a third current mirror circuit that copies the current of the third current source and flows the copied current from the emitters of the first transistor and the second transistor toward ground. It is a current sensing circuit. [6] A coil and A capacitor to which one end of the coil is connected; a seventh transistor that is provided between a voltage source to which a second input voltage is supplied and the other end of the coil, and that turns on and off the supply of the second input voltage to the coil; a sense resistor provided between one end of the coil and the capacitor; a control circuit for controlling the on / off of the seventh transistor to output an output voltage obtained by converting the second input voltage. 1. A DC / DC converter comprising: The control circuit includes: a current sense circuit according to any one of claims 1 to 5, which outputs a current detection signal corresponding to a voltage drop occurring across the sense resistor; generating a signal for turning on and off the seventh transistor based on a comparison between an error signal corresponding to a difference between a voltage corresponding to the output voltage and a reference voltage and a slope signal corresponding to the current detection signal; It is a DC / DC converter. Effect of the Invention

[0010] The current sense circuit and DC / DC converter according to the present invention have the advantage that the common-mode input range can be widened while the circuit scale is reduced.

[0011] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following description of the preferred embodiment of the present invention (hereinafter, referred to as "embodiment") with reference to the accompanying drawings. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a circuit diagram showing an embodiment of a DC / DC converter incorporating a current sensing circuit of the present invention. [Diagram 2] FIG. 2 is a circuit diagram showing details of the current sensing circuit shown in FIG. [Diagram 3] FIG. 3 is a circuit diagram for explaining the operation of the current sense circuit shown in FIG. 2 when the input voltage VIN is low. [Figure 4] FIG. 4 is a circuit diagram for explaining the operation of the current sense circuit shown in FIG. 2 when the input voltage VIN is high. [Diagram 5] FIG. 5 is a circuit diagram showing an example of a conventional current sensing circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0014] The current sense circuit 4 of the present invention is used in the DC / DC converter 1 shown in Fig. 1. The DC / DC converter 1 senses an input voltage V +and outputs it as output voltage Vout. The DC / DC converter 1 includes a MOS transistor MP11, a diode D, a coil Lout, a capacitor Cout, voltage detection resistors R21 and R22, a sense resistor Rs for current detection, and a control IC2 as a control circuit that controls the on / off of the MOS transistor MP11.

[0015] The MOS transistor MP11 is a P-channel field effect transistor. The source of the MOS transistor MP11 is connected to the input voltage V + is supplied to the control IC 2, the drain of which is connected to the coil Lout and the cathode of the diode D, and the gate of which is connected to the gate terminal GATE of the control IC 2. The anode of the diode D is connected to the ground GND.

[0016] One end of the coil Lout is connected to the drain of the MOS transistor MP11, and the other end is connected to one end of the capacitor Cout via a sense resistor Rs. An output voltage Vout is output from one end of the capacitor Cout. The other end of the capacitor Cout is connected to the ground GND.

[0017] The voltage detection resistors R21 and R22 are connected in parallel to the capacitor Cout and in series with each other. The end of the voltage detection resistor R21 opposite the connection point with the voltage detection resistor R22 is connected to one end of the capacitor Cout. The end of the voltage detection resistor R22 opposite the connection point with the voltage detection resistor R21 is connected to the ground GND. As a result, the detection voltage Vouts (= a voltage according to the output voltage Vout) obtained by dividing the output voltage Vout by the voltage detection resistors R21 and R22 is supplied to the feedback terminal FB of the control IC2.

[0018] The sense resistor Rs is connected between the coil Lout and the capacitor Cout. Both ends of the sense resistor Rs are connected to the input terminals INP and INN of the control IC2, respectively.

[0019] The control IC2 controls the on / off of the MOS transistor MP11 so that the detection voltage Vouts becomes the reference voltage Vref. The control IC2 includes an error detection circuit 3, a current sense circuit 4, an oscillator 5, an adder 6, a PWM comparator 7, a flip-flop 8, a MOS transistor MN11, a NOT circuit 9, and a driver 10.

[0020] The error detection circuit 3 receives the detection voltage Vouts at its inverting input and the reference voltage Vref at its non-inverting input, and outputs an error signal Verr that is the difference between the detection voltage Vouts and the reference voltage Vref. The current sense circuit 4 outputs a current detection signal Vis that corresponds to the voltage drop Rs×Is (=current flowing through the sense resistor Rs) that occurs across the sense resistor Rs. The oscillator 5 outputs a clock signal CLOCK and a triangular wave Vramp synchronized with the clock signal CLOCK. The adder 6 outputs a slope signal Vslope that is the sum of the triangular wave Vramp and the current detection signal Vis. The PWM comparator 7 receives the error signal Verr at its inverting input and the slope signal Vslope at its non-inverting input, and outputs a comparison signal Vcomp that compares the error signal Verr with the slope signal Vslope.

[0021] The flip-flop 8 has a set terminal S to which the clock signal CLOCK is input, and a reset terminal R to which the comparison signal Vcomp is input. The output terminal Q of the flip-flop 8 is connected to the input of a NOT circuit 9, and the output of the NOT circuit 9 is input to a driver 10. The output of the driver 10 is connected to the gate of a MOS transistor MP11. Meanwhile, the inverted output terminal QB of the flip-flop 8 is connected to the gate of a MOS transistor MN11. The MOS transistor MN11 is composed of an N-channel field effect transistor. The drain of the MOS transistor MN11 is connected to the non-inverted input of the PWM comparator 7, and the source is connected to ground GND.

[0022] With the above configuration, when the clock signal CLOCK rises, the flip-flop 8 is set, the output terminal Q goes to H level, and the MOS transistor MP11 turns on. After that, when Vslope>Verr, the comparison signal Vcomp is inverted, the flip-flop 8 is reset, the output terminal Q goes to L level, and the MOS transistor MP11 turns off. Also, the inverted output terminal QB of the flip-flop 8 goes to H level, the MOS transistor MN11 turns on, and the slope signal Vslope is reset to 0V.

[0023] Next, details of the above-mentioned current sense circuit 4 will be described with reference to Fig. 2. As shown in the figure, the current sense circuit 4 includes a current detection signal generation circuit 41 for outputting a current detection signal Vis equivalent to a voltage drop Rs×Is occurring in the sense resistor Rs, a common-mode input range expansion circuit 42 for expanding the common-mode input range of the current detection signal generation circuit 41, and an input bias reduction circuit 43 for reducing the input bias current.

[0024] The current detection signal generating circuit 41 has transistors Q1 to Q3 as first to third transistors, and resistors R1 to R3 as first to third resistors. The transistors Q1 to Q3 are configured from NPN-type bipolar transistors. The transistor Q1 is connected to a voltage V + The collector and emitter of the transistor Q1 are connected between a power supply line to which a second input voltage is supplied and one end of the sense resistor Rs. To explain in more detail, the collector of the transistor Q1 is connected to the power supply line via the drain and source of the MOS transistor MP3, and the emitter is connected to one end of the sense resistor Rs via the resistor R1 and the input terminal INP.

[0025] The collector and emitter of the transistor Q2 are connected between the power supply line and the other end of the sense resistor Rs. In more detail, the collector of the transistor Q2 is connected to the power supply line via the drain and source of the MOS transistor MP4, and the emitter is connected to the other end of the sense resistor Rs via the resistor R2 and the input terminal INN.

[0026] The bases of the transistors Q1 and Q2 are connected to each other, and the base and collector of the transistor Q2 are connected. That is, the transistors Q1 and Q2 form a current mirror circuit. The resistor R1 is connected between one end of the sense resistor Rs and the emitter of the transistor Q1, and the resistor R2 is connected between the other end of the sense resistor Rs and the emitter of the transistor Q2. The resistors R1 and R2 have the same resistance value (R1=R2).

[0027] The base of the transistor Q3 is connected to the collector of the transistor Q1 and the drain of the MOS transistor MP3, and the emitter is connected to the emitter of the transistor Q2 and the resistor R2. The collector of the transistor Q3 is connected to the power supply line via the resistor R3.

[0028] With the above configuration, the emitter currents Ie1 and Ie2 of transistors Q1 and Q2 are equal due to the action of the current mirror circuit formed by transistors Q1 and Q2. When current Is does not flow through sense resistor Rs, equal emitter currents Ie1 and Ie2 flow through resistors R1 and R2, respectively, and the emitters of transistors Q1 and Q2 are at the same potential. In contrast, when current Is flows through sense resistor Rs, a potential difference is created in the emitters of transistors Q1 and Q2 by the voltage drop Rs×Is across sense resistor Rs. For this reason, transistor Q3 flows emitter current Ie3, as shown in the following equation (3), so that the emitters of transistors Q1 and Q2 are equal. Ie3 = Is × Rs / R1 … (3)

[0029] Therefore, a current detection signal Vis corresponding to the current Is is generated across the resistor R3 as shown in the following equation (4). Vis = Is × Rs × R3 / R1 … (4) As is clear from equation (4), R3 / R1 is the amplification factor (gain).

[0030] By the way, the base-emitter voltage V of transistor Q1 BEQ1 is the minimum operating voltage V BEQ1MINIt needs to be higher. V BEQ1 =(V + -VIN)-(V DSMP3 +VR1)>V BEQ1MIN …(5) V DSMP3 : Drain-source voltage of MOS transistor MP3 VR1: Voltage across resistor R1

[0031] For this reason, the common-mode input voltage of the input voltage VIN as the first input voltage input to the input terminal INP is as shown in the following equation (6), and the current detection signal generating circuit 41 cannot handle a high input voltage VIN. VIN <V + -(V BEQ1MIN +V DSMP3 +VR1) …(6)

[0032] Therefore, in this embodiment, a common-mode input range expansion circuit 42 is provided. The common-mode input range expansion circuit 42 includes resistors R4 and R5 as fourth and fifth resistors, and a current supply circuit 421. The resistors R4 and R5 are connected in series between the connection point of the emitter of the transistor Q1 and the resistor R1, and the connection point of the emitter of the transistor Q2 and the resistor R2. The resistors R4 and R5 have the same resistance value.

[0033] The current supply circuit 421 is connected to the junction voltage V1 of the resistors R4 and R5 and a predetermined voltage (V + -V2), and the connection point voltage V1 is compared with a specified voltage (V + When the input voltage Vcc is higher than -V2, as shown in Fig. 4, a constant current M x I1 / 2 flows from a path from one end of the sense resistor Rs to resistor R1 via the input terminal INP and from a path from the other end of the sense resistor Rs to resistor R2 via the input terminal INN toward the connection point of resistors R4 and R5. Here, M represents a mirror ratio set in a first current mirror circuit 424, which will be described later. Next, the configuration of this current supply circuit 421 will be described. The current supply circuit 421 includes a comparison circuit 422, a voltage generation circuit 423, a first current mirror circuit 424, a diode D1, and a resistor R6.

[0034] The comparison circuit 422 compares the voltage V1 at the junction of resistors R4 and R5 with a predetermined voltage (V + -V2). The connection point voltage V1 is equal to the input voltage VIN and is a voltage that corresponds to the input voltage VIN. The comparison circuit 422 includes MOS transistors MP5 and MP6 as the fourth and fifth transistors, and a constant current source 422A as the first current source. The MOS transistors MP5 and MP6 are configured by P-channel field effect transistors.

[0035] The sources of the MOS transistors MP5 and MP6 are connected to each other and to the other end of the constant current source 422A. The drain of the MOS transistor MP5 is connected to the ground GND, and the drain of the MOS transistor MP6 is connected to the ground GND via the drain-source of a MOS transistor MN5 described later. A connection point voltage V1 is supplied to the gate of the MOS transistor MP5. Note that, in this embodiment, the drain of the MOS transistor MP5 is connected to the ground GND, but this is not limiting. For example, it may be connected to the ground GND via a resistor.

[0036] A certain voltage (V + When a diode D1, which will be described later, is in a non-conducting state, the current flowing through the resistor R6 is zero. In other words, a predetermined voltage (V + When a diode D1 (to be described later) is in a conductive state, a predetermined voltage (V + A voltage obtained by subtracting the voltage drop caused by the current flowing through resistor R6 from -V2) is supplied.

[0037] The constant current source 422A is a current source that supplies a constant current I1 to the MOS transistors MP5 and MP6. One end of the constant current source 422A is connected to the power supply line, and the other end is connected to the sources of the MOS transistors MP5 and MP6.

[0038] With the above configuration, the connection point voltage V1>predetermined voltage (V + -V2), a constant current I1 flows through the MOS transistor MP6, and the current flowing through the MOS transistor MP5 is zero. + -V2), a constant current I1 flows through the MOS transistor MP5, and the current flowing through the MOS transistor MP6 becomes zero.

[0039] The voltage generating circuit 423 generates a predetermined voltage (V + The circuit has transistors Q4 to Q6 as a plurality of sixth transistors and a constant current source 423A as a second current source. These transistors Q4 to Q6 are formed of NPN bipolar transistors, and generate a voltage V + The transistors Q4 to Q6 are connected in series between a power supply line through which power is supplied and a resistor R6 connected to the gate of the MOS transistor MP6. The transistors Q4 to Q6 have their bases and collectors connected together, forming a diode connection. The constant current source 423A is connected between the transistors Q4 to Q6 and the ground GND. The constant current source 423A supplies a constant current I2 to the transistors Q4 to Q6. When the constant current I2 is supplied to the transistors Q4 to Q6, a voltage V2 is generated, and a predetermined voltage (V + -V2) is supplied.

[0040] The voltage V2 is set as shown in the following equation (7): That is, the number of transistors Q4 to Q6 is set. V2>(V BEQ1MIN +V DSMP3 ) …(7)

[0041] The first current mirror circuit 424 has MOS transistors MN4 and MN5. The MOS transistors MN4 and MN5 are composed of N-channel field effect transistors. The gates of the MOS transistors MN4 and MN5 are connected to each other, and the sources are connected to the ground GND. The drain of the MOS transistor MN4 is connected to the gate of the MOS transistor MP5. The gate and drain of the MOS transistor MN5 are connected. The drain of the MOS transistor MN5 is connected to the drain of the MOS transistor MP6. In addition, the gate aspect ratio of the MOS transistors MN4 and MN5 is set to M:1. As a result, the mirror ratio of the first current mirror circuit is M.

[0042] With the above configuration, the connection point voltage V1>predetermined voltage (V + -V2), and when a constant current I1 flows through the MOS transistor MP6, the constant current I1 is supplied to the MOS transistor MN5. A current (M×I1) according to the constant current I1 flowing through the MOS transistor MN5 flows as a drain current of the MOS transistor MN4. As a result, as shown in FIG. 4, a constant current M×I1 / 2 flows from a path that flows from one end of the sense resistor Rs through the input terminal INP to the resistor R1, and from a path that flows from the other end of the sense resistor Rs through the input terminal INN to the resistor R2, toward the connection point of the resistors R4 and R5, and a constant current M×I1 flows from the connection point toward the MOS transistor MN4.

[0043] The diode D1 has the role of protecting the MOS transistor MP6 from excessive voltage application between the gate and source. The anode is connected to the gate of the MOS transistor MP6, and the cathode is connected to the gate of the MOS transistor MP5. Specifically, when the input voltage VIN is low and the power line voltage V +is high, a voltage greater than the voltage at the source of the MOS transistor MP6 may be applied to the gate of the MOS transistor MP6. Even in such a case, the diode D1 limits the gate of the MOS transistor MP6 to a voltage V1+VF, which is the sum of the junction voltage V1 and the forward voltage VF of the diode D1, so that the MOS transistor MP6 can be protected. Note that even in such a case where the diode is in a conductive state, the junction voltage V1<predetermined voltage (V + −V2), a constant current I1 flows through the MOS transistor MP5, and the current flowing through the MOS transistor MP6 becomes zero.

[0044] The resistor R6 is a resistor for limiting the current flowing from the diode D1 to the junction point of the resistors R4 and R5 to an extremely small current value when the gate of the MOS transistor MP6 is limited to the above-mentioned voltage V1+VF and the diode D1 is in a conductive state. In other words, the resistor R6 is set to a large resistance value.

[0045] According to the common-mode input range expansion circuit 42 having the above-mentioned configuration, when the input voltage VIN is low, the connection point voltage V1<a predetermined voltage (V + -V2). In this case, as shown in Figure 3, a constant current I1 flows through the MOS transistor MP5, and the currents flowing through the MOS transistors MP6, MN4, and MN5 are zero. Therefore, the currents flowing through the resistors R4 and R5 are also zero. Because the resistors R4 and R5 can be ignored, the circuit operates in the same way as the conventional circuit, and the current detection signal Vis is expressed by the above equation (4).

[0046] On the other hand, when the input voltage VIN becomes high, the voltage V2 is set as shown in equation (7), so the input voltage VIN becomes V + -(V BEQ1MIN +V DSMP3 ) before the connection point voltage V1 exceeds a certain voltage (V +In this case, as shown in FIG. 4, a constant current I1 flows through the MOS transistors MP6, MN4, and MN5, and the current flowing through the MOS transistor MP5 is zero. Therefore, a current of M×I1 / 2 flows through the resistors R1, R2, R4, and R5, lowering the emitter potential of the transistors Q1 and Q2. This ensures the operating voltage of the transistors Q1 and Q2, and the common-mode input voltage of the input voltage VIN becomes the voltage V + The current flowing through resistors R1 and R4 is equal to the current flowing through resistors R2 and R5. Therefore, the difference Ie1-Ie2 between the emitter currents of transistors Q1 and Q2 does not change, and the current detection signal Vis also remains unchanged as expressed by the above equation (4).

[0047] According to the above-described current sense circuit 4, the common-mode input range expanding circuit 42 can widen the common-mode input range while reducing the circuit scale.

[0048] According to the above-described current sense circuit 4, the common-mode input range expansion circuit 42 includes the MOS transistors MP5 and MP6, a comparison circuit 422 including a constant current source 422A, and a first current mirror circuit 424. This makes it possible to realize, with a simple configuration, a condition in which the connection point voltage V1>a predetermined voltage (V + When the load current V is -V2, a current M×I1 / 2 can flow through resistors R4 and R5.

[0049] Moreover, according to the above-described current sense circuit 4, the connection point voltage V1 is supplied to the gate of the MOS transistor MP5 as a voltage corresponding to the input voltage VIN. This makes it possible to supply a voltage corresponding to the input voltage VIN to the gate of the MOS transistor MP5 with a simple configuration.

[0050] According to the above-described current sense circuit 4, the common-mode input range expansion circuit 42 has a voltage generation circuit 423 including a plurality of transistors Q4 to Q6 and a constant current source 423A. This allows a predetermined voltage (V + -V2) can be generated.

[0051] Next, the input bias reduction circuit 43 will be described. The input bias reduction circuit 43 has a constant current source 431 as a third current source, a second current mirror circuit 432, and a third current mirror circuit 433. The constant current source 431 is connected between the drain of the MOS transistor MP1 and the ground GND, and is a constant current source that generates a constant current I3.

[0052] The second current mirror circuit 432 copies the constant current I3 and supplies it to the collectors of the transistors Q1 and Q2, respectively. The second current mirror circuit 432 has MOS transistors MP1, MP3, and MP4. The MOS transistors MP1, MP3, and MP4 are the same size. The MOS transistors MP1, MP3, and MP4 are each composed of a P-channel field effect transistor. The MOS transistor MP1 has a source connected to a voltage V + The drain is connected to a power supply line through which a current is supplied, and the drain is connected to a constant current source 431. The drain and gate of the MOS transistor MP1 are connected to each other.

[0053] The gate of the MOS transistor MP3 is connected to the gate of the MOS transistor MP1, and the source is connected to the voltage V + The MOS transistor MP4 has a gate connected to the gate of the MOS transistor MP1 and a source connected to the power supply line supplied with a voltage V + is connected to the power supply line, and its drain is connected to the collector of transistor Q2.

[0054] The third current mirror circuit 433 copies the constant current I3 using MOS transistors MP2 and MN1, and causes the copied constant current I3 to flow from the emitters of the transistors Q1 and Q2 to the ground GND. The third current mirror circuit 433 has MOS transistors MP2, MN1, MN2, and MN3. The MOS transistor MP2 has the same size as the MOS transistor MP1. The MOS transistors MN1, MN2, and MN3 have the same size. The MOS transistor MP2 has a gate connected to the gate of the MOS transistor MP1 and a source connected to a voltage V + The drain of the MOS transistor MN1 is connected to the drain of the MOS transistor MP2 and the source is connected to the ground GND. The gate and drain of the MOS transistor MN1 are connected to each other.

[0055] The gate of the MOS transistor MN2 is connected to the gate of the MOS transistor MN1, the drain is connected to the connection point between the transistor Q1 and the resistor R1, and the source is connected to the ground GND. The gate of the MOS transistor MN3 is connected to the gates of the MOS transistors MN1 and MN2, the drain is connected to the connection point between the transistor Q2 and the resistor R2, and the source is connected to the ground GND.

[0056] According to the above configuration, the second current mirror circuit 432 supplies a constant current I3 to the collectors of the transistors Q1 and Q2. The third current mirror circuit 433 copies the constant current I3 to the drains of the MOS transistors MN2 and MN3. When the drain currents of the MOS transistors MP3 and MP4 are equal to the drain currents of the MOS transistors MN3 and MN4, all of the currents flowing from the emitters of the transistors Q1 and Q2 flow to the MOS transistors MN2 and MN3, and the input bias currents output from the input terminals INP and INN can be set to zero.

[0057] According to the above-described embodiment, the input bias reduction circuit 43 can reduce the input bias current flowing through the input terminals INP, INN, and can reduce the increase in the output voltage Vout when there is no load.

[0058] According to the above-described DC / DC converter 1, the sense resistor Rs is provided between the coil Lout and the capacitor Cout. As a result, loss occurs in the sense resistor Rs whether the MOS transistor MP11 is on or off, but since spike noise does not occur in the sense resistor Rs depending on whether the MOS transistor MP11 is on or off, there is no need for time to mask the spike noise, and the oscillation frequency of the oscillator 5 can be increased.

[0059] The present invention is not limited to the above-described embodiment, and can be appropriately modified, improved, etc. In addition, the material, shape, size, number, arrangement location, etc. of each component in the above-described embodiment are arbitrary as long as the present invention can be achieved, and are not limited.

[0060] For example, in the above-described embodiment, the input bias reducing circuit 43 is provided, but the present invention is not limited to this. The input bias reducing circuit 43 is not essential, and may not be provided.

[0061] In the above embodiment, the voltage generating circuit 423 is composed of a plurality of transistors Q4 to Q6 and the constant current source 423A, but is not limited to this. The voltage generating circuit 423 may be another known voltage generating circuit using, for example, a Zener diode. [Explanation of symbols]

[0062] 1 DC / DC Converter 2 Control IC (control circuit) 4 Current Sense Circuit 41 Current detection signal generation circuit 42 Common-mode input range expansion circuit 43 Input bias reduction circuit 421 Current supply circuit 422 Comparison circuit 422A constant current source (first current source) 424 First current mirror circuit 423 Voltage Generation Circuit 423A constant current source (second current source) 431 Constant current source (third current source) 432 Second Current Mirror Circuit 433 Third Current Mirror Circuit Lout coil Cout Capacitor MP5 MOS transistor (fourth transistor) MP6 MOS transistor (5th transistor) MP11 MOS transistor (7th transistor) Q1 transistor (first transistor) Q2 transistor (second transistor) Q3 transistor (third transistor) Q4~Q6 transistors (sixth transistor) R1 Resistor (first resistor) R2 Resistor (second resistor) R3 Resistor (third resistor) R4 Resistor (4th resistor) R5 Resistor (5th resistor) Rs Sense resistor VIN Input voltage (first input voltage) V1 Connection point voltage V + Input voltage (second input voltage) V + -V2 Specific voltage

Claims

1. A current sense circuit that outputs a current detection signal corresponding to a voltage drop occurring in a sense resistor, a first transistor having a collector-emitter connected between a power supply line to which a second input voltage is supplied and one end of the sense resistor; a second transistor having a collector-emitter connected between the power supply line and the other end of the sense resistor, a base connected to the base of the first transistor, and a base-collector connected thereto; a first resistor connected between one end of the sense resistor and the emitter of the first transistor; a second resistor connected between the other end of the sense resistor and the emitter of the second transistor, the second resistor having the same resistance as the first resistor; a third transistor having an emitter connected to the emitter of the second transistor and a base connected to the collector of the first transistor; a current detection signal generating circuit including a third resistor connected between the power supply line and the collector of the third transistor; a fourth resistor and a fifth resistor, each having the same resistance value, connected in series between a connection point between the emitter of the first transistor and the first resistor and a connection point between the emitter of the second transistor and the second resistor; a common-mode input range expanding circuit including a current supply circuit that compares a voltage corresponding to a first input voltage input to one end of the sense resistor with a predetermined voltage, and, when the voltage corresponding to the first input voltage is higher than the predetermined voltage, causes a current to flow from the one end of the sense resistor and the other end of the sense resistor toward a connection point of the fourth resistor and the fifth resistor. Current sense circuit.

2. 2. The current sense circuit of claim 1, The current supply circuit includes: a comparison circuit including a fourth transistor and a fifth transistor whose sources are connected to each other, and a first current source that supplies current to the fourth transistor and the fifth transistor, in which a voltage according to the first input voltage is supplied to a gate of the fourth transistor and the predetermined voltage is supplied to a gate of the fifth transistor; a first current mirror circuit that outputs a current corresponding to a current flowing through the fifth transistor from a connection point between the fourth resistor and the fifth resistor. Current sense circuit.

3. 3. A current sense circuit according to claim 1, The voltage according to the first input voltage is a voltage at a connection point between the fourth resistor and the fifth resistor. Current sense circuit.

4. A current sense circuit according to any one of claims 1 to 3, The common mode input range expansion circuit comprises: The voltage generating circuit includes a plurality of sixth transistors that are diode-connected and connected in series with each other, and a second current source that supplies a current to the sixth transistors, and generates the predetermined voltage according to a voltage generated across the plurality of sixth transistors. Current sense circuit.

5. A current sense circuit according to any one of claims 1 to 4, a third current source that supplies a constant current; a second current mirror circuit that copies the current of the third current source and supplies the copied current to the collectors of the first transistor and the second transistor, respectively; a third current mirror circuit that copies the current of the third current source and flows the copied current from the emitters of the first transistor and the second transistor toward ground. Current sense circuit.

6. A coil and A capacitor to which one end of the coil is connected; a seventh transistor that is provided between a voltage source to which a second input voltage is supplied and the other end of the coil, and that turns on and off the supply of the second input voltage to the coil; a sense resistor provided between one end of the coil and the capacitor; a control circuit for controlling the on / off of the seventh transistor to output an output voltage obtained by converting the second input voltage.

1. A DC / DC converter comprising: The control circuit includes: a current sense circuit according to any one of claims 1 to 5, which outputs a current detection signal corresponding to a voltage drop occurring across the sense resistor; generating a signal for turning on and off the seventh transistor based on a comparison between an error signal corresponding to a difference between a voltage corresponding to the output voltage and a reference voltage and a slope signal corresponding to the current detection signal; DC / DC converter.

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