Multiple error detection circuit for detecting multiple errors in multiple links and error correction circuit having multiple error detection circuit

Abstract

To improve the detection rate of multiple error bits of data that propagates in 2D LINKs.SOLUTION: A multiple error detection circuit includes a transmission circuit to output a signal to two-dimensional links and a reception circuit to receive a signal from the two-dimensional links. The transmission circuit outputs, to the two-dimensional links, a codeword obtained by adding row parity bits and column parity bits to MxN data. The reception circuit generates row check bits that are parity bits of (N+1) row bit groups in each row of the codeword that has propagated through the two-dimensional links and column check bits that are parity bits of (M+1) column bit groups in each column, and generates multiple error detection signals when the number of 1 of the row check bits is 2 or more or the number of 1 of the column cheek bits is 2 or more. The M column bit groups in each column is a bit group shifted in a plus or minus row direction by a row shift amount in from a second row to an M-th row, or N row bit groups in each row is a bit group shifted in a plus or minus column direction by a column shift amount in from a second column to an N-th column.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a multiple error detection circuit for detecting multiple errors in multiple links and an error correction circuit having the multiple error detection circuit. [Background technology]

[0002] A link is a connection wiring that transmits signals between multiple devices. Multiple IC (Integrated Circuit) chips arranged in a two-dimensional array transmit multiple signals via multiple links. A three-dimensional integrated circuit (3D IC) has a structure in which multiple IC chips are stacked in the Z-axis direction. The multiple IC chips in a 3D IC transmit multiple signals via a two-dimensional array of through silicon vias (TSVs) formed in each chip. In this case, the TSVs function as links.

[0003] In 3D ICs, it is important to improve the reliability of TSVs. TSV defects include TSVs being open (disconnected), TSVs being shorted to the silicon substrate, two or more TSVs being connected by conductive material, etc. In TSVs with these defects, signals, i.e. high and low level voltages, from the sending chip cannot be transmitted correctly to the receiving chip.

[0004] The present inventors have proposed a two-dimensional parity product code (2D PPC) based on parity check that enables error bit correction in TSVs of 3D ICs. 2D PPC is disclosed in Non-Patent Document 1. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] KN Dang, M. Meyer, AB Ahmed, AB Abdallah, and X.-T. Tran, “2DPPC: A single-correction multiple-detection method for Through-Silicon-Via Faults,” in 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2019), 2019. [Non-Patent Document 2] “Hardened Design Based on Advanced Orthogonal Latin Code against Two Adjacent Multiple Bit Upsets (MBUs) in Memories”, 2015 IEEE, Liyi Xiao, Jiaqiang Li, Jie Li and Jing Guo Microelectronics Center, Harbin Institute of Technology, Harbin, HLJ 150001, China [Non-Patent Document 3] “A Method to Extend Orthogonal Latin Square Codes”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 7, JULY 2014, Pedro Reviriego, Salvatore Pontarelli, Alfonso Sanchez-Macian, and Juan Antonio Maestro Summary of the Invention [Problem to be solved by the invention]

[0006] When a single defective TSV is detected among multiple TSVs arranged in a two-dimensional array, 2D PPC can correct the signal error of that single defective TSV. On the other hand, when two or more multiple defective TSVs are detected, the errors in those signals cannot be corrected. In this case, the error-corrected signal output by the error correction circuit of the receiving chip is unreliable.

[0007] However, 2D PPC may not be able to correctly detect multiple defects, for example, when an even number of defects exist on the same column or row of a two-dimensional TSV, the defects cannot be detected by the parity bits of 2D PPC.

[0008] Therefore, an object of a first aspect of this embodiment is to provide a multiple defect detection circuit that has a high detection rate for multiple defects that occur in multiple links that are arranged two-dimensionally, and an error correction circuit having a multiple defect detection circuit. [Means for solving the problem]

[0009] A first aspect of the present embodiment includes a transmission circuit that outputs a 1-bit signal to each of a plurality of links arranged in a matrix; a receiving circuit for receiving signals propagated through the plurality of links; The transmission circuit includes: generating row parity bits for N row bit groups for each row included in the data having M rows and N columns, and generating column parity bits for M column bit groups for each column; outputting a codeword having M+1 rows and N+1 columns obtained by adding the row parity bit and the column parity bit to the data having the M rows and N columns to the plurality of links; The receiving circuit includes: generating row check bits which are parity bits of N+1 row bit groups in each row of the codeword propagated through the plurality of links, and column check bits which are parity bits of M+1 column bit groups in each column of the codeword; generating a multiple error detection signal if the number of 1's in the row check bits is 2 or more than 2 or the number of 1's in the column check bits is 2 or more than 2; The M column bit groups in each column are bit groups shifted in the row direction in plus or minus directions by a row shift amount from the second row to the Mth row, or The N row bit groups in each row are bit groups shifted in the column direction in plus or minus directions by a column shift amount from the second column to the Nth column, which is a multiple error detection circuit. Effect of the Invention

[0010] According to the first aspect, the detection rate of multiple errors can be increased. [Brief description of the drawings]

[0011] [Figure 1] 1A and 1B show cross-sectional and plan views of an example of a 3D IC. [Diagram 2] FIG. 2 is a schematic circuit diagram showing a sending device, a receiving device and the links provided between them; [Diagram 3] FIG. 11 is a diagram illustrating the operation of an encoder of a transmission circuit Tx. [Figure 4] FIG. 11 is a diagram illustrating the operation of a decoder in the receiving circuit Rx. [Diagram 5] FIG. 13 is a diagram for explaining detection of an error bit based on a check bit. [Figure 6] FIG. 2 is a diagram illustrating the configuration of an encoder and a decoder. [Figure 7] FIG. 1 illustrates the challenges of PPC. [Figure 8] FIG. 13 is a diagram showing an example of a codeword CDWD_2 in an extended PPC. [Figure 9] FIG. 2 is a diagram illustrating an example of a schematic configuration of a transmitting device and a receiving device according to the first embodiment. [Figure 10] FIG. 10 is a diagram illustrating a detailed example of the circuit configuration of FIG. 9. [Figure 11] FIG. 13 is a diagram showing row shifting and column shifting operations in a transmission circuit. [Figure 12] FIG. 13 is a diagram showing row shifting and column shifting operations in a transmission circuit. [Figure 13] FIG. 13 is a diagram showing row shifting and column shifting operations in a receiving circuit. [Figure 14] FIG. 13 is a diagram showing row shifting and column shifting operations in a receiving circuit. [Figure 15] FIG. 13 is a diagram showing an example in which multiple error bits cannot be detected even when the extended PPC is applied; [Figure 16] FIG. 13 is a diagram illustrating a method for calculating a row shift amount that maximizes the minimum Euclidean distance between adjacent bits on a parity link in an extended PPC. [Figure 17] FIG. 13 is a diagram showing an example of check bits sr, sc of a codeword CDWD_2 generated by extended PPC with row shift amount s=±1 and column shift amount s=±1 for a certain defective TSV pattern. [Figure 18] FIG. 18 is a diagram showing an example of check bits sr, sc of a codeword CDWD_2 generated by extended PPC with a row shift amount s=N1 / 2 or a column shift amount s=M1 / 2 for the same defective TSV pattern as in FIG. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] FIG. 1 shows a cross-sectional view and a plan view of an example of a 3D IC. FIG. 1(A) is a cross-sectional view of the 3D IC cut vertically, and FIG. 1(B) is a plan view of the chip CHP3 cut horizontally. As shown in the cross-sectional view, the 3D IC is, for example, stacked on a chip CHP0 on which a control circuit is formed, four chips CHP1 to CHP4 on which controlled circuits are formed. The chip CHP0 is mounted on a package substrate (not shown). A control circuit is formed on the upper surface of the chip CHP0. The four chips CHP1 to CHP4 are stacked on the chip CHP0 with the surfaces on which the controlled circuits are formed face down. A plurality of TSVs for transmitting signals between the chips are formed in a matrix on the three chips CHP1 to CHP3. The chip CHP0 and the chips CHP1 to CHP4 are stacked via solder bumps BMP. The solder bumps BMP electrically connect the TSVs in the vertical direction and stack the five chips CHP0 to CHP4.

[0013] 1B is a plan view showing a plurality of TSVs arranged in a matrix of 5 rows and 5 columns on the chip CPH3. The 5-row, 5-column TSVs propagate a 25-bit signal in parallel.

[0014] For example, the four chips CHP1 to CHP4 are DRAM chips. The chip CHP0 transmits control signals and write data to the four DRAM chips via the TSVs, and the four DRAM chips transmit read data to the chip CHP0 via the TSVs. A bump BMP connecting the TSVs is a link that propagates data signals between the chips.

[0015] [Outline of PPC] Product Code (PC) is the usual technical term for Error Correction Code (ECC). PC is a code in which each row and each column of two-dimensional input data is given its own ECC. Product Code (PC) is referred to as two-dimensional encoding, for example, in U.S. Patent 8,856,616. In this specification, codes that use parity bits as ECC in product codes are referred to as Parity Product Coding (PPC). Below, we will provide an overview of PPC.

[0016] 2 is a schematic circuit diagram showing a transmitting device, a receiving device, and a link provided between them. The transmitting device DEVICE_1 has a transmitting circuit Tx. The transmitting circuit Tx converts data DATA_1 output by the transmitting device into a code word CDWD_1 and outputs it to a link LINK. The receiving device DEVICE_2 has a receiving circuit Rx. The receiving circuit Rx generates error-corrected data DATA_2 from the code word CDWD_2 propagated through the link LINK. The error-corrected data DATA_2 is input to the receiving device. The link LINK is a two-dimensional plurality of TSVs shown in FIG. 1.

[0017] The transmitting circuit Tx is an ECC (Error Correction Code) encoder that adds a parity bit to the data DATA_1 to generate a code word CDWD_1. The receiving circuit Rx is an ECC decoder. The ECC decoder generates a parity bit for the code word CDWD_2 that has propagated through the link LINK, detects errors in the code word CDWD_2, corrects one-bit errors, and outputs the received data DATA_2. The encoder and decoder correct errors in the received data that have occurred due to defective TSVs.

[0018] Error correction using a parity bit can correct a single-bit error, but cannot correct two-bit errors or errors of more than two bits (multiple errors). Therefore, the decoder of the receiving circuit checks whether multiple errors have occurred in the received codeword CDWD_2, and outputs a multiple error detection signal NACK if multiple errors have occurred. Based on the multiple error detection signal NACK, the receiving device DEVICE_2 determines whether the data DATA_2 output by the decoder is reliable.

[0019] In this specification, an error bit or a faulty bit caused by a faulty TSV is often referred to as a faulty bit. Error bit, faulty bit, and faulty bit have the same meaning.

[0020] 3 is a diagram showing the operation of the encoder of the transmission circuit Tx. The transmitting device DEVICE_1 transmits data DATA_1 of 4 rows and 4 columns (16 bits) to the receiving device DEVICE_2. The value of the 16-bit data (0 or 1) is determined based on the operation of the transmitting device, or based on the operation of the receiving circuit of the receiving device. 4 rows and 4 columns is an example, and in general, the data DATA_1 is data of M rows and N columns.

[0021] The encoder ENCODER generates a codeword by adding the parity bit PRTY_row of each row of bits to the corresponding bit group. The encoder also generates a codeword by adding the parity bit PRTY_col of each column of bits to the corresponding bit group. A codeword is a bit group with an even number of 1s. The parity bit PRTY_row is the row parity bit r i , the parity bit PRTY_col is the column parity bit c j Also, the all parity bit PRTY_all is the parity bit of all bits in 4 rows and 4 columns, or the parity bit of the row parity bit PRTY_row and the column parity bit PRTY_col.

[0022] The encoder calculates the code word CDWD_1 in the (M+1)th row and (N+1)th column from the data DATA_1 in the (M)th row and (N)th column by the following formula.

[0023]

number

[0024] The 5-row, 5-column codeword CDWD_1 is input in parallel to the 5-row, 5-column TSV shown in Fig. 1. The 5-row, 5-column TSV has 16 TSVs that propagate the 4-row, 4-column data DATA_1 and 9 TSVs that propagate the parity bits PRTY_row, PRTY_col, and PRTY_all.

[0025] 4 is a diagram showing the operation of the decoder of the receiving circuit Rx. The decoder, which is the receiving circuit Rx, inputs the code word CDWD_2 propagated through the TSV, and checks the check bits sr i (i=0~M-1), sr M and the check bit sc of each column j (j=0~N-1), sc N is calculated using the following formula:

[0026]

number

[0027] Fig. 5 is a diagram for explaining detection of an error bit based on a check bit. Fig. 5(A) is an example in which only one error bit EB (bad TSV or faulty TSV) or inverted bit is included in the received codeword CDWD_2. In this example, the error bit EB occurs at the (2,2) position of the codeword CDWD_2. In this case, the check bits are sr2=1 and sc2=1 according to the above-mentioned formulas (4) and (5), and it is detected that there is an error bit or faulty TSV at the (2,2) position.

[0028] That is, the decoder inverts the bit f by the following formula (8): i,j According to formula (8), the inverted bit f i,j check bit is sr j =1, sc i If f = 1 i,j = 1, otherwise f i,j = 0. And this inverted bit f i,j mask bits m i,j Based on the mask matrix Mask (equation (9)) where F k = F k ... The conversion formula is shown in equation (10).

[0029]

number

[0030] Thus, in a codeword error correction using a parity product code (PPC), the decoder can correct an error only if it detects one erroneous or inverted bit, with one row and one column check bit each being "1". On the other hand, if it detects two or more erroneous or inverted bits, with multiple row or column check bits being "1", then it must determine that the error-corrected codeword is unreliable.

[0031] Therefore, the decoder has a multiple error detection circuit and an error correction circuit for detecting multiple error bits. The equation of the error correction circuit is explained in Equation (10). The equation of the multiple error detection circuit is as follows:

[0032]

number

[0033] FIG. 6 is a diagram showing the configuration of an encoder and a decoder. The encoder ENCODER inputs data DATA_1 with M rows and N columns as an input Din. The encoder has row encoders (Row Encoders) 10 that generate row parity bits (M bits) for the bit group (N bits) of each row of the data DATA_1, column encoders (Col. Encoders) 11 that generate column parity bits (N bits) for the bit group (M bits) of each column, and an ultimate encoder (Ultimate Encoder) 12 that generates a one-bit ultimate parity bit (Ultimate Check Bit) from the row parity bits and column parity bits. The encoder adds the row parity bits, column parity bits, and ultimate parity bits to the data DATA_1, and outputs a code word CDWD_1 with M+1 rows and N+1 columns. The code word CDWD_1 becomes the encoder output Dout.

[0034] On the other hand, the decoder DECODER inputs the received codeword CDWD_2 of M+1 rows and N+1 columns as an input Din. The decoder has row decoders (Row Decoders) 20 that generate row check bits (M+1 bits) sr of the bit group (N+1 bits) of each row of the received codeword CDWD_2, and column decoders (Col. Decoders) 21 that generate column check bits (N+1 bits) sc of the bit group (M+1 bits) of each column. Then, the error correction circuit 26 corrects error bits of the received codeword CDWD_2 based on a mask Mask (equation (9)) generated based on the row check bits sr and the column check bits sc. The output Dout is the received data DATA_2 error-corrected by the error correction circuit 26.

[0035] The decoder further has a multiple-error detection circuit 25. The multiple-error detection circuit 25 has a row multiple-error detection circuit 22 that counts 1's in the row check bits sr and determines whether the count value is 2 or more, and a column multiple-error detection circuit 23 that counts 1's in the column check bits sc and determines whether the count value is 2 or more. The multiple-error detection circuit 25 has a logical OR gate 24 that calculates the logical OR of the outputs of both the multiple-error detection circuits 22, 23. The multiple-error detection circuit 25 sets a multiple-error detection signal NACK to 1 when it detects multiple errors.

[0036] This multiple error detection signal NACK is output to the receiving device DEVICE_2 as shown in Fig. 2. If the multiple error detection signal NACK is 1, the receiving device DEVICE_2 determines that the input error-corrected received data DATA_2 is unreliable and discards the received data. If the multiple error detection signal NACK is 0, it determines that the error-corrected received data DATA_2 is reliable. The multiple error signal NACK may be supplied to an error correction circuit 26 in the decoder. In this case, the error correction circuit 26 does not output the error-corrected received data DATA_2 when the multiple error detection signal NACK is 0, and outputs DATA_2 when NACK is 1.

[0037] [PPC Challenges] FIG. 7 is a diagram showing the problem of PPC. FIG. 7 shows four examples of a received codeword CDWD_2 having multiple error bits. As shown in the figure, white circles are normal TSVs, crossed circles are defective TSVs, and squares are defective TSVs that are erroneously determined to be defective TSVs. Also, the dashed lines indicate bit groups from which check bits sr and sc are generated, and in this specification, the line connecting these bit groups is called a parity link PL. Data propagating through the defective TSVs becomes error bits or inverted bits. And, unlike in FIGS. 3 and 4, the received codeword CDWD_2 in FIG. 7 has 6 rows and 6 columns. In this case, the data DATA_1 and DATA_2 are bits in 5 rows and 5 columns, and the row index is i=0 to M-1, so M=5, M+1=6, and the column index is 0 to N-1, so N=5, N+1=6.

[0038] In Fig. 7(a), three defective TSVs are located in different rows and different columns. Therefore, the check bits of the rows and columns to which the defective TSVs belong are sr0=1, sr1=1, sr2=1, sc1=1, sc3=1, and sc4=1. In this case, the multiple error detection circuit of the decoder can detect multiple errors based on equation (11) and outputs NACK=1.

[0039] In Fig. 7(b), two pairs of two defective TSVs out of three defective TSVs are located in the same row and the same column. Therefore, the check bits of the row and column to which the defective TSVs belong are sr1=0, sr4=1, sc1=0, and sc3=1. In this case, the multiple error detection circuit of the decoder cannot detect multiple errors based on equation (11) and outputs NACK=0. Then, the error correction circuit corrects the inverted bit of (4,3) that was mistakenly detected as a defective TSV. In other words, the decoder cannot detect the multiple error bit (defective TSV).

[0040] In Fig. 7(c), two pairs of defective TSVs among four defective TSVs are located in the same row and the same column. Therefore, the check bits of the row and column to which the defective TSVs belong are sr1=0, sr4=0, sc1=0, and sc3=0. In this case, the multiple error detection circuit of the decoder cannot detect multiple errors based on equation (11) and outputs NACK=0. Then, the error correction circuit does not correct the inverted bit of the defective TSV. In other words, the decoder cannot detect multiple error bits (defective TSVs).

[0041] In FIG. 7(d), two pairs of defective TSVs among five defective TSVs are located in the same row and the same column, and one defective TSV is located in a different row and column. Therefore, the check bits of the row and column to which the defective TSVs belong are sr1=0, sr2=0, sr3=1, sc1=1, sc2=0, and sc3=0. In this case, the multiple error detection circuit of the decoder cannot detect multiple errors based on equation (11) and outputs NACK=0. Then, the error correction circuit corrects only the inverted bit of the defective TSV at (3,2). In other words, the decoder cannot detect multiple error bits (defective TSVs).

[0042] As described above, if there are an even number of defective TSVs in the same row or column, the check bits will be sr=0, sc=0, and multiple errors may not be detected. Therefore, a multiple defect detection circuit that has a high detection rate for multiple defects in the received codeword CDWD_2 is required. According to the embodiment shown below, the detection rate for multiple error bits is increased.

[0043] [First embodiment: Extended PPC, EPPC, Extended Parity Product Coding] In the extended PPC of the first embodiment, the encoder that generates the code word CDWD_1 adds a parity bit c j , r i is calculated as follows:

[0044] (1) Row-shift The encoder calculates the parity bit c of the jth column. j is calculated from the bit group of columns whose column indexes are shifted by s in the row direction corresponding to row index i=0, 1, 2 to M-1. That is, the parity bit c j The bits of the column for which the calculation is performed are the bits obtained by switching TSV(i,j) in the case of PPC to TSV(i,(j+s*i)mod N). N is the number of columns of data Data_1, N+1 is the number of columns of TSV or codeword CDWD, and the last index is the parity bit. i=0~M, j=0~N. The parity bit c of column jj The bit group of the column for calculating is the bit group of the parity link as described above.

[0045] For example, when M=N=5 and s=2, the new columns or parity links for parity check at column j=0 in the extended PPC have bit indices (0,0)(1,2)(2,4)(3,1)(4,3)(5,0), where the last index (5,0) is parity bit c0. In row shifting, the column index shifts by s in the row direction in response to an increase in row index in the bits of the parity link. s can be either + or -.

[0046] (2) Column shift The encoder calculates the parity bit r of row i. i is calculated from the bit group of the column where the row index is shifted by s in the column direction, corresponding to the column index j=0, 1, 2 to N-1. That is, the parity bit r i The bits of the row for which s is calculated are the bits obtained by switching TSV(i,j) in the case of PPC to TSV((i+s*j)mod M,j). M is the number of rows of data Data_1, M+1 is the number of rows of codeword CDWD, and the last index is the parity bit. i=0~M, j=0~N. The parity bit r of row i i The bits of the string for which is calculated are called the bits of the parity link.

[0047] For example, for M=N=5 and s=2, the new columns or parity links for parity check in row i=1 in the extended PPC have bit indices (1,0)(3,1)(0,2)(2,3)(4,4)(1,5), where the last index (1,5) is parity bit r1. In column shifting, the row index shifts column-wise by s in response to the increment of the column index in the bits of the parity link. s can be either + or -.

[0048] 8 is a diagram showing an example of a codeword CDWD_2 in the extended PPC. The example of defective TSV in FIG. 8 is the same as that in FIG. 7(b). As described above, the codeword CDWD_1 generated by the encoder is generated by adding row and column parity bits r i , c j It is a code with 6 rows and 6 columns (indexes (0,0) to (5,5)) with the final parity bit u added.

[0049] Figures 8(a) and (b) are examples of row shifts s=+1 and s=-1, respectively. There is no column shift (s=0). The row-shifted parity links are shown with dashed lines. As mentioned above, a parity link means a link that connects a group of bits for which the encoder calculates check bits. The bit group of the parity link is row-shifted or column-shifted within the data area DATA area. In Figure 8, only the dashed lines of the parity links that pass through the three defective TSVs are shown, and only the check bits of each parity link are shown.

[0050] (a) With row shift s=+1, the check bits are sr1=0, sr4=1, sc0=1, sc2=1, and sc3=1, and (b) With row shift s=-1, the check bits are sr1=0, sr4=1, sc0=1, sc2=1, and sc4=1. In this case, with row shift s=-1, the parity links of the check bits sc0, sc2, and sc4 of the three columns each contain only one defective TSV. As a result, the check bits sc0, sc2, and sc4 of the three columns are all 1. For the check bits sr1 and sr4 of the two rows, the parity link of the check bit sr1 contains two defective TSVs. Therefore, the multiple error detection circuit 25 of the decoder detects the presence of multiple defective bits based on equation (11) and outputs a multiple error detection signal NACK=1. (a) With a row shift of s=+1, the column check bit sc0 and row check bit sr4 become 1 and the rest all become 0, so that the multiple error detection circuit 25 cannot detect multiple defective bits.

[0051] Figure 8(c) and (d) are examples of column shifts s=+1 and s=-1. There is no row shift (s=0). The column-shifted parity links are shown with dashed lines. The check bits for each parity link are shown. (c) With a column shift s=+1, the check bits are sr0=1, sr3=0, sr4=0, sc1=0, and sc3=1, and (d) with a column shift s=-1, the check bits are sr0=1, sr2=1, sr3=1, sc1=0, and sc3=1. In the case of (c), only one check bit in each row and column is 1, so the multiple error detection circuit does not detect the presence of multiple defective bits and outputs a multiple error detection signal NACK=0. On the other hand, in the case of (d), the check bits in three rows are 1, so the multiple error detection circuit detects the presence of multiple defective bits and outputs NACK=1.

[0052] As described above, in the first embodiment, the parity bit r of the data DATA_1 is i , c j Parity link to calculate the check bit sr of the codeword CDWD_2 i , sc j The row shift or column shift of the extended PPC is applied to the parity link that calculates . The multiple error detection circuit of the decoder in the extended PPC can detect multiple error bits in the received codeword CDWD_2 having three defective TSVs in FIG. 7(b) in the cases of FIG. 8(b) and FIG. 8(d).

[0053] 9 is a diagram showing a schematic configuration example of a transmitting device and a receiving device in the first embodiment. The transmitting device DEVICE_1 has a shift circuit 31 and a transmitting circuit Tx, converts data DATA_1 into a code word CDWD_1 and outputs it to the link LINK. The receiving device DEVICE_2 has a shift circuit 32 and a receiving circuit Rx, and receives error-corrected data DATA_2 obtained by converting the code word CDWD_2 propagating through the link LINK.

[0054] The shift circuit 31 on the transmitting side performs row and / or column shifting on the data DATA_1 based on a control signal CNTR_1 from the control circuit 30, and inputs the data to the encoder ENDOCER. The encoder outputs a code word CDWD_1, which is the data DATA_1 plus a parity bit, to the links LINKs (or TSVs) in parallel. The shift circuit 32 on the receiving side performs row and / or column shifting on the code word CDWD_2 based on a control signal CNTR_2 from the control circuit 30, and inputs the code word to the decoder DECODER. The decoder generates check bits from the row-shifted and / or column-shifted bits of the parity link, detects multiple error bits, and corrects the error bits.

[0055] Fig. 10 is a diagram showing a detailed circuit configuration example of the configuration in Fig. 9. Fig. 10 shows a transmission circuit Tx and a reception circuit Rx. The transmission circuit Tx has the shift circuit 31 in Fig. 9, circuits 10 to 12 that generate parity bits in the encoder, and a circuit 13 that combines the parity bits with the original data DATA_1. On the other hand, the reception circuit Rx has the shift circuit 32 in Fig. 9, circuits 20 and 21 that generate check bits in the decoder, a multiple error detection circuit 25, and an error correction circuit 26 that corrects errors in the data of the code word CDWD_2 using a mask Mask.

[0056] 10 is a multiplexer that selects either data DATA_1 or data DATA_1 shifted to a row-shifted and / or column-shifted position by internal wiring. Also, the shift circuit 32 is a multiplexer that selects either the received codeword CDWD_2 or data DATA_2 shifted to a row-shifted and / or column-shifted position by internal wiring.

[0057] 11 and 12 are diagrams showing row and column shift operations in a transmission circuit. Here, we will explain using simplified data DATA_1 with 3 rows and 3 columns as an example. The left side of the diagram shows operation when PPC (original PPC) that does not use row or column shifts is applied, and the right side shows operation when PPC (extended PPC, EPPC) that does use row or column shifts is applied.

[0058] When the original PPC that does not use row or column shifting is applied, the transmission circuit Tx performs the following operations. (A) The multiplexer MUX, which is the shift circuit 31, selects the data DATA_1 in the 3rd row and 3rd column, and inputs it to the encoders 10 to 12. (B) The parity bit generation circuits 10 to 12 of the encoder generate parity bits for each column bit group and each row bit group of the input data DATA_1, and further generate a final parity bit. (C) The combining circuit 13 of the transmitting circuit Tx adds a parity bit to the data DATA_1 and transmits it in parallel to the links LINKs, which are TSVs.

[0059] On the other hand, when row-shifting extended PPC is applied, the transmission circuit Tx performs the following operation. (A) A multiplexer MUX, which is a shift circuit 31, selects data DATA_1_row.shift, which is obtained by row-shifting the data DATA_1 of 3 rows and 3 columns, and inputs the data to encoders 10 to 12. The row-shifted data DATA_1_row.shift has the bits of indexes (1,1) and (2,2) of data DATA_1 at indexes (1,0) and (2,0). Similarly, data DATA_1_row.shift has the bits of indexes (1,2) and (2,0) of data DATA_1 at indexes (1,1) and (2,1), and has the bits of indexes (1,0) and (2,1) of data DATA_1 at indexes (1,2) and (2,2). (B) The parity bit generation circuits 10 to 12 of the encoder generate parity bits for each column and each row of the input data DATA_1_row.shift, and further generate the final parity bit. The generated column parity bit c0 is the row-shifted bit group b 0,0 , b 1,1 , b 2,2 The column parity bits c1 and c2 are the parity bits of the row-shifted bits. (C) The combining circuit 13 of the transmitting circuit Tx adds a parity bit to the data DATA_1 and transmits the code word CDWD_2_row.shift in parallel to the TSVs. That is, the non-row-shifted data DATA_1 and the parity bit calculated from the row-shifted bits are input to the link LINKs.

[0060] 13 and 14 are diagrams showing row shift and column shift operations in a receiving circuit. When the original PPC that does not use row or column shift is applied, the receiving circuit Rx performs the following operations. (D) The receiving circuit Rx inputs the codeword CDWD_2 received from the TSVs. (E) The codeword CDWD_2 is input to the decoder via the multiplexer MUX. (F) The check bit generation circuits 20 and 21 in the decoder generate check bits sc and sr from the column bit group and row bit group of the codeword CDWD_2. Furthermore, the multiple error detection circuit 25 outputs a multiple error detection signal NACK. (G) Then, a mask Mask is generated from the check bits sc and sr based on equation (8). The error correction circuit 26 corrects the error bit of the received codeword CDWD_2 based on the mask Mask, and outputs the error-corrected data DATA_2.

[0061] When row-shifting extended PPC is applied, the receiving circuit Rx performs the following operations. (D) The receiving circuit Rx inputs the codeword CDWD_2 received from the TSVs. (E) The multiplexer MUX selects the row-shifted codeword CDWD_2_row.shift, in which the data DATA is row-shifted and the positions of the row and column parity bits r, c are the same as those of the codeword CDWD_2 received from the TSVs. (F) The check bit generation circuits 20 and 21 in the decoder generate check bits sc and sr from the column bits and row bits of the codeword CDWD_2_row.shift. Furthermore, the multiple error detection circuit 25 outputs a multiple error detection signal NACK. (G) Then, a mask Mask is generated from the check bits sc and sr based on equation (8). The index of the mask Mask generated from the row-shifted codeword CDWD_2_row.shift is the same as that of the PPC mask. Then, the error correction circuit 26 corrects the error bit of the received codeword CDWD_2 based on the mask Mask, and outputs the error-corrected data DATA_2.

[0062] As shown in FIG. 8, the above-described extended PPC increases the probability of detecting multiple error bits in two-dimensional (2D) LINKs.

[0063] [Second embodiment: Distance Aware Extended Parity Product Check] Fig. 15 is a diagram showing an example in which multiple error bits cannot be detected even when the extended PPC is applied. Fig. 15 shows an example in which error bits (defective TSVs) exist at indexes (1,1), (1,2), and (2,2) of the received codeword CDWD_2.

[0064] FIG. 15(a) shows the check bits sr and sc when the original PPC is applied. In this case, sr1=0, sr2=1, sc1=1, and sc2=0, and the decoder detects one sr=1 in the row check bit sr and one sc=1 in the column check bit sc based on equation (11). In other words, the decoder cannot detect multiple error bits. FIG. 15(b) and (c) show examples of the extended PPC with row shift (s=+1) and column shift (s=+1), respectively. In these cases, the decoder also detects one sr=1 in the row check bit sr and one sc=1 in the column check bit sc based on equation (11). In other words, the decoder cannot detect multiple error bits.

[0065] On the other hand, Fig. 15(d) is an example of extended PPC with row shift (s = -1). The decoder detects three sr = 1 in the row check bit sr based on equation (11). Therefore, the decoder can detect multiple error bits.

[0066] As described above, compared to the original PPC, the extended PPC has a higher probability of detecting multiple error bits in 2D LINKs, but there are also cases where multiple error bits cannot be detected, as shown in Figs. 15(b) and (c).

[0067] The decoder of the second embodiment uses the distance-aware extended PPC to improve the detection rate of multiple error bits. The distance-aware extended PPC sets the column shift amount or row shift amount of the extended PPC to an optimal value based on the size of the matrix of the 2D TSVs, based on the fact that the 2D TSVs have a cluster of defective TSVs (a group of multiple defective TSVs). Specifically, the column shift amount or row shift amount that maximizes the Euclidean distance between bits of the bit group of the parity link for calculating the parity check is set to the extended PPC. In other words, the column shift amount or row shift amount that maximizes the minimum Euclidean distance between bits of the bit group on the parity link is set to the extended PPC.

[0068] FIG. 16 is a diagram showing a method for calculating a row shift amount that maximizes the minimum Euclidean distance between adjacent bits on a parity link in an extended PPC. FIG. 16 shows 2D TSVs with N columns. A parity link proceeding in the row direction from index (0,0) and a parity link proceeding in the row direction from index (1,0) are each shown by a dashed line with an arrow. The row shift amount is s. Bits on a parity link move, for example, from index (0,0) to (1,s), (2,2s), (i, (j + s*i) mod N). Once the column index (j+s*i) exceeds N-1 at the right end, the column index circulates back to the remainder position calculated by (j + s*i) mod N. In the example of row shift s=2, N=6 in FIG. 18(g), the bits on the parity link are, for example, (0,0), (1,2), (2,4), (3,0), (4,2), (5,4).

[0069] The distance D1 between adjacent b(0,0) and b(1,s) is shown in the following formula. And the index when returning to the first loop is b(ceil(N / s), as shown in Figure 16. s - (N mod s)). The adjacent b(0,0) and b(ceil(N / s), s - The distance D2 between the two points (N mod s) is given by the following formula: And, ceil(N / s), s - The minimum value that (N mod s) can take is ceil(N / s) ≒ N / s. s - If we approximate (N mod s) ≒ 0, the distance D2 is N / s. Therefore, if we set D1 = D2, the optimal row shift amount s that maximizes the minimum Euclidean distance is ±N 1 / 2 become.

[0070]

number

[0071] Here, the reason for setting D1 = D2 is as follows. When the row shift amount s is increased, the distance D1 becomes longer, but the distance D2 = N / s becomes shorter. Conversely, when the row shift amount s is decreased, the distance D1 becomes shorter, but the distance D2 = N / s becomes longer. Therefore, the shift amount s for maximizing the minimum value of the Euclidean distance between multiple adjacent bits is the s when D1 = D2 is satisfied.

[0072] Fig. 17 is a diagram showing an example of check bits sr, sc of a codeword CDWD_2 generated by an extended PPC with a row shift amount s = ±1 and a column shift amount s = ±1 for a certain defective TSV pattern. The defective TSV pattern in Fig. 17 is the same as the defective TSV pattern in Fig. 7(d).

[0073] FIG. 17(a) shows row check bits sr and column check bits sc of the received codeword CDWD_2 calculated by the original PPC. In the original PPC, the row shift amount s and column shift amount s are 0. As shown in the figure, a defective TSV exists on the parity link (dashed line) indicating the bit group for calculating the row check bit sr and the column check bit sc. That is, in the figure, the row check bit sr and the column check bit sc of the parity link in which the defective TSV exists are shown. In this example, only one sr3 out of the three row check bits sr1, sr2, and sr3 is 1, and only one sc1 out of the three column check bits sc1, sc2, and v is 1. The fact that the parity bit is 1 means that a defective TSV (error bit) exists on that parity link. Therefore, in this example, the decoder of the receiving circuit Rx detects a single defect and does not detect multiple defects (NACK=0).

[0074] 17(b) and 17(c) show the row check bits sr and column check bits sc of the received codeword CDWD_2 by the extended PPC with the column shift amount s of +1 and -1, respectively. The row shift amount s is 0. In this example, too, only one of the three row check bits sr is 1, and only one of the three column check bits sc is 1. Therefore, in this example, the decoder of the receiving circuit Rx erroneously detects a single defect and does not detect multiple defects (NACK=0).

[0075] 17(d) and 17(e) show the row check bits sr and column check bits sc of the received codeword CDWD_2 by the extended PPC with row shift amounts s of +1 and -1, respectively. The column shift amount s is 0. In this example, too, only one of the three row check bits sr is 1, and only one of the three column check bits sc is 1. Therefore, in this example, the decoder of the receiving circuit Rx erroneously detects a single defect and does not detect multiple defects (NACK=0).

[0076] Figure 18 shows the same defect TSV pattern as in Figure 17, but with a row shift of s=N 1 / 2 Or column shift amount s=M 1 / 2 18A and 18B are diagrams showing examples of check bits sr and sc of codeword CDWD_2 generated by the extended PPC of FIG. 18F shows an example where the column shift amount s is -2 and the row shift amount s is 0, FIG. 18G shows an example where the row shift amount s is +2 and the column shift amount s is 0, and FIG. 18H shows an example where the row shift amount s is +3 and the column shift amount s is 0. These shift amounts s=-2, +2, +3 are obtained by dividing the row shift amount s by N. 1 / 2 Corresponds to.

[0077] In Fig. 18(f), the row check bits sr0 and sr3 are 1, and the decoder's multiple-error detection circuit can detect multiple error bits. In Fig. 18(g), the column check bits sc0 and sc2 are 1, and the decoder's multiple-error detection circuit can detect multiple error bits. In Fig. 18(h), the column check bits sc3 and sc4 are 1, and the decoder's multiple-error detection circuit can detect multiple error bits.

[0078] As described above, the detection rate of multiple error bits can be increased by applying distance-aware PPC (or extended PPC) to calculate the parity bits of the transmitted data DATA_1 and the check bits of the received codeword CDWD_2. In addition, in the extended PPC, the detection rate of multiple error bits can be increased by repeating multiple error bit detection by changing the row shift amount s and column shift amount s. On the other hand, in the distance-aware extended PPC, the minimum distance between bits on the parity link can be maximized, so that the presence of multiple error bits can be detected in one clock cycle by performing multiple error bit detection with the optimal row shift amount and / or optimal column shift amount.

[0079] [Variations] In Fig. 10, the index array of data DATA_1 is row-shifted or column-shifted by internal wiring and selected by the multiplexer MUX. However, the original index array data DATA_1 may be converted to row-shifted and / or column-shifted index array data DATA_1_row.shift, etc. by a conversion circuit corresponding to row shift or column shift, and input to the encoder. Also, the received codeword CDWD_2 may be converted to row-shifted and / or column-shifted index array data by a similar conversion circuit, and input to the decoder.

[0080] In the distance-aware extended PPC, for data DATA_1 with M rows and N columns, the row shift amount is a positive or negative integer value rounded up or down by 1 / 2 power of N. Also, the column shift amount is a positive or negative integer value rounded up or down by 1 / 2 power of M.

[0081] As described above, according to this embodiment, the parity bit of the transmission data DATA_1 is calculated by applying the extended PPC or the extended PPC that considers distance to calculate the codeword CDWD_1, and the check bit of the received codeword CDWD_2 is calculated by applying the extended PPC or the extended PPC that considers distance. Then, based on the calculated check bits, the position of the error bit is detected, the error bit is corrected, and multiple error bits are detected. By detecting multiple error bits based on the calculated check bits, the accuracy of detecting multiple error bits can be improved. [Explanation of symbols]

[0082] DEVICE_1: Sending device DATA_1: Transmission data 31: Row or column shift circuit Tx, ENCODER: Transmitting circuit, encoder CDWD_1: Codeword TSVs, LINKs: 2D TSVs CDWD_2: Codeword 32: Row or column shift circuit Rx, DECODER: Receiving circuit, decoder DEVICE_2: Receiving device PL: Parity link r i , c j : Parity bit sr i , sc j :Check bit EB: Error bit, defective bit, defective TSV 25: Multiple error detection circuit 26: Error detection circuit

Claims

1. A transmission circuit that outputs a one-bit signal to each of a plurality of links arranged in a matrix; a receiving circuit for receiving signals propagated through the plurality of links; The transmission circuit includes: generating row parity bits for N row bit groups for each row included in the data of M rows and N columns and generating column parity bits for M column bit groups for each column; outputting a codeword having M+1 rows and N+1 columns, which is obtained by adding the row parity bit and the column parity bit to the data having M rows and N columns, to the plurality of links; The receiving circuit includes: generating row check bits which are parity bits of N+1 row bit groups in each row of the codeword propagated through the plurality of links, and column check bits which are parity bits of M+1 column bit groups in each column of the codeword; generating a multiple error detection signal if the number of ones in the row check bits is two or more than two or the number of ones in the column check bits is two or more than two; The M column bit groups in each column are bit groups shifted in the row direction in plus or minus directions by a row shift amount from the second row to the Mth row, or The N row bit groups of each row are bit groups shifted in the column direction in a positive or negative direction by a column shift amount from the second column to the Nth column, the row shift amount is a positive or negative integer value rounded up or down to the power of 1 / 2 of M, The column shift amount is a positive or negative integer value rounded up or down to the 1 / 2 power of N.

2. A transmission circuit that outputs a one-bit signal to each of a plurality of links arranged in a matrix; a receiving circuit for receiving signals propagated through the plurality of links, The transmission circuit includes: generating row parity bits for N row bit groups for each row included in the data of M rows and N columns and generating column parity bits for M column bit groups for each column; outputting a codeword having M+1 rows and N+1 columns, which is obtained by adding the row parity bit and the column parity bit to the data having M rows and N columns, to the plurality of links; The receiving circuit includes: generating row check bits which are parity bits of N+1 row bit groups in each row of the codeword propagated through the plurality of links, and column check bits which are parity bits of M+1 column bit groups in each column of the codeword; generating a multiple error detection signal if the number of ones in the row check bits is two or more than two or the number of ones in the column check bits is two or more than two; The M column bit groups in each column are bit groups shifted in the row direction in plus or minus directions by a row shift amount from the second row to the Mth row, or The N row bit groups of each row are bit groups shifted in the column direction in a positive or negative direction by a column shift amount from the second column to the Nth column, the row shift amount is a positive or negative integer value rounded up or down to the power of 1 / 2 of M, The column shift amount is a positive or negative integer value rounded up or down to the power of 1 / 2 of N.

3. A transmission circuit that outputs a one-bit signal to each of a plurality of links arranged in a matrix; a receiving circuit for receiving signals propagated through the plurality of links; The transmission circuit includes: generating row parity bits for N row bit groups for each row included in the data of M rows and N columns and generating column parity bits for M column bit groups for each column; outputting a codeword having M+1 rows and N+1 columns, which is obtained by adding the row parity bit and the column parity bit to the data having M rows and N columns, to the plurality of links; The receiving circuit includes: generating row check bits which are parity bits of N+1 row bit groups in each row of the codeword propagated through the plurality of links, and column check bits which are parity bits of M+1 column bit groups in each column of the codeword; generating a multiple error detection signal if the number of ones in the row check bits is two or more than two or the number of ones in the column check bits is two or more than two; inverting a signal of a link at an intersection of a row bit group whose row check bit is 1 and a column bit group whose column check bit is 1 to perform error correction, and if the multiple error detection signal is not generated, outputting the error-corrected data of M rows and N columns; The M column bit groups in each column are bit groups shifted in the row direction in plus or minus directions by a row shift amount from the second row to the Mth row, or The N row bit groups of each row are bit groups shifted in the column direction in a positive or negative direction by a column shift amount from the second column to the Nth column, the row shift amount is a positive or negative integer value rounded up or down to the power of 1 / 2 of M, The column shift amount is a positive or negative integer value obtained by rounding up or down N to the power of 1 / 2.

4. A transmission circuit that outputs a one-bit signal to each of a plurality of links arranged in a matrix; and a receiving circuit for receiving signals propagated through the plurality of links. A correction method comprising: The transmission circuit includes: generating row parity bits for N row bit groups for each row included in the data of M rows and N columns and generating column parity bits for M column bit groups for each column; outputting a codeword having M+1 rows and N+1 columns, which is obtained by adding the row parity bit and the column parity bit to the data having M rows and N columns, to the plurality of links; The receiving circuit includes: generating row check bits which are parity bits of N+1 row bit groups in each row of the codeword propagated through the plurality of links, and column check bits which are parity bits of M+1 column bit groups in each column of the codeword; generating a multiple error detection signal if the number of ones in the row check bits is two or more than two or the number of ones in the column check bits is two or more than two; inverting a signal of a link at an intersection of a row bit group whose row check bit is 1 and a column bit group whose column check bit is 1 to perform error correction, and if the multiple error detection signal is not generated, outputting the error-corrected data of M rows and N columns; The M column bit groups in each column are bit groups shifted in the row direction in plus or minus directions by a row shift amount from the second row to the Mth row, or The N row bit groups of each row are bit groups shifted in the column direction in a positive or negative direction by a column shift amount from the second column to the Nth column, the row shift amount is a positive or negative integer value rounded up or down to the power of 1 / 2 of M, The column shift amount is a positive or negative integer value obtained by rounding up or down N to the power of 1 / 2.

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