Photoelectric conversion devices, AD converters and devices

Abstract

To change the setting of a ΔΣ AD converter that converts an analog current signal to a digital signal.SOLUTION: A photoelectric conversion apparatus includes: a light receiving circuit that converts light into an electrical signal; a readout circuit that reads an analog current signal corresponding to the electrical signal; a ΔΣ AD converter that converts the analog current signal into a digital signal; and a control circuit that changes the settings of the ΔΣ AD converter. The ΔΣ AD converter includes: a subtractor supplied with the analog current signal; an integrator that integrates the output from the subtractor; a quantizer that quantizes the result of integration by the integrator; a decimation filter that performs decimation processing on the output from the quantizer; and a DA converter that supplies an analog current corresponding to the output from the quantizer to the subtractor such that the analog current is subtracted from the analog current signal. The integrator includes a variable capacitor charged by the output from the subtractor to integrate the output. The changing the setting of the ΔΣ AD converter includes changing the capacitance value of the variable capacitor.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device, an AD converter, and an apparatus. [Background technology]

[0002] Various techniques have been proposed to expand the range of input signals in photoelectric conversion devices. In Patent Document 1, a sample-and-hold circuit that holds a noise signal and a data signal is configured with multiple capacitive elements, and the gain is changed by changing the number of capacitive elements used for holding. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 describes that an analog current signal from a sample-and-hold circuit is converted into a digital signal by a downstream ΔΣAD (analog-digital) converter. The settings of this AD converter cannot be changed. Therefore, for example, when the input signal to the AD converter is small, the number of times the output from the comparator of the ΔΣ converter is inverted decreases, and there is a concern that the accuracy of the AD conversion may decrease. If the settings of the AD converter can be changed, the degree of freedom in designing a photoelectric conversion device is increased. Some aspects of the present invention aim to provide a technology that makes it possible to change the settings of a ΔΣAD converter that converts an analog current signal into a digital signal. [Means for solving the problem]

[0005] In view of the above problem, a photoelectric conversion device is provided, which includes a light receiving circuit for converting light into an electric signal, and a readout circuit for reading out an analog current signal corresponding to the electric signal. Then, a noise signal is read out from the light receiving circuit in the reset state. a read circuit for reading the analog current signal; and each of the noise signalsa ΔΣ AD converter that converts an analog current signal into a digital signal, and a control circuit that changes settings of the ΔΣ AD converter, wherein the ΔΣ AD converter includes a subtractor to which the analog current signal is supplied, an integrator that integrates an output from the subtractor, a quantizer that quantizes an integration result by the integrator, a decimation filter that performs a decimation process on the output from the quantizer, and a DA converter that supplies an analog current corresponding to the output from the quantizer to the subtractor so as to be subtracted from the analog current signal, and the integrator includes a variable capacitance that is charged by the output from the subtractor so as to integrate the output, and changing the settings of the ΔΣ AD converter includes changing a capacitance value of the variable capacitance. The control circuit changes the value of the variable capacitance when the ΔΣ AD converter converts the analog current signal and when the control circuit converts the value of the noise signal. A photoelectric conversion device is provided. Effect of the Invention

[0006] The above means makes it possible to change the settings of the ΔΣ AD converter that converts an analog current signal into a digital signal. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the arrangement of a photoelectric conversion device 100 according to some embodiments. [Diagram 2] FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel circuit 111 according to some embodiments. [Diagram 3] FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel circuit 111 according to some embodiments. [Figure 4] FIG. 2 is a diagram for explaining an example of a circuit configuration of a read circuit 121 according to some embodiments. [Diagram 5] FIG. 2 is a diagram illustrating an example of a circuit configuration of a ΔΣ modulator according to some embodiments. [Figure 6] FIG. 2 is a diagram illustrating an example of a circuit configuration of a current generating circuit according to some embodiments. [Figure 7] FIG. 2 is a diagram illustrating an example of a circuit configuration of a variable capacitor according to some embodiments. [Figure 8] FIG. 2 is a diagram illustrating an example of the configuration of a device according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0009] In the following, an embodiment in which the photoelectric conversion device 100 is used for imaging will be mainly described. In this case, the photoelectric conversion device 100 can be used as an imaging element (image sensor) for generating an image. Other examples of the photoelectric conversion device 100 include a distance measuring element (a sensor used for focus detection or distance measurement using TOF (Time Of Flight), a photometric element (a sensor used for measuring the amount of incident light, etc.), and a LiDAR (Light Detection and Ranging) sensor. The embodiment described below can be applied to photoelectric conversion devices in general.

[0010] An example of the configuration of a photoelectric conversion device 100 according to some embodiments will be described with reference to the block diagram of Fig. 1. In the example shown in Fig. 1, the photoelectric conversion device 100 includes a pixel unit 110, a readout unit 120, an AD conversion unit 130, a horizontal scanning circuit 140, a signal processing circuit 150, an output circuit 160, a vertical scanning circuit 170, and a timing control circuit 180.

[0011] The pixel section 110 includes a plurality of pixel circuits 111 arranged in a two-dimensional array, a plurality of drive lines 112 provided for each pixel row, and a plurality of signal lines 113 provided for each pixel column. The pixel rows refer to the plurality of pixel circuits 111 arranged in the left-right direction in Fig. 1. The pixel columns refer to the plurality of pixel circuits 111 arranged in the up-down direction in Fig. 1.

[0012] The pixel circuits 111 convert incident light into an electric signal. Therefore, the pixel circuits 111 may also be called light receiving circuits. A control signal is supplied to each of the pixel circuits 111 from the vertical scanning circuit 170 via a drive line 112. An electric signal is read out by the readout unit 120 via a signal line 113 from the pixel circuits 111 to which an active level control signal has been supplied.

[0013] The readout unit 120 includes a plurality of readout circuits 121 provided for each signal line 113, and a control circuit 122 that controls the operation of these readout circuits 121. The readout circuits 121 read out analog signals corresponding to the electrical signals generated by the pixel circuits 111, and supply the analog signals to the AD conversion unit 130.

[0014] The AD conversion unit 130 includes a plurality of AD converters 131 provided for each signal line 113, and a control circuit 132 that controls the operation of these AD converters 131. The AD converters 131 convert the analog signal supplied from the readout circuit 121 into a digital signal. In the following description, the AD converters 131 are ΔΣ AD converters.

[0015] The horizontal scanning circuit 140 sequentially reads out digital signals from the multiple AD converters 131 and supplies them to the signal processing circuit 150. The photoelectric conversion device 100 may have a memory circuit for storing digital signals between the AD conversion unit 130 and the horizontal scanning circuit 140. The signal processing circuit 150 processes digital signals corresponding to the electrical signals generated in each pixel circuit 111. The signal processing circuit 150 may perform, for example, correction processing or complementation processing on the digital signals.

[0016] The digital signal processed by the signal processing circuit 150 is output from the output circuit 160 to an external device 190 outside the photoelectric conversion device 100. The external device 190 may be, for example, a control device of an apparatus incorporating the photoelectric conversion device 100. The timing control circuit 180 controls the overall operation of the photoelectric conversion device 100 by supplying control signals to each circuit of the photoelectric conversion device 100. For example, the timing control circuit 180 may change the drive mode of the photoelectric conversion device 100 in response to an instruction from the external device 190. The timing control circuit 180 changes the gain of the photoelectric conversion device 100 in response to the change in the drive mode of the photoelectric conversion device 100. A specific example of a method of changing the gain will be described later. The change in the drive mode may include a change between a still image capture mode and a video capture mode of shooting using the photoelectric conversion device 100. The change in the drive mode may include a change in the sensitivity of shooting using the photoelectric conversion device 100. The change in the drive mode may include a change in the resolution of AD conversion by the AD converter 131. The change in the drive mode may include a change in the frame rate of moving image capture using the photoelectric conversion device 100. The change in the drive mode may include at least one of the above examples.

[0017] A specific example of the circuit configuration of the pixel circuit 111 will be described with reference to the circuit diagram of Fig. 2. The pixel circuit 111 can have any configuration that converts incident light into an electric signal. Although Fig. 2 describes one example, the pixel circuit 111 may have another configuration.

[0018] 2, the pixel circuit 111 includes a photoelectric conversion element 201, a transfer transistor 202, a reset transistor 203, an amplification transistor 204, and a selection transistor 205. In the example of Fig. 2, the pixel unit 110 includes three drive lines 112 for each pixel row, which supply control signals PRES, PTX, and PSEL to the pixel circuit 111, respectively.

[0019] The photoelectric conversion element 201 converts incident light into an electric charge and accumulates the electric charge. The photoelectric conversion element 201 may be, for example, a photodiode or a phototransistor. The photoelectric conversion element 201 may be a CMOS (Complementary Metal Oxide Semiconductor) sensor. Alternatively, the photoelectric conversion element 201 may be a SPAD (Single Photon Avalanche Diode) sensor.

[0020] The photoelectric conversion element 201 is connected to a floating diffusion 206 through a transfer transistor 202. A control signal PTX is supplied to the gate of the transfer transistor 202 from the vertical scanning circuit 170. In response to the control signal PTX becoming active level, the transfer transistor 202 becomes conductive. In response to this, the signal charge accumulated in the photoelectric conversion element 201 is transferred to the floating diffusion 206.

[0021] The floating diffusion 206 is also connected to the gate of the amplification transistor 204. One main electrode of the amplification transistor 204 is connected to the signal line 113 via the selection transistor 205. The other main electrode of the amplification transistor 204 is connected to the power supply potential VDD. A control signal PSEL is supplied to the gate of the selection transistor 205 from the vertical scanning circuit 170. In response to the control signal PSEL becoming active level, the selection transistor 205 becomes conductive. In response to this, one main electrode of the amplification transistor 204 is connected to the current source of the readout circuit 121. As a result, the amplification transistor 204 operates as a source follower, and a signal corresponding to the potential of the floating diffusion 206 is read out to the signal line 113.

[0022] The reset transistor 203 is connected between the floating diffusion 206 and a power supply potential VDD. A control signal PRES is supplied to the gate of the reset transistor 203 from the vertical scanning circuit 170. In response to the control signal PRES becoming active level, the reset transistor 203 becomes conductive. In response to this, the potential of the floating diffusion 206 is reset to the power supply potential VDD.

[0023] A specific example of the circuit configuration of the readout circuit 121 will be described with reference to the circuit diagram of Fig. 3. The readout circuit 121 can have any configuration for reading out an electrical signal generated in the pixel circuit 111. Although Fig. 3 describes one example, the readout circuit 121 may have another configuration.

[0024] In the example illustrated in FIG. 3, the readout circuit 121 includes current sources 301 , 308 , and 309 , sample-and-hold circuits 302 and 303 , amplifiers 304 and 306 , transistors 305 and 307 , and a resistor 312 .

[0025] The current source 301 supplies a bias current to the pixel circuit 111 (specifically, the amplifying transistor 204 thereof). The sample and hold circuits 302 and 303 each hold an output voltage from the pixel circuit 111. The timing control circuit 180 controls the pixel circuit 111 to output an electrical signal when the photoelectric conversion element 201 is in a reset state (hereinafter referred to as a noise signal) and an electrical signal corresponding to incident light (hereinafter referred to as a data signal). The control circuit 122 controls the readout circuit 121 to read out the noise signal and hold it in the sample and hold circuit 302 in accordance with an instruction from the timing control circuit 180. The control circuit 122 also controls the readout circuit 121 to read out the data signal from the pixel circuit 111 and hold it in the sample and hold circuit 303 in accordance with an instruction from the timing control circuit 180.

[0026] The amplifier 304 and the transistor 305 function as a source follower. The current source 308 supplies a bias current to the source follower. The potential of a node 310 between the current source 308 and the transistor 305 has a value according to the voltage (noise signal) held in the sample-and-hold circuit 302.

[0027] The amplifier 306 and the transistor 307 function as a source follower. The current source 309 supplies a bias current to the source follower. The potential of a node 311 between the current source 309 and the transistor 307 has a value according to the voltage (data signal) held in the sample-and-hold circuit 303.

[0028] The resistor 312 is connected between the node 310 and the node 311. Therefore, the voltage applied to the resistor 312 is the potential difference between the node 310 and the node 311. Therefore, an analog current signal corresponding to the difference between the data signal and the noise signal is supplied from the read circuit 121 to the AD converter 131. In this manner, the read circuit 121 has a function of performing correlated double sampling (CDS).

[0029] A specific circuit configuration example of the AD converter 131 will be described with reference to the block diagram of FIG. 4. The AD converter 131 is a ΔΣ AD converter. The AD converter 131 converts an input analog signal into a digital signal. The AD converter 131 of FIG. 4(a) has a first-order ΔΣ modulator 404 and a decimation filter 405. The AD converter 131 of FIG. 4(b) has a second-order ΔΣ modulator 407 and a decimation filter 405. Alternatively, the AD converter 131 may have a third-order or higher ΔΣ modulator. By using a higher-order ΔΣ modulator, the effect of noise shaping is improved. The ΔΣ modulators 404 and 407 convert the input analog signal into a 1-bit digital signal string. The decimation filter 405 performs decimation processing (thinning processing) on ​​this 1-bit digital signal string. For example, the decimation filter 405 generates a digital signal corresponding to the ratio of the time when the 1-bit digital signal string is 1 in a predetermined time length. The ΔΣ modulator 404 may convert the input analog signal into a digital signal string of 2 or more bits.

[0030] 4(a), the first-order ΔΣ modulator 404 has a subtractor 401, an integrator 402, a quantizer 403, and a DA converter (DAC) 406. The subtractor 401 is supplied with an input to the AD converter 131 (i.e., an analog signal from the readout circuit 121). In addition, the subtractor 401 is also supplied with an analog signal from the DA converter 406. The subtractor 401 supplies the difference between the analog signal from the readout circuit 121 and the analog signal from the DA converter 406 to the integrator 402.

[0031] The integrator 402 integrates the output from the subtractor 401. The quantizer 403 quantizes the integration result by the integrator 402. For example, the quantizer 403 generates a 1-bit digital signal string based on the integration result and supplies it to the decimation filter 405. The output from the quantizer 403 becomes the output from the ΔΣ modulator 404.

[0032] The output from the quantizer 403 is also supplied to the DA converter 406. The DA converter 406 generates a signal according to the output from the quantizer 403 and supplies this to the subtractor 401. The signal supplied from the DA converter 406 to the subtractor 401 is subtracted from the analog signal supplied from the read circuit 121, as described above.

[0033] 4(b), the second-order ΔΣ modulator 404 has subtractors 401 and 408, integrators 402 and 409, a quantizer 403, and DA converters (DACs) 406 and 410. The configurations of the subtractor 401, the integrator 402, the quantizer 403, and the DA converter (DAC) 406 are similar to those of the first-order ΔΣ modulator 404.

[0034] The output from the integrator 402 is supplied to the subtractor 408. In addition, an analog signal from a DA converter 410 is also supplied to the subtractor 408. The subtractor 408 supplies the difference between the analog signal from the integrator 402 and the analog signal from the DA converter 410 to the integrator 409. The integrator 409 integrates the output from the subtractor 408. The quantizer 403 quantizes the integration result by the integrator 409.

[0035] The output from the quantizer 403 is also supplied to a DA converter 410. The DA converter 410 generates a signal according to the output from the quantizer 403 and supplies this to a subtractor 408. The signal supplied from the DA converter 410 to the subtractor 408 is subtracted from the analog signal supplied from the integrator 402, as described above.

[0036] 5, an example of the circuit configuration of the ΔΣ modulators 404, 407 when the input to the AD converter 131 is an analog current signal will be described. Fig. 5(a) shows an example of the circuit configuration of the first-order ΔΣ modulator 404, and Fig. 5(b) shows an example of the circuit configuration of the second-order ΔΣ modulator 407.

[0037] First, a description will be given of an example of the circuit configuration of the first-order ΔΣ modulator 404. The subtractor 401 is composed of a node 501 connected to each of the readout circuit 121, the DA converter 406, and the integrator 402. The analog current from the DA converter 406 is subtracted from the analog current signal from the readout circuit 121 supplied to the node 501, and the resulting current is supplied to the integrator 402.

[0038] The integrator 402 is composed of a capacitor 502. The capacitor 502 may be a variable capacitor whose capacitance value changes according to an instruction from the control circuit 132. The capacitor 502 is charged by the output from the subtractor 401 so as to integrate the output. The voltage of the capacitor 502 is supplied to the quantizer 403. The quantizer 403 is composed of a comparator 503. The comparator 503 outputs a high-level or low-level voltage according to the value of the voltage supplied from the integrator 402.

[0039] The DA converter 406 is composed of a switch element 504 and a current generating circuit 505. The current generating circuit 505 generates an analog current to be supplied to the subtractor 401. The switch element 504 is located on a signal path between the subtractor 401 and the current generating circuit 505. The on / off state of the switch element 504 is switched by the output from the quantizer 403. When the output from the quantizer 403 is at a high level, the switch element 504 is turned on, and as a result, a current is supplied from the current generating circuit 505 to the subtractor 401. On the other hand, when the output from the quantizer 403 is at a low level, the switch element 504 is turned off, and as a result, no current is supplied from the current generating circuit 505 to the subtractor 401. In this way, the value of the analog current supplied from the DA converter 406 to the subtractor 401 changes depending on the output from the quantizer 403.

[0040] Next, an example of the circuit configuration of the second-order ΔΣ modulator 407 will be described. The ΔΣ modulator 407 has subtractors 401 and 408, integrators 402 and 409, a Gm amplifier 506, a quantizer 403, and DA converters 406 and 410. The circuit configurations of the subtractor 401, the integrator 402, the quantizer 403, and the DA converter 406 are similar to those of the first-order ΔΣ modulator 404. The Gm amplifier 506 is an amplifier, and converts the analog voltage signal supplied from the integrator 402 into an analog current signal, which is supplied to the subtractor 408. An analog voltage signal is supplied from the integrator 402 to an inverting input terminal of the Gm amplifier 506, and a reference voltage Vref is supplied from the control circuit 132 to a non-inverting input terminal of the Gm amplifier 506.

[0041] The subtractor 408 is configured with a node 507 connected to each of the Gm amplifier 506, the DA converter 410, and the integrator 409. The analog current from the DA converter 410 is subtracted from the analog current signal from the Gm amplifier 506 supplied to the node 507, and the resulting current is supplied to the integrator 409. The integrator 409 is configured with a capacitance 508. The capacitance 508 may be a variable capacitance whose capacitance value changes according to an instruction from the control circuit 132. The capacitance 508 is charged by the output from the Gm amplifier 506 so as to integrate the output. The voltage of the capacitance 508 is supplied to the quantizer 403.

[0042] The DA converter 410 is composed of a switch element 509 and a current generating circuit 510. The current generating circuit 510 generates an analog current to be supplied to the subtractor 408. The switch element 509 is located on a signal path between the subtractor 408 and the current generating circuit 510. The on / off state of the switch element 509 is switched by the output from the quantizer 403. When the output from the quantizer 403 is at a high level, the switch element 509 is turned on, and as a result, a current is supplied from the current generating circuit 510 to the subtractor 408. On the other hand, when the output from the quantizer 403 is at a low level, the switch element 509 is turned off, and as a result, no current is supplied from the current generating circuit 510 to the subtractor 408. In this way, the value of the analog current supplied from the DA converter 416 to the subtractor 408 changes depending on the output from the quantizer 403.

[0043] A specific example of the circuit configuration of the current generating circuit 505 will be described with reference to the circuit diagram of Fig. 6. The current generating circuit 505 can have any configuration that can change the amount of current to be generated. Although an example is described in Fig. 6, the current generating circuit 505 may have another configuration. The current generating circuit 510 may have the same circuit configuration as the current generating circuit 505.

[0044] The current generating circuit 505 has transistors 601 and 602, switch elements 603 and 604, and a capacitor 605. The transistor 601 is connected between the switch element 504 and the ground. The transistor 602 and the switch element 603 are connected in series between the switch element 504 and the ground. A bias voltage Vbias is supplied to the gates of the transistors 601 and 602 from the control circuit 132 via the switch element 604. The bias voltage Vbias is also supplied to the capacitor 605.

[0045] The switch element 604 and the capacitor 605 form a sample-and-hold circuit. Even when the switch element 604 is turned off, the bias voltage Vbias held in the capacitor 605 is supplied to the gates of the transistors 601 and 602.

[0046] Each of the transistors 601 and 602 functions as a current source that generates a current according to a bias voltage Vbias supplied to the gate. The current generated by the transistor 601 is supplied to the switch element 504. The current generated by the transistor 602 is supplied to the switch element 504 when the switch element 603 is on. The current generated by the transistor 602 is not supplied to the switch element 504 when the switch element 603 is off. The on / off of the switch elements 603 and 604 is controlled by a control signal supplied from the control circuit 132.

[0047] In this way, the value of the analog current supplied from current generating circuit 505 to switching element 504 changes depending on whether switching element 603 is on or off. Specifically, a larger current is supplied when switching element 603 is on than when switching element 603 is off. Furthermore, it is also possible to change the current values ​​generated by each of transistors 601 and 602 by changing the value of bias voltage Vbias. By having such a current generating circuit 505, DA converter 406 can change the value of the analog current supplied from DA converter 406 to subtractor 401 for the same output (high level in the above example) from quantizer 403.

[0048] A specific example of the circuit configuration of the capacitor 502 will be described with reference to the circuit diagram of Fig. 7. The capacitor 502 can have any configuration that allows the capacitance value to be changed. Although an example is described in Fig. 7, the capacitor 502 may have another configuration. The capacitor 508 may also have the same configuration as the capacitor 502.

[0049] The capacitance 502 has a plurality of pairs of unit capacitances 701 and switching elements 702 connected in series between the node 501 and the ground. Although three pairs of unit capacitances 701 and switching elements 702 are shown in Fig. 7, the number is not limited to this. In the example of Fig. 7, the switching element 702 is connected to the node 501 side, but the switching element 702 may be connected to the ground side.

[0050] The unit capacitors 701 have the same capacitance value. The on / off of the switch elements 702 is controlled by a control signal supplied from the control circuit 132. The control circuit 132 sets the capacitance value of the capacitor 502 by controlling the number of switch elements 702 that are turned on at the same time.

[0051] A method of changing the setting of the AD converter 131 described above will be described. In the first-order ΔΣ modulator 404 shown in FIG. 4(a), the control circuit 132 can change the capacitance value of at least one of the capacitances 502 and 508. The following describes a case where the capacitance value of the capacitance 502 is changed. By increasing the capacitance value of the capacitance 502, the time required to charge the capacitance 502 becomes longer. As a result, the frequency of inversion of the output of the quantizer 403 decreases, and the gain of the AD converter 131 decreases. Conversely, by decreasing the capacitance value of the capacitance 502, the time required to charge the capacitance 502 becomes shorter. As a result, the frequency of inversion of the output of the quantizer 403 increases, and the gain of the AD converter 131 increases. In this way, by making the capacitance value of the capacitance 502 variable, the drive timing, range, and gain of the AD converter 131 can be adjusted, and as a result, the AD conversion setting can be optimized. For example, when the subject to be photographed is a low-luminance subject, the control device 132 may reduce the capacitance value of the capacitance 502 compared to when the subject is a high-luminance subject. This ensures a sufficient frequency of inversion of the output of the quantizer 403.

[0052] In conjunction with changing the capacitance value of the capacitor 502, the control circuit 132 may change the value of the analog current supplied from the DA converter 406 to the subtractor 401 for the same output from the quantizer 403. Changing the value of the analog current supplied from the DA converter 406 to the subtractor 401 may include changing the number of transistors connected to the subtractor 401 among the multiple transistors 601, 602, as described above. Alternatively or in addition to this, changing the value of the analog current supplied from the DA converter 406 to the subtractor 401 may include changing the value of the voltage Vbias supplied to the gates of the transistors 601, 602. By changing the value of the voltage Vbias, the current can be changed more finely than when the number of transistors is changed.

[0053] When the capacitance value of the capacitor 502 is increased, the control circuit 132 may reduce the value of the analog current supplied from the DA converter 406 to the subtractor 401. Conversely, when the capacitance value of the capacitor 502 is decreased, the control circuit 132 may increase the value of the analog current supplied from the DA converter 406 to the subtractor 401. By controlling in this manner, the control circuit 132 can appropriately adjust the operating point at the start of integration in the integrator 402. Specifically, the operating point at the start of integration in the integrator 402 can be kept constant before and after the change in the capacitance value of the capacitor 502, thereby reducing variations due to differences in the operating points.

[0054] Alternatively or in addition, the control circuit 132 may change the settings of the decimation filter 405 in conjunction with changing the capacitance value of the capacitor 502. The changed settings may be, for example, a constant of the decimation filter 405 or a frequency of a clock signal of the decimation filter 405. By controlling in such a manner in conjunction, the control circuit 132 can appropriately adjust the settings of the AD converter 131.

[0055] In the second-order ΔΣ modulator 404 shown in FIG. 4(b), the control circuit 132 can change the gain of the photoelectric conversion device 100 by changing the capacitance values ​​of the capacitance 502 and the capacitance 508. The control circuit 132 may change the capacitance value of only the capacitance 502, may change the capacitance value of only the capacitance 508, or may change the capacitance values ​​of both the capacitances 502 and 508. The operation of the AD converter 131 by changing the capacitance 508 is similar to the case of changing the capacitance 502. When changing the capacitance value of only one of the capacitances 502 and 508, the capacitance that is not changed does not need to be a variable capacitance.

[0056] The control circuit 132 may change the value of the analog current supplied from the DA converter 410 to the subtractor 408 for the same output from the quantizer 403 in conjunction with changing the capacitance value of the capacitor 508. Alternatively or in addition to this, the control circuit 132 may include changing the setting of the decimation filter 405 in conjunction with changing the capacitance value of the capacitor 508.

[0057] The control circuit 132 may be able to change the capacitance value of the capacitor 502 and the capacitance value of the capacitor 508 individually. For example, the control circuit 132 may set the capacitance value of the capacitor 502 and the capacitance value of the capacitor 508 to different values. For example, the control circuit 132 may adjust the variation in the circuit characteristics of the pixel circuit 111 and the readout circuit 121 by changing the capacitance value of the capacitor 502, and may adjust the variation in the characteristics of the AD converter 131 itself by changing the capacitance value of the capacitor 508.

[0058] In the above embodiment, correlated double sampling is performed in the readout circuit 121. Alternatively, the readout circuit 121 may supply the noise signal and the data signal to the AD converter 131, respectively, without performing correlated double sampling. The AD converter 131 performs AD conversion on the noise signal and the data signal, respectively. The signal processing circuit 150 may take the difference between the noise signal and the data signal after AD conversion. This can reduce variation in the characteristics of the AD converter 131 for each pixel column.

[0059] The control circuit 132 may set the capacitance 502 (and capacitance 508) to a different value when the AD converter 131 AD converts the data signal and when the AD converter 131 AD converts the noise signal. Generally, the noise signal has a smaller value than the data signal. Therefore, the control circuit 132 may set the capacitance value of the capacitance 502 when the AD converter 131 AD converts the noise signal to a smaller value than the capacitance value of the capacitance 502 when the AD converter 131 AD converts the data signal. This increases the number of inversions of the comparator 503 during the AD conversion of the noise signal, thereby improving the noise shaping effect. When different gains are set for the AD conversion of the data signal and the AD conversion of the noise signal, the difference in gain is adjusted by the signal processing circuit 150.

[0060] In the above embodiment, the photoelectric conversion device 100 has one AD converter 131 for each pixel column. Alternatively, the photoelectric conversion device 100 may have a common AD converter 131 for multiple pixel columns.

[0061] With reference to FIG. 8(a), an embodiment of a device 800 including a semiconductor device 803 will be described in detail. The semiconductor device 803 may be the photoelectric conversion device of any of the above-mentioned embodiments. The semiconductor device 803 may include a semiconductor device 801 and a package 802 that houses the semiconductor device 801. The package 802 may include a base to which the semiconductor device 801 is fixed, and a lid such as glass that faces the semiconductor device 801. The package 802 may further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a terminal (bonding pad) provided on the semiconductor device 801.

[0062] The device 800 may include at least one of an optical device 804, a control device 805, a processing device 806, a display device 807, a storage device 808, and a mechanical device 809. The optical device 804 is, for example, a lens, a shutter, or a mirror. The optical device 804 corresponds to a photoelectric conversion device. The control device 805 controls the semiconductor device 803. The control device 805 is, for example, a semiconductor device such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0063] The processing device 806 processes the signal output from the semiconductor device 803. The processing device 806 is a semiconductor device such as a CPU (Central Processing Unit) or ASIC for configuring an AFE (Analog Front End) or a DFE (Digital Front End). The display device 807 is an EL (Electro-Luminescence) display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 803. The storage device 808 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 803. The storage device 808 is a volatile memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory), or a non-volatile memory such as a flash memory or a hard disk drive.

[0064] The mechanical device 809 has a moving part or a propulsion part such as a motor or an engine. In the device 800, the signal output from the semiconductor device 803 is displayed on a display device 807, or transmitted to the outside by a communication device (not shown) included in the device 800. For this purpose, the device 800 may further include a storage device 808 and a processing device 806 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 803. The mechanical device 809 may be controlled based on the signal output from the semiconductor device 803.

[0065] The device 800 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 809 in the camera may drive components of the optical device 804 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 809 in the camera may move the semiconductor device 803 for vibration isolation operation.

[0066] The device 800 may be a transport device such as a vehicle, a ship, or an aircraft. The mechanical device 809 in the transport device may be used as a moving device. The device 800 as a transport device may be one that transports the semiconductor device 803, or one that assists and / or automates driving (piloting) by using a photographing function. The processing device 806 for assisting and / or automating driving (piloting) may perform processing for operating the mechanical device 809 as a moving device based on information obtained by the semiconductor device 803. Alternatively, the device 800 may be a medical device such as an endoscope, a measuring device such as an analytical distance sensor, an analytical device such as an electron microscope, or an office machine such as a copying machine.

[0067] An embodiment of an imaging system and a moving body will be described with reference to FIG. 8(b) and FIG. 8(c). FIG. 8(b) shows an example of an imaging system 810 related to an on-vehicle camera. The imaging system 810 has a photoelectric conversion device 811. The photoelectric conversion device 811 may be any of the photoelectric conversion devices of the above-mentioned embodiments. The imaging system 810 has an image processing unit 812, which is a processing device that performs image processing on a plurality of image data acquired by the photoelectric conversion device 811. The imaging system 810 also has a parallax acquisition unit 813, which is a processing device that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion device 811. The imaging system 810 further has a distance acquisition unit 814, which is a processing device that calculates a distance to an object based on the calculated parallax, and a collision determination unit 815, which is a processing device that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 813 and the distance acquisition unit 814 are examples of information acquisition means that acquire information such as distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 815 may determine the possibility of a collision using any of these pieces of distance information. The above-mentioned various processing devices may be realized by dedicated hardware, or may be realized by general-purpose hardware that performs calculations based on software modules. In addition, the processing device may be realized by an FPGA, an ASIC, or the like, or may be realized by a combination of these.

[0068] The imaging system 810 is connected to a vehicle information acquisition device 816, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 810 is also connected to a control ECU 817, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 815. That is, the control ECU 817 is an example of a moving body control means that controls a moving body based on distance information. The imaging system 810 is also connected to an alarm device 818 that issues an alarm to the driver based on the judgment result of the collision judgment unit 815. For example, when the judgment result of the collision judgment unit 815 indicates that a collision is highly likely, the control ECU 817 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 818 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., and vibrating a seat belt or steering wheel.

[0069] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are captured by the imaging system 810. Fig. 8(c) shows the imaging system 810 capturing an image of the area in front of the vehicle (imaging range 819). The vehicle information acquisition device 816 sends an instruction to operate the imaging system 810 to perform imaging.

[0070] In the above description, an example of control to avoid collision with other vehicles has been described, but the system can also be applied to automatic driving control to follow other vehicles, automatic driving control to avoid going out of lanes, etc. Furthermore, the imaging system is not limited to vehicles such as automobiles, but can be applied to moving bodies (transportation equipment) such as ships, aircraft, and industrial robots. The moving devices in moving bodies (transportation equipment) are various types of moving means such as engines, motors, wheels, and propellers. In addition, the system can be applied not only to moving bodies, but also to a wide range of equipment that uses object recognition, such as intelligent transport systems (ITS).

[0071] The above-described embodiments can be modified as appropriate without departing from the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the concepts described in this specification. In other words, if this specification contains a statement that "A is greater than B," for example, this specification discloses that "A is not greater than B" even if the statement that "A is not greater than B" is omitted. This is because when "A is greater than B" is stated, it is assumed that the case where "A is not greater than B" is taken into consideration. Claims are attached to publicize the scope of the invention. [Explanation of symbols]

[0072] 100 photoelectric conversion device, 111 pixel circuit, 121 readout circuit, 131 AD converter

Claims

1. A photoelectric conversion device, a light receiving circuit that converts light into an electrical signal; a read circuit that reads out an analog current signal corresponding to the electrical signal and reads out a noise signal from the light receiving circuit in a reset state; a ΔΣ AD converter that converts each of the analog current signal and the noise signal into a digital signal; A control circuit for changing a setting of the ΔΣ AD converter; The ΔΣ AD converter is a subtractor to which the analog current signal is supplied; an integrator for integrating an output from the subtractor; a quantizer for quantizing an integration result by the integrator; a decimation filter that performs a decimation process on the output from the quantizer; a digital-to-analog converter that supplies an analog current corresponding to an output from the quantizer to the subtractor so that the analog current signal is subtracted from the analog current signal; the integrator includes a variable capacitance that is charged by an output from the subtractor so as to integrate the output; changing the setting of the ΔΣ AD converter includes changing a capacitance value of the variable capacitor; The control circuit changes the value of the variable capacitance when the ΔΣ AD converter converts the analog current signal and when the ΔΣ AD converter converts the value of the noise signal.

2. 2. The photoelectric conversion device according to claim 1, wherein the control circuit changes a value of an analog current supplied from the DA converter to the subtractor for the same output from the quantizer in conjunction with changing a capacitance value of the variable capacitor.

3. 3. The photoelectric conversion device according to claim 1, wherein the control circuit changes a setting of the decimation filter in conjunction with changing a capacitance value of the variable capacitor.

4. the subtractor, the integrator, the analog current signal, the analog current, and the DA converter are a first subtractor, a first integrator, a first analog current signal, a first analog current, and a first DA converter, respectively; The ΔΣ AD converter is a second subtractor to which the second analog current signal is supplied from the first integrator; a second integrator that integrates an output from the second subtractor; a second DA converter that supplies a second analog current corresponding to the output from the quantizer to the second subtractor to be subtracted from the second analog current signal; The photoelectric conversion device according to claim 1 , further comprising:

5. the variable capacitance is a first variable capacitance, 5. The photoelectric conversion device according to claim 4, wherein the second integrator includes a second variable capacitance that is charged by the output from the second subtractor so as to integrate the output.

6. 6. The photoelectric conversion device according to claim 5, wherein the control circuit changes a value of a second analog current supplied from the second DA converter to the second subtractor for the same output from the quantizer in conjunction with changing the capacitance value of the second variable capacitor.

7. The photoelectric conversion device according to claim 6 , wherein the control circuit changes a setting of the decimation filter in conjunction with changing a capacitance value of the second variable capacitor.

8. 8. The photoelectric conversion device according to claim 5, wherein the control circuit is capable of changing a value of the first variable capacitance and a value of the second variable capacitance separately.

9. A photoelectric conversion device according to any one of claims 1 to 8, wherein the capacitance value of the variable capacitance when the ΔΣ AD converter converts the noise signal is smaller than the capacitance value of the variable capacitance when the ΔΣ AD converter converts the value of the analog current signal.

10. The photoelectric conversion device according to claim 1 , an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; A storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

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