Composition for semiconductor processing and method for manufacturing semiconductor device using the same

Abstract

To provide a composition for semiconductor processing, capable of achieving flat polishing results without deviation between films, and a method of fabricating a semiconductor device.SOLUTION: Provided is a composition for semiconductor processing, which is applicable to a semiconductor process including a semiconductor wafer polishing process including a through-silicon via 10, is capable of achieving excellent polishing performance, is capable of minimizing defects such as dishing, erosion, and protrusion, and is capable of achieving flat polishing results without deviation between films when polishing a surface where a plurality of different films are exposed to the outside. The composition for semiconductor processing includes abrasive grains and at least one additive, and has a value of 1.45 to 1.90 as calculated by the following equation. In the equation, RO represents a polishing rate (Å / min, same hereafter) of the polishing composition for semiconductor processing for a silicon oxide film, RN represents a polishing rate of the polishing composition for semiconductor processing for a silicon nitride film, and RCu represents a polishing rate of the polishing composition for semiconductor processing for a copper film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to compositions applicable to semiconductor manufacturing and processing steps, and more particularly to compositions applicable to polishing steps during semiconductor manufacturing and processing. [Background technology]

[0002] Chemical mechanical polishing (CME) is a technique that polishes the surface of a sample to a desired level by injecting a polishing slurry into the interface between the polishing pad and the surface of the object to be polished while rubbing the polishing pad against the surface of the object to be polished. Modern CME is used as an essential technique in the manufacture of large-scale semiconductor integrated circuits, for example, planarizing the surface of elements such as transistors and interlayer insulating films of multilayer wiring, planarizing various films such as oxide films and nitride films, and forming tungsten and copper wiring. As the integration density of semiconductor elements increases and the chip size decreases every year, the structure of the surface of semiconductor elements becomes more complex and the steps of interlayer films become larger. Therefore, high-resolution lithography and atomic level planarization technology are required for the chemical mechanical polishing (CMP) process applied to the manufacturing process of semiconductor elements. The CMP process uses physical friction and chemical reactions to flatten a film, and even slight differences in the process parts and / or process solutions used can produce completely different polishing results. Therefore, the precision required for the manufacture and design of these process parts and / or process solutions is currently at a higher level. Summary of the Invention [Problem to be solved by the invention]

[0003] An embodiment of the present invention provides a composition for semiconductor processing that is applied to a semiconductor wafer polishing process, more specifically, a semiconductor wafer polishing process including a through silicon via (TSV), and that realizes excellent polishing performance, minimizes defects such as dishing, erosion, and protrusion, and realizes flat polishing results without deviation between the film qualities when polishing a surface having a plurality of different film qualities.

[0004] The present invention provides a method for manufacturing semiconductor devices with minimized defect rates by applying the semiconductor process composition to polishing semiconductor wafers having TSVs formed therein, so that multiple stacked chips connected by the TSVs can realize the function of a memory chip without errors or defects. [Means for solving the problem]

[0005] The semiconductor processing composition according to the embodiment contains abrasive particles and at least one additive, and the value of the following formula 1 is 1.45 to 1.9.

[0006] [Formula 1] JPEG0007660607000001.jpg1017

[0007] In the above formula 1, the R O is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R N is the polishing rate (Å / min) of the semiconductor processing composition for the silicon nitride film, and R Cu is the polishing rate (Å / min) of the semiconductor process composition for the copper film; R O , R N and R Cuis a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and using this to polish wafers having each film for 60 seconds while supplying the semiconductor processing composition at a flow rate of 300 mL / min under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm.

[0008] In the composition for semiconductor processing according to an embodiment, the value of the following formula 2 may be 110.0 to 230.0.

[0009] [Formula 2] JPEG0007660607000002.jpg1024

[0010] In the above formula 2, R O , R N and R Cu is as defined in formula 1 above.

[0011] In the composition for semiconductor processing according to an embodiment, the value of the following formula 3 may be 0.90 to 1.00.

[0012] [Formula 3] JPEG0007660607000003.jpg97

[0013] In the above formula 3, R O and R Cu is as defined in formula 1 above.

[0014] In the composition for semiconductor processing according to an embodiment, the value of the following formula 4 may be 1.55 to 2.40.

[0015] [Formula 4] JPEG0007660607000004.jpg97

[0016] In the above formula 4, R N and R Cuis as defined in formula 1 above.

[0017] In one embodiment, the abrasive particles are silica (SiO 2 ), Ceria (CeO 2 ), Alumina (Al 2 O 3 ), Zirconia (ZrO 2 ), and combinations thereof.

[0018] In one embodiment, the abrasive particles may have a positive (+) zeta potential in the semiconductor processing composition.

[0019] In an embodiment, the additive may include one selected from the group consisting of an azole-based compound, a phosphoric acid-based compound, a fluorine-based compound, an organic acid, and combinations thereof.

[0020] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: preparing a platen on which a polishing pad having a polishing surface is mounted; preparing a carrier containing an object to be polished; rotating the platen and the carrier while rotating the platen and the carrier in a state in which the polishing surface of the polishing pad and the surface to be polished of the object to be polished are arranged to be in contact with each other; and supplying a composition for semiconductor processing onto the polishing surface, the composition for semiconductor processing including abrasive particles and at least one additive, and having a value of the following formula 1 of 1.45 to 1.90.

[0021] [Formula 1] JPEG0007660607000005.jpg1017

[0022] In the above formula 1, the R O is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R N is the polishing rate (Å / min) of the semiconductor processing composition for the silicon nitride film, and R Cuis the polishing rate (Å / min) of the semiconductor process composition for the copper film; R O , R N and R Cu is a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor process composition, and then using this to polish wafers having each film under conditions of carrier pressure of 3.0 psi, carrier rotation speed of 120 rpm, and platen rotation speed of 117 rpm, while pouring the semiconductor process composition onto the polishing surface at a flow rate of 300 mL / min for 60 seconds.

[0023] In one embodiment, the object to be polished may include a semiconductor wafer having a through silicon via.

[0024] In one embodiment, the rotation speed of the platen and the carrier may be 10 rpm to 500 rpm, respectively.

[0025] In one embodiment, the flow rate of the semiconductor processing composition injected onto the polishing surface may be 10 mL / min to 1,000 mL / min.

[0026] A method for manufacturing a semiconductor device according to an embodiment includes the steps of: forming a substrate including a via; forming a copper electrode disposed in the via; forming a silicon nitride film on the substrate and the copper electrode; forming a silicon oxide film on the silicon nitride film; and polishing the copper electrode, the silicon nitride film, and the silicon oxide film using a composition for semiconductor processing, the composition for semiconductor processing including abrasive particles and at least one additive, and having a value of the following formula 1 of 1.45 to 1.90.

[0027] [Formula 1] JPEG0007660607000006.jpg1017

[0028] In the above formula 1, the R Ois the polishing rate (Å / min) of the semiconductor process composition for the silicon oxide film, and R N is the polishing rate (Å / min) of the semiconductor processing composition for the silicon nitride film, and R Cu is the polishing rate (Å / min) of the semiconductor processing composition for the copper electrode.

[0029] In the method for manufacturing a semiconductor device according to an embodiment, the value of the above formula 1 may be about 1.50 to about 1.80.

[0030] In the method for manufacturing a semiconductor device according to an embodiment, the value of the following formula 2 may be about 110 to about 230.

[0031] [Formula 2] JPEG0007660607000007.jpg1024

[0032] In the method for manufacturing a semiconductor device according to an embodiment, the value of the following formula 3 may be 0.9 to 1.

[0033] [Formula 3] JPEG0007660607000008.jpg97

[0034] In the method for manufacturing a semiconductor device according to an embodiment, the polishing rate (R O ) is about 1000 Å / min to about 5000 Å / min, and the polishing rate (R N ) is about 400 Å / min to about 3000 Å / min, and the polishing rate (R Cu ) may be from about 1000 Å / min to about 5000 Å / min.

[0035] In the method for manufacturing a semiconductor device according to an embodiment, after the step of polishing the copper electrode, the silicon nitride film, and the silicon oxide film, a height difference between a polished surface of the copper electrode and a polished surface of the silicon nitride film may be less than about 5 nm.

[0036] In the method for manufacturing a semiconductor device according to an embodiment, after the step of polishing the copper electrode, the silicon nitride film, and the silicon oxide film, a height difference between a polished surface of the copper electrode and a polished surface of the silicon oxide film may be less than about 20 nm.

[0037] In the method for manufacturing a semiconductor device according to an embodiment, the additive may include one selected from the group consisting of an azole-based compound, a phosphate-based compound, a fluorine-based compound, an organic acid, and combinations thereof.

[0038] In the manufacturing method of a semiconductor device according to an embodiment, the abrasive particles may have a value of D90 divided by D80 ranging from 1 to 1.5. Effect of the Invention

[0039] The composition for semiconductor processing according to one embodiment is applied to a semiconductor process involving a semiconductor wafer polishing process, more specifically, a semiconductor wafer polishing process including a through silicon via (TSV), and realizes excellent polishing performance, minimizes defects such as dishing, erosion, and protrusion, and can realize a flat polishing result without deviation between the film qualities when polishing a surface having a plurality of different film qualities.

[0040] In addition, when the method for manufacturing a semiconductor device using the composition for semiconductor processing is applied, a semiconductor device with a minimized defect rate can be manufactured so that a plurality of stacked chips connected by structures such as the TSV can embody the function of a memory chip without errors or defects. [Brief description of the drawings]

[0041] [Figure 1] 2 is a schematic cross-sectional view in a thickness direction of a semiconductor wafer before being polished using a composition for semiconductor processing according to an embodiment; [Diagram 2]2 is a schematic cross-sectional view in a thickness direction of a semiconductor wafer after polishing, the semiconductor wafer being polished with a composition for semiconductor processing according to an embodiment; [Diagram 3] FIG. 3 is a partial plan view showing a schematic view of part A in FIG. 2. [Figure 4] 2 is a diagram illustrating a schematic configuration of an apparatus for manufacturing a semiconductor device according to an embodiment; [Diagram 5] 2 is a schematic diagram illustrating some examples of defects that may occur during polishing of a semiconductor wafer, which is an object of polishing using the semiconductor processing composition according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] The advantages and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the following embodiments or examples. However, the present invention is not limited to the embodiments or examples disclosed below, and may be embodied in various different forms. The embodiments or examples described below are provided only to complete the disclosure of the present invention and to inform those skilled in the art of the scope of the invention, and the scope of the present invention is defined by the scope of the claims.

[0043] In this specification, the terms "comprise," "contain," or "have" mean that other components may also be included, unless otherwise specified.

[0044] In describing a numerical range in this specification, the description "X to Y" means any one numerical value within the numerical range from X to Y, inclusive of X and Y.

[0045] In the drawings, the thickness of some components is exaggerated as necessary to clearly show layers or regions. Also, in the drawings, the thickness of some layers and regions is exaggerated for convenience of explanation. The same reference numerals throughout the specification refer to the same components.

[0046] In addition, when a layer, film, region, plate, or other part is referred to herein as being "on" or "above" another part, this is to be construed as including not only the case where it is "directly on" the other part, but also the case where there are other parts therebetween. When a part is referred to as being "directly on" another part, this is to be construed as meaning that there are no other parts therebetween. When a part is referred to as being "directly below" another part, this is to be construed as meaning that there are no other parts therebetween. When a part is referred to as being "directly below" another part, this is to be construed as meaning that there are no other parts therebetween.

[0047] Hereinafter, embodiments according to the present invention will be described in detail.

[0048] In one embodiment of the present invention, there is provided a composition for semiconductor processing, which comprises abrasive particles and at least one additive, and has a value of the following formula 1 of about 1.45 to about 1.90.

[0049] [Formula 1] JPEG0007660607000009.jpg1017

[0050] In the above formula 1, the R O is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R N is the polishing rate (Å / min) of the semiconductor processing composition for the silicon nitride film, and R Cu is the polishing rate (Å / min) of the semiconductor processing composition for the copper film.

[0051] At this time, the R O , R N and R Cuis a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and using this to polish wafers having each film for 60 seconds while supplying the semiconductor processing composition at a flow rate of 300 mL / min under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm.

[0052] As the integration of semiconductor devices becomes more advanced, packaging technology has been developed that forms fine vias in chips and then provides electrodes inside the vias to connect upper and lower chips with the electrodes, unlike the conventional technology of connecting chips using wires. These vias can be referred to as Through Silicon Vias (TSVs) in this specification. The TSV is a technology for stacking multiple chips to realize a large capacity semiconductor device, and has the advantage of significantly improving speed and power consumption compared to the existing wire bonding technology that connects chips using wires. However, a sophisticated processing technology is required to form fine vias in a semiconductor wafer and fill them with electrode material. Structurally, the TSV is a combination of a silicon oxide film that forms the main area of ​​a semiconductor wafer, copper that is mainly used as an electrode material charged in the via, and silicon nitride that performs a barrier function between the silicon oxide film and the copper electrode, and a process of simultaneously polishing various film qualities is necessarily included compared to a wafer that does not include TSVs. In this process, in order for different film qualities to be polished to have substantially the same flatness, it can be said that a fine and sophisticated design of the physical and / or chemical functions of the semiconductor processing composition used here is a very important factor.

[0053] The semiconductor processing composition according to an embodiment can polish the semiconductor wafer including the TSV to be flat without surface defects by satisfying the above formula 1, which shows the correlation between the polishing rates (Å / min) measured for each of a silicon oxide film, a copper film, and a silicon nitride film under specific conditions, within a predetermined range. More specifically, the composition can prevent defects such as excessive dishing or excessive protrusion caused by one side being excessively over-polished based on the boundary of a discontinuous structure on the polished surface, such as the TSV.

[0054] The above formula 1 means a ratio of the squared value of the polishing rate for the silicon oxide film to the value obtained by multiplying the polishing rate for the silicon nitride film by the polishing rate for the copper film, and can function as a technical means showing a significantly improved correlation in terms of predicting a polishing result without defects such as dishing, protrusion, erosion, or peaking, compared to the conventional polishing selectivity defined as a one-dimensional ratio of the polishing rates for the silicon oxide film, the copper film, and / or the silicon nitride film. That is, even if the one-dimensional polishing selectivity for each film quality, for example, the polishing rate ratio of silicon oxide film:copper film or the polishing rate ratio of silicon nitride film:copper film, satisfies a predetermined range, the actual polishing performance for the semiconductor wafer including the TSV may not reach a target level. However, it has been confirmed that the composition for semiconductor processing, which satisfies the value of the above formula 1 within a predetermined range, shows a correlation capable of realizing a performance with substantially no error when the polishing performance for the semiconductor wafer having the TSV formed therein reaches a target level.

[0055] FIG. 5 is a schematic diagram showing some examples of defects that may occur during polishing of a semiconductor wafer, which is a polishing target of the semiconductor processing composition according to an embodiment. Specifically, FIG. 5 is a schematic diagram showing some examples of defects that may occur during polishing of a semiconductor wafer 100 having a through-silicon via 10. More specifically, FIG. 5(a) is an example of dishing, which shows an example of a defect in which a copper film is polished more than other surrounding film materials. FIG. 5(b) is an example of protrusion, which shows an example of a defect in which a copper film is polished less than other surrounding film materials. FIG. 5(c) is an example of peaking, which shows an example of a defect in which a silicon nitride film protrudes from other surrounding film materials. 5(d) is an example of erosion, which shows an example of a defect in which a copper film, a silicon nitride film, and a silicon oxide film constituting a through silicon via (TSV) and its surroundings are generally over-polished compared to the surrounding silicon oxide film. It was confirmed that the composition for semiconductor processing satisfies the value of Equation 1 within a predetermined range, thereby showing a correlation capable of realizing a substantially error-free performance in terms of preventing the defects shown in FIG. 5 when the polishing performance for the semiconductor wafer having the TSV formed therein reaches a target level.

[0056] Specifically, the value of the formula 1 of the composition for semiconductor processing may be about 1.45 to about 1.90, for example, about 1.45 to about 1.80, for example, about 1.45 to about 1.70, for example, about 1.50 to about 1.90, for example, about 1.50 to about 1.90, for example, about 1.50 to about 1.80, for example, about 1.50 to about 1.70. If the value of the formula 1 is too small or too large, one side of the boundary of the discontinuous structure of various film materials related to the TSV may be excessively over-polished, causing dishing or protrusion, or peaking in which a silicon nitride film, which is a barrier film material, protrudes from a copper electrode and a silicon oxide film, or erosion in which a copper electrode and a barrier film containing silicon nitride are over-polished from a silicon oxide film may occur. The TSV structure occupies a relatively small area compared to the entire area of ​​the semiconductor wafer, and even a slight difference in the value of the above formula 1, for example a difference of about ±0.01, can affect whether or not these defects occur.

[0057] In an embodiment, the composition for semiconductor processing may have a value of about 110.0 to about 230.0 in the following formula 2:

[0058] [Formula 2] JPEG0007660607000010.jpg1024

[0059] In the above formula 2, the R O is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R N is the polishing rate (Å / min) of the semiconductor processing composition for the silicon nitride film, and R Cu is the polishing rate (Å / min) of the semiconductor processing composition for the copper film.

[0060] In addition, the R O , R N and R Cuis a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and using this to polish wafers having each film for 60 seconds while supplying the semiconductor processing composition at a flow rate of 300 mL / min under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm.

[0061] The composition for semiconductor processing may be more advantageous for polishing the semiconductor wafer including the TSVs flat without surface defects since the value of the formula 1 satisfies the above-mentioned range and the value of the formula 2 falls within the range of about 110.0 to about 230.0. Specifically, the composition may be more advantageous for preventing defects such as excessive dishing or excessive protrusion caused by excessive over-polishing on one side based on the boundary of a discontinuous structure of the polished surface such as the TSVs.

[0062] Specifically, the value of formula 2 of the composition for semiconductor processing may be, for example, about 110.0 to about 230.0, for example, about 110.0 to about 200.0, for example, about 110.0 to about 190.0, for example, about 110.0 to about 180.0, for example, about 110.0 to about 170.0, for example, about 110.0 to about 160.0, for example, about 110.0 to about 150.0, for example, about 110.0 to about 140.0, for example, about 115.0 to about 135.0. By satisfying such a range, the value of formula 2 can be further improved in the polishing of a semiconductor wafer having a structure including a through silicon via (TSV) in a predetermined area of ​​the entire area, so that various film qualities due to the through silicon via (TSV) can be polished flat at the same time.

[0063] In an embodiment, the composition for semiconductor processing may have a value of about 0.90 to about 1.00 in the following formula 3:

[0064] [Formula 3] JPEG0007660607000011.jpg97

[0065] In the above formula 3, the R O is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R Cu is the polishing rate (Å / min) of the semiconductor processing composition for the copper film, and R O and R Cu is a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and using this to polish wafers having each film for 60 seconds while supplying the semiconductor processing composition at a flow rate of 300 mL / min under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm.

[0066] Specifically, the value of the above formula 3 of the composition for semiconductor processing may be, for example, about 0.90 to about 1.00, for example, about 0.90 or more and less than about 1.00, for example, about 0.90 to about 0.99, for example, about 0.91 to about 0.99, for example, about 0.92 to about 0.99, for example, about 0.93 to about 0.99, for example, about 0.94 to about 0.99, for example, about 0.95 to about 0.99. The through silicon via (TSV) structure occupies a relatively small area with respect to the entire area of ​​the semiconductor wafer, and even a slight difference, for example, a difference of about ±0.01, in the value of the above formula 3 may affect the occurrence of defects such as dishing, protrusion, erosion, and / or peaking. From this perspective, the composition for semiconductor processing has a polishing rate (R Cu ) is the polishing rate (R O ), it is more advantageous for simultaneously polishing flat the copper electrode portion of the through silicon via (TSV) and the silicon oxide film portion occupying a major area of ​​the entire area of ​​the semiconductor wafer in a semiconductor wafer including the through silicon via (TSV) at a predetermined area ratio. More specifically, the polishing rate (R Cu ) is the polishing rate (R O) these technical effects can be further improved.

[0067] In an embodiment, the semiconductor processing composition may be more advantageous in that, in a semiconductor wafer including the through silicon via (TSV) at a predetermined area ratio, boundaries of discontinuous various film qualities due to the through silicon via (TSV) can be polished flat at the same time without defects such as dishing, protrusion, erosion, and / or peaking, since the formula 1, the formula 2, and the formula 3 simultaneously satisfy the respective ranges described above.

[0068] In an embodiment, the composition for semiconductor processing may have a value of about 1.55 to about 2.40 in the following formula 4:

[0069] [Formula 4] JPEG0007660607000012.jpg97

[0070] In the above formula 4, the R N is the polishing rate (Å / min) of the semiconductor processing composition for the silicon nitride film, and R Cu is the polishing rate (Å / min) of the semiconductor processing composition for the copper film, and R N and R Cu is a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and using this to polish wafers having each film for 60 seconds while supplying the semiconductor processing composition at a flow rate of 300 mL / min under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm.

[0071] Specifically, the value of the above formula 4 of the composition for semiconductor processing is, for example, about 1.55 to about 2.40, for example, about 1.55 to about 2.30, for example, about 1.55 to about 2.20, for example, about 1.55 to about 2.10, for example, about 1.55 to 2.00, for example, about 1.55 to 1.95, for example, about 1.55 to about 1.90, for example, about 1.55 to about 1.8 5, for example, 1.60 to about 2.40, for example, about 1.60 to about 2.30, for example, about 1.60 to about 2.20, for example, about 1.60 to about 2.10, for example, about 1.60 to about 2.00, for example, about 1.60 to about 1.95, for example, about 1.60 to about 1.90, for example, about 1.60 to about 1.85, for example, about 1.65 to about 1.85. The through silicon via (TSV) structure occupies a relatively small area with respect to the entire area of ​​the semiconductor wafer, and even a slight difference in the value of the above formula 4, for example, a difference of about ±0.01, may affect the occurrence of defects such as dishing, protrusion, erosion, and / or peaking. From this perspective, the composition for semiconductor processing has a polishing rate (R Cu ) and the polishing rate for silicon nitride film (R N ) is designed to satisfy the above-mentioned ratio, it may be more advantageous to simultaneously polish flatly the copper electrode portion of the through-silicon via (TSV) and the silicon nitride film surrounding the copper electrode portion and functioning as a barrier film in a semiconductor wafer including the through-silicon via (TSV) at a predetermined area ratio.

[0072] In one embodiment, the composition for semiconductor processing may be more advantageous in that, in a semiconductor wafer including the through silicon via (TSV) at a predetermined area ratio, the boundaries of various discontinuous film qualities due to the through silicon via (TSV) are simultaneously polished flat without defects such as dishing, protrusion, erosion, and / or peaking, when the formulas 1, 2, 3, and 4 of the composition for semiconductor processing simultaneously satisfy the respective ranges described above, so that the technical effects are maximized.

[0073] In the semiconductor processing composition according to an embodiment, the polishing rate (R O ) may be, for example, about 1000 Å / min to about 5000 Å / min, for example, about 1500 Å / min to about 5000 Å / min, for example, about 2000 Å / min to about 5000 Å / min, for example, about 2500 Å / min to about 5000 Å / min, for example, about 3000 Å / min to about 5000 Å / min, for example, about 3500 Å / min to about 5000 Å / min, for example, about 4000 Å / min to about 5000 Å / min, for example, about 4000 Å / min to about 4500 Å / min. O is a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and using the mixture to polish a semiconductor wafer having a silicon oxide film for 60 seconds under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm, while pouring the semiconductor processing composition at a flow rate of 300 mL / min. The semiconductor processing composition realizes a polishing rate for the silicon oxide film, which occupies a major part of the entire area of ​​the semiconductor wafer, within these ranges, thereby improving the overall process efficiency and being more advantageous in terms of preventing defects such as erosion in simultaneous polishing of discontinuous film quality related to the through silicon via (TSV).

[0074] In the semiconductor processing composition according to an embodiment, the polishing rate (R N ) may be about 400 Å / min to about 3000 Å / min, for example, about 450 Å / min to about 2800 Å / min, for example, about 1500 Å / min to about 3000 Å / min, for example, about 1600 Å / min to about 3000 Å / min, for example, about 1800 Å / min to about 3000 Å / min, for example, about 1900 Å / min to about 3000 Å / min, for example, about 2000 Å / min to about 3000 Å / min, for example, about 2000 Å / min to about 2800 Å / min, for example, about 2200 Å / min to about 2800 Å / min. N is a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and polishing a semiconductor wafer having a silicon oxide film for 60 seconds using the composition under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm, while pouring the composition into the semiconductor processing composition at a flow rate of 300 mL / min. By realizing the polishing rate of the semiconductor processing composition for the silicon nitride film functioning as a barrier film surrounding the edge of the through silicon via (TSV) within these ranges, it may be more advantageous to effectively prevent silicon nitride film peaking defects that occur when other film qualities around the silicon nitride film are over-polished compared to the silicon nitride film.

[0075] In the semiconductor processing composition according to an embodiment, the polishing rate (R Cu ) may be about 1000 Å / min to about 5000 Å / min, for example, about 1500 Å / min to about 5000 Å / min, for example, about 2000 Å / min to about 5000 Å / min, for example, about 2500 Å / min to about 5000 Å / min, for example, about 3000 Å / min to about 5000 Å / min, for example, about 3500 Å / min to about 5000 Å / min, for example, about 4000 Å / min to about 5000 Å / min, for example, about 4000 Å / min to about 4500 Å / min. Cuis a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and using the mixture to polish a semiconductor wafer having a silicon oxide film for 60 seconds under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm, while pouring the semiconductor processing composition at a flow rate of 300 mL / min. The semiconductor processing composition exhibits a polishing rate within these ranges for copper used as an electrode material for filling the through silicon via (TSV), which may be more advantageous in terms of preventing defects such as dishing caused by over-polishing of the copper film or protrusion caused by the copper film not being polished to a desired level.

[0076] As described above, the semiconductor processing composition can be applied to polishing the surface of a semiconductor wafer having a through silicon via (TSV). Fig. 1 is a schematic cross-sectional view in a thickness direction of a semiconductor wafer 100 before polishing, which is a target of polishing with the semiconductor processing composition according to an embodiment, Fig. 2 is a schematic cross-sectional view in a thickness direction of the semiconductor wafer 100 after polishing, and Fig. 3 is a schematic partial plan view of part A of Fig. 2.

[0077] 1 to 3, the semiconductor wafer 100 may include a substrate 50, and a silicon nitride film 20 and a silicon oxide film 40 disposed on the substrate 50. The semiconductor wafer 100 may also include a through-silicon electrode 10, which may include a via 11 penetrating the substrate 50 and a copper electrode 30 disposed therein. In one embodiment, the substrate 50 may include silicon (Si).

[0078] 1 and 2, in a polishing process in a semiconductor device manufacturing process, as the unpolished wafer 100 is polished from the top surface, each film is polished away, and as shown in FIG. 2, the wafer 100 after polishing has a structure in which a silicon oxide film 40, a silicon nitride film 20, and a copper electrode 30 are all present on the top surface. In the semiconductor device manufacturing process, after a certain time has passed since polishing began, different types of films appear on the top surface of the wafer, i.e., the surface to be polished. However, since different types of films are polished simultaneously under the same physical polishing conditions, such as the rotation speed of the carrier, the rotation speed of the polishing pad, and the pressure conditions of the carrier, the chemical action of the semiconductor process composition is important in order to polish them flatly.

[0079] The semiconductor processing composition can polish different film qualities on the wafer 100 to substantially the same flatness due to the through silicon electrode 10, by satisfying the above-mentioned ranges of Formula 1, Formula 2, Formula 3, and / or Formula 4, respectively. In particular, in polishing the semiconductor wafer 100 having a structure in which the areas of the through silicon electrode 10 and the silicon nitride film 20 have a predetermined area ratio to the entire area of ​​the semiconductor wafer 100, the numerical ranges of Formula 1, Formula 2, Formula 3, and / or Formula 4 may be more advantageous in terms of showing a correlation corresponding to the effect of realizing a polishing flatness without defects.

[0080] 2 and 3, the silicon nitride film 20 has a structure in which a portion thereof surrounds the periphery of the copper electrode 30, and this portion may function as an insulating film and a barrier film. Specifically, the silicon nitride film 20 may function to prevent copper atoms from diffusing from the copper electrode 30 to the substrate 50.

[0081] 3, in one embodiment, the ratio (D2 / D1) of the diameter (D2) of the copper electrode 30 to the overall diameter (D1) of the copper electrode 30 and the silicon nitride film 20 surrounding it may be about 0.5 to about 1.0, for example, about 0.7 to about 1.0, for example, about 0.5 or more and less than about 1.0, for example, about 0.7 or more and less than about 1.0. The composition for semiconductor processing is used to polish semiconductor wafers having these pattern structures, and the characteristic that the numerical ranges of the formula 1, the formula 2, the formula 3, and / or the formula 4 of the composition for semiconductor processing satisfy the above-mentioned ranges may be more advantageous in terms of showing an excellent correlation with the effect of preventing excessive dishing or protrusion of the copper electrode 30.

[0082] In one embodiment, the ratio (2T1 / D1) of the thickness (T1) of the silicon nitride film 20 to the overall diameter (D1) of the copper electrode 30 and the silicon nitride film 20 surrounding it may be about 0.1 to about 0.5, for example, about 0.1 to about 0.3. By using semiconductor wafers having such pattern structures as the polishing target, the characteristic that the numerical ranges of the formula 1, the formula 2, the formula 3, and / or the formula 4 of the composition for semiconductor processing satisfy the above-mentioned ranges respectively may be more advantageous in terms of showing an excellent correlation with the effect of preventing peaking of the silicon nitride film 20.

[0083] The composition for semiconductor processing may include abrasive particles and at least one additive. The numerical range of the formula 1, the formula 2, the formula 3, and / or the formula 4 of the composition for semiconductor processing may reach an optimal range as a comprehensive result of carefully designing the composition and content of the abrasive particles and at least one additive.

[0084] In one embodiment, the abrasive particles may include inorganic particles, organic particles, or organic-inorganic composite particles. In this specification, "inorganic particles" and "organic particles" refer to particulate structures mainly composed of inorganic and organic components, respectively, and should be understood as a concept that includes the case where each contains a trace amount of a different component, that is, in the case of the inorganic particles, a trace amount of organic components, and in the case of the organic particles, a trace amount of inorganic components. In this case, "trace amount" refers to a content of about 0.005 wt% to about 0.03 wt% of the total 100 wt% of the abrasive particles. In this specification, "organic-inorganic composite particles" refers to particles that contain an organic component and an inorganic component, but one of the two components is contained in an amount of 50 wt% to 90 wt%.

[0085] In one embodiment, the abrasive particles may include inorganic particles. The inorganic particles may be, for example, silica (SiO 2 ), Ceria (CeO 2 ), Alumina (Al 2 O 3 ), Zirconia (ZrO 2 ), and combinations thereof. When the abrasive particles include inorganic particles, the chemical compatibility with the at least one additive can be adjusted within a predictable range during application of the semiconductor processing composition, thereby minimizing side effects due to sudden changes in polishing performance.

[0086] In some embodiments, the abrasive particles may be in a colloidal state, for example, the abrasive particles may include colloidal inorganic particles.

[0087] The hydrogen ion concentration (pH) of the semiconductor process composition may be about 2 to about 5, for example, about 3 or more and about 5 or less, for example, about 3 or more and less than about 5.

[0088] The zeta potential value of the polishing particles in the semiconductor process composition can show a positive (+) value. Specifically, the polishing particles in the semiconductor process composition include inorganic particles and can show a positive (+) zeta potential value. The zeta potential value of the polishing particles in the semiconductor process composition can be about +5 mV to about +50 mV, for example, about +10 mV to about +40 mV, for example, about +10 mV to about +30 mV, for example, about 18 mV to about 40 mV. The zeta potential of the polishing particles in the semiconductor process composition is not particularly limited in its measurement method, but can be measured, for example, by using a zeta potential measurement device (Malvern, Zeta-sizer Nano ZS) after putting about 1 mL of the semiconductor process composition into a measurement cell. For example, the zeta potential value can be an average value of about 100 measurements.

[0089] When the hydrogen ion concentration (pH) of the composition for semiconductor processing satisfies the above-mentioned range and the zeta potential value of the abrasive particles in the composition for semiconductor processing satisfies the above-mentioned range, the polishing characteristics for the semiconductor wafer can be optimally designed. Specifically, the abrasive particles should be adsorbed to the polished surface of the semiconductor wafer at a predetermined level or higher and be easily separated at a predetermined level or higher. If the abrasive particles are adsorbed to the polished surface of the semiconductor wafer due to excessive adsorption force and are not easily separated, defects such as scratches may occur on the polished surface. Conversely, if the abrasive particles are not adsorbed to the polished surface with a predetermined attraction force and have excessive fluidity, the physical friction force may decrease and the polishing rate may not reach the desired level. Considering this, when the hydrogen ion concentration (pH) of the composition for semiconductor processing satisfies the above-mentioned range and the zeta potential value of the abrasive particles in the composition for semiconductor processing satisfies the above-mentioned range, the abrasive particles can secure an appropriate level of adsorption to the polished surface of the semiconductor wafer and can be easily separated from the polished surface, which can be advantageous for securing a desired level of polishing rate and maximizing the defect prevention effect. These technical effects can be expressed in meaningful polishing results when the surface to which the composition for semiconductor processing is applied includes a silicon nitride film and a copper film, and can be further maximized in particular in polishing including a silicon oxide film.

[0090] In one embodiment, the abrasive particles may include particles that have been surface-treated so that the zeta potential value of the abrasive particles in the semiconductor processing composition is positive (+). Specifically, the abrasive particles may include inorganic particles, and the inorganic particles may include particles that have been surface-treated with at least one organic component.

[0091] The amount of the at least one organic component applied to the inorganic particle surface treatment, relative to 100 parts by weight of the inorganic particles, may be, for example, about 0.005 parts by weight to about 0.05 parts by weight, for example, about 0.005 parts by weight to about 0.04 parts by weight, for example, about 0.005 parts by weight to about 0.030 parts by weight, for example, about 0.005 parts by weight to about 0.020 parts by weight, for example, about 0.005 parts by weight or more and less than about 0.020 parts by weight, for example, about 0.005 parts by weight to about 0.015 parts by weight, for example, about 0.005 parts by weight to about 0.010 parts by weight, for example, about 0.005 parts by weight or more and less than about 0.010 parts by weight. From another perspective, if the surface modification rate is defined as 100% when the amount of at least one organic component applied to the inorganic particle surface treatment is 0.010 parts by weight per 100 parts by weight of the inorganic particles, the modification rate of the inorganic particle surface may be about 50% to about 500%, for example, about 50% to about 400%, for example, about 50% to about 300%, for example, about 50% to about 200%, for example, about 50% or more and less than about 200%, for example, about 50% to about 150%, for example, about 50% to about 100%, for example, about 50% or more and less than about 100%. When the treatment level of the inorganic particle surface satisfies these ranges, the polishing action of the abrasive particles can be advantageous because the values ​​of the above formula 1, formula 2, formula 3, and / or formula 4 satisfy the optimal ranges, and as a result, when simultaneously polishing different types of films, it can be more advantageous in terms of realizing excellent flatness and preventing surface defects such as scratches. Also, when the treatment level of the inorganic particle surface is excessive, it can be more advantageous in effectively preventing side effects caused by the abrasive particles remaining as excess material.

[0092] For the inorganic particle surface treatment, the at least one organic component may include, for example, one selected from the group consisting of amino silane, alkoxy silane, ethoxy silane, epoxy silane, and combinations thereof.

[0093] In another embodiment, the abrasive particle may include particles having cation sites disposed therein such that the zeta potential value of the abrasive particle in the semiconductor processing composition is positive (+). Specifically, the abrasive particle may include inorganic particles, and the inorganic particles may include cation sites disposed therein. The cation sites may be disposed in the interior of the particles by reacting a base component of the particles with a component providing the cation sites during preparation of the inorganic particles.

[0094] The cationic site providing component may include, for example, one selected from the group consisting of amino silane, alkoxy silane, ethoxy silane, epoxy silane, and combinations thereof.

[0095] In one embodiment, the inorganic particles are silica (SiO 2 ), and at least one organic component applied to the inorganic particle surface treatment, or the cation site providing component for providing cation sites in the interior of the particle, can comprise an aminosilane or an epoxysilane.

[0096] For example, the at least one organic component or the cationic site providing component applied in the surface treatment may comprise an aminosilane and an epoxysilane, and the molar ratio of the aminosilane to the epoxysilane may be from about 10:1 to about 5:1, such as from about 10:1 to about 6:1, such as from about 10:1 to about 7:1, such as from about 10:1 to about 8:1, such as from about 9.5:1 to about 8.5:1, such as about 9:1.

[0097] In another embodiment, the abrasive particles may include organic / inorganic composite particles, which may be particles having a core-shell structure including, for example, a core including a polymer and a shell including an inorganic component disposed on the surface of the core.

[0098] In an embodiment, the core polymer of the organic-inorganic composite particle may include, for example, polymethylmethacrylate (PMMA), polystyrene (PS), etc. The shell inorganic component may include, for example, silica (SiO 2 ), Ceria (CeO 2 ), Alumina (Al 2 O 3 ), Titania (TiO 2 ), Zirconia (ZrO 2 ), Germanium (GeO 2 ) etc.

[0099] The abrasive particles may have an average particle size (D50) of, for example, about 5 nm to about 150 nm, for example, about 5 nm to about 100 nm, for example, about 5 nm to about 80 nm, for example, about 10 nm to about 80 nm, for example, about 30 nm to about 50 nm, for example, about 35 nm to about 50 nm, for example, about 40 nm to about 50 nm, for example, about 42 nm to about 48 nm. By applying abrasive particles of these sizes, the chemical and physical etching function of the semiconductor process composition is also appropriately ensured, and it may be more advantageous for the values ​​of the above formula 1, the above formula 2, the above formula 3, and / or the above formula 4 to satisfy the optimal range.

[0100] In this particle distribution, the abrasive particles may have a 10% cumulative mass particle size distribution diameter (D10) of, for example, about 5 nm to about 50 nm, for example, about 5 nm to about 35 nm, for example, about 10 nm to about 35 nm, for example, about 20 nm to about 35 nm, for example, about 23 nm to about 33 nm.

[0101] In this particle distribution, the abrasive particles may have an 80% cumulative mass particle size distribution diameter (D80) of, for example, about 5 nm to about 60 nm, for example, about 10 nm to about 60 nm, for example, about 20 nm to about 60 nm, for example, about 25 nm to about 60 nm, for example, about 35 nm to about 60 nm, for example, about 40 nm to about 55 nm, for example, about 40 nm to about 50 nm.

[0102] In this particle distribution, the abrasive particles may have a 90% cumulative mass particle size distribution diameter (D90) of, for example, about 40 nm to about 150 nm, for example, about 40 nm to about 100 nm, for example, about 45 nm to about 80 nm, for example, about 45 nm to about 65 nm, for example, 50 nm to about 60 nm.

[0103] For example, in this particle distribution, the abrasive particles may have a 10% cumulative mass particle size distribution diameter (D10) of about 23 nm to about 33 nm, a 50% cumulative mass particle size distribution diameter (D80) of about 40 nm to about 50 nm, and a 90% cumulative mass particle size distribution diameter (D90) of about 50 nm to about 60 nm.

[0104] The abrasive particles may satisfy the condition of 1.00≦D90 / D80≦1.50, for example, 1.50≦D90 / D10≦2.70, for example, 1.20≦D80 / D10≦2.20 in this particle distribution. By applying the abrasive particles having such a particle distribution, the composition for semiconductor processing may be more advantageous in satisfying the value of the above formula 1 in a predetermined range, and may be more advantageous in calculating the corresponding excellent polishing result.

[0105] The method for measuring the particle size distribution of the abrasive particles is not particularly limited, and can be derived using any general-purpose equipment used in the art for analyzing particle sizes of nano (nm)-sized particle powders.

[0106] In an embodiment, the composition for semiconductor processing may include the abrasive particles in an amount of about 0.5 wt % to about 5.0 wt %, for example, about 0.5 wt % to about 4.5 wt %, for example, about 0.5 wt % to about 4.0 wt %, for example, about 0.5 wt % to about 3.5 wt %, for example, about 1.0 wt % to about 5.0 wt %, for example, about 1.5 wt % to about 5.0 wt %, for example, about 2.0 wt % to about 5.0 wt %, for example, about 2.5 wt % to about 5.0 wt %, for example, about 1.0 wt % to about 4.5 wt %, for example, about 1.5 wt % to about 4.0 wt %, for example, about 2.0 wt % to about 4.0 wt %, for example, about 2.5 wt % to about 3.5 wt %. By including the abrasive particles in these amounts, the composition for semiconductor processing can appropriately ensure fluidity during the polishing process, and this physical etching action can be more advantageous in realizing a polishing rate by making the values ​​of Equation 1, Equation 2, Equation 3, and / or Equation 4 reach optimal ranges.

[0107] The composition for semiconductor processing may include at least one additive, which may mainly play a role in adjusting the state of the surface to be polished by chemical reaction to obtain optimal polishing results.

[0108] The at least one additive may include an organic acid. The organic acid may mainly play a role in adjusting the hydrogen ion concentration (pH) of the composition for semiconductor processing. The organic acid may be, for example, acetic acid (CH 3 The acid may include one selected from the group consisting of COOH, acetic acid, formic acid, benzoic acid, nicotinic acid, picolinic acid, and combinations thereof.

[0109] In one embodiment, the organic acid is used in an amount of about 0.50 parts by weight to about 10.00 parts by weight, for example, about 0.50 parts by weight to about 9.00 parts by weight, for example, about 0.50 parts by weight to about 8.00 parts by weight, for example, about 0.50 parts by weight to about 7.00 parts by weight, about 0.50 parts by weight to about 6.00 parts by weight, for example, about 0.50 parts by weight to about 5.00 parts by weight, for example, about 0.50 parts by weight to about 4.00 parts by weight, for example, about 0.50 parts by weight to about 3.50 parts by weight, for example, about It may be contained in an amount of 1.00 parts by weight to about 10.00 parts by weight, for example, about 1.00 parts by weight to about 10.00 parts by weight, for example, about 1.50 parts by weight to about 10.00 parts by weight, for example, about 1.00 parts by weight to about 8.00 parts by weight, for example, about 1.00 parts by weight to about 6.00 parts by weight, for example, about 1.50 parts by weight to about 5.00 parts by weight, for example, about 1.00 parts by weight to about 3.50 parts by weight, for example, about 1.50 parts by weight to about 3.50 parts by weight, for example, about 1.60 parts by weight to about 3.00 parts by weight.

[0110] The at least one additive may include an inorganic acid. The inorganic acid may mainly control the hydrogen ion concentration (pH) of the composition for semiconductor processing. The inorganic acid may be, for example, hydrochloric acid (HCl), phosphoric acid (H 3 PO 4 ), sulfuric acid (H 2 SO 4 ), nitric acid (HNO 3 ), boric acid (H 3 BO 3 ), Carbonic acid (H 2 CO 3 ), hydrofluoric acid (HF), hydrobromic acid (HBr), perchloric acid (HClO 4 ), hydroiodic acid (HI), and combinations thereof. More specifically, the inorganic acid may include one selected from the group consisting of phosphoric acid (H 3 PO 4 ), nitric acid (HNO 3 ), and combinations thereof. When these types of inorganic acids are used, the pH is easily adjusted and the effect of preventing the occurrence of aggregation is excellent.

[0111] In one embodiment, the inorganic acid is used in an amount of about 0.50 parts by weight to about 10.00 parts by weight, for example, about 0.50 parts by weight to about 9.00 parts by weight, for example, about 0.50 parts by weight to about 8.00 parts by weight, for example, about 0.50 parts by weight to about 7.00 parts by weight, about 0.50 parts by weight to about 6.00 parts by weight, for example, about 0.50 parts by weight to about 5.00 parts by weight, for example, about 0.50 parts by weight to about 4.00 parts by weight, for example, about 0.50 parts by weight to about 3.50 parts by weight, for example, about It may be contained in an amount of 1.00 parts by weight to about 10.00 parts by weight, for example, about 1.00 parts by weight to about 10.00 parts by weight, for example, about 1.50 parts by weight to about 10.00 parts by weight, for example, about 1.00 parts by weight to about 8.00 parts by weight, for example, about 1.00 parts by weight to about 6.00 parts by weight, for example, about 1.50 parts by weight to about 5.00 parts by weight, for example, about 1.00 parts by weight to about 3.50 parts by weight, for example, about 1.50 parts by weight to about 3.50 parts by weight, for example, about 1.60 parts by weight to about 3.00 parts by weight.

[0112] The at least one additive may include an azole-based compound, which may mainly play a role in adjusting the properties of the copper film surface. The azole compound may include, for example, one selected from the group consisting of imidazole, 5-aminotetrazole, benzotriazole (BTA), 5-methyl-1H-benzotriazole (5-MBTA), 3-amino-1,2,4-triazole, 5-phenyl-1H-tetrazole, 3-amino-5-methyl-4H-1,2,4-triazole, 5-aminotetrazole (ATZ), 1,2,4-triazole, tolyltriazole, and combinations thereof.

[0113] In one embodiment, the composition for semiconductor processing contains about 0.01 parts by weight to about 5.00 parts by weight, for example, about 0.01 parts by weight to about 4.50 parts by weight, for example, about 0.01 parts by weight to about 4.00 parts by weight, for example, about 0.01 parts by weight to about 3.50 parts by weight, for example, about 0.01 parts by weight to about 3.00 parts by weight, for example, about 0.01 parts by weight to about 2.50 parts by weight, for example, about 0.01 parts by weight to about 2.00 parts by weight, for example, about 0.01 parts by weight to about 1.5 0 parts by weight, for example, about 0.05 parts by weight to about 5.00 parts by weight, for example, about 0.10 parts by weight to about 5.00 parts by weight, for example, about 0.20 parts by weight to about 5.00 parts by weight, for example, about 0.10 parts by weight to about 4.00 parts by weight, for example, about 0.20 parts by weight to about 3.00 parts by weight, for example, about 0.20 parts by weight to about 2.50 parts by weight, for example, about 0.20 parts by weight to about 2.00 parts by weight, for example, about 0.20 parts by weight to about 1.50 parts by weight, for example, more than about 0.20 parts by weight and not more than about 1.50 parts by weight.

[0114] The at least one additive may include an organic acid salt. The organic acid salt may mainly play a role in adjusting the properties of the copper film surface. The organic acid salt may include, for example, one selected from the group consisting of a salicylate, a benzoate, a phthalate, and combinations thereof. In one embodiment, the organic acid salt may include a salicylate, more specifically, a betaine salicylate.

[0115] In one embodiment, the composition for semiconductor processing contains about 0.01 parts by weight to about 5.00 parts by weight, for example, about 0.01 parts by weight to about 4.50 parts by weight, for example, about 0.01 parts by weight to about 4.00 parts by weight, for example, about 0.01 parts by weight to about 3.50 parts by weight, for example, about 0.01 parts by weight to about 3.00 parts by weight, for example, about 0.01 parts by weight to about 2.50 parts by weight, for example, about 0.01 parts by weight to about 2.00 parts by weight, for example, about 0.01 parts by weight to about 1.50 parts by weight, of the organic acid salt relative to 100 parts by weight of the abrasive particles. For example, about 0.05 parts by weight to about 5.00 parts by weight, for example, about 0.10 parts by weight to about 5.00 parts by weight, for example, about 0.50 parts by weight to about 5.00 parts by weight, for example, about 0.10 parts by weight to about 4.00 parts by weight, for example, about 0.50 parts by weight to about 3.00 parts by weight, for example, about 0.50 parts by weight to about 2.50 parts by weight, for example, about 0.50 parts by weight to about 2.00 parts by weight, for example, about 0.50 parts by weight to about 1.50 parts by weight, for example, more than about 0.50 parts by weight, or less than about 1.50 parts by weight.

[0116] In one embodiment, the composition for semiconductor processing includes the azole-based compound and the organic acid salt, and the weight ratio of the azole-based compound to the organic acid salt may be greater than about 1:1 and less than about 1:3, for example, about 1:1.2 to about 1:3.0, for example, about 1:1.5 to about 1.2.5, for example, about 1:1.8 to about 1:2.2. By using the azole-based compound and the organic acid salt in this weight ratio, it may be advantageous to realize adjustment of polishing characteristics for copper film to a desired level.

[0117] The at least one additive may include a phosphoric acid compound. The phosphoric acid compound may play a role in adjusting the polishing characteristics of the silicon nitride film. For example, the phosphoric acid compound may include one selected from the group consisting of tetrapotassium pyrophosphate, phosphomolybdic acid, nitrilotris(methylenephosphonic acid), phosphorus trichloride, and combinations thereof.

[0118] In an embodiment, the composition for semiconductor processing contains about 0.10 parts by weight to about 2.00 parts by weight, for example, about 0.10 parts by weight to about 1.80 parts by weight, for example, about 0.10 parts by weight to about 1.60 parts by weight, for example, about 0.10 parts by weight to about 1.40 parts by weight, for example, about 0.10 parts by weight to about 1.20 parts by weight, for example, about 0.20 parts by weight to about 2.00 parts by weight, for example, about 0.40 parts by weight to about 2.00 parts by weight, for example, about It may be contained in an amount of 0.50 parts by weight to about 2.00 parts by weight, for example, about 0.60 parts by weight to about 2.00 parts by weight, for example, about 0.40 parts by weight to about 1.80 parts by weight, for example, about 0.40 parts by weight to about 1.60 parts by weight, for example, about 0.50 parts by weight to about 1.50 parts by weight, for example, about 0.50 parts by weight to about 1.40 parts by weight, for example, about 0.50 parts by weight to about 1.20 parts by weight, for example, about 0.60 parts by weight to about 1.40 parts by weight, for example, about 0.60 parts by weight to about 1.20 parts by weight.

[0119] The at least one additive may include a fluorine-based compound, which is a surfactant and can provide the abrasive particles with appropriate fluidity.

[0120] The fluorine-based compound may have a static surface tension of about 50 dynes / cm or less, for example, about 45 dynes / cm or less, for example, about 10 dynes / cm to about 50 dynes / cm, for example, about 10 dynes / cm to about 45 dynes / cm, in a 0.001 wt% aqueous solution state. The fluorine-based compound may have a static surface tension of about 30 dynes / cm or less, for example, about 25 dynes / cm or less, for example, about 5 dynes / cm to about 30 dynes / cm, for example, about 5 dynes / cm to about 25 dynes / cm, in a 0.01 wt% aqueous solution state. By applying a fluorine-based compound having such a surface tension, it is possible to appropriately ensure the fluidity of the semiconductor processing composition, prevent defects such as scratches on the polished surface, and be more advantageous in realizing a polishing rate for each film quality that can satisfy the optimal range of the above formula 1, the above formula 2, the above formula 3, and / or the above formula 4. In addition, the fluorine-based compound may be advantageous in that the surface state of the silicon oxide film is maintained in a state suitable for polishing, and the fluorine component may be advantageous in that the composition for semiconductor processing may be prevented from growing bacteria and mold, thereby improving long-term storage stability.

[0121] In one embodiment, the composition for semiconductor processing contains, for example, about 0.01 to about 1.00 parts by weight, for example, about 0.01 to about 0.80 parts by weight, for example, about 0.01 to about 0.70 parts by weight, for example, about 0.01 to about 0.60 parts by weight, for example, about 0.01 to about 0.50 parts by weight, for example, about 0.01 to about 0.40 parts by weight, for example, about 0.01 to about 0.30 parts by weight, for example, about 0.01 about 0.02 to about 1.00 parts by weight, for example, about 0.03 to about 1.00 parts by weight, for example, about 0.04 to about 1.00 parts by weight, for example, about 0.05 to about 1.00 parts by weight, for example, about 0.02 to about 0.50 parts by weight, for example, about 0.03 to about 0.40 parts by weight, for example, about 0.04 to about 0.30 parts by weight, for example, about 0.05 to about 0.30 parts by weight, for example, about 0.05 to about 0.20 parts by weight.

[0122] The composition for semiconductor processing may include the abrasive particles, the at least one additive, and a solvent as the balance. The solvent may be, for example, water (H 2 O), and specifically, ultrapure water can be used.

[0123] The semiconductor processing composition may have a solid content of about 3.5% by weight to about 20% by weight, for example, about 3.5% by weight to about 15% by weight, for example, about 3.5% by weight to about 10% by weight. If the solid content is too low, the polishing rate for each film quality of the polishing target may not be sufficiently ensured, and if the solid content is too high, defects such as scratches may occur during the polishing process due to unnecessary aggregation. The semiconductor processing composition includes the abrasive particles, the at least one additive, and the solvent, and has a solid content within the above range, which may be more advantageous for injection at a uniform flow rate when applied to the polishing process, and may be more advantageous in terms of ensuring uniform dispersion and storage stability during distribution and storage of the semiconductor processing composition.

[0124] As described above, the composition for semiconductor processing satisfies the optimum range of the values ​​of the above formula 1, the above formula 2, the above formula 3, and / or the above formula 4, which are the constituent factors of the polishing rates for the silicon oxide film, the silicon nitride film, and the copper film, respectively, and therefore can exhibit excellent flatness without defects such as dishing, protrusion, erosion, and / or peaking on a polished surface including different film qualities at the same time, and more specifically, can realize a technical advantage of maximizing these effects on a semiconductor wafer including a through-silicon via (TSV) with a specific structure and pattern.

[0125] In another embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: preparing a platen on which a polishing pad having a polishing surface is mounted; preparing a carrier containing an object to be polished; rotating the platen and the carrier while rotating the platen and the carrier in a state in which the polishing surface of the polishing pad and the surface to be polished of the object to be polished are arranged to be in contact with each other; and supplying a composition for semiconductor processing onto the polishing surface, wherein the composition for semiconductor processing includes abrasive particles and at least one additive, and the value of the following formula 1 is about 1.45 to about 1.90.

[0126] [Formula 1] JPEG0007660607000013.jpg1017

[0127] In the above formula 1, the R O is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R N is the polishing rate (Å / min) of the semiconductor processing composition for the silicon nitride film, and R Cu is the polishing rate (Å / min) of the semiconductor processing composition for the copper film.

[0128] At this time, the R O , R N and R Cu is a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the semiconductor processing composition, and using this to polish wafers having each film for 60 seconds while supplying the semiconductor processing composition at a flow rate of 300 mL / min under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm.

[0129] In the method for manufacturing a semiconductor device, when a semiconductor wafer having a structure in which different film qualities must be polished simultaneously, such as a through silicon via (TSV), is subjected to polishing, the different film qualities can be polished to have substantially the same flatness by applying the composition for semiconductor processing, in which the value of the above formula 1 satisfies a predetermined range, and as a result, a semiconductor device of improved quality can be manufactured.

[0130] The matters relating to the semiconductor processing composition applied to the method for manufacturing a semiconductor device may be applied and interpreted in a unified manner not only when the matters described above regarding the semiconductor processing composition according to an embodiment are repeated below, but also when they are not repeated below.

[0131] In the composition for semiconductor processing applied to the method for manufacturing a semiconductor device, the values ​​of Formula 2, Formula 3, and / or Formula 4 may each satisfy the above-mentioned ranges.

[0132] 4 is a schematic diagram illustrating an apparatus configuration for the method of manufacturing a semiconductor device according to an embodiment. Referring to FIG. 4, the method of manufacturing a semiconductor device may include a step of preparing a platen 120 on which a polishing pad 110 having a polishing surface is mounted, and a step of preparing a carrier 160 containing a polishing target 130.

[0133] In the method for manufacturing a semiconductor device, the polishing target 130 may include a semiconductor wafer having a through silicon via (TSV). With reference to Figs. 1 to 3, the semiconductor wafer 100 having the TSV included in the polishing target 130 may include a substrate 50, a silicon nitride film 20 disposed on the substrate 50, and a silicon oxide film 40. The semiconductor wafer 100 also includes a through silicon via 10, which may include a via 11 penetrating the substrate 50 and a copper electrode 30 charged therein.

[0134] 2 and 3, in one embodiment, the silicon nitride film 20 has a structure in which a part or the whole of the silicon nitride film 20 surrounds the periphery of the copper electrode 30, and can function as a barrier film that prevents copper atoms from diffusing from the copper electrode to the substrate 50. A ratio (D2 / D1) of a diameter (D2) of the copper electrode 30 to a total diameter (D1) of the copper electrode 30 and the silicon nitride film 20 surrounding the copper electrode 30 may be, for example, about 0.5 to about 1.0, for example, about 0.7 to about 1.0, or may be, for example, about 0.5 or more and less than about 1.0, or may be, for example, about 0.7 or more and less than about 1.0. By using semiconductor wafers having these pattern structures as the polishing target, the characteristic of the composition for semiconductor processing in which the numerical ranges of the formula 1, the formula 2, the formula 3, and / or the formula 4 satisfy the above-mentioned ranges, respectively, may be more advantageous in terms of showing an excellent correlation with the effect of preventing excessive dishing or protrusion of the copper electrode 30.

[0135] In one embodiment, the ratio (2T1 / D1) of the thickness (T1) of the silicon nitride film 20 to the overall diameter (D1) of the copper electrode 30 and the silicon nitride film 20 surrounding it may be about 0.1 to about 0.5, for example, about 0.1 to about 0.3. By using semiconductor wafers having such pattern structures as the polishing target, the characteristic that the numerical ranges of the formula 1, the formula 2, the formula 3, and / or the formula 4 of the composition for semiconductor processing satisfy the above-mentioned ranges respectively may be more advantageous in terms of showing an excellent correlation with the effect of preventing peaking of the silicon nitride film 20.

[0136] The method for manufacturing a semiconductor device may include a step of preparing a platen 120 on which a polishing pad 110 having the polishing surface 111 is attached. In an embodiment, the polishing pad 110 includes a polishing layer, and the polishing layer may include the polishing surface 111. The polishing layer 110 may include, but is not limited to, a cured product of a composition including a urethane-based prepolymer. The urethane-based prepolymer may include, for example, a reaction product of an isocyanate compound and a polyol compound.

[0137] In one embodiment, the polishing surface 111 may have a Shore D surface hardness of about 45 to about 70 at 25° C., for example, about 50 to about 70, for example, about 55 to about 70, for example, about 45 to about 65, for example, about 45 to about 60, for example, about 50 to about 65, for example, about 55 to about 60. The Shore D surface hardness may be measured by a method widely used in the art, for example, by cutting the polishing pad into a sample of 2 cm×2 cm (thickness: 2 mm) and leaving it for 16 hours in an environment of 25° C. and 50±5% humidity, and then measuring the Shore D surface hardness using a hardness tester (D-type hardness tester). By applying a polishing pad having a polishing surface having such surface hardness to the method for manufacturing a semiconductor device, the technical advantages of the composition for semiconductor processing supplied on the polishing surface may be further maximized. Specifically, the semiconductor processing composition is supplied onto the polishing surface, and then flows to the interface between the polishing surface and the polished surface of the object to be polished, thereby polishing the polished surface. Since the polishing surface exhibits these surface hardnesses, the contact interface with the polished surface, mediated by the semiconductor processing composition, can exhibit appropriate elasticity, which can be more advantageous from the viewpoint of preventing defects on the polished surface.

[0138] The method for manufacturing a semiconductor device may include a step of rotating the platen 120 and the carrier 160 while the polishing surface 111 of the polishing pad 110 and the surface to be polished of the object to be polished 130 are arranged so as to be in contact with each other. The polishing pad 110 may be mounted on the platen 120 so that the polishing surface 111 is the uppermost surface, and the object to be polished 130 may be accommodated in the carrier 160 so that the surface to be polished is the lowermost surface, so that the polishing surface 111 and the surface to be polished are arranged so as to be in contact with each other. The polishing surface 111 and the surface to be polished being in contact with each other may be interpreted as including not only a case where they are in direct physical contact, but also a case where they are indirectly contacted through the abrasive particles in the composition for semiconductor processing.

[0139] As the platen 120 rotates, the polishing pad 110 also rotates at substantially the same trajectory and speed, and as the carrier 160 rotates, the polishing target 130 also rotates at substantially the same trajectory and speed. The platen 120 and the carrier 160 may rotate in the same direction or in opposite directions.

[0140] In one embodiment, the rotation speed of the platen 120 and the carrier 160 may be about 10 rpm to about 500 rpm, for example, about 30 rpm to about 200 rpm. When the platen 120 and the carrier 160 rotate at the rotation speed in the above range, the friction behavior of the polishing surface 111 and the surface to be polished due to the centrifugal force may be excellent in terms of ensuring the polishing flatness of the surface to be polished and preventing side effects such as protrusions and dishing, in cooperation with the composition for semiconductor processing 150 supplied onto the polishing surface 111. More specifically, the structure of the TSV may be more advantageous in terms of the polishing result for the surface to be polished including a copper film, a silicon oxide film, and a silicon nitride film at the same time.

[0141] In an embodiment, the rotation speed of the carrier 160 may be higher than the rotation speed of the platen 120. By rotating the carrier 160 at a high speed relative to the platen 120, it may be advantageous to ensure polishing stability and to polish the surface of the polishing object 130 without defects.

[0142] In one embodiment, the method for manufacturing a semiconductor device rotates the platen 120 and the carrier 160, but the rotation can be performed under a pressure condition against the polishing surface 111 of the carrier 160. By pressing the carrier 160 against the polishing surface 111 under a predetermined pressure condition, excellent polishing performance can be realized both when the surface to be polished of the object to be polished 130 is polished by directly contacting with the polishing surface 111 of the polishing pad 110 and when the surface is polished by indirectly contacting with the composition for semiconductor processing 150. For example, the load with which the carrier 160 is pressed against the polishing surface 111 may be about 0.01 psi to about 20 psi, for example, about 0.1 psi to about 15 psi.

[0143] The method for manufacturing a semiconductor device includes a step of supplying the semiconductor processing composition 150 onto the polishing surface 111. Specifically, the semiconductor processing composition 150 may be supplied onto the polishing surface 111 through a supply nozzle 140.

[0144] In an embodiment, the flow rate of the semiconductor process composition 150 supplied through the supply nozzle 140 may be about 10 mL / min to about 1,000 mL / min, for example, about 10 mL / min to about 800 mL / min, for example, about 50 mL / min to about 500 mL / min. When the semiconductor process composition 150 satisfying the formula 1, formula 2, formula 3, and / or formula 4 in a predetermined range is supplied onto the polishing surface at a flow rate within the above range, the friction behavior between the polishing surface 111 and the polished surface of the polishing object 130 through the medium of the composition 150 may be more advantageous for improving the polishing performance of the polishing surface. More specifically, the polishing result of the polishing surface including a copper film, a silicon oxide film, and a silicon nitride film simultaneously due to the structure of the TSV may be more advantageous in terms of ensuring polishing flatness and preventing side effects such as protrusions and dishing.

[0145] The composition for semiconductor processing may contain abrasive particles and at least one additive, and the matters related to the abrasive particles and the at least one additive are the same as those described for the composition for semiconductor processing. That is, all the specific examples of the abrasive particles and the at least one additive described above for the composition for semiconductor processing and their technical advantages can be integrated and applied to the composition for semiconductor processing applied to the semiconductor manufacturing method, and can form advantageous interactions from the viewpoint of achieving technical objectives with respect to other components of the semiconductor manufacturing method, such as the structure and drive of the platen and the carrier.

[0146] Referring to FIG. 4, the method for manufacturing a semiconductor device may further include a step of processing the polishing surface 111 of the polishing pad 110 through a conditioner 170. The polishing surface 111 of the polishing pad 110 is chemically affected as the composition for semiconductor processing 150 is continuously supplied, and is also physically affected by physical contact with the surface to be polished of the object to be polished 130. If the state of the polishing surface 111 is deformed by these chemical / physical effects, it may be difficult to uniformly maintain the polishing performance for the surface to be polished. The conditioner 170 is a means for processing the polishing surface 111 during the polishing process, and can contribute to the polishing surface 111 uniformly maintaining a state suitable for polishing throughout the entire polishing process.

[0147] For example, the conditioner 170 can rotate at a predetermined speed to roughen the polishing surface 111. The rotation speed of the conditioner 170 may be, for example, about 10 rpm to about 500 rpm, for example, about 50 rpm to about 500 rpm, for example, about 100 rpm to about 500 rpm, for example, about 200 rpm to about 500 rpm, for example, more than about 200 rpm and less than about 400 rpm.

[0148] The conditioner 170 can rotate while being pressed at a predetermined pressure against the polishing surface 111 of the polishing pad 110. For example, the pressure of the conditioner 170 against the polishing surface 111 may be about 1 psi to about 20 psi, for example, about 1 psi to about 15 psi, for example, about 5 psi to about 15 psi, for example, about 5 psi to about 10 psi.

[0149] By performing surface treatment using the conditioner 170 under the above-mentioned process conditions, the polishing surface 111 can maintain an optimal surface condition throughout the entire polishing process, and the polishing life can be extended under the application conditions of the semiconductor processing composition 150.

[0150] The method for manufacturing a semiconductor device can realize the technical advantage that different film qualities are simultaneously polished to excellent flatness in the polishing object, specifically, the semiconductor wafer having the through silicon via (TSV), due to the above-mentioned characteristics. In particular, by applying a composition for semiconductor processing that satisfies the above formula 1, the above formula 2, the above formula 3, and / or the above formula 4 within a predetermined range, the technical advantages can be maximized, and as a result, a semiconductor device of improved quality can be provided.

[0151] 1 and 2, a method for manufacturing a semiconductor device according to an embodiment may include the steps of: forming a substrate 50 including a via 11; forming a copper electrode 30 disposed in the via 11; forming a silicon nitride film 20 on the substrate 50 and the copper electrode 30; forming a silicon oxide film 40 on the silicon nitride film 20; and polishing the copper electrode 30, the silicon nitride film 20, and the silicon oxide film 40 using a semiconductor processing composition.

[0152] The substrate 50 is a semiconductor substrate, and may be a silicon wafer.

[0153] The via 11 penetrates at least a portion of the substrate 50. The via 11 may be a groove formed by a selective etching process of the substrate 50.

[0154] The copper electrode 30 is disposed in the via 11. The copper electrode 30 may be formed by a vacuum deposition process such as a sputtering process. A barrier layer including tantalum oxide or the like may be formed between the copper electrode 30 and the via 11.

[0155] The silicon nitride layer 20 may be formed by a chemical vapor deposition process, etc. The silicon nitride layer 20 may cover the substrate 50 and the copper electrode 30.

[0156] The silicon oxide layer 40 may be formed by a chemical vapor deposition process, etc. The silicon oxide layer 40 may cover the silicon nitride layer 20.

[0157] The polishing step can be carried out in the same manner as described above.

[0158] The composition for semiconductor processing may include abrasive particles and at least one additive. The composition for semiconductor processing may have the above-mentioned characteristics.

[0159] In addition, in the method for manufacturing a semiconductor device according to an embodiment, the value of the above formula 1 may have the same characteristics as described above.

[0160] In addition, in the method for manufacturing a semiconductor device according to an embodiment, the value of the above formula 2 may have the same characteristics as described above.

[0161] In addition, in the method for manufacturing a semiconductor device according to an embodiment, the value of the above formula 3 may have the same characteristics as described above.

[0162] In addition, in the method for manufacturing a semiconductor device according to an embodiment, the value of the above formula 4 may have the same characteristics as described above.

[0163] In this case, in the above formula 1, the above formula 2, the above formula 3, and the above formula 4, O is the polishing rate (Å / min) of the semiconductor process composition for the silicon oxide film 40, and R N is the polishing rate (Å / min) of the semiconductor process composition for the silicon nitride film 20, and R Cu may be the polishing rate (Å / min) of the semiconductor process composition for the copper electrode 30.

[0164] In the method for manufacturing a semiconductor device according to an embodiment, after polishing the copper electrode 30, the silicon nitride film 20, and the silicon oxide film 40, a height difference between a polished surface of the copper electrode 30 and a polished surface of the silicon nitride film 20 may be less than about 5 nm. That is, after the polishing step, a height difference between a protruding portion of the silicon nitride film 20 and the copper electrode 30 may be less than about 5 nm.

[0165] In the method for manufacturing a semiconductor device according to an embodiment, after the step of polishing the copper electrode 30, the silicon nitride film 20, and the silicon oxide film 40, a height difference between a polished surface of the copper electrode 30 and a polished surface of the silicon oxide film 40 may be less than about 20 nm. That is, a height difference between an upper surface of the copper electrode 30 and an upper surface of the silicon oxide film 40 may be less than about 20 nm.

[0166] The method for manufacturing a semiconductor device according to the embodiment can manufacture a semiconductor wafer 100 having improved flatness by using the above-described composition for semiconductor processing and the above-described polishing process.

[0167] Hereinafter, specific examples of the present invention will be presented. However, the examples described below are merely intended to specifically illustrate or explain the present invention, and should not be construed as limiting the scope of the present invention, which is determined by the claims.

[0168] <Examples and Comparative Examples> Colloidal silica (Nouryon, EXSKC-01) was used as the abrasive particles, and the surface of the silica particles was modified with a silane composition having an aminosilane to epoxysilane weight ratio of 9: 1. In this case, the surface modification rate was defined as 100% when 0.01 part by weight of the silane composition was used for 100 parts by weight of the abrasive particles, and the surface modification rates for the abrasive particles of each Example and Comparative Example were modified as shown in Tables 1 to 3 below. The abrasive particles were mixed with 5-aminotetrazole (Merck Korea, EL grade), betaine salicylate (BOH, Bien Ochem), potassium pyrophosphate (SIC-801, Seoul IC), acetic acid, and a fluorine-based compound (Capstone FS-3100, Dupont) in amounts shown in Tables 1 to 3 below per 100 parts by weight of the silica particles. Ultrapure water solvent was added to the mixture to give a solid content of 15% by weight, to prepare a composition for semiconductor processing.

[0169] <Evaluation> Experimental example 1: Measurement of hydrogen ion concentration (pH) The pH of each of the semiconductor process compositions of the above Examples and Comparative Examples was measured using a hydrogen ion concentration (pH) measuring device (Horiba, Laqua) while stirring at 200 rpm under room temperature conditions of 20° C. to 25° C. The results are shown in Tables 1 to 3 below.

[0170] Experimental Example 2: Measurement of polishing rate and derivation of values ​​of formulas 1 to 4 A copper wafer having a thickness of about 20,000 Å, a silicon nitride wafer having a thickness of about 12,000 Å, and a silicon oxide wafer having a thickness of about 20,000 Å were prepared. As shown in FIG 4, each wafer was placed in a carrier 160 as the polishing object 130 with the surface to be polished facing downward. The carrier 160 was placed on the platen 120 on which the polishing pad 110 (SKC, HD-319B) was attached so that the polishing surface 111 was facing upward, and the carrier 160 was placed so that the polished surface and the polishing surface 111 were in contact with each other. Then, for 60 seconds, the carrier 160 was operated at a pressure of 3.0 psi on the polishing surface, a rotation speed of 120 rpm for the carrier 160, and a rotation speed of 117 rpm for the platen 120. The polishing surface was polished by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of each of the semiconductor process compositions of the above examples and the above comparative examples, and applying the mixture at a flow rate of 300 ml / min. At the same time, the conditioner 170 (Sesol Diamond, SKC-CI45) was driven at a rotation speed of 250 rpm and a pressure of 8 psi. The polishing surface was processed by driving the conditioner 170. The thickness of each wafer after polishing was measured to calculate the polishing rate (Å / min). Using the polishing rate values ​​measured for each film quality, the values ​​of the above formulas 1 to 4 were calculated and derived, and are shown in the following Tables 1 to 3.

[0171] Experimental Example 3: Polishing performance evaluation 3, a wafer having an overall diameter of 300 mm was prepared, which had a pattern including a through-silicon via (TSV) having a copper electrode 30 with a planar reference diameter (D2) of 5 μm and a second silicon nitride film 22 with a planar reference thickness (T1) of 0.5 μm, which was positioned outside the copper electrode 30 so as to surround it. As shown in FIG 4, each wafer was placed in a carrier 160 as the polishing target 130 with the polished surface facing downward. The carrier 160 was positioned so that the polished surface 111 of the polishing pad 110 (SKC, HD-319B) was in contact with the polished surface 111 of the platen 120, and the carrier 160 was operated for 60 seconds at a pressure of 3.0 psi on the polishing surface of the carrier 160, a rotation speed of 120 rpm of the carrier 160, and a rotation speed of 117 rpm of the platen 120. The polishing surface was polished by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of each of the semiconductor process compositions of the examples and the comparative examples, and applying the mixture at a flow rate of 300 ml / min. After the polishing was completed, a cleaning process was performed by spraying a cleaning solution at a brush rotation speed of 500 rpm for 60 seconds at a spray rate of 2,000 cc / min. Next, the polished surface of the patterned wafer was divided into three equal parts from the center to the edge, and each area was sampled to a size of 1 cm x 1 cm (horizontal x vertical). Each area was subjected to non-contact AFM analysis using an AFM analysis device (Park System, NX-20). The specific analysis area was 80 μm x 80 μm (horizontal x vertical), and the tip profiling scan speed was 8 μm / s.

[0172] When the compositions for semiconductor processing of the above Examples and Comparative Examples were applied, the degree of dishing of the copper electrode 30 was measured as shown in Fig. 5(a), and the direction in which dishing occurred based on the plane was given a (+) value, which is shown in the following Tables 1 to 3. That is, the (-) values ​​in the following Tables 1 to 3 indicate the degree of protrusion of the copper electrode 30 as shown in Fig. 5(b).

[0173] In addition, for each of the semiconductor process compositions of the above examples and comparative examples, the occurrence of SiN peaking was evaluated as O or X based on the criteria that SiN peaking occurs when the height of the second silicon nitride film 22 exceeds 5 nm with the top surface of the silicon oxide film 40 as the reference plane. The results are shown in Tables 1 to 3 below.

[0174] In addition, when each of the semiconductor process compositions of the above examples and comparative examples was applied, erosion was evaluated as occurring (O) or not (X) based on the criteria that erosion is evaluated as occurring when the copper film, silicon nitride film, and silicon nitride film constituting the through-silicon via (TSV) and its surrounding area are generally over-polished to a depth of more than 10 nm, as shown in FIG. 5(d), with the top surface of silicon oxide film 40 as the reference surface, compared to the surrounding silicon oxide film constituting most of the area of ​​the semiconductor wafer. The results are shown in Tables 1 to 3 below.

[0175] [Table 1]

[0176] [Table 2]

[0177] [Table 3]

[0178] Referring to the results of Tables 1 to 3, the compositions for semiconductor processing of Examples 1 to 4 have values ​​of Formula 1 in the range of about 1.45 to about 1.90, for example, about 1.50 to about 1.70, and thus do not suffer from defects such as peaking and erosion, and at the same time, the degree of copper film dishing reaches less than 15 nm, thereby realizing an optimized polishing performance in polishing semiconductor wafers including through-silicon vias (TSVs). On the other hand, the compositions for semiconductor processing of Comparative Examples 1 to 7 have values ​​of Formula 1 less than about 1.45 or more than about 1.90, and thus, unlike the compositions for semiconductor processing of Examples 1 to 4 which effectively prevent all of the defects of peaking, erosion, and dishing at the same time, at least one of these defects occurs, thereby failing to realize the technical effect of the present invention. [Explanation of symbols]

[0179] 100 Semiconductor Wafers 10 Through silicon via 11 Via 20 Silicon nitride film 30 copper electrode 40 Silicon oxide film 50 Substrates 110 Polishing pad 111 Polished surface 120 Fixed Plate 130 Polishing target 140 Nozzle 150 Compositions for semiconductor processing 160 Careers 170 Conditioner D1 Overall diameter of copper electrode and silicon nitride film D2 Diameter of copper electrode T1 Silicon nitride film thickness

Claims

1. Abrasive particles; At least one additive; The value of the following formula 1 is 1.45 to 1.90, The value of the following formula 2 is 110.0 to 230.0, Semiconductor processing compositions: [Formula 1] [Formula 2] In the above formulas 1 and 2, the R Ｏ is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R Ｎ is the polishing rate (Å / min) of the semiconductor processing composition for a silicon nitride film, and R Ｃｕ is the polishing rate (Å / min) of the semiconductor process composition for the copper film, The R Ｏ , R Ｎ and R Ｃｕ is a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the composition for semiconductor processing, and then using the mixture to polish wafers having each film under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm, while feeding the composition for semiconductor processing at a flow rate of 300 mL / min for 60 seconds.

2. The value of the following formula 3 is 0.90 to 1.

00. The composition for semiconductor processing according to claim 1: [Formula 3] In the above formula 3, The R Ｏ and R Ｃｕ is as defined in formula 1 above.

3. The value of the following formula 4 is 1.55 to 2.

40. The composition for semiconductor processing according to claim 1: [Formula 4] In the above formula 4, The R Ｎ and R Ｃｕ is as defined in formula 1 above.

4. The abrasive particles have a positive (+) zeta potential in the semiconductor process composition. The composition for semiconductor processing according to claim 1 .

5. The additive includes one selected from the group consisting of an azole-based compound, a phosphoric acid-based compound, a fluorine-based compound, an organic acid, and a combination thereof; The composition for semiconductor processing according to claim 1 .

6. preparing a platen on which a polishing pad having a polishing surface is mounted; Providing a carrier containing an object to be polished; Rotating the platen and the carrier while the polishing surface of the polishing pad and the surface to be polished of the object to be polished are in contact with each other; and providing a semiconductor processing composition on the polishing surface; The composition for semiconductor processing includes abrasive particles and at least one additive, and has a value of the following formula 1 of 1.45 to 1.90: The value of the following formula 2 is 110.0 to 230.0, Manufacturing method of semiconductor device: [Formula 1] [Formula 2] In the above formulas 1 and 2, the R Ｏ is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R Ｎ is the polishing rate (Å / min) of the semiconductor processing composition for a silicon nitride film, and R Ｃｕ is the polishing rate (Å / min) of the semiconductor process composition for the copper film, The R Ｏ , R Ｎ and R Ｃｕ is a value calculated by mixing 0.25 parts by weight of hydrogen peroxide with 100 parts by weight of the composition for semiconductor processing, and then using the mixture to polish wafers having each film under conditions of a carrier pressure of 3.0 psi, a carrier rotation speed of 120 rpm, and a platen rotation speed of 117 rpm, while feeding the composition for semiconductor processing at a flow rate of 300 mL / min for 60 seconds.

7. The object to be polished includes a semiconductor wafer having a silicon through electrode; The method for manufacturing a semiconductor device according to claim 6 .

8. forming a substrate including a via; forming a copper electrode disposed in the via; forming a silicon nitride film on the substrate and the copper electrode; forming a silicon oxide film on the silicon nitride film; and polishing the copper electrode, the silicon nitride film, and the silicon oxide film using a semiconductor processing composition; The semiconductor processing composition includes abrasive particles and at least one additive, and has a value of the following formula 1 of 1.45 to 1.90: Manufacturing method of semiconductor device: [Formula 1] In the above formula 1, the R Ｏ is the polishing rate (Å / min) of the semiconductor process composition for a silicon oxide film, and R Ｎ is the polishing rate (Å / min) of the semiconductor processing composition for a silicon nitride film, and R Ｃｕ is the polishing rate (Å / min) of the semiconductor processing composition for the copper film.

9. After the step of polishing the copper electrode, the silicon nitride film, and the silicon oxide film, a height difference between the polished surface of the copper electrode and the polished surface of the silicon nitride film is less than about 5 nm; After the step of polishing the copper electrode, the silicon nitride film, and the silicon oxide film, a height difference between the polished surface of the copper electrode and the polished surface of the silicon oxide film is less than about 20 nm. The method for manufacturing a semiconductor device according to claim 8 .

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