Semiconductor Device

Abstract

To provide a semiconductor device capable of initializing memory cell data at a relatively high speed while suppressing an increase in area.SOLUTION: A control circuit of a semiconductor device initializes a plurality of memory cells, based on that a reset signal is made to a high level, by bringing a first transistor into an off state, a plurality of word lines into selected states, a precharge circuit into off states, a column switch for writing into an on state, and the column switch for reading into an off state, and by bringing, by a write circuit, a first-bit line into a low level, and a second-bit line into a high level.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including a static random access memory (SRAM). [Background technology]

[0002] Many semiconductor devices, such as data processing devices, have a built-in static random access memory (SRAM) as a memory device for holding data. When storing important data in this SRAM, tamper-proof measures are required. To prevent malicious users from reading the contents of the important data stored in the SRAM, a technology is required to instantly erase or initialize the important data stored in the SRAM all at once.

[0003] Techniques for initializing data stored in memory cells are disclosed in Patent Documents 1 to 3 and Non-Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2010 / 0046173 [Patent Document 2] US Patent Application Publication No. 2006 / 0023521 [Patent Document 3] US Patent Application Publication No. 2014 / 0293679 [Non-patent literature]

[0005] [Non-Patent Document 1] Kevin Self, APPLICATION NOTE 2033, SRAM-Based Microcontroller Optimizes Security, [online], Jun 27, 2003, [Retrieved November 25, 2020], Internet<URL:https: / / pdfserv.maximintegrated.com / en / an / AN2033.pdf> Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 discloses a circuit configuration in which the word line rise timing is changed in a domino fashion by adding a delay circuit, and memory cells are initialized one word line at a time from the lower to the upper word line. With this configuration, if there are many memory cells connected to one bit line, it takes a long time to fully initialize the memory cell data. In addition, a delay circuit is required to shift the word line rise timing, which increases the area of ​​the word line decoder section (also called row decoder section).

[0007] Patent Document 2 discloses a configuration in which a dedicated bit line control circuit for initialization is provided for the bit line. In this configuration, the bit line control circuit is added to the normal read and write control circuit of the SRAM, so the area of ​​the SRAM macro becomes large.

[0008] Patent Document 3 discloses a configuration in which the lines (319, 321) connected to the NFETs (3N8, 3N9) of the memory cells are separated for left and right memory cell nodes for voltage control, making it easy to initialize memory cell data. In this configuration, the wiring layout of the lines 319, 321 connected to the memory cells needs to be separated into a True node and a Bar node, which increases the memory cell area.

[0009] Non-Patent Document 1 discloses that "When the self-destruct input is turned on, the power supply to the SRAM is cut off, and the program memory and data memory are also all erased." However, at low temperatures, it is difficult to erase data from the SRAM. In other words, this is because all the transistors that make up the memory cell are turned off, and the charge in the data retention node of the memory cell cannot be discharged.

[0010] An object of the present disclosure is to provide a technique capable of initializing data in memory cells relatively quickly while suppressing an increase in area.

[0011] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0012] A brief summary of representative aspects of this disclosure is as follows.

[0013] A semiconductor device according to an embodiment includes a plurality of word lines, a plurality of pairs of first and second bit lines, a plurality of memory cells connected to the plurality of word lines and the plurality of pairs of first and second bit lines so as to be connected to one word line and a pair of the first and second bit lines, a first transistor provided between the plurality of memory cells and a power supply potential, a plurality of word line drivers connected to the plurality of word lines, a write column switch connected to each of the plurality of pairs of the first and second bit lines, a read column switch connected to each of the plurality of pairs of the first and second bit lines, a precharge circuit connected to each of the plurality of pairs of the first and second bit lines, a write circuit connected to each write column switch, and a control circuit receiving a reset signal. When the reset signal is set to a high level, the control circuit sets the first transistor to an off state, the plurality of word lines to a selected state, the precharge circuit to an off state, the write column switch to an on state, and the read column switch to an off state, and initializes the plurality of memory cells by setting the first bit line to a low level and the second bit line to a high level using the write circuit. Effect of the Invention

[0014] According to the semiconductor device according to the above embodiment, data in memory cells can be initialized relatively quickly while suppressing an increase in area. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram illustrating the overall configuration of a memory device according to the first embodiment. [Diagram 2] FIG. 2 is a diagram illustrating a memory cell portion of the memory device of FIG. [Diagram 3] FIG. 3 is a diagram illustrating an input / output section of the memory device of FIG. [Figure 4] FIG. 4 is a diagram for explaining a word driver section of the memory device of FIG. [Diagram 5] FIG. 5 is a diagram illustrating a control unit of the memory device of FIG. [Figure 6] FIG. 6 is a timing chart when the reset signal is turned on during normal operation. [Figure 7] FIG. 7 is a timing chart when the reset signal is turned on in the standby state. [Figure 8] FIG. 8 is a diagram for explaining the timing according to the first embodiment. [Figure 9] FIG. 9 is a diagram for explaining the timing according to the second embodiment. [Figure 10] FIG. 10 is a diagram for explaining the timing when a reset request occurs during a read / write operation in the first embodiment. [Figure 11] FIG. 11 is a diagram for explaining the timing when a reset request occurs during a read / write operation in the second embodiment. [Figure 12] FIG. 12 is a diagram illustrating the overall configuration of a memory device according to the second embodiment. [Figure 13] FIG. 13 is a diagram for explaining a memory cell portion of the memory device of FIG. [Figure 14] FIG. 14 is a diagram illustrating the control unit of the memory device of FIG. [Figure 15] FIG. 15 is a diagram for explaining the reset control circuit of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, the embodiments will be described with reference to the drawings. However, in the following description, the same components are given the same reference numerals and the repeated description may be omitted. Note that the drawings may be shown more diagrammatically than the actual embodiment in order to clarify the description, but they are merely examples and do not limit the interpretation of the present invention.

[0017] (Embodiment 1) Hereinafter, the present disclosure will be described with reference to the drawings. FIG. 1 is a diagram for explaining the overall configuration of a memory device according to a first embodiment. FIG. 2 is a diagram for explaining a memory cell unit of the memory device of FIG. 1. FIG. 3 is a diagram for explaining an input / output unit of the memory device of FIG. 1. FIG. 4 is a diagram for explaining a word driver unit of the memory device of FIG. 1. FIG. 5 is a diagram for explaining a control unit of the memory device of FIG. 1. FIG. 6 is a timing chart when a reset signal is turned on in a normal operating state. FIG. 7 is a timing chart when a reset signal is turned on in a standby state.

[0018] 1 shows the overall configuration of a static random access memory (hereinafter referred to as SRAM) 1, which is a memory device. SRAM 1 is a memory device for holding data that is built into a semiconductor device such as a data processing device. A central processing unit CPU, SRAM 1, other peripheral devices, etc. are built into a semiconductor chip on which the data processing device is formed.

[0019] The SRAM1 includes a memory cell array unit AR, a word line decoder unit (also called a row decoder unit) RDE, an input / output unit IO, a control unit (also called a control circuit) CONT, a bit line decoder unit (also called a column decoder) CDE, and the like.

[0020] (Memory array section AR) The memory array section AR includes a plurality of memory cells MC arranged in a matrix, a plurality of word lines, and a plurality of pairs of first bit lines BT and second bit lines BB. Each memory cell is connected to a pair of the first bit line BT and the second bit line BB, and one word line WL (denoted as WL0 in FIG. 1). Each memory cell includes two transfer transistors N3 and N4 each composed of an N-channel MOS field effect transistor, two load transistors P1 and P2 each composed of a P-channel MOS field effect transistor, and two drive transistors N1 and N2 each composed of an N-channel MOS field effect transistor. The source-drain path of the load transistor P1 and the source-drain path of the drive transistor N1 are connected in series between the memory array power supply potential ARVDD and the ground potential VSS. The source-drain path of the load transistor P2 and the source-drain path of the drive transistor N2 are connected in series between the memory cell power supply potential ARVDD and the ground potential VSS.

[0021] The gate of the load transistor P1 and the gate of the drive transistor N1 are connected to form a common gate, the drain of the load transistor P2 and the drain of the drive transistor N2 are connected to form a common drain, and the common gate of the load transistor P1 and the drive transistor N1 is connected to the common drain of the load transistor P2 and the drive transistor N2. Similarly, the gate of the load transistor P2 and the gate of the drive transistor N2 are connected to form a common gate, the drain of the load transistor P1 and the drain of the drive transistor N1 are connected to form a common drain, and the common gate of the load transistor P2 and the drive transistor N2 is connected to the common drain of the load transistor P1 and the drive transistor N1.

[0022] The source-drain path of the transfer transistor N3 is connected between the first bit line BT and the common drain of the load transistor P1 and the drive transistor N1. The gate of the transfer transistor N3 is connected to the word line WL0. The source-drain path of the transfer transistor N4 is connected between the second bit line BB and the common drain of the load transistor P2 and the drive transistor N2. The gate of the transfer transistor N4 is connected to the word line WL.

[0023] When the first bit line BT is set to write data of high level "1", the second bit line BB is set to write data of low level "0", and the word line WL is set to a selection level such as a high level, the transfer transistors N3 and N4 are turned on, and high level "1" data is stored in the memory cell MC. On the other hand, when the first bit line BT is set to write data of low level "0", the second bit line BB is set to write data of high level "1", and the word line WL is set to a selection level such as a high level, the transfer transistors N3 and N4 are turned on, and low level "0" data is stored in the memory cell MC. In this specification, the state in which the memory cell MC stores low level "0" data is referred to as a low level data write state or an initialization state of the memory cell MC. Of course, the state in which the memory cell MC stores high level "1" data may be defined as an initialization state of the memory cell MC.

[0024] As shown in FIG. 1 and FIG. 2, the source-drain path of a transistor (first transistor) T1 composed of a P-channel MOS field effect transistor is connected between the power supply potential VDD and the memory array power supply potential ARVDD, and the control signal RSTE, which is set to high level "H" at the time of reset, is supplied to the gate of the transistor T1 from the control unit CONT. As shown in FIG. 2, in a plurality of memory cells MC constituting one column connected between the first bit line BT and the second bit line BB, the sources of the load transistors P1 and P2 of each memory cell MC are connected to the power supply potential VDD via the source-drain path of the transistor T1. Other columns (not shown) are configured in the same way. As a result, the transistor T1 is turned off at the time of reset, and the memory retention ability of all the memory cells MC in the memory array AR is disabled, so that the stored data of each memory cell MC can be easily initialized. In addition, it is possible to collectively initialize all the memory cells MC in the memory array AR at once.

[0025] (Word Line Decoder RDE) The word line decoder RDE includes a row decoder circuit (not shown) that decodes an address signal and selects one word line, and a plurality of word line drivers WDR connected to receive the output of the row decoder circuit. The plurality of word line drivers WDR are respectively connected to the plurality of word lines WL0-WLn and drive the selected word line. As shown in FIG. 1 and FIG. 4, a source-drain path of a transistor (second transistor) T2 made of a P-channel MOS field effect transistor is connected between the VDD side terminal of the final driver of the plurality of word line drivers WDR and the power supply potential VDD, and a control signal LCM2 that is set to a low level "L" at the time of reset is supplied to the gate of the transistor T2 from the control unit CONT. The plurality of word line drivers WDR are configured to select all the word lines WL0-WLn at the time of reset. The transistor T2 is a current limiting PMOS transistor that is provided to reduce rush current generated when all the word lines WL0-WLn are simultaneously raised to the selected state and has the role of limiting the amount of rush current.

[0026] As shown in FIG. 4, the word line driver WDR includes a final driver FDR composed of a P-channel MOS field effect transistor T3 and an N-channel MOS field effect transistor T4, and an N-channel MOS field effect transistor T5 having a source-drain path connected between the source of the N-channel MOS field effect transistor T4 and a ground potential VSS. The input of the final driver FDR is connected to receive an output from a row decoder circuit. The word line driver WDR further includes a P-channel MOS field effect transistor T6 having a source-drain path connected between a word line WLn connected to the output of the final driver FDR and the source of the transistor T2, and an N-channel MOS field effect transistor T7 having a source-drain path connected between the word line WLn and a ground potential VSS. The gates of the transistors T5 and T6 are connected to a wiring to receive a control signal RSTWD, and the gate of the transistor T7 is connected to a wiring to receive a control signal LCMWD. The control signal RSTWD is converted to a control signal RSTWDBACK by an inverter IV1 and returned to the control unit CONT. To start precharging the bit lines BT and BB after the word line falls, the control signal RSTWD is inverted by an inverter IV1 to generate a control signal RSTWDBACK, which is returned to the control unit CONT. The control unit CONT takes the logic of the control signal RSTWDBACK and the control signal RESTE. In other words, when reset is released (when the reset signal transitions from high level to low level), the signal of the far end of the word line lowering signal is fed back to the control unit CONT, and the precharging of the bit lines BT and BB is started after all word line falls are completed. This prevents excess through power due to overlap between the high level active period of the word line WL and the precharge period of the bit lines BT and BB, and reduces the operating current during the reset operation.

[0027] (I / O section IO) As shown in FIG. 1, the input / output unit IO has a precharge circuit including an equalizing transistor EQ composed of a P-channel MOS field effect transistor whose source-drain path is connected between bit lines BT and BB, a precharge transistor PC1 composed of a P-channel MOS field effect transistor whose source-drain path is connected to a power supply potential VDD and the bit line BT, and a precharge transistor PC2 composed of a P-channel MOS field effect transistor whose source-drain path is connected to a power supply potential VDD and the bit line BB. The gates of the transistors EQ, PC1, and PC2 are commonly connected and configured to receive a control signal CWSE. The transistors EQ, PC1, and PC2 are turned off by a control signal CWSE of high level "H" and turned on by a control signal CWSE of low level "L". At the time of reset, the transistors EQ, PC1, and PC2 are turned off by a control signal CWSE of high level "H". The control signal CWSE can also be called a column write select signal.

[0028] The input / output unit IO also includes a first write circuit (also called a write buffer) WBT for supplying write data to the bit line BT, and a second write circuit (also called a write buffer) WBB for supplying write data to the bit line BB. At the time of reset, the write circuit WBT supplies write data of low level "L" to the bit line BT, and the write circuit WBB supplies write data of high level "H" to the bit line BB. Therefore, at the time of reset, all bit lines BT of all columns are set to a potential level of low level "L", and all bit lines BB of all columns are set to a potential level of high level "H".

[0029] The input / output unit IO also has first and second column switches CTW and CBW for writing. The column switch CTW has a source-drain path connected between the output of the write circuit WBT and the bit line BT. The column switch CBW has a source-drain path connected between the output of the write circuit WBB and the bit line BT. A control signal CWSE is supplied to the gates of the column switches CTW and CBW. The input / output unit IO also has first and second column switches CTR and CBR for reading (see FIG. 3). The column switch CTR has a source-drain path connected between the bit line BT and the input of the sense amplifier SA. The column switch CBR has a source-drain path connected between the bit line BT and the input of the sense amplifier SA. At the time of reset, the write column switches CTW and CBW of all columns are configured to be in an on state, and the read column switches CTR and CBR of all columns are configured to be in an off state.

[0030] That is, at the time of reset, the transistor T1 is turned off, all the word lines WL are selected, and the transfer transistors N3 and N4 of all the memory cells MC are turned on. Then, the write column switches CTW and CBW of all the columns are turned on, the write circuit WBT supplies low level "L" write data to the bit line BT, and the write circuit WBB supplies high level "H" write data to the bit line BB. This allows the stored data of all the memory cells to be initialized at high speed.

[0031] FIG. 3 shows a detailed circuit configuration of the input / output unit IO. The input / output unit IO includes a column selector and precharge unit CPP and a write buffer and sense amplifier unit WSP. As described in FIG. 1, the column selector and precharge unit CPP includes transistors EQ, PC1, and PC2 as a precharge circuit, column switches CTW and CBW for writing, and column switches CTR and CBR for reading. A control signal CRSE is supplied to the gates of the column switches CTR and CBR for reading. The control signal CRSE can also be called a column read select signal. At the time of reset, the control signals CRSE of all columns are configured to be at high level "H".

[0032] The column selector and precharge unit CPP is configured to receive a selection signal Y from the bit line decoder unit CDE during normal write and normal read. In normal write mode and based on the selection signal Y at the selection level "H", the control signal CWSE is set to high level "H" and the control signal CRSE is set to high level "H". In normal read mode and based on the selection signal Y at the selection level "H", the control signal CRSE is set to low level "L" and the control signal CWSE is set to low level "L".

[0033] The write buffer and sense amplifier section WSP has a data input circuit DIN to which input data Din to be written to a selected memory cell during normal write is supplied, and a sense amplifier SA to detect data stored in a selected memory cell during normal read and output it as read data Dout. During normal write, the data input circuit DIN generates write data DT to the bit line BT and write data DB to the bit line BB based on the input data Din. The data DT, BT are supplied to the bit lines BT, BB via the write column switches CTW, CBW that are turned on. DTB, DBB denote inverted signals of the data DT, BT.

[0034] As shown in FIG. 3, the write buffer and sense amplifier unit WSP receives control signals RSTE, LCMN, and WTE from the control unit CONT. The control signal RSTE is a signal that is set to high level "H" at the time of reset. The control signal WTE is a signal that is set to high level "H" at the time of normal write. The control signal RSTEB indicates an inverted signal of the control signal RSTE. The control signal WTEB indicates an inverted signal of the control signal WTE. The control signal TIEH is a dummy signal for maintaining symmetry with the control signal RSTEB in a combination circuit of a NAND circuit and an OR circuit provided on the output side of the data input circuit DIN. At the time of reset, when the control signal RSTE is set to high level "H" (the control signal RSTEB is set to low level "L"), the inverted data signal DTB is set to high level "H" and the inverted data signal DBB is set to low level "L". As a result, at the time of reset, the bit line BT is set to low level "L" and the bit line BB is set to high level "H", so that the memory cell MC can be initialized.

[0035] (Control unit CONT) 1, at the time of reset, the control unit CONT controls so as to fall the internal one-shot clock, turn off the write operation and the read operation, and turn off the column selection. Also, when leaving the reset state (at the time of reset release or reset mode release), the control unit CONT controls so as to wait for the word line WL to rise before starting precharging of the bit lines BT and BB.

[0036] 5 shows a detailed circuit configuration of the control unit CONT. The control unit CONT is configured to receive a standby signal RS, a reset signal RESET, and a clock signal CLK. When the standby signal RS is set to a high level "H", the SRAM1 is placed in a standby state. When the standby signal RS is set to a low level "L", the SRAM1 is placed in a normal operation mode. The normal operation mode includes a read mode and a write mode.

[0037] When the reset signal RESET is set to high level "H", the SRAM 1 is reset. When the SRAM 1 is reset, all the memory cells MC in the SRAM 1 are set to an initialized state.

[0038] The control unit CONT is composed of a plurality of logic circuits shown in FIG. 5. The control unit CONT generates control signals LCM2, LCMWD, and RSTWD from the standby signal RS and the reset signal RESET, and supplies them to the word line driver WDR. The control unit CONT also receives a control signal RSTWDBACK from the word line driver WDR. The control unit CONT generates a control signal RSTE based on the reset signal RESET and the control signal RSTWDBACK. The control signal RSTE is used as a control signal for applying a potential setting for memory cell data initialization to the bit lines BT and BB, and as a control signal for cutting off the VDD side power supply of the memory cell (turning off the transistor T1). The control signal RSTWDBACK is a return signal of a falling signal at the far end of the word line for starting re-precharging of the bit line after the word line falls when reset is released. The control unit CONT also incorporates an internal clock generation circuit CLKGEN for writing and reading, which receives a clock signal CLK and generates a control signal TDEC such as an internal one-shot clock. The internal clock generating circuit CLKGEN is configured to receive a control signal RSTE and to stop generating an internal clock (internal one-shot clock) for write and read operations at the time of reset. The internal clock generating circuit CLKGEN may be referred to as an internal clock generating circuit.

[0039] (Timing chart) Fig. 6 is a timing chart showing a case where the reset signal RESET is changed from low level "L" to high level "H" in a normal operating state where the standby signal RS is at low level "L" and SRAM1 is in a reset state. Fig. 7 is a timing chart showing a case where the reset signal RESET is changed from low level "L" to high level "H" in a standby state where the standby signal RS is at high level "H" and SRAM1 is in a reset state. The waveforms of the clock signal CLK and the control signals LCM2 and LCMWD are different between Fig. 6 and Fig. 7.

[0040] 6 and 7, the control signal RSTE transitions to high level "H" based on the reset signal RESET going to high level "H". Based on the transition of the control signal RSTE to high level "H", transistor T1 is turned off, all word lines are set to selection level "H", all bit lines BT are set to low level, and all bit lines BB are set to high level. As a result, the storage node MEMT of the memory cell MC is set to low level, the storage node MEMB of the memory cell MC is set to high level, and all memory cells MC are set to an initialized state. The storage node MEMT is a common drain node of transistors P1 and N1 of the memory cell MC. The storage node MEMB is a common drain node of transistors P2 and N2 of the memory cell MC.

[0041] 6 and 7, when the reset signal RESET is changed from high level "H" to low level "L", the transistor T1 is turned on, all the word lines are set to the non-selected level "L", and all the bit lines BT and BB are set to a precharge level such as a high level. Note that the memory cell MC maintains the initialized state.

[0042] According to the first embodiment, one or more of the following effects can be obtained.

[0043] 1) The VDD side of the memory cell array AR is connected to VDD via switch T1. During reset, the circuit is configured so that switch T1 is turned off. Turning switch T1 off disables the memory retention capability of all memory cells, allowing them to be initialized all at once. This shortens the initialization time for all memory cells without increasing the area.

[0044] 2) The circuit is designed to select (start) all word lines simultaneously during reset. By starting the word lines simultaneously, memory cells can be initialized in one go, shortening the initialization time for all memory cells.

[0045] 3) At the time of reset, the normal data write circuits (WBT, WBB) in the SRAM are used to apply low and high levels for initialization to all bit lines BT and BB.Since the normal data write circuits (WBT, WBB) for memory cells are used, there is no increase in area.

[0046] 4) The circuit is configured so that the one-shot clock of the internal clock generation circuit CLKGEN for write / read is turned off by the reset signal. Because the internal clock generation circuit CLKGEN is turned off, no matter when the reset signal RESET transitions to high level, it is possible to immediately move to the initialization operation of all memory cells, so all memory cells can be initialized in a short time regardless of the SRAM operation mode.

[0047] 5) The source of the PMOS (T3) of the word line rise inverter (final driver FDR) is connected to the power supply potential VDD via a current limiting MOS (T2). The current limiting PMOS (T2) limits and suppresses rush current caused by all word lines rising at the same time, reducing the peak current of the word line driver WDR during reset.

[0048] 6) When the reset mode is released, the circuit is configured to generate timing such that the word line is first pulled down and then precharging of the bit lines BT and BB begins with transistors EQ, PC1, and PC2. This prevents excess through current caused by the overlap between the high-level active period of the word line WL and the precharging period of the bit lines BT and BB, thereby reducing the operating current during the reset operation.

[0049] (Embodiment 2) Next, the drawings will be described with respect to embodiment 2. For ease of understanding, first, the matters considered by the present inventors will be described with reference to Figs. 8 to 11.

[0050] Fig. 8 is a diagram for explaining the timing in the first embodiment. Fig. 9 is a diagram for explaining the timing in the second embodiment. Fig. 10 is a diagram for explaining the timing when a reset request occurs during a read / write operation in the first embodiment. Fig. 11 is a diagram for explaining the timing when a reset request occurs during a read / write operation in the second embodiment. The reset may be rephrased as a reset mode.

[0051] In the first embodiment shown in FIG. 8, when the reset is released (the reset signal RESET transitions from high level "H" to low level "L"), the supply of the power supply VDD to the memory cell MC is in an off state (the power supply potential VDD is not supplied due to the off state of the transistor T1), and the word line WL transitions from high level "H" to low level "L". As a result, the transfer transistors N3 and N4 of the memory cell MC are closed, and it is possible that the data retention capability DH of the high level "H" side (storage node MEMB side) of the memory cell MC becomes insufficient (weak state: W). As a result, it is possible that the data written in the memory cell MC during the reset operation is not retained in the memory cell MC. Alternatively, it is possible that the data written in the memory cell MC during the reset operation is destroyed. In FIG. 8, in the data retention capability DH, S indicates a state in which the data retention capability of the storage node MEMB side is sufficient.

[0052] 9, in order to reduce the possibility that data written during the reset operation described in FIG. 8 will not be retained in the memory cell MC, the timing is changed so that when the reset is released (the reset signal RESET transitions from high level "H" to low level "L"), the word line WL transitions from high level "H" to low level "L" while the supply of power supply VDD to the memory cell MC is in the ON state (the power supply potential VDD is being supplied due to the ON state of the transistor T1). This makes it possible to configure the memory cell MC so that the data retention capability DH on the high level "H" side (storage node MEMB side) of the memory cell MC is in a sufficient state (S), and the data written in the memory cell MC during the reset operation is reliably retained in the memory cell MC.

[0053] Therefore, the control unit CONT is configured to generate timing such that, when the reset mode is released (after the reset signal RESET transitions from high level "H" to low level "L"), the transistor T1 on the VDD side of the memory array AR is turned on, the word line WL is lowered to low level "L", and then the transistors EQ, PC1, and PC2 are turned on to start precharging the bit lines BT and BB. The control unit CONT capable of generating such timing will be described below with reference to the drawings.

[0054] Fig. 10 shows the timing when a reset request occurs during a read operation or a write operation in the normal read mode or normal write mode of the first embodiment. In Fig. 10, a memory operation MC_OP is shown including a wait and a read operation or a write operation (Re_Wri_OP). A reset operation RST_OP is shown including a wait and a reset write.

[0055] As shown in Figure 10, when the reset signal RESET transitions from low level "L" to high level "H" during a read operation or write operation Re_Wri_OP and a reset request occurs, based on the transition of the reset signal RESET to high level "H", the memory operation MC_OP transitions from the read / write operation Re_Wri_OP to a wait state, the read / write operation Re_Wri_OP is terminated, and the reset operation RST_OP transitions from the wait state to a reset write Reset write, and the reset write Reset write is started.

[0056] However, when the reset signal RESET goes to high level "H", the normal read / write operation Re_Wri_OP is stopped, but a certain time TC is required before the normal read / write operation Re_Wri_OP is stopped. During this certain time TC, the read / write operation Re_Wri_OP remains (continues), so there is a possibility that the read / write operation Re_Wri_OP and the reset write Reset write may conflict. If a conflict occurs between the read / write operation Re_Wri_OP and the reset write Reset write, it may lead to the generation of a shoot-through current path, and there is a risk of a large current flowing.

[0057] Fig. 11 shows the timing when a reset request occurs during a read / write operation in the second embodiment. As in Fig. 10, the memory operation MC_OP is shown as including a wait and a read or write operation (Re_Wri_OP). The reset operation RST_OP is shown as including a wait and a reset write.

[0058] As shown in Fig. 11, when the reset signal RESET transitions from low level "L" to high level "H" during the read / write operation Re_Wri_OP and a reset request occurs, first, the memory operation MC_OP transitions from the read / write operation Re_Wri_OP to a wait state based on the transition of the reset signal RESET to high level "H", and the read / write operation Re_Wri_OP is terminated. Next, after the read / write operation Re_Wri_OP is terminated, the reset operation RST_OP transitions from the wait state to reset write Reset write, and reset write Reset write is started.

[0059] In this way, the read / write operation Re_Wri_OP and the reset write Reset write do not overlap in time, so the generation of a through current path can be prevented. This eliminates the risk of a large current flowing. The control unit CONT that can generate such timing will be explained below with reference to the diagram.

[0060] The memory device of the second embodiment will be described with reference to Fig. 12 to Fig. 15. Fig. 12 is a diagram for explaining the overall configuration of the memory device according to the second embodiment. Fig. 13 is a diagram for explaining a memory cell unit of the memory device of Fig. 12. Fig. 14 is a diagram for explaining a control unit of the memory device of Fig. 12. Fig. 15 is a diagram for explaining the reset control circuit of Fig. 14.

[0061] 12 and 13 are different from FIG. 1 and FIG. 2 in that in FIG. 12 and FIG. 13, a control signal RSTASW is supplied to the gate of the transistor T1. Other configurations in FIG. 12 and FIG. 13 are the same as other configurations in FIG. 1 and FIG. 2, so duplicated explanations will be omitted. The control signal RSTASW is generated by the control unit CONT and is a signal for cutting off the supply of the power supply potential VDD to the memory cell MC. The control signal RSTASW is set to high level "H" at the time of reset. At the time of reset release, the control signal RSTASW is configured to transition from high level to low level first so as to turn on the transistor T1. As a result, the power supply potential VDD is supplied to the memory cell MC as the memory array power supply potential ARVDD, so that the low level "L" and high level "H" of the initialization data written to the memory cell MC by the reset write Reset write are reliably held in the memory cell MC. After that, all the word lines WL are controlled to transition from high level "H" to low level "L". The control unit CONT will be described in detail in FIG. 14.

[0062] Fig. 14 shows a detailed circuit configuration of the control unit CONT according to the embodiment 2. The control unit CONT in Fig. 14 differs from the control unit CONT in Fig. 5 in the following points.

[0063] 1) The internal clock generating circuit CLKGEN receives a reset signal RESET instead of a control signal RSTE. The internal clock generating circuit CLKGEN is an internal clock generating circuit for read and write operations, and is configured to stop the internal clocks for read and write operations at the start of or during a reset period.

[0064] 2) A reset control circuit RSCNT is provided. The reset control circuit RSCNT is configured to receive a reset signal RESET and generate a reset start signal IRESET after the read operation and the write operation are completed. The reset start signal IRESET is supplied to the gate of the transistor T1 as a control signal RSTASW.

[0065] 3) The control signal RSTE is generated by a negative OR circuit (NOR) of the reset start signal IRESET and the control signal RSTWDBACK.

[0066] The reset start signal IRESET is generated by supplying it to a wiring path LL formed so as to circle the outer periphery of the memory array unit AR or the outer periphery of the memory macro, as shown in Fig. 15. This makes it possible to configure the timing of the reset start signal IRESET so that, when the reset signal RESET is generated during a read operation or a write operation, the reset write of the memory cell MC can be started after the read operation or the write operation is completed. The memory macro refers to the entire area of ​​the SRAM1 including the memory cell array unit AR, the word line decoder unit (row decoder unit) RDE, the input / output unit IO, the control unit CONT, the bit line decoder unit (column decoder unit) CDE, etc. shown in Fig. 12 and Fig. 15.

[0067] Next, the operation of the SRAM 1, which transitions from normal mode 1 (standby state) -> entry into reset state -> release from reset state -> normal mode 2 (standby state), will be described.

[0068] (1) Normal mode 1 (standby state): In this state, the word line WL is at low level "L", the transistor T1 is turned on by the control signal RSTASW at low level "L", and the ground potential VSS is at a low level such as 0 V. In addition, the control signal CWSE is at low level "L", and the first bit line BT and the second bit line BB are precharged to a precharge level such as a high level. The memory cell MC is in a state in which predetermined data is held.

[0069] (2) Entry into the reset state: (2-1) When entering the reset state, the reset signal RESET transitions from low level "L" to high level "H". Then, the control signal RSTASW is made high level "H", the control signal CWSE is made high level "H", and the write column switches CTW and CBW for all columns are turned on. Then, the write circuit WBT supplies write data of low level "L" to the bit line BT, and the bit line BT is made low level "L". The write circuit WBB supplies write data of high level "H" to the bit line BB. Here, the high level of the bit line BB is set to H-Vtn (Vtn: threshold value of the column switch CBW).

[0070] (2-2) Next, all word lines WL are set to high level "H", and the low level "L" of the bit line BT and the high level "H-Vtn" of the bit line BB are written to all memory cells MC as initialization data. This causes the stored data of all memory cells to be initialized at high speed.

[0071] (3) Release from reset state: (3-1) To release the reset state, the reset signal RESET transitions from high level "H" to low level "L". After that, the control signal RSTASW is first changed from high level "H" to low level "L". All word lines WL maintain the high level "H", and the control signal CWSE maintains the high level "H". As the control signal RSTASW goes to low level "L", the level of the high-level storage nodes MEMB of all memory cells MC changes from high level "H-Vtn" to high level "H".

[0072] (3-2) Next, all the word lines WL are transitioned from high level “H” to low level “L.” The control signal RSTASW is at low level “L,” and the control signal CWSE maintains at high level “H.”

[0073] (4) Normal mode 2 (standby state): In normal mode 2, the control signal CWSE transitions from high level "H" to low level "L". The control signal RSTASW maintains low level "L", and all word lines WL maintain low level "L". As a result, the bit lines BT and BB are precharged to a precharge level similar to a high level, and the write column switches CTW and CBW of all columns are turned off. Initialization data written in the reset state is stored in all memory cells MC.

[0074] As described above, the operation of the SRAM 1 according to the second embodiment is transitioned.

[0075] According to the second embodiment, one or more of the following effects can be obtained.

[0076] (1) When the reset mode is released, a circuit (CONT) is provided that generates timing such that the switch (first transistor) T1 that supplies the power supply potential VDD to the memory cell MC is turned on, the word line WL is first turned off, and then the precharging of the bit lines BT and BB is started last.

[0077] (2) According to the above (1), when the reset is released, the power supply potential VDD is supplied to the memory cell MC, and the internal data of the memory cell MC is set to a reliable low level "L" and high level "H", and then all the word lines WL are transitioned from the selection level (high level "H") to the non-selection level (low level "L"), thereby preventing the internal data of the memory cell MC from being inverted.

[0078] (3) The above (1) prevents the generation of excess through current due to the overlap of activation of all word lines WL and precharging of bit lines BT and BB, thereby reducing the operating current during the reset operation.

[0079] (4) A circuit is provided that resets (reset writes) the memory cell MC when a reset signal occurs during a read / write operation and after the read / write operation is completed.

[0080] (5) As a result of (4) above, by having a signal (TDEC) that stops read / write operations and a signal (IRESET) that starts resetting the memory cells, the reset operation can be performed without being hindered by read / write operations.

[0081] (6) The circuit (control circuit CONT) that generates the reset start signal (IRESET) of the memory cell MC generates the timing of the reset start signal (IRESET) by routing the wiring path of the reset start signal (IRESET) around the periphery of the memory array AR of SRAM1 or the periphery of the macro cell of SRAM1. In other words, the control circuit CONT generates the reset start signal (IRESET) by a wiring path that routes around the periphery of the memory array AR or the periphery of the memory macro. When a reset signal occurs during a read / write operation, the timing of the reset start signal (IRESET) can be generated according to the layout direction and number of word lines WL of the memory array AR and the layout direction and number of bit lines BT, BB, so that the start time of the reset write of the memory array AR can be optimized. This shortens the initialization time of the memory cell MC.

[0082] The disclosure made by the present inventor has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the above-described embodiments and can be modified in various ways. [Explanation of symbols]

[0083] 1: SRAM AR: Memory cell array section RDE: Word line decoder section (row decoder section) IO: Input / output section CONT: Control section

Claims

1. A plurality of word lines; a plurality of pairs of first and second bit lines; a plurality of memory cells connected to the plurality of word lines and the plurality of pairs of first and second bit lines so as to be connected to one word line and one pair of first and second bit lines; a first transistor provided between the plurality of memory cells and a power supply potential; a plurality of word line drivers connected to the plurality of word lines; a write column switch connected to each of the pairs of first bit lines and second bit lines; a read column switch connected to each of the pairs of first bit lines and second bit lines; a precharge circuit connected to each of the pairs of first bit lines and second bit lines; a write circuit connected to each write column switch; a control circuit for receiving a reset signal; the control circuit, based on the reset signal being at a high level, sets the first transistor to an off state, the plurality of word lines to a selected state, the precharge circuit to an off state, the write column switch to an on state, and the read column switch to an off state, and sets the first bit line to a low level and the second bit line to a high level by the write circuit, thereby initializing the plurality of memory cells; The control circuit includes: When the reset signal transitions from the high level to the low level, the first transistor is turned on to supply the power supply potential to the plurality of memory cells; Then, the plurality of word lines are all controlled to be at a non-selected level; Thereafter, controlling the precharge circuit to start precharging the pairs of first bit lines and second bit lines. Semiconductor device.

2. 2. The semiconductor device according to claim 1, a second transistor for current limiting provided between the plurality of word line drivers and a power supply potential; The control circuit turns on the second transistor when the reset signal is at a high level.

3. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the control circuit controls the precharge circuit to start precharging the multiple pairs of first bit lines and second bit lines when the reset signal transitions from the high level to a low level and after all of the multiple word lines become unselected levels.

4. 2. The semiconductor device according to claim 1, the control circuit includes an internal clock generation circuit for writing and reading; The control circuit stops the internal clock generating circuit when the reset signal is set to a high level.

5. A semiconductor memory device comprising: a plurality of word lines; a plurality of pairs of first and second bit lines; a plurality of memory cells connected to the plurality of word lines and the plurality of pairs of first and second bit lines so as to be connected to one word line and one pair of first and second bit lines; a first transistor provided between the plurality of memory cells and a power supply potential; a plurality of word line drivers connected to the plurality of word lines; a write column switch connected to each of the pairs of first bit lines and second bit lines; a read column switch connected to each of the pairs of first bit lines and second bit lines; a precharge circuit connected to each of the pairs of first bit lines and second bit lines; a write circuit connected to each write column switch; a control circuit for receiving a reset signal; the control circuit, based on the reset signal being at a high level, sets the first transistor to an off state, the plurality of word lines to a selected state, the precharge circuit to an off state, the write column switch to an on state, and the read column switch to an off state, and sets the first bit line to a low level and the second bit line to a high level by the write circuit, thereby initializing the plurality of memory cells; A write operation or a read operation for the plurality of memory cells is performed, The semiconductor device, wherein when the reset signal transitions from a low level to the high level during the write operation or the read operation, the control circuit starts initialization of the plurality of memory cells after the write operation or the read operation is completed.

6. 6. The semiconductor device according to claim 5, a memory array including the plurality of memory cells, the plurality of word lines, and the plurality of pairs of first and second bit lines; a memory macro including the memory array, the plurality of word line drivers, the write column switch, the read column switch, the precharge circuit, the write circuit, and the control circuit; The control circuit generates a reset start signal for the plurality of memory cells by a wiring path that goes around an outer periphery of the memory array or an outer periphery of the memory macro.

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