SENSING CIRCUIT, SENSING METHOD, AND RESISTANCE CHANGE MEMORY

Abstract

To provide a resistance change type memory, a sense circuit, and a method that suppress consumption current during reading.SOLUTION: A sense circuit 10 has: a current source 11 for generating a first current having a current value being n times a current value (Iref) of a reference current; a current path 12a through which a cell current of a current value (Icell) corresponding to a resistance value of a memory cell 20 of a resistance change type memory, of the first current, flows; a current path 12c through which a current obtained by copying the cell current of the first current and multiplying it by (n-1) / 2, flows; a current path 12b through which a second current of a current value (Idif) obtained by subtracting a value of a current (Icell×{1+(n-1) / 2}=Icell×(n+1) / 2) of the current paths 12a and 12c from Iref×n, of the first current, flows; and an output circuit 15 that outputs a result of reading data from the memory cell 20 based on a current difference obtained from Icell×(n-1) / 2 and Idif, which is n times (three times in FIG. 1) a difference between Icell and Iref.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a sensing circuit, a sensing method, and a resistance change memory. [Background technology]

[0002] Known examples of resistance change memories include resistive random access memories (ReRAMs), magnetic random access memories (MRAMs), and phase-change random access memories (PCRAMs) (see, for example, Patent Documents 1 and 2).

[0003] A memory cell of a resistance change memory changes to a high resistance state or a low resistance state depending on an applied voltage, and holds each resistance state in association with binary data. When reading, a sense circuit (also called a sense amplifier) ​​is connected to the memory cell to be read. Then, depending on the magnitude relationship between the cell potential, which is the product of the current value of a constant reference current and the resistance value of the memory cell, and a predetermined reference potential, data (0 or 1) corresponding to the resistance value of the memory cell is output. In such a sense circuit, the closer the resistance value of the memory cell is to the value obtained by dividing the reference potential by the current value of the reference current, the smaller the potential difference between the cell potential and the reference potential. If this potential difference falls below the limit of the read sensitivity (read margin) of the sense circuit, normal reading is not possible, the memory cell is deemed "defective," and the yield decreases.

[0004] Conventionally, there has been a sense circuit that uses a current mirror circuit to copy the current flowing through a memory cell (hereinafter referred to as the cell current) and a reference current, and outputs the complementary potential difference resulting from the difference between the two currents as read data using a differential amplifier (see, for example, Patent Document 3). With this sense circuit, a determined bias voltage is applied to the memory cell, so there is no decrease in the cell current, and a relatively large current difference is input to the differential amplifier, realizing a relatively high read sensitivity. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-172703 A [Patent Document 2] JP 2011-134383 A [Patent Document 3] JP 2004-164766 A Summary of the Invention [Problem to be solved by the invention]

[0006] A sense circuit that uses a current mirror circuit to increase the current difference between the cell current and the reference current has many current paths and consumes a large current during reading. In one aspect, the present invention has an object to provide a sense circuit, a sense method, and a resistance change memory that can suppress current consumption during reading. [Means for solving the problem]

[0007] In one embodiment, a sense circuit is provided that includes: a current source that generates a first current having a second current value that is n times (n is a real number equal to or greater than 3) a first current value of a reference current; a first current path through which a cell current of a third current value corresponding to a resistance value of a memory cell of a resistive memory flows, among the first currents; a second current path through which a second current of a fourth current value obtained by subtracting n-1 times the third current value from the second current value flows, among the first currents; a first current mirror circuit that copies the cell current flowing in the first current path to generate a third current of the third current value; a second current mirror circuit that copies the second current flowing in the second current path to generate a fourth current of the fourth current value; and an output circuit that outputs a result of reading data from the memory cell based on a current difference that is n times the difference between the third current value and the first current value, which is obtained from the third current value of the third current and the fourth current value of the fourth current.

[0008] Also provided in one embodiment is a sensing method. Also, in one embodiment, a resistance change memory is provided. Effect of the Invention

[0009] According to one aspect of the present invention, current consumption during reading can be reduced. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 illustrates an example of a sense circuit according to the first embodiment; [Diagram 2] FIG. 13 is a diagram illustrating a sense circuit of a comparative example. [Diagram 3] FIG. 1 is a diagram showing an example of a resistance change memory. [Figure 4] FIG. 2 is a diagram showing an example of a circuit of one input / output portion of a column control circuit. [Diagram 5] FIG. 1 is a diagram showing an example of a memory in a resistance change memory. [Figure 6] FIG. 2 is a diagram illustrating an example of a voltage control circuit. [Figure 7] FIG. 2 is a diagram illustrating an example of a current source. [Figure 8] FIG. 13 illustrates an example of a sense circuit according to a second embodiment; [Figure 9] FIG. 13 illustrates an example of a sense circuit according to a third embodiment. [Figure 10] FIG. 13 illustrates an example of a sense circuit according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the invention will be described with reference to the drawings. (First embodiment) FIG. 1 is a diagram illustrating an example of a sense circuit according to a first embodiment.

[0012] The sense circuit 10 of the first embodiment is used to read data stored in a memory cell 20 (including a memory element 20a) of a resistance change memory. Other configurations of the resistance change memory will be described later (see FIG. 3, FIG. 4, etc.).

[0013] The sense circuit 10 has a current source 11 that generates a current having a current value (3Iref) three times the current value (Iref) of the reference current. The current source 11 limits the maximum value of the current flowing through the sense circuit 10 to 3Iref.

[0014] The sense circuit 10 also has a current path 12a through which a cell current of a current value (Icell) corresponding to the resistance value of the memory cell 20 flows, out of the current 3Iref. The sense circuit 10 also has a current path 12b through which a current of a current value (Idif) obtained by subtracting twice the value of Icell from 3Iref flows, out of the current generated by the current source 11.

[0015] Furthermore, the sense circuit 10 includes current mirror circuits 13 and 14, an output circuit 15, and a current adjustment circuit 16. The current mirror circuit 13 copies the cell current flowing through the current path 12a and generates a current having the same current value (Icell) as the cell current in the output circuit 15. In the example of FIG. 1, the current mirror circuit 13 has p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) (hereinafter referred to as pMOSs) 13a and 13b and n-channel MOSFETs (hereinafter referred to as nMOSs) 13c and 13d. In the sense circuit 10 of the first embodiment, the transistor sizes of the pMOSs 13a and 13b are the same (their channel lengths and channel widths are equal), and the transistor sizes of the nMOSs 13c and 13d are the same. Note that the transistor sizes being the same also include cases where there are some manufacturing errors (the same applies below).

[0016] The pMOS 13a is provided on the current path 12a, its source is connected to the current source 11, and its drain is connected to the memory cell 20. The gate of the pMOS 13a is connected to its own drain, and is also connected to the gate of the pMOS 13b and the current adjustment circuit 16.

[0017] The pMOS 13b is provided on a current path 12c through which a current obtained by copying the cell current flows, and has a source connected to the current source 11 and a drain connected to the drain of the nMOS 13c.

[0018] The nMOS 13c is provided on the current path 12c through which a current obtained by copying the cell current flows, and its source is at the ground potential (VSS (for example, 0 V)). The gate of the nMOS 13c is connected to its own drain and is also connected to the gate of an nMOS 13d that functions as an input transistor of the output circuit 15.

[0019] The current mirror circuit 13 in FIG. 1 includes a current mirror circuit made up of pMOSs 13a and 13b, and a current mirror circuit made up of nMOSs 13c and 13d. The current mirror circuit 14 copies the current flowing through the current path 12b and generates a current having the same current value (Idif) as that current in the output circuit 15. In the example of Fig. 1, the current mirror circuit 14 has nMOSs 14a and 14b. The transistor sizes of the nMOSs 14a and 14b are the same.

[0020] The nMOS 14a is provided on the current path 12b, and its drain is connected to the current source 11 via a pMOS 16b (described later) of the current adjustment circuit 16. Furthermore, the drain of the nMOS 14a is connected to its own gate as well as to the gate of an nMOS 14b that also functions as another input transistor of the output circuit 15. The source of the nMOS 14a is VSS.

[0021] 1 outputs the result of reading data from the memory cell 20 based on a current difference obtained from Icell and Idif, which is three times the difference between Icell and Iref. In the example of FIG. 1, the output circuit 15 is an amplifier circuit that amplifies the difference between differentially input signals, and has pMOSs 15a and 15b, an nMOS 15c, and nMOSs 13d and 14b that are part of the current mirror circuits 13 and 14.

[0022] A power supply voltage (VDD) is applied to the sources of pMOS 15a and 15b, and the gates of pMOS 15a and 15b are connected to each other and to the drain of pMOS 15b. The drain of pMOS 15a is connected to the output terminal OUT and the drain of nMOS 13d. The drain of pMOS 15b is connected to the drain of nMOS 14b. The sources of nMOS 13d and 14b are connected to the drain of nMOS 15c. The source of nMOS 15c is VSS. An enable signal SAen is input to the gate of nMOS 15c to enable the sense circuit 10 during a read operation.

[0023] The current adjustment circuit 16 detects a voltage (bias voltage) applied to the memory cell 20, and adjusts a value of a current (Idif) flowing through the current path 12b so that a value of the bias voltage (VBIAS) becomes equal to a reference voltage value (Vref). The current adjustment circuit 16 includes a voltage control circuit 16a and a pMOS 16b.

[0024] The voltage control circuit 16a detects the gate voltages of the pMOSs 13a and 13b of the current mirror circuit 13, which are the bias voltages applied to the memory cells 20, and controls the gate voltage (VGP) of the pMOS 16b so that VBIAS=Vref. This makes the source voltage (VC) of the pMOSs 13a and 13b constant. An example of the circuit of the voltage control circuit 16a will be described later (see FIG. 6).

[0025] The pMOS 16b is provided on the current path 12b, has a source connected to the current source 11, and has a drain connected to the drain of the nMOS 14a of the current mirror circuit 14. The pMOS 16b adjusts Idif in response to VGP. By adjusting Idif, Icell is also adjusted.

[0026] By providing such a current adjustment circuit 16, it is possible to limit the voltage applied to the memory element 20a, and to prevent an overvoltage from being applied to the memory element 20a. The operation of the sense circuit 10 will now be described.

[0027] When data is read from the memory cell 20, the logical level of the enable signal SAen becomes H (High) level, and the nMOS 15c turns on. In addition, the voltage control circuit 16a adjusts VBIAS=Vref, and the absolute value of the gate-source voltage of the pMOSs 13a and 13b of the current mirror circuit 13 becomes greater than the absolute value of the threshold voltage of the pMOSs 13a and 13b, and the pMOSs 13a and 13b turn on. In addition, the current source 11 generates a current of 3Iref.

[0028] The current 3Iref is branched into current paths 12a, 12b, and 12c. A cell current having a current value (Icell) corresponding to the resistance value of the memory cell 20 flows through the current path 12a, which is part of the current 3Iref. The current mirror circuit 13 also causes the current Icell to flow through the current path 12c. In addition, the nMOSs 13c and 13d of the current mirror circuit 13 are turned on, so that the current Icell is supplied to the output circuit 15.

[0029] On the other hand, a current of Icell flows through the current paths 12a and 12c, and thus a current of Idif=3Iref-2Icell flows through the current path 12b. Then, the nMOSs 14a and 14b of the current mirror circuit 14 are turned on, and thus a current of Idif is supplied to the output circuit 15.

[0030] The pMOSs 15a and 15b of the output circuit 15 are turned on when VDD is applied to their sources. Also, since the pMOSs 15a and 15b are connected in a current mirror configuration, the current Idif flowing between the source and drain of pMOS 15b also flows between the source and drain of pMOS 15a.

[0031] As a result, the output circuit 15 outputs, from the output terminal OUT, the read result (voltage ΔV) of the data from the memory cell 20 based on the current difference between Icell and three times Iref obtained from Idif and Icell. The reason why the current difference between Icell and three times Iref is obtained is that Idif - Icell = (Iref - Icell) × 3. When Icell > Iref, "1" data (H-level voltage ΔV) is output from the output terminal OUT, and when Icell < Iref, "0" data (L (Low)-level voltage ΔV) is output from the output terminal OUT.

[0032] In the sense circuit 10 as described above, the output circuit 15 does not output the read result of the data based on the difference between the current value (Iref) of the reference current and the current value (Icell) of the cell current, but outputs the read result based on (Iref - Icell) × 3. That is, since the signal difference (Idif - Icell) differentially input to the output circuit 15, which is an amplifier circuit, is an amplified version of Iref - Icell, even if Iref - Icell is a minute value, data can be read with high read sensitivity.

[0033] Also, compared to using a sense circuit that copies the cell current and the reference current respectively using current mirror circuits and reads out the complementary potential difference resulting from the difference between the two currents as read data using a differential amplifier, the sense circuit 10 as described above can suppress the power consumption.

[0034] Hereinafter, for comparison, an example of the above-described sense circuit is shown. FIG. 2 is a diagram showing a sense circuit of a comparative example. The sense circuit 30 of the comparative example has pMOSs 31 to 37 and nMOSs 38 to 42. pMOSs 31 and nMOSs 42 are turned on when the logical level of the enable signal SAen is H level and the logical level of the signal / SAen having the opposite logic to the enable signal SAen is L level during readout. VDD is applied to the source of pMOS 31, and the sources of pMOSs 32 and 35 are connected to the drain of pMOS 31. The drain of nMOS 42 is connected to the sources of nMOSs 38 to 41, and the source of nMOS 42 is VSS.

[0035] The pMOSs 32, 33, and are connected in a current mirror configuration, and a current having the same value (Icell) as the cell current flowing between the source and drain of the pMOS 32 also flows between the source and drain of the pMOSs 33 and .

[0036] The pMOSs 35, 36, and 37 are also connected as a current mirror, and a current having the same current value (Iref) as the reference current flowing between the source and drain of the pMOS 35 also flows between the source and drain of the pMOSs 36 and 37.

[0037] A current of Icell also flows between the drain and source of an nMOS 38 whose drain is connected to the drain of the pMOS 33, and a current of Icell also flows between the drain and source of an nMOS 39 which is current-mirror connected to the nMOS 38.

[0038] The current Iref also flows between the drain and source of an nMOS 40, whose drain is connected to the drain of the pMOS 36, and between the drain and source of an nMOS 41, which is connected to the nMOS 40 in a current mirror configuration.

[0039] Here, since the drains of pMOS 34 and nMOS 41 are connected to each other, a potential difference +ΔV corresponding to the current difference Icell-Iref is output from the node between the drains of pMOS 34 and nMOS 41 as one of the complementary outputs of the sense circuit 30.

[0040] In addition, since the drains of pMOS 37 and nMOS 39 are connected to each other, a potential difference −ΔV corresponding to the current difference Iref−Icell is output from the node between the drains of pMOS 37 and nMOS 39 as the other complementary output of the sense circuit 30.

[0041] To obtain the current difference of (Icell-Iref)×2=ΔI×2 that generates the complementary output difference ΔV×2 as shown above, a current of Icell×3+Iref×3 is consumed. When Icell≒Iref, a current of Iref×6 is consumed. This is because there are six current paths through which current is consumed.

[0042] In contrast, in the sense circuit 10 of the first embodiment, the current consumption to obtain the current difference Icell-Idif=(Icell-Iref)×3=ΔI×3 that generates the above voltage ΔV is Iref×3+Idiff×2=Iref×9-Icell×4. Even when Icell≈Iref, the current consumption is Iref×5, and although the current difference is larger (read sensitivity is higher) than in the sense circuit 30 of the comparative example, the number of current paths through which current is consumed is five, and the current consumption is small.

[0043] In addition, in the sense circuit 30, by changing the mirror ratio of the mirror circuit, it is possible to obtain a current difference (ΔI×3) similar to that of the sense circuit 10. That is, the channel width of the pMOS 34 is set to 1.5 times the channel width of the pMOS 32, 33, and the channel width of the pMOS 37 is set to 1.5 times the channel width of the pMOS 35, 36. Also, the channel width of the nMOS 39 is set to 1.5 times the channel width of the nMOS 38, and the channel width of the nMOS 41 is set to 1.5 times the channel width of the nMOS 40. As a result, a current difference of ΔI×3 can be obtained in the sense circuit 30, but in this case, the current consumption is Icell×3.5+Iref×3.5. When Icell≈Iref, the current consumption is Iref×7. The current consumption of the sense circuit 10 in the first embodiment is suppressed to 5 / 7 times this.

[0044] (Resistance change memory) A resistance change memory including the above-described sense circuit 10 will now be described. FIG. 3 is a diagram showing an example of a resistance change memory.

[0045] The resistance change memory 50 includes an I / F (interface) circuit 51 , an address decoder 52 , a command decoder 53 , a data input / output buffer 54 , a row control circuit 55 , a column control circuit 56 , a memory cell array 57 , and a power supply circuit 58 .

[0046] The I / F circuit 51 receives inputs of addresses, commands, and write data from outside the resistance change memory 50, and outputs read data. The address decoder 52 generates a row selection address and a column selection address from the address supplied from the I / F circuit 51, supplies the row selection address to a row control circuit 55, and supplies the column selection address to a column control circuit 56.

[0047] The command decoder 53 decodes the command supplied from the I / F circuit 51 and outputs various control signals. The data input / output buffer 54 holds write data supplied from the I / F circuit 51 and read data read from the memory cell array 57 .

[0048] The row control circuit 55 selects and drives one of a plurality of word lines (not shown) of the memory cell array 57 based on a row selection address supplied from the address decoder 52 and a control signal output from the command decoder 53 .

[0049] The column control circuit 56 selects one of a plurality of bit lines and a plurality of source lines (not shown) of the memory cell array 57 based on a column selection address supplied from the address decoder 52. Then, the column control circuit 56 applies a voltage for reading or writing to the selected bit line or source line based on a control signal output from the command decoder 53. The column control circuit 56 also has a sense circuit 10 as shown in FIG. 1. A circuit example of the column control circuit 56 will be described later.

[0050] The memory cell array 57 has a plurality of memory cells arranged in an array, each of which is connected to a word line, a bit line, and a source line. The power supply circuit 58 supplies a predetermined voltage to the row control circuit 55 and the column control circuit 56 .

[0051] (Column control circuit) FIG. 4 is a diagram showing an example of a circuit of one input / output portion of a column control circuit. For example, if the resistance change memory 50 has 32 input / output terminals, the column control circuit 56 includes 32 circuit units as shown in FIG.

[0052] The circuit portion of the column control circuit 56 shown in FIG. 4 includes column switches 61, 62, a BL driver 63, a SL driver 64, a write control circuit 65, a read switch 66, a read control circuit 67, a data output circuit 68, a data input circuit 69, and the sense circuit 10 shown in FIG.

[0053] The column switch 61 selects a plurality of bit lines (32 bit lines (BL <0> ~BL <31> )) is connected to the BL driver 63 and the reed switch 66.

[0054] The column switch 62 selects a plurality of source lines (32 source lines (SL) in the example of FIG. 4) based on a column selection address supplied from the address decoder 52. <0> ~SL <31> )) is connected to the SL driver 64.

[0055] In response to a control signal output from a write control circuit 65, the BL driver 63 applies a voltage corresponding to the write data to the bit line connected to the BL driver 63 by the column switch 61.

[0056] In response to a control signal output from a write control circuit 65, the SL driver 64 applies a voltage corresponding to the write data to the source line connected to the SL driver 63 by the column switch 62.

[0057] The write control circuit 65 receives a write signal "Write", which is one of the control signals output by the command decoder 53. When the write control circuit 65 is instructed to write data by "Write", it outputs a control signal for causing the BL driver 63 and the SL driver 64 to generate a voltage corresponding to the write data ("0" or "1") supplied from the data input circuit 69.

[0058] The reed switch 66 receives a read signal “Read”, which is one of the control signals output by the command decoder 53. When “Read” instructs the reed switch 66 to read data, the reed switch 66 connects the bit line, which the column switch 61 connects to the reed switch 66, to the sense circuit 10.

[0059] When a data read is instructed by "Read", the read control circuit 67 sets the logic level of the enable signal SAen shown in FIG. 1 to H level in order to enable the sense circuit 10.

[0060] When the data output circuit 68 is instructed to output data by the control signal “Read-Out” output by the command decoder 53, it outputs the read result of the data output by the sense circuit 10 as data “DQ<#>” of input / output number “#”.

[0061] When data input is instructed by the control signal “Write-In” output by the command decoder 53, the data input circuit 69 supplies the write data input as data “DQ<#>” of input / output number “#” to the write control circuit 65.

[0062] (Memory Cell) Next, an example of a memory cell in the resistance change memory 50 will be described. FIG. 5 is a diagram showing an example of a memory in a resistance change memory.

[0063] The memory cell 20 includes a memory element 20a and an nMOS 20b, which is an example of a cell transistor. The memory element 20a is an element whose resistance value changes according to an applied voltage. For example, the memory element 20a changes to a low resistance state or a high resistance state, and holds each resistance state in correspondence with binary data ("0" or "1"). The memory element 20a has a structure in which, for example, a metal oxide is sandwiched between electrodes. A source line (SL) is connected to one end of the memory element 20a, and one of the drain or source of the nMOS 20b is connected to the other end.

[0064] The other of the drain or source of the nMOS 20b is connected to a bit line (BL), and the gate of the nMOS 20b is connected to a word line (WL). When "0" is written to such a memory element 20a (when writing "0"), a high voltage (+HV) is applied to SL and BL is set to VSS (for example, 0V). This causes the memory element 20a to have a high resistance. When "1" is written to the memory element 20a (when writing "1"), SL is set to VSS and a high voltage (+HV) is applied to BL. This causes the memory element 20a to have a low resistance.

[0065] On the other hand, when data is read from the memory element 20a, a voltage (+LV) lower than +HV is applied to SL, and BL is set to VSS. (Voltage control circuit) Next, a circuit example of the voltage control circuit 16a included in the sense circuit 10 shown in FIG. 1 will be described.

[0066] FIG. 6 is a diagram showing an example of a voltage control circuit. The voltage control circuit 16a has pMOSs 16a1, 16a2 and nMOSs 16a3, 16a4, 16a5.

[0067] VDD is applied to the sources of pMOSs 16a1, 16a2. The gates of pMOSs 16a1, 16a2 are connected to each other and are connected to the drain of pMOS16a2. The drain of pMOS16a1 is connected to the drain of nMOS16a3, and the drain of pMOS16a2 is connected to the drain of nMOS16a4.

[0068] A bias voltage with a voltage value of VBIAS shown in FIG. 1 is applied to the gate of nMOS16a3, and a reference voltage with a voltage value of Vref shown in FIG. 1 is applied to the gate of nMOS16a4. The sources of nMOSs 16a3, 16a4 are connected to the drain of nMOS16a5.

[0069] An enable signal SAen is input to the gate of nMOS16a5, and the source of nMOS16a5 is at VSS. The potential of the node between the drain of pMOS16a1 and the drain of nMOS16a3 is output as the voltage value (VGP) of the gate of pMOS16b.

[0070] In such a voltage control circuit 16a, when Vref > VBIAS, VGP rises. As a result, the voltage value (VC) of the sources of pMOSs 13a, 13b shown in FIG. 1 rises, and VBIAS also rises. When Vref < VBIAS, VGP drops. As a result, VC drops, and VBIAS also drops.

[0071] In this way, the voltage control circuit 16a can perform control such that VBIAS ≈ Vref. The value of the current consumed by the voltage control circuit 16a as described above is sufficiently smaller than Iref, which is the current value of the reference current (for example, 1 / 10 or less of Iref).

[0072] (current source) Next, a circuit example of the current source 11 included in the sense circuit 10 shown in FIG. 1 will be described. FIG. 7 is a diagram illustrating an example of a current source.

[0073] Although not shown in FIG. 1, the current source 11 is connected to a power supply circuit 58 shown in FIG. The power supply circuit 58 includes resistors 58a and 58b, a pMOS 58c, and a differential amplifier 58d.

[0074] One end of the resistor 58a is connected to VSS, and the other end is connected to one end of the resistor 58b and the inverting input terminal ("-") of the differential amplifier 58d. The other end of the resistor 58b is connected to the drain of the pMOS 58c and the output terminal of the differential amplifier 58d.

[0075] The gate of the pMOS 58c is connected to its own drain and is also connected to the current source 11. VDD is applied to the source of the pMOS 58c. A signal of a constant potential (VREFC) is input to the non-inverting input terminal ("+") of the differential amplifier 58d which is powered by VDD.

[0076] The current source 11 has pMOSs 11a, 11b, and 11c. VDD is applied to the sources of the pMOSs 11a to 11c, and the gates of the pMOSs 11a to 11c are connected to the gate and drain of the pMOS 58c of the power supply circuit 58. That is, the pMOSs 11a to 11c and the pMOS 58c are current-mirror-connected. The drains of the pMOSs 11a to 11c are connected to each other. The transistor size of each of the pMOSs 11a to 11c is the same as that of the pMOS 58c. This realizes a current mirror circuit with a mirror ratio of 1:3, and a current three times the reference current Iref (3Iref) flowing between the source and drain of the pMOS 58c is generated and output by the current source 11.

[0077] The output potential of the differential amplifier 58d is Vo, the potential of the inverting input terminal is Vfb, the resistance value of the resistor 58a is R0, and the resistance value of the resistor 58b is R1. In this case, the resistors 58a and 58b are used which have R0 and R1 such that Iref=Vo / (R0+R1) and Vfb=R0 / Vo(R0+R1)=VREFC for the desired Iref.

[0078] It should be noted that constant potentials such as Vref and VREFC can be generated by, for example, a bandgap reference circuit. (Second embodiment) Fig. 8 is a diagram showing an example of a sense circuit according to the second embodiment, in which the same elements as those shown in Fig. 1 are denoted by the same reference numerals.

[0079] A sense circuit 70 of the second embodiment performs complementary output, similar to the sense circuit 30 of the comparative example shown in Fig. 2. In order to generate a current Icell and a current Idif in an output circuit 73 that performs complementary output, the configurations of current mirror circuits 71 and 72 are also different from the configurations of the current mirror circuits 13 and 14 of the sense circuit 10 shown in Fig. 1.

[0080] The current mirror circuit 71 includes pMOSs 13a, 13b and nMOS 13c included in the current mirror circuit 13, as well as nMOSs 71a, 71b and pMOSs 71c, 71d.

[0081] The nMOSs 71a and 71b are connected to the nMOS 13c as a current mirror. The transistor sizes of the nMOSs 13c, 71a, and 71b are the same. Therefore, the current Icell flowing between the drain and source of the nMOS 13c also flows between the drain and source of the nMOSs 71a and 71b. The nMOS 71b also functions as one of the input transistors of the output circuit 73.

[0082] The drain of pMOS 71c is connected to the drain of nMOS 71a. pMOS 71d is connected to pMOS 71c in a current mirror configuration. VDD is applied to the sources of pMOS 71c and 71d. In addition, pMOS 71c and 71d have the same transistor size. Therefore, the current Icell flowing between the source and drain of pMOS 71c also flows between the source and drain of pMOS 71d. pMOS 71d also functions as one of the input transistors of output circuit 73.

[0083] The current mirror circuit 72 includes nMOS 14a included in the current mirror circuit 14, as well as nMOSs 72a and 72b and pMOSs 72c and 72d. The nMOSs 72a and 72b are connected to the nMOS 14a as a current mirror. The transistor sizes of the nMOSs 14a, 72a, and 72b are the same. Therefore, the current Idif=3Iref-2Icell that flows between the drain and source of the nMOS 14a also flows between the drain and source of the nMOSs 72a and 72b. The nMOS 72b also functions as one of the input transistors of the output circuit 73.

[0084] The drain of pMOS 72c is connected to the drain of nMOS 72a. pMOS 72d is connected to pMOS 72c in a current mirror configuration. VDD is applied to the sources of pMOS 72c and 72d. In addition, pMOS 72c and 72d have the same transistor size. Therefore, the current Idif flowing between the source and drain of pMOS 72c also flows between the source and drain of pMOS 72d. pMOS 72d also functions as one of the input transistors of the output circuit 73.

[0085] In the output circuit 73, the drain of the pMOS 71d is connected to the drain of the nMOS 72b, and the drain of the pMOS 72d is connected to the drain of the nMOS 71b. As a result, a potential difference -ΔV corresponding to the current difference Idif-Icell is output from the output terminal OUT connected to the node between the drain of nMOS 71b and the drain of pMOS 72d. Also, a potential difference +ΔV corresponding to the current difference Icell-Idif is output from the output terminal / OUT connected to the node between the drain of nMOS 72b and the drain of pMOS 71d. In this way, complementary outputs are obtained from the output circuit 73.

[0086] The current consumed to obtain a current difference of (Icell-Idif)x2=((Icell-Iref)x3)x2=ΔIx6 that produces the complementary output difference (ΔVx2) is Irefx3+Icellx2+Idifx2=Irefx9-Icellx2. When Icell≒Iref, a current of Irefx7 is consumed.

[0087] According to the sense circuit 70 of the second embodiment, the current difference obtained in the output circuit 73 is ΔI×6, and therefore the read sensitivity can be improved compared to the sense circuit 10 of the first embodiment (the current difference obtained is ΔI×3). The current consumption of the sense circuit 70 is larger than that of the sense circuit 10, but the current consumption can be reduced compared to the case where the same read sensitivity is realized by the sense circuit 30 of the comparative example shown in FIG.

[0088] In the sense circuit 30 shown in FIG. 2, to obtain the same current difference (ΔI×6) as the sense circuit 70, the channel width of pMOS 34 is tripled compared to the channel widths of pMOS 32 and 33, and the channel width of pMOS 37 is tripled compared to the channel widths of pMOS 35 and 36. The channel width of nMOS 39 is tripled compared to the channel width of nMOS 38, and the channel width of nMOS 41 is tripled compared to the channel width of nMOS 40. This allows the sense circuit 30 to obtain a current difference of ΔI×6, but in this case, the current consumption is Icell×5+Iref×5. When Icell≈Iref, the current consumption is Iref×10. The current consumption of the sense circuit 70 of the second embodiment is suppressed to 7 / 10 times this.

[0089] (Third embodiment) Fig. 9 is a diagram showing an example of a sense circuit according to the third embodiment, in which the same elements as those shown in Fig. 1 are denoted by the same reference numerals.

[0090] In a sense circuit 80 of the third embodiment, a current source 81 generates a current having a current value (4Iref) four times that of Iref, unlike the current source 11 of the sense circuit 10 of Fig. 1. Such a current source 81 can be realized by adding one pMOS (having the same transistor size as the pMOS 58c) that is current-mirror connected to the pMOS 58c of the power supply circuit 58 in the current source 11 shown in Fig. 7.

[0091] 1. The current mirror circuit 82 also has pMOSs 82a, 82b and nMOSs 82c, 82d which have the same connection as the pMOSs 13a, 13b and nMOSs 13c, 13d of the current mirror circuit 13 in FIG.

[0092] However, in the current-mirror-connected pMOSs 82a and 82b, the channel width of the pMOS 82b is twice that of the pMOS 82a. Therefore, the mirror ratio is 1:2, and a current of 2Icell flows between the source and drain of the pMOS 82b and in the current path 12c. As a result, a current of Idif=4ref-3Icell flows in the current path 12b.

[0093] In the current-mirror-connected nMOSs 82c and 82d, the channel width of the nMOS 82c is twice as large as that of the nMOS 82d, so that the mirror ratio is 2:1 and a current of Icell flows between the drain and source of the nMOS 82d.

[0094] The current difference obtained in the output circuit 15 of the sense circuit 80 of the third embodiment is Icell-Idif=(Icell-Iref)×4=ΔI×4. The current consumed to obtain this current difference is Iref×4+Idif×2=Iref×12-Icell×6. When Icell≈Iref, a current of Iref×6 is consumed.

[0095] According to the sense circuit 80 of the third embodiment, the current difference obtained in the output circuit 15 is ΔI×4, and therefore the read sensitivity can be improved compared to the sense circuit 10 of the first embodiment (the current difference obtained is ΔI×3). The current consumption of the sense circuit 80 is larger than that of the sense circuit 10, but the current consumption can be reduced compared to the case where the same read sensitivity is realized by the sense circuit 30 of the comparative example shown in FIG.

[0096] In the sense circuit 30 shown in FIG. 2, to obtain the same current difference (ΔI×4) as the sense circuit 80, the channel width of pMOS 34 is doubled relative to the channel width of pMOS 32, 33, and the channel width of pMOS 37 is doubled relative to the channel width of pMOS 35, 36. The channel width of nMOS 39 is doubled relative to the channel width of nMOS 38, and the channel width of nMOS 41 is doubled relative to the channel width of nMOS 40. This allows the sense circuit 30 to obtain a current difference of ΔI×4, but in this case, the current consumption is Icell×4+Iref×4. When Icell≈Iref, the current consumption is Iref×8. The current consumption of the sense circuit 80 of the third embodiment is suppressed to 6 / 8 times this.

[0097] 8, the magnitude of the current generated by the current source 11 may be set to 4Iref, similarly to the above-mentioned sense circuit 80. The channel width of pMOS 13b may be set to twice the channel width of pMOS 13a, and the channel width of nMOS 13c may be set to twice the channel width of nMOSs 71c and 71b.

[0098] In this case, the resulting current difference is (Icell-Idf)×2=((Icell-Iref)×4)×2=ΔI×8, which makes it possible to further increase the read sensitivity. (Fourth embodiment) Fig. 10 is a diagram showing an example of a sense circuit according to the fourth embodiment, in which the same elements as those shown in Figs.

[0099] The sense circuit 90 of the fourth embodiment has a current source 81 that generates a current of 4Iref, similar to the sense circuit 80 shown in FIG. A sense circuit 90 of the fourth embodiment differs from the sense circuits 10 and 80 in that the current path 12c is divided into two current paths 12c1 and 12c2, and the current 4Iref branches into four current paths to flow.

[0100] Therefore, the circuit configuration of the current mirror circuit 91 is different from the circuit configurations of the current mirror circuits 13 and 82 of the sense circuits 10 and 80. The current mirror circuit 91 includes, in addition to the elements of the current mirror circuit 13 in FIG. 1, a pMOS 91a and an nMOS 91 for forming the above-mentioned current path 12c2.

[0101] The pMOS 91a is connected to the pMOS 13a in a current mirror configuration, and a current of Icell flows between the source and drain. The source of the pMOS 91a is connected to the current source 81, and the drain is connected to the drain of the nMOS 91b. The gate of the nMOS 91b is connected to its own drain, and the source is VSS.

[0102] In such a sense circuit 90 as well, Idif=4Iref-3Icell is obtained, and a current difference of ΔI×4 is obtained in the output circuit 15, similarly to the sense circuit 80. The magnitude of the current consumption is also similar to that of the sense circuit 80. Therefore, in the sense circuit 90 of the fourth embodiment, the same effect as that of the sense circuit 80 of the third embodiment is obtained.

[0103] While one aspect of the sense circuit, the sense method, and the resistance change memory of the present invention has been described above based on the embodiment, these are merely examples and the present invention is not limited to the above description.

[0104] For example, in the above example, the value of the current generated by the current sources 11, 81 is three or four times Iref, but is not limited to this and may be n times (n is a real number equal to or greater than 3). The value of the current flowing through the current path 12b may be between Iref×n and Icell×(n-1). The circuit configuration and mirror ratio of the current mirror circuits 13, 71, 82 may be appropriately changed so that a current of such value flows through the current path 12b.

[0105] In addition, appropriate modifications are possible, such as swapping pMOS and nMOS. [Explanation of symbols]

[0106] 10 Sense Circuit 11 Current source 12a, 12b, 12c Current paths 13,14 Current mirror circuit 13a, 13b, 15a, 15b, 16b pMOS 13c, 13d, 14a, 14b, 15c nMOS 15 Output circuit 16 Current adjustment circuit 16a Voltage control circuit 20 memory cells 20a Memory element

Claims

1. a current source that generates a first current having a second current value that is n times (n is a real number equal to or greater than 3) a first current value of a reference current; a first current path through which a cell current having a third current value corresponding to a resistance value of a memory cell of a resistance change type memory flows, the cell current being included in the first current; a second current path through which a second current of a fourth current value, which is obtained by subtracting a value that is n-1 times the third current value from the second current value, flows, out of the first current; a first current mirror circuit that copies the cell current flowing through the first current path to generate a third current having the third current value; a second current mirror circuit that copies the second current flowing through the second current path to generate a fourth current having the fourth current value; an output circuit that outputs a result of reading data from the memory cell based on a current difference that is n times a difference between the third current value and the first current value, the current difference being obtained from the third current value of the third current and the fourth current value of the fourth current; A sense circuit having

2. 2. The sense circuit of claim 1, further comprising a current adjustment circuit that detects a voltage applied to the memory cell and adjusts the fourth current value of the second current flowing through the second current path so that the voltage value of the voltage is equal to a reference voltage value.

3. 3. The sense circuit of claim 1, wherein the output circuit outputs a complementary read result based on the current difference obtained from the third current value and the fourth current value, the current difference being n×2 times the difference between the third current value and the first current value.

4. a current source generating a first current having a second current value that is n times (n is a real number equal to or greater than 3) a first current value of a reference current; a first current path passes a cell current of a third current value corresponding to a resistance value of a memory cell of a resistance change type memory, among the first currents; a second current path flows a second current of the first current, the second current having a fourth current value obtained by subtracting a value that is n-1 times the third current value from the second current value; a first current mirror circuit that copies the cell current flowing through the first current path to generate a third current having the third current value; a second current mirror circuit copies the second current flowing through the second current path to generate a fourth current having the fourth current value; an output circuit outputs a result of reading data from the memory cell based on a current difference that is n times a difference between the third current value and the first current value, the current difference being obtained from the third current value of the third current and the fourth current value of the fourth current; Sense method.

5. A memory cell whose resistance value changes depending on an applied voltage; a first current path through which a cell current of a third current value corresponding to a resistance value of the memory cell flows from the first current; a second current path through which a second current of a fourth current value obtained by subtracting n-1 times the third current value from the second current value flows from the first current; a first current mirror circuit that copies the cell current flowing through the first current path to generate a third current of the third current value; a second current mirror circuit that copies the second current flowing through the second current path to generate a fourth current of the fourth current value; and an output circuit that outputs a result of reading data from the memory cell based on a current difference of n times a difference between the third current value and the first current value, the current difference being obtained from the third current value of the third current and the fourth current value of the fourth current; A resistive change memory having the above structure.

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