Microelectronic package with three-dimensional (3D) monolithic memory die.

Abstract

To provide a microelectronic package.SOLUTION: A microelectronic package 100 has a 3D monolithic memory die 130. The 3D monolithic memory die 130 has: a first memory cell at a first layer of the 3D monolithic memory die 130; a second memory cell at a second layer of the 3D monolithic memory die 130; and a via in the 3D monolithic memory die 130 that communicatively couples an active die 105 with a package substrate 140 of the microelectronic package 100.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] Mobile devices such as smartphones can contain significant amounts of memory. For example, some mobile devices may have between about 4 and about 16 gigabytes (GB) of package-on-package (POP) memory. [Brief description of the drawings]

[0002] [Figure 1] 1 depicts an example of a microelectronic package having a three-dimensional (3D) monolithic memory die, according to various embodiments.

[0003] [Diagram 2] 1 depicts example memory cells of a 3D monolithic memory die, according to various embodiments.

[0004] [Diagram 3] 1 depicts an example circuit architecture for a 3D monolithic memory die, according to various embodiments.

[0005] [Figure 4] FIG. 1 illustrates a top view of a wafer and a die that may be or include a 3D monolithic memory die, according to various embodiments.

[0006] [Diagram 5] FIG. 1 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include a microelectronic package with a 3D monolithic memory die, according to various embodiments.

[0007] [Figure 6] FIG. 1 is a block diagram of an example electrical device that may include a microelectronic package with a 3D monolithic memory die, according to various embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which like numerals refer to like parts throughout, and in which are shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be construed in a limiting sense.

[0009] For purposes of this disclosure, the phrase "A or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0010] The descriptions may use perspective illustrations, such as, for example, top / bottom, in / out, above / below, etc. Such illustrations are used for ease of discussion only and are not intended to limit application of the embodiments described herein to any particular orientation.

[0011] In the description, the phrases "in one embodiment" or "in an embodiment" may be used, each of which may mean one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," and "having," etc., used with respect to the embodiments of the present disclosure, are synonymous.

[0012] The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following: "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, or that one or more other elements are coupled or connected between the elements that are said to be coupled. The term "directly coupled" may mean that two or more elements are in direct contact.

[0013] In various embodiments, a "first feature (e.g., formed / deposited / disposed on) a second feature" can mean that the first feature is, e.g., formed / deposited / disposed on a feature layer, and that at least a portion of the first feature may be in direct contact (e.g., direct physical or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a portion of the second feature.

[0014] The embodiments herein may be described with respect to various figures. Unless expressly stated, the dimensions of the figures are intended to be simplified illustrative examples rather than relative dimensional depictions. For example, the various length / width / heights of elements in the figures may not be drawn to scale unless otherwise indicated. Furthermore, although some schematic diagrams of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, it should be understood that such schematic diagrams may not reflect actual fabrication limitations that may cause features to appear less "ideal" when any of the structures described herein are inspected, for example, using scanning electron microscope (SEM) or transmission electron microscope (TEM) images. In such images of the actual structure, possible processing defects may be visible, such as edges of materials that are not perfectly straight, tapered vias or other openings, unintentional rounding of corners or variations in thickness of different material layers, occasional screw, edge or combination dislocations within crystalline regions, and / or occasional single atom or cluster of atoms dislocation defects. There may be other defects not listed here but that are common within the field of device manufacturing.

[0015] As mentioned, mobile devices may include significant amounts of memory, such as 4-16 GB of POP memory. However, POP memory typically uses wire bonds to communicatively couple cells of the POP memory to pads or interconnects that couple the POP memory to another element of the microelectronic package, such as a package substrate, which may have disadvantages in terms of cost and z-height of the memory. Additionally, the number of connections between dies may need to be limited based on the use of wire bonds.

[0016] In contrast, embodiments herein may relate to a 3D monolithic memory die that is connected face-to-face to an active die, such as a system-on-chip (SOC), by microbumps. The memory die may include multiple layers of memory cells that are communicatively or physically coupled to one another by conductive elements, such as vias. The memory die may further include one or more vias by which the active die may be communicatively coupled to a package substrate. The 3D monolithic memory die may provide several benefits. For example, the 3D monolithic memory die may enable a reduction in the overall z-height for a package by using face-to-face interconnects between the active die and the memory die, for example, instead of wire bonds. Additionally, the 3D monolithic memory die may enable higher performance, higher bandwidth, and lower power usage than traditional POP memories.

[0017] Some embodiments herein may enable between 10x and 100x increases in bandwidth compared to legacy POP memory. As an example, embodiments herein may enable between 100 and 10,000 wires providing approximately 500 gigabits per second (Gb / s) of bandwidth. The large wire count may be enabled by the three-dimensional nature of the interconnects of embodiments herein. Embodiments may also enable lower power based on the use of lower voltages.

[0018] FIG. 1 depicts an example of a microelectronic package 100 having a three-dimensional (3D) monolithic memory die according to various embodiments. For ease of reading, the 3D monolithic memory die is referred to herein as a "memory die 130." It will be understood that the depiction of the microelectronic package 100 is intended as a high-level, highly simplified depiction of an example. Unless expressly stated otherwise, the relative size, shape, quantity, or location of various elements is not intended to be shown in the figures. Furthermore, it will be understood that an actual embodiment may include elements not depicted in the figures, such as various conductive elements, molding materials, underfills, active or passive elements, for example.

[0019] The microelectronic package 105 may include an active die 105. The active die 105 may be or include a processor, such as, for example, a central processing unit (CPU), a graphics processing unit (GPU), a core of a distributed processor, or some other type of processor. In some embodiments, the active die 105 may be or include a radio frequency (RF) chip or RF circuitry configured to generate, process, transmit, or receive wireless signals, such as third generation (3G), fourth generation (4G), fifth generation (5G), Wi-Fi, or some other type of wireless signal. In some embodiments, the die 105 may include one or more passive components, such as, for example, capacitors, resistors, etc. Various active or passive components may be located within, partially within, or on the surface of the active die 105. In some embodiments, the active die 105 may be or may be referred to as a SOC.

[0020] The microelectronic package 100 may be coupled to or may include a package substrate 140. The package substrate 140 may be considered, for example, as a cored or coreless substrate. The package substrate 140 may include one or more layers of insulating material, which may be organic or inorganic. The package substrate 140 may further include one or more conductive elements, such as, for example, vias, pads, traces, microstrips, striplines, etc. The conductive elements may be internal to the package substrate or on its surface. In general, the conductive elements may enable routing of signals through the package substrate 140 or between elements coupled to the package substrate 140. In some embodiments, the package substrate 140 may be, for example, a printed circuit board (PCB), an interposer, a motherboard, or some other type of substrate.

[0021] Microelectronic package 100 may further include a memory die 130. Similar to the description of package substrate 140, memory die 130 may be formed from one or more layers of insulating material, which may be organic or inorganic. In some embodiments, the layers may be physically distinct from one another, such as being stacked or deposited at different times, while in other embodiments, memory die 130 may be a unitary element, where for purposes of discussion, the only logical separation is the layers discussed herein.

[0022] Specifically, the memory die may include a complementary metal oxide semiconductor (CMOS) layer 125 and several n-type metal oxide semiconductor (NMOS) layers 120a and 120b (collectively, "NMOS layers 120"). In general, the CMOS layer 125 may include several CMOS elements or circuits that may function as control logic for the memory die 130. One such logic is logic 145, which may be or include circuitry that may control memory cells of the NMOS layer 120. For example, the logic 145 may be a decoder, a sense amplifier, or some other type of logic. Although FIG. 1 depicts only two NMOS layers, it will be understood that actual embodiments may have between one and four layers, while other embodiments may have up to 128 layers or more. Additionally, it will be understood that the memory die may include additional layers, such as routing layers or other types of layers not depicted in FIG. 1.

[0023] The NMOS layers 120a / 120b may include a number of memory cells 140. In general, each one of the memory cells 140 may be an NMOS dynamic random access memory (DRAM). Specifically, each one of the memory cells 140 may be a DRAM memory including an NMOS transistor (sometimes referred to as an n-type transistor). The NMOS DRAM may have a memory capacity between about 1 Gb and about 128 GB. In some embodiments, the memory cells 140 may be implemented using passive and active elements within an insulating material of the memory die 130. In other embodiments, the memory cells 140 may be implemented as separate dies within a larger die package of the memory die 130. Although each one of the NMOS layers 120 is depicted as having one or two memory cells each, it will be understood that in other embodiments, the NMOS layers 120 may have between about 128 and about 1024 memory cells. It will also be understood that one or more of the NMOS layers may have the same or a different number of memory cells as another NMOS layer.

[0024] The various memory cells 140 may be communicatively coupled to one another by one or more conductive elements 115, as shown. The conductive elements 115 may be or include a conductive material that enables communication between elements of the memory die. The conductive elements 115 may be formed from a material such as, for example, copper, gold, etc. The conductive elements 115 may include, for example, microstrips, striplines, vias, traces, pads, etc. As will be appreciated, the conductive elements 115 may communicatively couple the various elements of the memory die 130 to one another or enable communication between different elements of the microelectronic package 100 via the memory die 130. By way of example, the conductive elements 115 may couple the various memory cells 140 to one another or to the memory cells 140 to the logic 145. Additionally or alternatively, the conductive elements 115 may enable communication between the active die 105 and the substrate 140 via the memory die 130. It will be appreciated that the layout and number of conductive elements 115 has been highly simplified in the depiction of FIG. 1 and that actual embodiments may include significantly more complex routing paths for conductive elements 115.

[0025] The memory die 130 may be coupled to the package substrate 140 by one or more interconnects 135. The interconnects 135 may be, for example, solder bumps formed from a material such as, for example, tin, silver, copper, or the like. If solder bumps are used for the interconnects 135, the solder bumps may be ball grid array (BGA) elements, as shown in FIG. 1. In other embodiments, the interconnects 135 may be pins of a pin grid array (PGA), solder grid array (SGA) elements, or some other type of interconnect. In general, the interconnects 135 may physically or communicatively couple the memory die 130 to the package substrate 140. For example, one or more of the interconnects 135 may physically couple to pads of the memory die 130 and pads of the package substrate 140 and may enable electrical signals to pass between the pads of the memory die 130 and the pads of the package substrate 140 (pads not shown to reduce clutter in FIG. 1). In other embodiments, the interconnects 135 may physically couple the memory die 130 and the package substrate 140, but the interconnects 135 may not communicatively couple the memory die 130 and the package substrate 140.

[0026] Similarly, memory die 130 may be coupled to active die 105 by interconnects 110. In general, interconnects 110 may be similar to interconnects 135 and may share one or more characteristics with interconnects 135. In particular, interconnects 110 may be formed from a solder material, such as, for example, tin, silver, copper, etc. Further, interconnects 110 may be BGA elements (as shown), while in other embodiments, PGA, SGA, etc. elements. In embodiments, interconnects 110 may enable a face-to-face connection between memory die 130 and active die 105. In other words, an active surface of memory die 130 may be coupled to an active surface of active die 105 by interconnects 110. As will be appreciated, in some embodiments, interconnect 110 may be smaller than interconnect 135, while in other embodiments, interconnect 110 may be the same size as or larger than interconnect 135.

[0027] In general, embodiments herein may provide several advantages over legacy POP memories, as discussed above. Specifically, by allowing interconnections between various memory cells 140 via conductive elements, such as conductive element 115, rather than wire bonds as may be used in legacy POP memories, the overall z-height of memory die 130 (e.g., the height of memory die 130 measured perpendicular to the plane of package substrate 140 to which microelectronic package 100 is bonded) may be lower than the overall z-height of legacy POP memories. For example, with a z-height between about 100 and about 150 micrometers ("microns"), memory die 130 may have a memory capacity between 4 GB and 16 GB. This is compared to the z-height of legacy POP memories, which may be between about 400 micrometers (microns) and about 1 millimeter ("mm").

[0028] As previously mentioned, FIG. 1 depicts a highly simplified example embodiment, and other embodiments may include variations from microelectronic package 100. For example, the number, positioning, relative size, etc. of the various elements of FIG. 1 may vary from embodiment to embodiment. For example, different embodiments may have more or fewer interconnects 110 / 135, memory cells 140, conductive elements 115, NMOS layer 120, etc. Additionally, in other embodiments, the relative placement of the various elements may differ. For example, active die 105 may be positioned between memory die 130 and substrate 140. In some embodiments, memory die 130 may be split such that active die 105 is between one or more layers of memory die 130. Other variations may be presented in other embodiments.

[0029] 2 depicts an example of a memory cell 240, according to various embodiments. In general, memory cell 240 may be similar to memory cell 140 of FIG. 1 and may share one or more characteristics.

[0030] The memory cell 240 may include a capacitor 203. The capacitor 203 may be, for example, a metal-insulator-metal (MIM) capacitor, or some other type of capacitor. The capacitor 203 may be coupled to a transistor 209 by a contact 207a. The contact 207a may be, for example, a conductive element such as a via. Specifically, the contact 207a may be coupled to a source or drain terminal of the transistor 209.

[0031] Capacitor 203 may be coupled to a cell plate 201 on the opposite side of the transistor. Cell plate 201 may be, for example, a polysilicon material and may be considered to be a source line. In particular, cell plate 201 may provide a control or reference voltage to a transistor of memory cell 240, such as transistor 209.

[0032] The transistor 209 may include several elements or layers, such as a thin film transistor layer 217. For example, the thin film transistor layer 217 may also be referred to as a "silicon transistor" layer and may be fabricated using a stack of layers. In some embodiments, the thin film transistor layer 217 may be or may include indium gallium zirconium oxide (IGZO). The thin film transistor layer 217 may be or may include a source or drain (or both) of the transistor 209. The thin film transistor layer 217 may be coupled to the contact 207a and may further include a contact 207b (which may be similar to the contact 207a), which may be coupled to a bit line 211 of a microelectronic package of which the memory cell 240 is a part. For example, in some embodiments, the source of the transistor 209 may be communicatively coupled to the contact 207a, while the drain of the transistor 209 may be communicatively coupled to the contact 207b (or vice versa).

[0033] The transistor 209 may further include a gate insulating material 219. The gate insulating material 219 may be, for example, silicon nitride, aluminum oxide, hafnium silicate, hafnium dioxide, zirconium dioxide, zirconium silicate, or the like, or some other suitable material. The transistor 209 may further include a metal gate 221, which may be, for example, indium tin oxide, indium zinc oxide, or the like, or some other material. The transistor 209 may further include a gate contact 223, which may be, for example, tantalum nitride, or some other material. The gate contact 223 may be coupled to a word line 227 of the microelectronic package.

[0034] In general, the voltage on word line 227 may represent whether data is being written to or read from memory cell 240. For example, a "high" voltage (e.g., a logical "1") may represent data being written to memory cell 240, while a "low" voltage (e.g., a logical "0") may represent data being read from memory cell 240. Bit line 211 may carry data to be read or written to memory cell 240.

[0035] 1, it will be understood that this depiction of memory cell 240 is intended as a highly simplified embodiment for purposes of discussion, and that the particular relative sizes of various elements, the particular shapes or locations of certain elements, etc. may differ in other embodiments.

[0036] FIG. 3 depicts an example of a circuit architecture of a memory die 330 according to various embodiments. The memory die 330 may be similar to, for example, the memory die 130 of FIG. 1. It will be understood that FIG. 3 is intended to depict an example of a high-level circuit architecture and is not intended to be a complete representation of a particular circuit or a particular physical structure. For example, various actual embodiments may have significantly more elements, such as passive, active, or conductive elements, than those depicted in FIG. 3. Furthermore, it will be understood that for clarity of illustration, not every single element in FIG. 3 may be labeled. However, elements sharing similar features in terms of depiction, arrangement, etc. may be presumed to be similar to one another unless expressly stated to the contrary.

[0037] In general, memory die 330 is depicted with two NMOS layers 320a and 320b (collectively "NMOS layers 320"), which may be similar to and share one or more features with NMOS layers 120a and 120b. Memory die 330 may further include a CMOS layer 325, which may be similar to and share one or more features with CMOS layer 125.

[0038] The memory die 330 may further include a number of memory cells 340. The memory cells 340 may be substantially similar to the memory cells 140 or 240 and may share one or more characteristics therewith. In FIG. 3, the memory die 330 is depicted as having two NMOS layers 320a and 320b, each of the NMOS layers 320a and 320b having two memory cells 340. However, it will be understood that an actual embodiment may have significantly more NMOS layers (as described above with respect to FIG. 1) and each of the NMOS layers may have significantly more memory cells. Each of the memory cells may include connections to a transistor 309, a capacitor 303, and a cell plate 301, which may be similar to the transistor 209, the capacitor 203, and the cell plate 201, respectively, and may share one or more characteristics therewith.

[0039] The memory die may further include several bitlines 311a, 311b, and 311c (collectively “bitlines 311”). Each of the bitlines 311 may be similar to bitline 211 and may share one or more characteristics with bitline 211. In particular, each of the bitlines 311 may carry data to be written to or read from a respective one of the memory cells 340.

[0040] 3, one of the source or drain of transistor 309 may be coupled to a bitline, such as bitline 311a or 311c, while the other of the source or drain of transistor 309 may be coupled to cell plate 301. In some embodiments, an NMOS layer may have two bitlines 311a and 311b, as depicted in NMOS layer 320a, while in other embodiments, an NMOS layer may have a single bitline, such as bitline 311c in NMOS layer 320b. In some embodiments, two bitlines 311a and 311b may be desirable because they may make it easier to read data from various memory cells 340 of memory die 330.

[0041] The various memory cells 340 may be communicatively coupled to word lines, such as word lines 327a and 327b, each of which may be similar to word line 227 of FIG. 2 and may share one or more characteristics with word line 227. Specifically, the gate of transistor 309 of memory cell 340 may be coupled to word lines 327a and 327b. In some embodiments, select transistor 331 may be located between the gate of transistor 309 and word line 327a or 327b. Operation of select transistor 331 may select a given memory cell 340 depending on whether select transistor 331 is open or closed.

[0042] The word lines 327a and 327b may be communicatively coupled to decoders 337a and 337b in the CMOS layer 325 as shown. The decoders 337a and 337b may be implemented as circuitry or logic in hardware, software, firmware, or a combination thereof. In general, the decoders 337a and 337b may be configured to perform memory address decoding or data routing for reading and writing the various memory cells 340.

[0043] The CMOS layer 325 may additionally include a sense amplifier 347, which may be coupled to the various bit lines 311a, 311b, and 311c by sense lines 343a and 343b. The sense amplifier 347 may be able to identify data in a particular memory cell 340 by sensing fluctuations in the voltage of a particular bit line 311a / 311b / 311c. In some embodiments, the memory die 330 may further include a select transistor 341, which may open or close to enable the sense amplifier 347 to read the value of a particular bit line 311a / 311b / 311c. In general, by applying a voltage change at the decoders 337a / 337b and selecting the sense transistors 331 and 341, one or more memory cells 340 of the memory die 330 may be identified by the sense amplifier 347, or data may be written to a given memory cell 340.

[0044] As with other figures herein, it will be understood that the embodiment of FIG. 3 is intended as a high level example embodiment, and that other embodiments may differ with respect to the number of elements, the particular arrangement of elements, etc.

[0045] FIG. 4 is a top view of a wafer 1500 and a die 1502, which may be or include a 3D monolithic memory die, or may be included in an IC package including one or more 3D monolithic memory dies, according to various embodiments. The wafer 1500 may be constructed from semiconductor material and may include one or more die 1502 with IC structures formed on the surface of the wafer 1500. Each of the die 1502 may be a repeating unit of a semiconductor product including an appropriate IC. After the fabrication of the semiconductor product is completed, the wafer 1500 may undergo a dicing process in which the die 1502 are separated from each other to provide individual "chips" of the semiconductor product. The die 1502 may include one or more 3D monolithic memory dies, one or more transistors, or supporting circuitry for routing electrical signals to the transistors, or some other IC component. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. A plurality of these devices may be combined on a single die 1502. For example, a memory array formed by a plurality of memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of FIG. 6) or other logic configured to store information in the memory devices or to execute instructions stored in the memory array.

[0046] 5 is a cross-sectional side view of an IC device assembly 1700 that may include one or more IC packages or other electronic components (e.g., dies) including one or more 3D monolithic memory dies according to any of the embodiments disclosed herein. The IC device assembly 1700 includes several components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposing second side 1742 of the circuit board 1702, and generally, the components may be disposed on one or both of the sides 1740 and 1742.

[0047] In some embodiments, the circuit board 1702 may be a PCB that includes multiple metal layers separated from one another by layers of insulating material and electrically interconnected by conductive vias. Any one or more of the metal layers may be formed into a desired circuit pattern (optionally in combination with other metal layers) to route electrical signals between components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a substrate that is not a PCB.

[0048] The IC device assembly 1700 illustrated in Figure 5 includes a package-on-interposer structure 1736 that is coupled to a first surface 1740 of a circuit board 1702 by a coupling component 1716. The coupling component 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (shown in Figure 5), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0049] The package-on-interposer structure 1736 may include an IC package 1720 coupled to the package interposer 1704 by a coupling component 1718. The coupling component 1718 may take any form suitable for the application, such as those discussed above with respect to the coupling component 1716. Although a single IC package 1720 is shown in FIG. 5, multiple IC packages may be coupled to the package interposer 1704, or, rather, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intermediate substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (die 1502 in FIG. 4), an IC device, or any other suitable component. In general, the package interposer 1704 may spread connections to a wider pitch or reroute connections to different connections. 5, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the package interposer 1704, while in other embodiments the IC package 1720 and the circuit board 1702 may be attached to the same side of the package interposer 1704. In some embodiments, more than two components may be interconnected via the package interposer 1704.

[0050] In some embodiments, the package interposer 1704 may be formed as a PCB including multiple metal layers separated from each other by layers of insulating material and electrically interconnected by conductive vias. In some embodiments, the package interposer 1704 may be formed from a polymeric material such as epoxy, fiberglass reinforced epoxy, epoxy with inorganic filler, ceramic material, or polyimide. In some embodiments, the package interposer 1704 may be formed from alternating rigid or flexible materials, which may include the same materials mentioned above used in semiconductor substrates such as silicon, germanium, and other III-V and IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to through silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art. In some embodiments, the package interposer 1704 may include one or more 3D monolithic memory dies.

[0051] The IC device assembly 1700 may include an IC package 1724 coupled to a first surface 1740 of the circuit board 1702 by a coupling component 1722. The coupling component 1722 may take the form of any of the embodiments discussed above with respect to the coupling component 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with respect to the IC package 1720.

[0052] 5 includes a POP structure 1734 coupled to a second side 1742 of a circuit board 1702 by a coupling component 1728. The POP structure 1734 may include an IC package 1726 and an IC package 1732 coupled by a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The POP structure 1734 may be configured according to any of the POP structures known in the art.

[0053] 6 is a block diagram of an example of an electrical device 1800 that may include one or more 3D monolithic memory dies according to any of the embodiments disclosed herein. For example, any suitable one of the components of the electrical device 1800 may include one or more of the IC device assembly 1700, IC package, IC device, or die 1502 disclosed herein. Although several components are illustrated in FIG. 6 as being included in the electrical device 1800, any one or more of these components may be omitted or duplicated as appropriate for an application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SOC die.

[0054] 6, the electrical device 1800 may include interface circuitry for coupling to one or more components. For example, the electrical device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuits) to which the display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input / output device interface circuitry (e.g., connectors and support circuits) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0055] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), CPUs, GPUs, cryptoprocessors (processors specialized for executing cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices, such as volatile memory, (e.g., DRAM), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0056] In some embodiments, the electrical device 1800 may include a communications chip 1812 (e.g., one or more communications chips). For example, the communications chip 1812 may be configured to manage wireless communications for the transfer of data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data by using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not include wires, although in some embodiments, they may not include wires.

[0057] The communications chip 1812 may implement any of several wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project, along with any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, where WiMAX is an acronym that stands for Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed IEEE 802.16 standard conformance and interoperability testing. The communications chip 1812 may operate in accordance with a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Communications (DECT), Evolution-Data Optimized (EV-DO), and their variants, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. The communications chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0058] In some embodiments, the communications chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., Ethernet). As mentioned above, the communications chip 1812 may include multiple communications chips. For example, a first communications chip 1812 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 1812 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications chip 1812 may be dedicated to wireless communications, and the second communications chip 1812 may be dedicated to wired communications.

[0059] The electrical processing device 1800 may include a battery / power circuit 1814. The battery / power circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1800 to an energy source (e.g., AC line power) separate from the electrical device 1800.

[0060] The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicator, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0061] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, a headset, or earphones.

[0062] The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a Musical Instrument Digital Interface (MIDI) output).

[0063] The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above), which may be in communication with a satellite-based system and may receive the location of the electrical device 1800, as is known in the art.

[0064] The electrical device 1800 may include another output device(s) 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device(s) 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0065] The electrical device 1800 may include another input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touch pad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0066] Electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other network computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, electrical device 1800 may be any other electronic device that processes data. [Examples of Various Embodiments]

[0067] Example 1 includes a microelectronic package including a package substrate; an active die; and a memory die communicatively coupled to the package substrate and the active die, where the memory die includes a first memory cell in a first tier of the memory die; a second memory cell in a second tier of the memory die; and vias in the memory die communicatively coupling the active die to the package substrate.

[0068] Example 2 includes the microelectronic package of example 1, where the memory die is between the package substrate and the active die.

[0069] Example 3 includes the microelectronic package of example 1, where the active surface of the memory die is coupled to the active surface of the active die by an interconnect.

[0070] Example 4 includes the microelectronic package of example 1, where the memory die has a z-height that is between 100 micrometers ("microns") and 150 microns.

[0071] Example 5 includes the microelectronic package of example 1, where the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB.

[0072] Example 6 includes the microelectronic package of example 1, where the active die and the memory die are communicatively coupled to the package substrate by interconnects other than wire bonds.

[0073] Example 7 includes the microelectronic package of any of examples 1-6, where the memory die further includes a third memory cell in the first layer of the memory die.

[0074] Example 8 includes the microelectronic package of any of Examples 1-6, where the first memory cell is a memory die.

[0075] Example 9 includes the microelectronic package of any of examples 1-6, where the first memory cell is a DRAM cell including a MOSFET.

[0076] Example 10 includes the microelectronic package of example 9, where the n-type MOSFET is coupled to a word line of the memory die, a bit line of the memory die, and a bias voltage of the memory die.

[0077] Example 11 includes an electronic device, the electronic device including an antenna that facilitates wireless communication between the electronic device and another electronic device; and a microelectronic package communicatively coupled to the antenna, where the microelectronic package includes a memory die communicatively coupled to a packaging substrate of the electronic device; and a SOC communicatively coupled to the packaging substrate of the electronic device by conductive elements in the memory die, where the memory die includes a first memory cell on a first layer of the memory die and a second memory cell on a second layer of the memory die.

[0078] Example 12 includes the electronic device of example 11, where the memory die has a z-height of less than 150 micrometers ("microns").

[0079] Example 13 includes the electronic device of example 11, wherein the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB.

[0080] Example 14 includes the electronic device of example 11, where the first memory cell is a DRAM cell including a MOSFET.

[0081] Example 15 includes the electronic device of any of Examples 11-14, where the memory die is between the SOC and the package substrate.

[0082] Example 16 includes the electronic device of any of Examples 11-14, where the SOC is communicatively coupled to the package substrate by interconnects other than wire bonds.

[0083] Example 17 includes a microelectronic package including a memory die communicatively coupled to a package substrate of an electronic device, and a SOC communicatively coupled to the package substrate of the electronic device by a conductive element in the memory die, where the memory die includes a first memory cell in a first layer of the memory die; a second memory cell in a second layer of the memory die; and the conductive element, where the first memory cell includes a first DRAM cell having a MOSFET and the second memory cell includes a second DRAM cell having an n-type MOSFET.

[0084] Example 18 includes the microelectronic package of example 17, wherein the memory die has a z-height of less than 100 micrometers ("microns").

[0085] Example 19 includes the microelectronic package of example 17, wherein the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB.

[0086] Example 20 includes the microelectronic package of any of Examples 17-19, where the n-type MOSFET of the first memory cell is coupled to a word line of the memory die, a bit line of the memory die, and a bias voltage of the memory die.

[0087] Various embodiments may include any suitable combination of the embodiments described above, including alternative (or) embodiments of the embodiments described above in the conjunctive form (e.g., "and" may be "and / or"). Additionally, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon that, when executed, lead to the actions of any of the embodiments described above. Additionally, some embodiments may include an apparatus or system having any suitable means for performing various operations of the embodiments described above.

[0088] The above description of exemplary embodiments, including those described in the Abstract, are not intended to be exhaustive or to be limited with respect to the precise forms disclosed. Specific implementations of, and examples for, various embodiments or concepts are described herein for purposes of illustration, but various equivalent modifications may be possible, as one of ordinary skill in the art will recognize. These modifications may be made in light of the above detailed description, Abstract, figures, or claims. [Item 1] A microelectronic package, comprising: A package substrate; An active die; a memory die communicatively coupled to the package substrate and to the active die, the memory die comprising: a first memory cell in a first layer of the memory die; a second memory cell in a second layer of the memory die; a via in the memory die that communicatively couples the active die to the package substrate; a memory die including 2. The microelectronic package of claim 1, wherein the memory die is between the package substrate and the active die. 3. The microelectronic package of claim 1, wherein the active surface of the memory die is coupled to the active surface of the active die by an interconnect. 4. The microelectronic package of claim 1, wherein the memory die has a z-height that is between 100 micrometers ("microns") and 150 microns. 5. The microelectronic package of claim 1, wherein the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB. 6. The microelectronic package of claim 1, wherein the active die and the memory die are communicatively coupled to the package substrate by an interconnect that is different from a wire bond. 7. The microelectronic package of claim 1, wherein the memory die further includes a third memory cell in a first layer of the memory die. 8. The microelectronic package of claim 1, wherein the first memory cell is a memory die. 9. The microelectronic package of claim 1, wherein the first memory cell is a dynamic random access memory (DRAM) cell including an n-type metal oxide semiconductor field effect transistor (MOSFET). Item 11. The microelectronic package of item 9, wherein the n-type MOSFET is coupled to a word line of the memory die, a bit line of the memory die, and a bias voltage of the memory die. 1. An electronic device comprising: an antenna for facilitating wireless communication between the electronic device and another electronic device; a microelectronic package communicatively coupled to the antenna, the microelectronic package comprising: a memory die communicatively coupled to a package substrate of the electronic device, the memory die including first memory cells in a first tier of the memory die and second memory cells in a second tier of the memory die; a system-on-chip (SOC) communicatively coupled to the package substrate of the electronic device by conductive elements in the memory die; and a microelectronic package having An electronic device comprising: Item 13. The electronic device of item 11, wherein the memory die has a z-height of less than 150 micrometers ("microns"). Item 14. The electronic device according to item 11, wherein the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB. Item 15. The electronic device of item 11, wherein the first memory cell is a dynamic random access memory (DRAM) cell including an n-type metal oxide semiconductor field effect transistor (MOSFET). Item 16. The electronic device of item 11, wherein the memory die is between the SOC and the package substrate. Item 17. The electronic device of item 11, wherein the SOC is communicatively coupled to the package substrate by interconnects other than wire bonds. 1. A microelectronic package comprising: 1. A memory die communicatively coupled to a packaging substrate of an electronic device, the memory die comprising: a first memory cell in a first layer of the memory die, the first memory cell including a first dynamic random access memory (DRAM) cell having an n-type metal oxide semiconductor field effect transistor (MOSFET); second memory cells in a second layer of the memory die, the second memory cells including a second DRAM cell having an n-type MOSFET; A conductive element a memory die including: a system-on-chip (SOC) communicatively coupled to the package substrate of the electronic device by the conductive elements in the memory die; A very small electronic package having a Item 19. The microelectronic package of item 17, wherein the memory die has a z-height of less than 100 micrometers ("microns"). Item 20. The microelectronic package of item 17, wherein the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB. Item 18. The microelectronic package of item 17, wherein the n-type MOSFET of the first memory cell is coupled to a word line of the memory die, a bit line of the memory die, and a bias voltage of the memory die.

Claims

1. 1. A microelectronic package comprising: A package substrate; An active die; a memory die communicatively coupled to the package substrate and to the active die; having The memory die includes: a first memory cell in a first n-type metal oxide semiconductor (NMOS) layer of the memory die; a second memory cell in a second NMOS layer of the memory die; control logic in a complementary metal oxide semiconductor (CMOS) layer of the memory die that controls the first memory cells and the second memory cells; a via in the memory die communicatively coupling the active die to the package substrate; The present invention relates to a microelectronic package comprising:

2. The microelectronic package of claim 1, wherein the first NMOS layer is stacked on the second NMOS layer, and the second NMOS layer is stacked on the CMOS layer.

3. The microelectronic package of claim 1 or 2, wherein the memory die is between the package substrate and the active die.

4. The microelectronic package of any one of claims 1 to 3, wherein the active surface of the memory die is coupled to the active surface of the active die by an interconnect.

5. The microelectronic package of any one of claims 1 to 4, wherein the memory die has a z-height that is between 100 micrometers ("microns") and 150 microns.

6. The microelectronic package of any one of claims 1 to 5, wherein the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB.

7. The microelectronic package of any one of claims 1 to 6, wherein the active die and the memory die are communicatively coupled to the package substrate by interconnects other than wire bonds.

8. The microelectronic package of any one of claims 1 to 7, wherein the memory die further comprises a third memory cell in a first NMOS layer of the memory die.

9. The microelectronic package of any one of claims 1 to 8, wherein the first memory cell is a memory die.

10. The microelectronic package of any one of claims 1 to 9, wherein the first memory cell is a dynamic random access memory (DRAM) cell including an n-type metal oxide semiconductor field effect transistor (MOSFET).

11. The microelectronic package of claim 10 , wherein the n-type MOSFET is coupled to a word line of the memory die, a bit line of the memory die, and a bias voltage of the memory die.

12. 1. An electronic device comprising: an antenna for facilitating wireless communication between the electronic device and another electronic device; a microelectronic package communicatively coupled to the antenna; Equipped with The microelectronic package comprises: a memory die communicatively coupled to a package substrate of the electronic device, the memory die including: a first memory cell in a first n-type metal oxide semiconductor (NMOS) layer of the memory die; a second memory cell in a second NMOS layer of the memory die; and control logic in a complementary metal oxide semiconductor (CMOS) layer of the memory die that controls the first memory cell and the second memory cell; a system-on-chip (SOC) communicatively coupled to the packaging substrate of the electronic device by conductive elements in the memory die; An electronic device comprising:

13. The electronic device of claim 12, wherein the first NMOS layer is stacked on the second NMOS layer, and the second NMOS layer is stacked on the CMOS layer.

14. 14. The electronic device of claim 12 or 13, wherein the memory die has a z-height of less than 150 micrometers ("microns").

15. The electronic device of any one of claims 12 to 14, wherein the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB.

16. The electronic device of any one of claims 12 to 15, wherein the first memory cell is a dynamic random access memory (DRAM) cell including an n-type metal oxide semiconductor field effect transistor (MOSFET).

17. The electronic device of any one of claims 12 to 16, wherein the memory die is between the SOC and the package substrate.

18. The electronic device of any one of claims 12 to 17, wherein the SOC is communicatively coupled to the package substrate by interconnects other than wire bonds.

19. 1. A memory die communicatively coupled to a packaging substrate of an electronic device, comprising: a first memory cell in a first n-type metal oxide semiconductor (NMOS) layer of the memory die, the first memory cell comprising a first dynamic random access memory (DRAM) cell having an n-type metal oxide semiconductor field effect transistor (MOSFET); a second memory cell in a second NMOS layer of the memory die, the second memory cell including a second DRAM cell having an n-type MOSFET; control logic in a complementary metal oxide semiconductor (CMOS) layer of the memory die that controls the first memory cells and the second memory cells; A conductive element a memory die including: a system-on-chip (SOC) communicatively coupled to the packaging substrate of the electronic device by the conductive elements in the memory die; A microelectronic package having 20. The microelectronic package of claim 19, wherein the first NMOS layer is stacked on the second NMOS layer, and the second NMOS layer is stacked on the CMOS layer.

21. 21. The microelectronic package of claim 19 or 20, wherein the memory die has a z-height of less than 100 micrometers ("microns").

22. The microelectronic package of any one of claims 19 to 21, wherein the memory die has a memory capacity between 4 gigabytes (GB) and 16 GB.

23. The microelectronic package of any one of claims 19 to 22, wherein the n-type MOSFET of the first memory cell is coupled to a word line of the memory die, a bit line of the memory die, and a bias voltage of the memory die.

Images