Signal generating circuit, radar device, and signal control method

Abstract

To provide a signal generation circuit, a radar device, and a signal control method that achieve multi-value and accurate power control.SOLUTION: A signal generation circuit includes a digital-to-analog converter (DAC) and a mixer. The DAC is configured to convert an input digital signal into two signals in a first mode. Encoded content of the input digital signal contains a plurality of bits. The mixer is coupled to the DAC and, in the first mode, inputs the two signals into which the input digital signal is converted to two input ports of the mixer, respectively, to generate an output signal. The output power of the output signal corresponding to the input digital signal having first encoded content is different from the output power of the output signal corresponding to the input digital signal having second encoded content. The strength of the output signal is related to a voltage difference between the two signals into which the input digital signal is converted.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority from Taiwan Patent Application Publication No. 111146073, filed on December 1, 2022. The entirety of the above-mentioned patent application is incorporated herein by reference and made a part of this specification.

[0002] The present invention relates to a signal processing technology, and more particularly to a signal generating circuit, a radar device, and a signal control method. [Background technology]

[0003] Radar and communication systems used for ultra-wideband (UWB) may have requirements for ultra-low power control. Among radar systems for UWB, frequency modulated continuous waveform (FMCW) and impulse radio radar systems are likely to face the following challenges: the need to roll off the spikes of chirp signals on the frequency spectrum, and the need to use coding schemes to carry digital information. Summary of the Invention

[0004] A signal generation circuit according to an embodiment of the present disclosure includes, but is not limited to, a digital-to-analog converter (DAC) and a mixer. The digital-to-analog converter is configured to convert an input digital signal into two signals in a first mode. The encoded content of the input digital signal includes a plurality of bits. The mixer is coupled to the digital-to-analog converter and configured to input two signals converted from the input digital signal in the first mode to two input ports of the mixer respectively to generate an output signal. An output power of the output signal corresponding to the input digital signal having the first encoded content is different from an output power of the output signal corresponding to the input digital signal having the second encoded content, and a strength of the output signal is related to a voltage difference between the two signals converted from the input digital signal.

[0005] A radar device according to an embodiment of the present disclosure includes, but is not limited to, the signal generating circuit and the transmission circuit described above. The transmission circuit is coupled to the signal generating circuit. The transmission circuit is configured to generate a transmission signal according to the output signal. The transmission signal is transmitted by the radar device.

[0006] A signal control method according to an embodiment of the present disclosure includes, but is not limited to, converting an input digital signal, in a first mode, whose coding content includes a plurality of bits, into two signals, and also generating an output signal according to the two signals converted from the input digital signal through a mixer in the first mode, where an output power of the output signal corresponding to the input digital signal having the first coding content is different from an output power of the output signal corresponding to the input digital signal having the second coding content, and the strength of the output signal is related to a voltage difference between the two signals converted from the input digital signal.

[0007] To make the above and other features and advantages of the present disclosure more comprehensible, exemplary embodiments are described in detail below with reference to the accompanying drawings. [Brief description of the drawings]

[0008] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0009] [Figure 1] FIG. 2 is a block diagram of components of a signal generation circuit according to one embodiment of the present disclosure. [Figure 2A] FIG. 2 is a block diagram of components of a radar device according to one embodiment of the present disclosure. [Figure 2B] FIG. 2 is a block diagram of components of a radar device according to one embodiment of the present disclosure. [Diagram 3] FIG. 2 is a circuit diagram of a mixer according to one embodiment of the present disclosure. [Figure 4A]FIG. 2 is a diagram of multiple encoded contents and corresponding waveforms according to one embodiment of the present disclosure. [Figure 4B] FIG. 2 is a spectral diagram of multiple encoded contents according to one embodiment of the present disclosure. [Figure 5A] FIG. 2 is a spectral diagram of an actual output signal and a predicted output signal according to one embodiment of the present disclosure. [Figure 5B] FIG. 2 is a waveform diagram of a carrier signal and two signals according to one embodiment of the present disclosure. [Figure 6] FIG. 2 is a diagram of encoded content and a corresponding pulse signal according to one embodiment of the present disclosure. [Figure 7] FIG. 13 is a spectrum diagram of power control according to one embodiment of the present disclosure. [Figure 8] 4 is a flowchart of a signal control method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] 1 is a block diagram of components of a signal generation circuit 3 according to an embodiment of the present disclosure. The signal generation circuit 3 includes (but is not limited to) a digital-to-analog converter (DAC) 31 and a mixer 32. The digital-to-analog converter 31 is coupled to the mixer 32. The digital-to-analog converter 31 is configured to convert an input digital signal DS in a digital format into signals (e.g., signals S1 and S2) in an analog format. The digital-to-analog converter 31 may be implemented by an N-stage (N is the number of bits of the input digital signal DS, a positive integer greater than zero) oversampling modulator or an N-bit Nyquist frequency sampler.

[0011] The architecture of the signal generating circuit 3 is applicable to radar or communication systems, in particular to ultra-wideband (UWB) radar or communication systems. In the following, in Fig. 2A and Fig. 2B, radar devices 10 and 20 are shown as exemplary embodiments to show how the signal generating circuit 3 (implemented as the signal generating circuit 13) works.

[0012] FIG. 2A is a block diagram of components 10 of a radar device according to an embodiment of the present disclosure. Referring to FIG. 2A, the radar device 10 includes (but is not limited to) a transmitting antenna 11, a transmitting circuit 12, a signal generating circuit 13, a receiving antenna 14, and a receiving circuit 15. The signal generating circuit 13 in FIG. 2A is an implementation of the signal generating circuit 3 in FIG. 1 applied to a radar device. The radar device 10 can be applied in fields such as meteorology, speed measurement, reversing, topography, and military. The radar device 10 can be a frequency modulated continuous wave (FMCW) radar or an impulse radio (IR) ultra-wideband (UWB) radar.

[0013] The transmitting circuitry 12 is coupled to a transmitting antenna 11. In one embodiment, the transmitting circuitry 12 is configured to transmit a signal via the transmitting antenna 11.

[0014] The signal generating circuit 13 is coupled to the transmitting circuit 12. The signal generating circuit 13 includes (but is not limited to) a digital-to-analog converter (DAC) 131 and a mixer 132.

[0015] The digital-to-analog converter 131 is coupled to the mixer 132. The digital-to-analog converter 131 is configured to convert the input digital signal DS in a digital format into signals (e.g., signals S1 and S2) in an analog format. The digital-to-analog converter 131 may be implemented by an N-stage (N is the number of bits of the input digital signal DS, a positive integer greater than zero) oversampling modulator or an N-bit Nyquist frequency sampler.

[0016] The mixer 132 is connected to the transmission circuit 12. The mixer 132 is configured to process an output signal (e.g., signals S1 and S2) of the digital-to-analog converter 131 and generate an output signal OS. The transmission circuit 12 may generate a transmission signal according to the output signal OS transmitted from the transmission antenna 11 of the radar device 10.

[0017] The receiving circuit 15 is coupled to the receiving antenna 14. The receiving circuit 15 is configured to receive an echo signal via the receiving antenna 14. The echo signal is generated when the transmission signal transmitted by the transmitting antenna 11 is reflected by an external object, including but not limited to the above.

[0018] The detailed hardware architecture of the radar device 10 is described below with reference to FIG. 2B.

[0019] 2B is a block diagram of components of a radar device 20 according to one embodiment of the present disclosure. Referring to FIG. 2B, the radar device 20 is a specific implementation of the radar device 10. The radar device 20 includes (but is not limited to) a transmitting antenna 11, a transmitting circuit 12, a signal generating circuit 13, a receiving antenna 14, a receiving circuit 15, a frequency synthesizer 16, a modulator 17, an intermediate frequency processing circuit 18, and a controller 19.

[0020] The transmission circuit 12 includes a power amplifier PA. The power amplifier PA amplifies the output signal OS to generate a transmission signal, and transmits the transmission signal to the outside via the transmission antenna 11 (i.e., the transmitted electromagnetic wave carries the output signal OS of the radar device 20).

[0021] The signal generating circuit 13 may further include a filter 133. The filter 133 performs low-pass filtering on the analog signal output from the digital-to-analog converter 131 to generate a signal (e.g., signals S1 and S2) to be input to the mixer 132. However, in other embodiments, the signal generating circuit 13 may not include the filter 133.

[0022] The receiving circuit 15 includes a low noise amplifier LNA. The low noise amplifier LNA amplifies the signal received by the receiving antenna 14 to generate a received radio frequency signal.

[0023] The frequency synthesizer 16 is coupled to the mixer 132 and the mixer 182 of the intermediate frequency processing circuit 18. The frequency synthesizer 16 inputs a carrier signal CS to the mixer 132 and / or the mixer 182. In one embodiment, the carrier signal CS may be a sawtooth wave or a triangular wave, or the carrier signal CS may be other carrier signals applied to FMCW (such as linear signals, geometric signals, other chirp signals, etc.), for example, a frequency sweep signal for FMCW radar, whose frequency changes with time during a frequency sweep period. In another embodiment, the carrier signal CS may be a fixed frequency continuous wave or a fixed frequency signal, for example, a fixed frequency carrier signal CS for IR-UWB radar.

[0024] The modulator 17 is coupled to the frequency synthesizer 16. The modulator 17 may be a Sigma-Delta Modulator (SDM). The modulator 17 is configured to adjust the step of changing the frequency of the carrier signal CS as a frequency sweep signal.

[0025] The intermediate frequency processing circuit 18 may include an analog-to-digital converter (ADC) 181, a mixer 182, and an adjustment circuit 183.

[0026] The mixer 182 is coupled to the receiving circuit 15, the frequency synthesizer 16, and the adjusting circuit 183. The mixer 182 is configured to process an output signal of the receiving circuit 15 (e.g., the received radio frequency signal described above) and the carrier signal CS to generate an intermediate frequency signal.

[0027] The conditioning circuit 183 may include an amplifier and / or a filter and is configured to amplify and / or low-pass filter the intermediate frequency signal.

[0028] The analog-to-digital converter 181 is configured to convert the intermediate frequency signal in analog form into a digital signal.

[0029] The controller 19 is coupled to the digital-to-analog converter 131 and the analog-to-digital converter 181. The controller 19 may be a chip, a processor, a microcontroller, an application specific integrated circuit (ASIC), or any type of digital circuit. In an embodiment, the controller 19 is configured to determine the coding content of the input digital signal DS, which will be described in detail in a later embodiment. In an embodiment, the controller 19 is configured to determine the mode, which will be described in detail in a later embodiment. In an embodiment, the controller 19 is configured to determine the position information of the external object according to the output signal of the intermediate frequency processing circuit 18.

[0030] In other embodiments, the signal generating circuit 13 may be incorporated in other radio frequency devices.

[0031] The operation of the radar systems 10 and 20 will now be described along with its various components.

[0032] In one embodiment, the digital-to-analog converter 131 is configured to convert the input digital signal DS into signals S1 and S2 in a first mode, which may be a power control mode or other mode related to power regulation and is used to regulate the output power of the signal generating circuit 13.

[0033] In one embodiment, the input digital signal DS is an encoded digital signal, and the digital-to-analog converter 131 outputs both the signal S1 and the signal S2 according to the encoded content of the input digital signal DS. The encoded content of the input digital signal DS includes multiple bits.

[0034] In one embodiment, the number of bits of the encoded content of the input digital signal DS is 2. For example, Table (1) is a comparison table showing the encoded content (2 bits) of the input digital signal DS and the output voltages of the signals S1 and S2. [Table 1] When the encoded content is "00", the signals S1 and S2 are DC signals with output voltages of 0 volts (e.g. ground) and 1.2 volts (e.g. power supply voltage), when the encoded content is "01", the signals S1 and S2 are DC signals with output voltages of 0.3 volts and 1 volt, when the encoded content is "10", the signals S1 and S2 are DC signals with output voltages of 0.6 volts, when the encoded content is "11", the signals S1 and S2 are DC signals with output voltages of 1 volt and 0.3 volt. The output signal OS of the signal generating circuit 13 will be described in detail in a later embodiment.

[0035] In another embodiment, the number of bits of the encoded content of the input digital signal DS is greater than 2. For example, Table (2) is a comparison table showing the encoded content (3 bits) of the input digital signal DS and the output voltages of the signals S1 and S2. [Table 2] When the encoded content is "000", the signals S1 and S2 are DC signals with output voltages of 0 volts and 1.2 volts, respectively; when the encoded content is "001", the signals S1 and S2 are DC signals with output voltages of 0.15 volts and 1.05 volts, respectively; when the encoded content is "010", the signals S1 and S2 are DC signals with output voltages of 0.3 volts and 0.9 volts, respectively; when the encoded content is "011", the signals S1 and S2 are DC signals with output voltages of 0.45 volts and 0.75 volts, respectively. When the encoded content is "100", the signals S1 and S2 are DC signals with output voltages of 0.6 volts, when the encoded content is "101", the signals S1 and S2 are DC signals with output voltages of 0.75 volts and 0.45 volts, when the encoded content is "110", the signals S1 and S2 are DC signals with output voltages of 0.9 volts and 0.3 volts, when the encoded content is "111", the signals S1 and S2 are DC signals with output voltages of 1.05 volts and 0.15 volts, when the encoded content is "111". The output signal OS will be described in detail in a later embodiment.

[0036] It should be noted that the coding content of the input digital signal DS may be composed of 4 bits, 5 bits, 6 bits, etc. Furthermore, there may be other variations in the correspondence between the coding content and the output voltages of the signals S1 and S2. The correspondence may be changed according to the requirements of the user, and the embodiments of the present invention are not intended to limit any variations.

[0037] In one embodiment, in a first mode (e.g., a power control mode or other mode related to power regulation), the mixer 132 inputs the signal S1 and the signal S2 to two input ports of the mixer 132, respectively, and generates the output signal OS. That is, the mixer 132 processes the signal S1 and the signal S2 input via the two input ports, respectively, to generate the output signal OS.

[0038] 3 is a circuit diagram of a mixer 132-1 according to an embodiment of the present disclosure. Referring to FIG. 3, the mixer 132-1 is a specific implementation of the mixer 132 or the mixer 182. The mixer 132-1 is a double-balanced mixer (e.g., a Gilbert cell).

[0039] Mixer 132-1 includes transistors T1, T2, T3, T4, T5, and T6. A control port (e.g., a gate) of transistor T1 is coupled to an output port of digital-to-analog converter 131, and serves as one of two input ports of mixer 132-1, receiving a control signal IF+ (e.g., either signal S1 or signal S2). A control port (e.g., a gate) of transistor T4 is coupled to an output port of digital-to-analog converter 131, and serves as the other of two input ports of mixer 132-1, receiving a control signal IF- (e.g., the other of signal S1 and signal S2).

[0040] In one embodiment, in the first mode, the two input ports of the mixer 132-1 are differential input ports. As an example, the control signal IF+ is a signal S1, and the control signal IF- is a signal S2. The signals S1 and S2 form a set of differential signals, and the output voltages of the signals S1 and S2 form a set of differential voltages.

[0041] In another embodiment, in the second mode, the control signals IF+ and IF- are intermediate frequency signals. For example, the signals S1 and S2 are AC type sinusoidal signals. The second mode may be a mixed mode or other modes for generating new frequencies according to multiple input signals.

[0042] A first port (e.g., source) of the transistor T1 is coupled to a current source SC (the other port is used to couple to a reference voltage port, e.g., ground), and a second port (e.g., drain) of the transistor T1 is used as an output port of the transistor T1. The transistor T1 is controlled by a control signal IF+ to change its conductive state. For example, the transistor T1 may be turned on or off to output or block the control signal IF+.

[0043] For example, when the control signal IF+ is a DC high voltage level, the transistor T1 is turned on and the transistor T1 outputs the control signal IF+ to the transistor T2. In another example, the control signal IF+ in AC form is input to the transistor T1 to dynamically control the conduction state, e.g., on or off, of the transistor T1. In another example, when the control signal IF+ is a DC low voltage level (i.e., the potential of a reference voltage such as ground potential), the transistor T1 is turned off and the transistor T1 has no output.

[0044] A control port (e.g., gate) of transistor T2 is configured to receive an input signal LO+, a first port (e.g., source) of transistor T2 is coupled to an output port of transistor T1, and a second port (e.g., drain serving as one of the other two input ports of mixer 132-1) of transistor T2 serves as an output port of transistor T2. The input signal LO+ may be a clock signal or a local oscillator signal. Transistor T2 is controlled by the input signal LO+ to change its conductive state. For example, transistor T2 may pass or block a control signal IF+ by turning on or off. Transistor T2 may process the control signal IF+ output by transistor T1 and the input signal LO+ to form an output signal RF+.

[0045] A control port (e.g., gate) of the transistor T3 is configured to receive an input signal LO-, a first port (e.g., source) of the transistor T3 is connected to an output port of the transistor T1, and a second port (e.g., drain) of the transistor T3 serves as an output port of the transistor T3 (optionally coupled to a choke coil CH to receive a power supply voltage VDD). The input signal LO- may be a clock signal or a local oscillator signal. The transistor T3 is controlled by the input signal LO- to change its conduction state. For example, the transistor T3 may pass or block the control signal IF+ by turning it on or off. The transistor T3 may process the control signal IF+ output by the transistor T1 and the input signal LO- to form an output signal RF- different from the output signal RF+.

[0046] Furthermore, a first port (e.g., a source) of the transistor T4 is connected to a current source SC, and a second port (e.g., a drain) of the transistor T4 serves as an output port of the transistor T4. The transistor T4 is controlled by a control signal IF- to change its conductive state. For example, the transistor T4 may be turned on or off to output or block the control signal IF-.

[0047] For example, when the control signal IF- is a DC high voltage level, the transistor T4 is turned on and the transistor T4 outputs the control signal IF- to the transistor T5. In another example, the control signal IF- in AC form is input to the transistor T4 to dynamically control the conduction state, e.g., on or off, of the transistor T4. In another example, when the control signal IF- is a DC low voltage level (i.e., the potential of a reference voltage such as ground potential), the transistor T4 is turned off and the transistor T4 has no output.

[0048] A control port (e.g., gate) of transistor T5 is configured to receive an input signal LO+, a first port (e.g., source) of transistor T5 is coupled to an output port of transistor T4, and a second port (e.g., drain) of transistor T5 serves as an output port of transistor T5. Transistor T5 is controlled by the input signal LO+ to change its conductive state. For example, transistor T5 may be turned on or off to pass or block a control signal IF-. Transistor T5 may process the control signal IF- output by transistor T4 and the input signal LO+ to form an output signal RF-.

[0049] A control port of transistor T6 (e.g., a gate serving as the other of the other two input ports of mixer 132-1) is configured to receive an input signal LO−, a first port (e.g., a source) of transistor T6 is coupled to an output port of transistor T4, and a second port (e.g., a drain) of transistor T6 serves as an output port of transistor T6 (optionally coupled to a choke coil CH). Transistor T6 is controlled by the input signal LO− to change its conduction state. For example, transistor T6 may pass or block a control signal IF− by turning it on or off. Transistor T6 may process the control signal IF− output by transistor T4 and the input signal LO− to form an output signal RF+, which is different from the output signal RF−.

[0050] In one embodiment, in the first mode, the signals S1 and S2 are DC signals. At this time, the control signals IF+ and IF- are DC signals, and the mixer 132-1 is used as a buffer, an attenuator, and a power supply. The output power of the output signal OS corresponding to the input digital signal DS having the first encoded content is different from the output power of the output signal OS corresponding to the input digital signal DS having the second encoded content. The output signal OS includes the output signal RF+ and the output signal RF- described above. That is, the input digital signal DS having different encoded content can generate the output signal OS having different output power. Also, the strength of the output signal OS is related to the voltage difference between the signals S1 and S2. That is, the output signal OS having different strength / output power can be generated by changing the voltage difference between the signals S1 and S2.

[0051] Taking table (1) as an example, if the encoded content is "00", the output signal OS is +V fLO_max Volts (V fLO_max is the maximum voltage), and if the encoded content is "01", the output signal OS is +V fLO Volts (V fLO is 0 to V fLO_max When the encoded content is "10", the output signal OS is 0 volts, and when the encoded content is "11", the output signal OS is -V fLO Volts. V fLO =V DC *COS(2πf LO t+φ), where V DC is the output voltage of signal S1 or S2, and f LO is the frequency of a carrier signal CS (eg, a sine wave signal or a clock signal) and φ is a phase constant.

[0052] The polarity of the output signal OS is related to the polarity of the voltage difference between the signals S1 and S2. For example, if the voltage difference between the signals S1 and S2 is positive, the output signal OS is positive, and if the voltage difference between the signals S1 and S2 is negative, the output signal OS is negative. That is, assuming that the voltage difference is the signal S1 minus the signal S2, if the signal S1 is greater than the signal S2, the output signal OS is positive, and if the signal S1 is less than the signal S2, the output signal OS is negative. Also, if the signals S1 and S2 are equal, the output signal OS is zero. That is, the mixer 132 / 132-1 has no output.

[0053] In one embodiment, the number of bits (i.e., the total number of bits) of the encoded content of the input digital signal DS is greater than 2, and the output signal OS has more than four different voltages. Take table (2) as an example, the number of bits is 3. The encoded content is "000", "001", "010", "011", "100", "101", "110", "111", and the output signal OS has more than four different voltages. 2 ΔV fLO , +3 2 ΔV fLO , +2 2 ΔV fLO , +1 2 ΔV fLO , 0 (i.e., NIL for no output), -1 2 ΔV fLO , -2 2 ΔV fLO , -3 2 ΔV fLO volts. That is, there are eight different voltages. As the absolute value of the voltage difference between signals S1 and S2 increases, the absolute value of the output signal OS also increases, and as the absolute value of the voltage difference between signals S1 and S2 decreases, the absolute value of the output signal OS also decreases until signals S1 and S2 become equal, that is, until there is no output.

[0054] 4A is a schematic diagram of a plurality of encoded contents and corresponding waveforms according to one embodiment of the present disclosure. Referring to FIG. 4A, the input signal LO+, LO- has a frequency f LOThe amplitude peak values ​​of the output signal OS corresponding to the encoded contents "001", "010", and "011" are different.

[0055] 4B is a spectrum diagram of multiple encoded contents according to one embodiment of the present disclosure. Referring to FIG. 4B, the frequencies of the output signal OS corresponding to the encoded contents “001”, “010”, and “011” are all f LO , but with different output powers in the frequency spectrum.

[0056] In one embodiment, there is a linear relationship between the peak amplitude value of the output signal OS corresponding to the input digital signal DS having the first encoded content and the peak amplitude value of the output signal OS corresponding to the input digital signal DS having the second encoded content. Taking table (2) as an example, the peak amplitude value of the output signal OS corresponding to the encoded content "000" is 42 times the peak amplitude value of the output signal OS corresponding to the encoded content "011". Similarly for the rest, the encoded contents "000", "001", "010", "011", "101", "110", "111" all have a ΔV fLO is an integer multiple of

[0057] In one embodiment, the linear relationship includes a slope that corresponds to a step. When the linear relationship is expressed as a linear function, the linear function includes a slope. The step is proportional to the amount of change between the amplitude peak value of the output signal OS corresponding to the input digital signal DS having the first encoded content and the amplitude peak value of the output signal corresponding to the input digital signal having the second encoded content, and the step is related to the number of these bits of encoded content (i.e., the number of bits). For example, the step may be ΔV fLO and the peak amplitude of the output signal OS is V fLO and ΔV fLO =2V fLO / (2 N -2) 2 N is the number of bits of the encoded content, which may be the bit scale of the digital-to-analog converter 131.

[0058] In some embodiments, in addition to the multiplier difference, there may also be a certain difference between the amplitude peak values ​​of the output signals OS in Table (2). Furthermore, the relationship between the amplitudes of the output signals corresponding to different encoded contents is not limited to a linear relationship, but may be other mathematical relationships or even unformulated relationships.

[0059] In one embodiment, the output power of the output signal OS may be -15 dBm or less, for example -40 dBm, however, the output power may be changed according to actual needs.

[0060] It is worth noting that the effect of rapidly switching the amplitude of the output signal OS can be achieved by the current drive of the digital-to-analog converter 131 and the mixer 132-1.

[0061] In one embodiment, the frequency of the carrier signal CS varies with time during a frequency sweep period. That is, the carrier signal CS is a frequency sweep signal, such as a sawtooth wave, a triangular wave, or other chirp / FMCW signal. FIG. 5A is a spectrum diagram of an actual output signal OS and a predicted output signal OS according to one embodiment of the present disclosure, and FIG. 5B is a waveform diagram of the carrier signal CS and two signals S1 and S2 according to one embodiment of the present disclosure. Referring to FIG. 5A, comparing the predicted spectrum 501 and the actual spectrum 502, the actual spectrum 502 may have spike peaks with higher intensity at the edge of the frequency band. The higher intensity spike peaks may require a reduction in transmission power according to the specifications of some communication technologies (e.g., UWB), which affects the sensing range of the radar.

[0062] Referring to Fig. 5B, a spike peak is formed because the waveform of the carrier signal CS includes two segments in the time domain. The frequency of one of the two segments increases / rises over time, as shown in Fig. 5B as the rising segment, i.e., the first segment 512, of the triangular wave 511. The frequency of the other of the two segments decreases / falls over time, as shown in Fig. 5B as the falling segment, i.e., the second segment 513, of the triangular wave 511. The turning segment is formed between the two segments, as shown in Fig. 5B as the turning point between the rising segment and the falling segment of the triangular wave 511, but the turning segment may also appear at the turning point between the falling segment and the rising segment.

[0063] The mixer 132 / 132-1 receives signals S1 and S2 and a carrier signal CS as a frequency sweep signal. For example, the signal S1 is input to the control port of the transistor T1 in FIG. 3, the signal S2 is input to the control port of the transistor T4, and the carrier signal CS is input to the control ports of the transistors T2, T3, T5, and T6. The amplitude of the output signal OS corresponding to the turning segment is different from the amplitude of the output signal OS corresponding to the first segment 512 and the second segment 513 (i.e., the rising segment and the falling segment). For example, the first output power of the output signal OS corresponding to the turning segment is smaller than the second output power of the output signal OS corresponding to one of the two segments (e.g., the first segment 512 / rising segment), and the first output power of the output signal OS corresponding to the turning segment is smaller than the third output power of the output signal OS corresponding to the other of the two segments (e.g., the second segment 513 / rising segment).

[0064] Furthermore, according to Tables (1) and (2), the voltage difference between the signal S1 and the signal S2 can be reflected in the output power of the output signal OS. The amplitudes of the signals S1 and S2 corresponding to the turning segments may also be different from the amplitudes of the signals S1 and S2 corresponding to the falling segment (i.e., the second segment 513) and the rising segment (i.e., the first segment 512). Taking FIG. 5B as an example, the amplitude DC of the signal S1 corresponding to the falling segment and the rising segment IF+ is the highest voltage level, and the amplitude DC of the signal S2 corresponding to the falling and rising segments IF- is the lowest voltage level, with amplitude DC IF+ and amplitude DC IF- Voltage difference with DC offset (absolute value) is the largest. The amplitude DC of the signal S1 corresponding to the turning segment IF+ and the amplitude DC of the signal S2 corresponding to the turning segment IF- Voltage difference between DC offset (absolute value) is the smallest. That is, the voltage difference DC between the signals S1 and S2 corresponding to the falling or rising segments offset is the voltage difference DC between the signals S1 and S2 corresponding to the turning segments offset That is, the voltage difference DCoffset between the signals S1 and S2 corresponding to the turning segment is greater than the voltage difference DC offset Voltage difference DC offset When the voltage difference DC corresponding to the different segments of the triangular wave 511 becomes smaller, the output power of the output signal OS becomes smaller. offset By controlling in the above manner, the intensity at the ends of the frequency band can be weakened (rolled off), and the frequency spectrum of the output signal OS can be brought closer to the expected spectrum 501 shown in FIG. 5A from the actual spectrum 502 shown in FIG. 5A.

[0065] In one embodiment, the frequency of the carrier signal CS is fixed, i.e. the carrier signal CS is a fixed frequency signal. In this case, the output signal OS is a pulsed signal, the amplitude of which corresponds to the coded content of the input digital signal DS, e.g. the magnitude of the amplitude and / or the phase polarity corresponds to the coded content of the input digital signal DS.

[0066] For example, FIG. 6 is a diagram of the encoded content and the corresponding pulse signal according to one embodiment of the present disclosure. Referring to FIG. 6, in a time interval TD, a positive short pulse (e.g., the encoded content in Table (2) is “010” and the corresponding output signal OS is +2 2 ΔV fLO ) or a negative short pulse (for example, the coding content in Table (2) is “110” and the corresponding output signal OS is −2 2 ΔV fLO (wherein TD is a positive short pulse, 0 is a negative short pulse, and 10 is a no output). Taking Table (1) as an example, an input digital signal with code "01" may correspond to a positive short pulse, an input digital signal with code "11" may correspond to a negative short pulse, and an input digital signal with code "10" may correspond to no output. Assuming that the value of the time interval TD is less than a certain threshold (e.g., less than or about 2 nanoseconds (ns)), the output signal OS forms a flat spread spectrum signal on the frequency spectrum, which can be used for UWB applications, and can also be used to determine distance and location.

[0067] In one embodiment, the output signal OS may be an in-phase signal or an out-of-phase signal. The in-phase signal may be generated, for example, as the encoded content of "001", "010", "011" in Table (2). The out-of-phase signal may be generated, for example, as the encoded content of "101", "110", "111" in Table (2).

[0068] In one embodiment, the output signal OS may be a binary phase shift keying (BPSK) signal. For example, a BPSK pulse / pulse train can be realized by selecting the coding contents of "010" (corresponding to an in-phase signal), "100" (corresponding to no output), and "110" (corresponding to an out-of-phase signal) in Table (2).

[0069] FIG. 7 is a spectrum diagram of power control according to an embodiment of the present disclosure. Referring to FIG. 7, according to design requirements, the controller 19 of FIG. 2B may define a power difference between the maximum output powers of the output signals OS corresponding to different encoded contents. For example, the power difference between the maximum values ​​of the output powers 701, 702, 703 of the output signals OS corresponding to three encoded contents is less than 10 dB (decibels), but the present disclosure is not limited thereto.

[0070] In one embodiment, in the second mode (e.g., a mixing mode for generating a new frequency according to multiple input signals or other modes), the signals S1 and S2 are AC intermediate frequency signals. The mixer 132 is also configured to mix the intermediate frequency signals with the carrier signal CS. The intermediate frequency signals are, for example, sine wave signals or AC signals with other waveforms. Taking FIG. 3 as an example, the control signals IF+, IF- are intermediate frequency signals (e.g., sine wave signals in AC form), and the input signals LO+, LO- are carrier signals CS (e.g., frequency sweep signals or fixed frequency signals). The mixer 132 mixes the intermediate frequency signals according to the carrier signal CS to generate output signals RF+ and RF-, and the output signals RF+ and RF- are radio frequency signals.

[0071] FIG. 8 is a flow chart of a signal control method according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 8, in a first mode, an input digital signal DS is converted into two signals S1 and S2, and the encoded content of the input digital signal DS includes a plurality of bits (step S810). In the first mode, an output signal is generated by the mixer 132 according to the two signals S1 and S2 converted from the input digital signal DS (step S820). The output power of the output signal OS corresponding to the input digital signal DS with the first encoded content is different from the output power of the output signal OS corresponding to the input digital signal DS with the second encoded content. Moreover, the intensity of the output signal OS is related to the voltage difference between the two signals S1 and S2 converted from the input digital signal DS.

[0072] The implementation details of each step in Fig. 8 are described in the above embodiments and examples, and will not be repeated here. In addition to being implemented in the form of a circuit, the steps and details of the embodiments of the present disclosure may also be implemented by a processor in the form of software, which is not limited by the embodiments of the present disclosure.

[0073] In summary, the signal generation circuit, radar device, and signal control method according to the embodiments of the present disclosure define input digital signals with different encoded contents and generate corresponding output signals with different output powers through a mixer, thereby realizing multi-value and accurate power control. By quickly switching the signals through a digital-to-analog converter, pulse trains and spread spectrum signals can be realized. Furthermore, the voltage difference between the two signals input to the mixer can be controlled to apply lower output power at the turning segment of the carrier signal, thereby preventing the FMCW signal from forming spike peaks at the edge of the frequency band on the frequency spectrum.

[0074] In terms of applications, the embodiments of the present disclosure can realize continuous wave (CW), FMCW, pulse-type CW, or short pulse signals, which can be applied to UWB remote sensing, or can be used for precise ultra-low power control (e.g., less than -15 dBm) for UWB with strict transmission requirements to realize indoor close-range sensors for presence sensing, vital signs monitoring, or liquid level detection, can quickly drop down FMCW signals at the edge of frequency bands on the frequency spectrum, can achieve BPSK high-speed encoding capability for pulse trains, and can be applied to other suitable transmission signals.

[0075] Although the present disclosure has been described above with reference to exemplary embodiments, these embodiments are not intended to limit the present disclosure. Those skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure should be defined by the following claims.

Claims

1. A signal generating circuit, a digital-to-analog converter (DAC) configured to convert, in a first mode, an input digital signal to a first signal and a second signal, the encoded content of the input digital signal comprising a plurality of bits; a mixer coupled to the digital-to-analog converter, the mixer configured in the first mode to receive the first signal and the second signal at two input ports of the mixer, respectively, to generate an output signal, an output power of the output signal corresponding to the input digital signal having a first encoded content being different from an output power of the output signal corresponding to the input digital signal having a second encoded content, and a strength of the output signal being related to a voltage difference between the first signal and the second signal; a frequency synthesizer coupled to the mixer and configured to input a carrier signal to the mixer; Equipped with the frequency of the carrier signal varies with time within a frequency sweep period of the carrier signal; the waveform of the carrier signal comprises a first segment and a second segment in the time domain; the frequency in the first segment increases over time and the frequency in the second segment decreases over time; a turning segment is formed between the first segment and the second segment; the first signal, the second signal and the carrier signal are input to the mixer; A signal generating circuit, wherein an amplitude of the output signal corresponding to the turning segment is different from an amplitude of the output signal corresponding to the first segment and the second segment.

2. 2. The signal generating circuit of claim 1, wherein the number of bits is greater than two and the output signal has more than four different voltages.

3. 2. The signal generation circuit of claim 1, wherein there is a linear relationship between a peak amplitude value of the output signal corresponding to the input digital signal having the first encoded content and a peak amplitude value of the output signal corresponding to the input digital signal having the second encoded content.

4. 4. The signal generation circuit of claim 3, wherein the linear relationship has a slope corresponding to a step that is proportional to an amount of change between the peak amplitude value of the output signal corresponding to the input digital signal having the first encoded content and the peak amplitude value of the output signal corresponding to the input digital signal having the second encoded content, the step being related to the number of bits.

5. The signal generating circuit according to claim 1 , wherein the two input ports are differential input ports.

6. 2. The signal generating circuit of claim 1, wherein a first voltage difference between the first signal and the second signal corresponding to the turning segment is less than a second voltage difference between the first signal and the second signal corresponding to the first segment or the second segment.

7. 2. The signal generating circuit according to claim 1, wherein the output power of the output signal is −15 dBm or less.

8. The signal generation circuit of claim 1 , wherein the mixer is further configured to mix an intermediate frequency signal in a second mode.

9. The signal generating circuit according to claim 1 , wherein the mixer is a double-balanced mixer.

10. A radar device, comprising: A signal generating circuit according to claim 1; a transmission circuit coupled to the signal generation circuit and configured to generate a transmission signal according to the output signal, the transmission signal being transmitted by the radar device; and A radar device comprising:

11. The transmission circuit, an amplifier coupled to the signal generating circuit and configured to amplify an amplitude of the output signal to generate the transmit signal, the transmit signal being further transmitted via an antenna; The radar device according to claim 10 .

12. A signal control method, comprising: converting an input digital signal into a first signal and a second signal in a first mode, the encoded content of the input digital signal comprising a plurality of bits; generating an output signal in the first mode according to the first signal and the second signal via a mixer, wherein an output power of the output signal corresponding to the input digital signal having a first encoded content differs from an output power of the output signal corresponding to the input digital signal having a second encoded content, and a strength of the output signal is related to a voltage difference between the first signal and the second signal; inputting a carrier signal into the mixer, a frequency of the carrier signal varies with time within a frequency sweep period of the carrier signal, a waveform of the carrier signal comprises a first segment and a second segment in the time domain, the frequency in the first segment increases with time and the frequency in the second segment decreases with time, and a turning segment is formed between the first segment and the second segment; inputting the first signal, the second signal, and the carrier signal into the mixer, wherein an amplitude of the output signal corresponding to the turning segment is different from an amplitude of the output signal corresponding to the first segment and the second segment; A signal control method comprising:

13. 13. The signal control method of claim 12, wherein the number of bits is greater than two and the output signal has more than four different voltages.

14. 13. The signal control method of claim 12, wherein there is a linear relationship between the peak amplitude value of the output signal corresponding to the input digital signal having the first encoded content and the peak amplitude value of the output signal corresponding to the input digital signal having the second encoded content.

15. 15. The method of claim 14, wherein the linear relationship has a slope corresponding to a step that is proportional to an amount of change between the peak amplitude value of the output signal corresponding to the input digital signal having the first encoded content and the peak amplitude value of the output signal corresponding to the input digital signal having the second encoded content, the step being related to the number of bits.

16. setting a first voltage difference between the first signal and the second signal corresponding to the turning segment to be smaller than a second voltage difference between the first signal and the second signal corresponding to the first segment or the second segment. The signal control method of claim 12, further comprising:

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