Quantum state measurement logic to facilitate the quantum state measurement back-end process

Abstract

Systems, devices, computer-implemented methods, and computer program products are provided for facilitating quantum state measurement logic used in a quantum state measurement back-end process. According to one embodiment, the system can include a memory that stores computer-executable components and a processor that executes the computer-executable components stored in the memory. The computer-executable components can have a stage control register component that defines data processing functions corresponding to at least one storage element of at least one stage of the quantum state measurement pipeline.

Description

[Technical field]

[0001] The subject disclosure relates to quantum state measurement processes and, more particularly, to quantum state measurement logic that facilitates quantum state measurement back-end processes. [Background technology]

[0002] Some existing quantum state measurement backend technologies define various layers of measurements associated with capturing the quantum state of a quantum bit (qubit). For example, some existing quantum state measurement backend technologies define three layers of measurements of the following qubit states: Level 0 is the raw data, which is a filtered version of the individual samples captured from an analog-to-digital converter (ADC) device. Level 1 decomposes the raw data via a kernel into a pair of complex numbers (e.g., an in-phase (I) vector and a quadrature-phase (Q) vector), and level 2 further decomposes it into a single binary bit via a discriminator.

[0003] Some existing quantum state measurement backend technologies allow an entity (e.g., a user) to specify the level, kernel, and discriminator to apply to each qubit measurement. A problem with such existing quantum state measurement backend technologies is that it is difficult to apply such flexibility to one or more quantum backend computing resources, or to various instances of quantum state measurement logic within a single quantum backend computing resource. Such challenges arise because implementations of various quantum backend computing resources may vary significantly in capture capabilities, the amount of samples that can be captured, and the flexibility in selecting various kernels and discriminators to apply to the data. Furthermore, some existing quantum measurement backend technologies use a compiler to map and schedule the entity's test criteria (e.g., user test criteria) to instances of measurement logic within the quantum backend computing resource. Given the above challenges, a problem with such existing quantum state measurement backend technologies is that a unique compiler implementation is required for each measurement instance. Summary of the Invention

[0004] The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, devices, computer-implemented methods and / or computer program products that facilitate quantum state measurement logic used in a quantum state measurement back-end process are described.

[0005] According to one embodiment, a system may include a memory storing computer-executable components and a processor executing the computer-executable components stored in the memory. The computer-executable components may have stage control register components defining data processing functions corresponding to at least one storage element of at least one stage of a quantum state measurement pipeline. An advantage of such a system is that it may enable a quantum state measurement backend system to more quickly and efficiently identify a greater amount of quantum backend computing resources capable of capturing quantum state measurements based on one or more entity definition criteria.

[0006] In some embodiments, the stage control register component defines a data processing capability based on one or more entity definition criteria corresponding to the quantum state measurement pipeline, and the stage control register component defines a data processing capability corresponding to a storage element of at least one stage of the quantum state measurement pipeline to enable a defined amount of quantum backend computing resources to capture quantum state measurements based on the quantum state measurement logic having the data processing capability. An advantage of such a system is that it can enable the quantum state measurement backend system to more quickly and efficiently identify a larger amount of quantum backend computing resources that can capture quantum state measurements based on the one or more entity definition criteria.

[0007] According to another embodiment, a computer-implemented method may include defining, by a system operatively coupled to a processor, a data processing function corresponding to at least one storage element of at least one stage of a quantum state measurement pipeline. An advantage of such a computer-implemented method is that it may be implemented to enable a quantum state measurement backend system to more quickly and efficiently identify a larger amount of quantum backend computing resources capable of capturing quantum state measurements based on one or more entity definition criteria.

[0008] In some embodiments, the computer-implemented method described above may further comprise: defining, by the system, a data processing function based on one or more entity definition criteria corresponding to the quantum state measurement pipeline; and defining, by the system, a data processing function corresponding to a storage element of at least one stage of the quantum state measurement pipeline to enable a defined amount of quantum backend computing resources to capture quantum state measurements based on the quantum state measurement logic having the data processing function. An advantage of such a computer-implemented method is that it may be implemented to enable a quantum state measurement backend system to more quickly and efficiently identify a larger amount of quantum backend computing resources that can capture quantum state measurements based on the one or more entity definition criteria.

[0009] According to another embodiment, a computer program product is provided for facilitating a quantum state measurement back-end process. The computer program product has a computer-readable storage medium having program instructions embodied therein, the program instructions executable by a processor to cause the processor to define data processing functions corresponding to at least one storage element of at least one stage of a quantum state measurement pipeline. An advantage of such a computer program product is that it can enable a quantum state measurement back-end system to more quickly and efficiently identify a greater amount of quantum back-end computing resources capable of capturing quantum state measurements based on one or more entity definition criteria.

[0010] In some embodiments, the program instructions are further executable by the processor to cause the processor to generate quantum state measurement logic based on data processing functions corresponding to storage elements of at least one stage of the quantum state measurement pipeline, and to identify, based on the quantum state measurement logic, one or more quantum backend computing resources having capabilities to capture quantum state measurements. An advantage of such a computer program product is that it can enable a quantum state measurement backend system to more quickly and efficiently identify a larger quantity of quantum backend computing resources capable of capturing quantum state measurements based on one or more entity definition criteria. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 illustrates a block diagram of an example, non-limiting system that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein.

[0012] [Diagram 2]FIG. 1 illustrates a block diagram of an example, non-limiting system that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein.

[0013] [Diagram 3] FIG. 1 illustrates an exemplary, non-limiting diagram that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein.

[0014] [Figure 4] FIG. 1 illustrates a block diagram of an example, non-limiting system that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein. [Diagram 5] FIG. 1 illustrates a block diagram of an example, non-limiting system that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein. [Figure 6] FIG. 1 illustrates a block diagram of an example, non-limiting system that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein.

[0015] [Figure 7] FIG. 1 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein. [Figure 8] FIG. 1 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein. [Figure 9]FIG. 1 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method that can facilitate quantum state measurement logic used in a quantum state measurement back-end process, according to one or more embodiments described herein.

[0016] [Figure 10] FIG. 1 illustrates a block diagram of an exemplary non-limiting operating environment capable of facilitating one or more embodiments described herein.

[0017] [Figure 11] 1 illustrates a block diagram of an exemplary, non-limiting cloud computing environment, in accordance with one or more embodiments of the present subject disclosure.

[0018] [Figure 12] 1 illustrates a block diagram of example, non-limiting abstraction model layers, in accordance with one or more embodiments of the present subject disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The following detailed description is merely illustrative and is not intended to limit the embodiments and / or the application or uses of the embodiments, nor is it intended to be bound by any express or implied information presented in the preceding "Background" or "Summary" sections or in the "Description of the Preferred Embodiments" section.

[0020] One or more embodiments will now be described with reference to the drawings, in which like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that in various instances, one or more embodiments may be practiced without these specific details.

[0021] Quantum computing generally uses quantum mechanical phenomena for the purposes of performing computing and information processing functions. Quantum computing may be contrasted with classical computing, which generally operates on binary values ​​using transistors. That is, while classical computers can operate on bit values ​​of either 0 or 1, quantum computers operate on quantum bits (qubits) with superpositions of both 0 and 1, and can entangle multiple qubits and use interference.

[0022] Given the above problems with some existing quantum state measurement backend technologies, the present disclosure may be implemented to provide solutions to these problems in the form of a system, computer-implemented method, and / or computer program product that may define data processing functionality corresponding to at least one storage element of at least one stage of a quantum state measurement pipeline. An advantage of such a system, computer-implemented method, and / or computer program product is that the quantum state measurement backend system may be implemented to enable faster and more efficient identification of a greater amount of quantum backend computing resources that may capture quantum state measurements based on one or more entity-defined criteria.

[0023] In some embodiments, the present disclosure may be implemented to provide a solution to the above problem in the form of a system, computer-implemented method and / or computer program product that allows a defined amount of quantum backend computing resources to define data processing capabilities based on one or more entity definition criteria corresponding to a quantum state measurement pipeline and / or to define data processing capabilities corresponding to storage elements of at least one stage of the quantum state measurement pipeline and to capture quantum state measurements based on quantum state measurement logic having data processing capabilities. An advantage of such a system, computer-implemented method and / or computer program product is that the quantum state measurement backend system may be implemented to allow a faster and more efficient identification of a larger amount of quantum backend computing resources that are capable of capturing quantum state measurements based on one or more entity definition criteria.

[0024] It should be understood that when an element is referred to herein as being "coupled" to another element, this can refer to one or more different types of coupling. For example, when an element is referred to herein as being "coupled" to another element, this can refer to one or more different types of coupling, including, but not limited to, a chemical coupling, a communicative coupling, a capacitive coupling, an electrical coupling, an electromagnetic coupling, an inductive coupling, a operative coupling, an optical coupling, a physical coupling, a thermal coupling, and / or another type of coupling.

[0025] As referred to herein, an entity may include a human being, a client, a user, a computing device, a software application, an agent, a machine learning model, an artificial intelligence, and / or another entity, It is to be understood that such an entity may implement one or more embodiments of the subject disclosure described herein.

[0026] 1 illustrates a block diagram of an exemplary, non-limiting system 100 that can facilitate quantum state measurement logic used in a quantum state measurement backend process according to one or more embodiments described herein. The system 100 can include a quantum state measurement logic system 102 that can be associated with a cloud computing environment. For example, the quantum state measurement logic system 102 can be associated with a cloud computing environment 1150 described below with reference to FIG. 11 and / or one or more functional abstraction layers (e.g., hardware and software layer 1260, virtualization layer 1270, management layer 1280, and / or workload layer 1290) described below with reference to FIG.

[0027] The quantum state measurement logic system 102 and / or its components (e.g., stage control register component 108, compiler component 110, etc.) may use one or more computing resources of a cloud computing environment 1150, described below with reference to FIG. 11, and / or one or more functional abstraction layers (e.g., quantum software, etc.), described below with reference to FIG. 12, to perform one or more operations in accordance with one or more embodiments of the present subject disclosure described herein. For example, the cloud computing environment 1150 and / or such one or more functional abstraction layers may have one or more classical computing devices (e.g., classical computers, classical processors, virtual machines, servers, etc.), quantum hardware and / or quantum software (e.g., quantum computing devices, quantum computers, quantum processors, quantum circuit simulation software, superconducting circuits, etc.) that may be used by the quantum state measurement logic system 102 and / or its components to perform one or more operations in accordance with one or more embodiments of the present subject disclosure described herein. For example, the quantum state measurement logic system 102 and / or components thereof may use one or more such classical and / or quantum computing resources to execute one or more classical and / or quantum mathematical functions, mathematical calculations, and / or mathematical equations, computing and / or processing scripts, algorithms, models (e.g., artificial intelligence (AI) models, machine learning (ML) models, etc.), and / or other operations in accordance with one or more embodiments of the subject disclosure described herein.

[0028] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that practice of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0029] Cloud computing is a model of service delivery that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, services) that can be rapidly provisioned and released with minimal administrative effort or interaction with the service provider. The cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0030] Its features are as follows:

[0031] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed, without the need for human interaction with the service provider.

[0032] Broad network access: Capabilities are available over the network and accessed via standard mechanisms that facilitate use by heterogeneous thin- or thick-client platforms (eg, cell phones, laptops, PDAs).

[0033] Resource Pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with various physical and virtual resources dynamically allocated and reallocated according to demand. Consumers generally have no control or knowledge of the exact location of the provided resources, but do have a sense of location independence in that they may be able to specify location at a higher level of abstraction (e.g., country, state, or data center).

[0034] Rapid Elasticity: Capacity can be provisioned rapidly and elastically, in some cases automatically, rapidly scaled out, rapidly released, and rapidly scaled in. To the consumer, the capacity available for provisioning often appears unlimited, and can be purchased in any quantity at any time.

[0035] Measured Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at a level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, active user accounts). Resource usage can be monitored, controlled, and reported to provide transparency to both providers and consumers of the services they utilize.

[0036] The service model is as follows:

[0037] Software as a Service (SaaS): The ability offered to a consumer is to use a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, storage, or even individual application functions, except for limited user-specific application configuration settings.

[0038] Platform as a Service (PaaS): The capability offered to a consumer is to deploy applications that the consumer creates or acquires, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does control the deployed applications and, in some cases, the configuration of the application hosting environment.

[0039] Infrastructure as a Service (IaaS): The ability offered to consumers is to provision processing, storage, network, and other basic computing resources on which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does control the operating systems, storage, deployed applications, and in some cases has limited control over selected network components (e.g., host firewalls).

[0040] The deployment model is as follows:

[0041] Private Cloud: The cloud infrastructure is operated solely for the organization. It is managed by the organization or a third party and can reside on-premise or off-premise.

[0042] Community Cloud: Cloud infrastructure is shared by multiple organizations to support a specific community with shared concerns (e.g., mission, security requirements, policies, compliance considerations). It may be managed by the organization or a third party and may reside on-premise or off-premise.

[0043] Public Cloud: Cloud infrastructure is made available to the general public or large industry entities and is owned by organizations that sell cloud services.

[0044] Hybrid Cloud: A cloud infrastructure is a composition of two or more clouds (private, community, or public) that remain a unique entity but are joined by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0045] Cloud computing environments are service-oriented with an emphasis on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0046] As shown in the exemplary embodiment depicted in FIG. 1, the quantum state measurement logic system 102 may include a memory 104, a processor 106, a stage control register component 108, a compiler component 110, and / or a bus 112.

[0047] It should be understood that the embodiments of the subject disclosure illustrated in the various figures disclosed herein are for illustrative purposes only, and thus the architecture of such embodiments is not limited to the systems, devices and / or components shown therein. For example, in some embodiments, the system 100 and / or quantum state measurement logic system 102 can further include various computer and / or computing-based elements described herein with reference to the operating environment 1000 and FIG. 10. In embodiments, such computer and / or computing-based elements can be used in connection with the implementation of one or more of the systems, devices, components and / or computer-implemented operations shown and described in connection with FIG. 1 and / or other figures disclosed herein.

[0048] Memory 104 may store one or more computer- and / or machine-readable, writeable, and / or executable components and / or instructions that, when executed by processor 106 (e.g., a classical processor, a quantum processor, etc.), can facilitate performance of operations defined by the executable components and / or instructions. For example, memory 104 may store computer- and / or machine-readable, writeable, and / or executable components and / or instructions that, when executed by processor 106, can facilitate performance of various functions described herein in connection with quantum state measurement logic system 102, stage control register component 108, compiler component 110, and / or other components associated with quantum state measurement logic system 102 described herein with or without reference to various figures of the subject disclosure.

[0049] The memory 104 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), etc.) and / or non-volatile memory (e.g., read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), etc.) that may use one or more memory architectures. Further examples of memory 104 are described below with reference to system memory 1016 and FIG. 10. Such examples of memory 104 may be used to implement any embodiment of the subject disclosure.

[0050] The processor 106 may include one or more types of processors and / or electronic circuits (e.g., classical processors, quantum processors, etc.) that may implement one or more computer- and / or machine-readable, writable, and / or executable components and / or instructions that may be stored in the memory 104. For example, the processor 106 may perform various operations that may be specified by such computer- and / or machine-readable, writable, and / or executable components and / or instructions, including, but not limited to, logic, control, input / output (I / O), arithmetic, and / or the like. In some embodiments, the processor 106 may have one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, system-on-a-chip (SOC), array processors, vector processors, quantum processors, and / or another type of processor. Further examples of the processor 106 are described below with reference to the processing unit 1014 and FIG. 10. Such examples of the processor 106 may be used to implement any embodiment of the subject disclosure.

[0051] The quantum state measurement logic system 102, memory 104, processor 106, stage control register component 108, compiler component 110, and / or other components of the quantum state measurement logic system 102 described herein may be communicatively, electrically, operatively, and / or optically coupled to one another via a bus 112 to perform the functions of the system 100, the quantum state measurement logic system 102, and / or any components coupled thereto. The bus 112 may have one or more memory buses, memory controllers, peripheral buses, external buses, local buses, quantum buses, and / or other types of buses that may use a variety of bus architectures. Further examples of the bus 112 are described below with reference to the system bus 1018 and FIG. 10. Such examples of the bus 112 may be used to implement any embodiment of the subject disclosure.

[0052] The quantum state measurement logic system 102 may include any type of component, machine, device, facility, apparatus, and / or equipment having a processor and / or capable of effective and / or operable communication with a wired and / or wireless network. All such embodiments are contemplated. For example, the quantum state measurement logic system 102 may include a server device, a computing device, a general purpose computer, a special purpose computer, a quantum computing device (e.g., a quantum computer), a tablet computing device, a handheld device, a server class computing machine and / or database, a laptop computer, a notebook computer, a desktop computer, a mobile phone, a smartphone, a consumer electronic device and / or equipment, an industrial and / or commercial device, a digital assistant, a multimedia Internet-enabled phone, a multimedia player, and / or another type of device.

[0053] The quantum state measurement logic system 102 may be communicatively coupled (e.g., communicatively, electrically, operatively, optically, etc.) to one or more external systems, sources and / or devices (e.g., classical and / or quantum computing devices, communications devices, etc.) via a data cable (e.g., High-Definition Multimedia Interface (HDMI), Recommended Standard (RS) 232, Ethernet cable, etc.). In some embodiments, the quantum state measurement logic system 102 may be communicatively coupled (e.g., communicatively, electrically, operatively, optically, etc.) to one or more external systems, sources and / or devices (e.g., classical and / or quantum computing devices, communications devices, etc.) via a network.

[0054] In some embodiments, such networks can include wired and wireless networks, including, but not limited to, cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). For example, the quantum state measurement logic system 102 can be connected to, but not limited to, wireless networks, such as Wireless Fidelity (Wi-Fi), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), Third Generation Partnership Project (3GPP) Long Term Evolution (LTE), Third Generation Partnership Project 2 (3GPP2) Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), Zi It may communicate with one or more external systems, sources and / or devices, e.g., computing devices (and vice versa), using virtually any desired wired or wireless technology, including gbee® and other 802.XX wireless technologies and / or legacy telecommunications technologies, BLUETOOTH®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low Power Wireless Area Network), Z-Wave, ANT, Ultra-Wideband (UWB) standard protocols and / or other proprietary and non-proprietary communication protocols.Thus, in such examples, the quantum state measurement logic system 102 may include hardware (e.g., a central processing unit (CPU), transceiver, decoder, quantum hardware, quantum processor, etc.), software (e.g., a set of threads, a set of processes, running software, quantum pulse schedules, quantum circuits, quantum gates, etc.), or a combination of hardware and software that facilitates communication of information between the quantum state measurement logic system 102 and external systems, sources, and / or devices (e.g., computing devices, communications devices, etc.).

[0055] The quantum state measurement logic system 102 may include one or more computer- and / or machine-readable, writeable, and / or executable components and / or instructions that, when executed by the processor 106 (e.g., a classical processor, a quantum processor, etc.), can facilitate performance of operations defined by such components and / or instructions. Additionally, in many embodiments, any component associated with the quantum state measurement logic system 102 described herein with or without reference to the various drawings of the subject disclosure can have one or more computer- and / or machine-readable, writeable, and / or executable components and / or instructions that, when executed by the processor 106, can facilitate performance of operations defined by such components and / or instructions. For example, the stage control register component 108, the compiler component 110, and / or any other components associated with (e.g., communicatively, electronically, operatively, and / or optically coupled to and / or used with) the quantum state measurement logic system 102 disclosed herein may have such computer and / or machine readable, writeable, and / or executable components and / or instructions. As a result, according to many embodiments, the quantum state measurement logic system 102 and / or any components associated therewith may use the processor 106 to execute such computer and / or machine readable, writeable, and / or executable components and / or instructions to facilitate the performance of one or more operations described herein with reference to the quantum state measurement logic system 102 and / or any such components associated therewith, as disclosed herein.

[0056] The quantum state measurement logic system 102 may facilitate (e.g., via the processor 106) the execution of operations performed by and / or associated with one or more of its components (e.g., stage control register component 108, compiler component 110, etc.). For example, the quantum state measurement logic system 102 may facilitate (e.g., via the processor 106) defining data processing functions that correspond to at least one storage element in at least one stage of the quantum state measurement pipeline.

[0057] In another example, as described in more detail below, the quantum state measurement logic system 102 may further facilitate generating quantum state measurement logic based on data processing functions corresponding to storage elements of at least one stage of the quantum state measurement pipeline (e.g., via the processor 106); identifying one or more quantum backend computing resources having capability to capture quantum state measurements based on the quantum state measurement logic; defining the data processing functions based on one or more entity definition criteria corresponding to the quantum state measurement pipeline; defining the data processing functions corresponding to the storage elements of the at least one stage of the quantum state measurement pipeline to enable a defined amount of the quantum backend computing resources to capture quantum state measurements based on the quantum state measurement logic having the data processing functions; and / or generating the quantum state measurement logic based on the first set of data processing functions or the second set of data processing functions, where the first set of data processing functions includes a reuse function corresponding to a single storage element of a bit stage of the quantum state measurement pipeline and the second set of data processing functions includes an archive function corresponding to all storage elements of the bit stage, thereby facilitating a reduction in computational costs associated with one or more quantum backend computing resources that capture quantum state measurements based on the quantum state measurement logic. In the above examples, the data processing function may have an archive function indicating saving a current quantum measurement result or a reuse function indicating overlapping a current quantum measurement result with a subsequent quantum measurement result, and / or the at least one stage may include a capture array stage, a kernel stage, a vector-to-value stage, a discriminator stage, and / or a bit stage.

[0058] The stage control register component 108 can define a data processing function corresponding to at least one storage element of at least one stage of the quantum state measurement pipeline. For example, the stage control register component 108 can define a data processing function that can include, but is not limited to, an archive function indicating to save a current quantum measurement result, a reuse function indicating to overlap a current quantum measurement result with a subsequent quantum measurement result, and / or another data processing function. The stage control register component 108 can define such a data processing function corresponding to at least one storage element of at least one stage of the quantum state measurement pipeline, such at least one stage can include, but is not limited to, a capture array stage, a kernel stage, a vector-to-value stage, a discriminator stage, a bit stage, and / or another stage of the quantum state measurement pipeline.

[0059] To define a data processing function corresponding to at least one storage element in at least one stage of the quantum state measurement pipeline, the stage control register component 108 can generate one or more stage control registers, each of which can correspond to a particular stage of the quantum state measurement pipeline. In various embodiments, each of such one or more stage control registers can have at least one data processing function corresponding to at least one storage element of such particular stage of the quantum state measurement pipeline. As noted above, it should be understood that the generation by the stage control register component 108 of such one or more stage control registers can be configured to define a data processing function corresponding to at least one storage element of at least one stage of the quantum state measurement pipeline.

[0060] In some embodiments, the stage control register component 108 can define a plurality of data processing functions corresponding respectively to a plurality of storage elements of at least one stage of the quantum state measurement pipeline. For example, the stage control register component 108 can generate a plurality of stage control registers corresponding respectively to a plurality of stages of the quantum state measurement pipeline. In this example, each such stage control register can include a plurality of storage elements, and at least two of such a plurality of storage elements can have a data processing function associated therewith.

[0061] In the above example, it should be understood that the stage control register component 108 can define a plurality of data processing functions, each corresponding to a plurality of storage elements of at least one stage of the quantum state measurement pipeline, to enable a defined amount of quantum backend computing resources to capture quantum state measurements based on the quantum state measurement logic having the data processing functions. For example, it should be understood that the stage control register component 108 can define a plurality of data processing functions, each corresponding to a plurality of storage elements of at least one stage of the quantum state measurement pipeline, to enable a larger amount of quantum backend computing resources (e.g., a larger amount compared to a certain amount of quantum backend computing resources having data processing functions that can capture quantum state measurements without using such quantum state measurement logic) to capture quantum state measurements based on the quantum state measurement logic having the data processing functions.

[0062] The stage control register component 108 can define data processing functions based on one or more entity-defined criteria corresponding to the quantum state measurement pipeline. For example, although not shown in the figures, in some embodiments, the quantum state measurement logic system 102 can have an interface component (e.g., a graphical user interface (GUI), an application programming interface (API), etc.) that the entities defined herein can use to input one or more criteria corresponding to the quantum state measurement pipeline. For example, such an entity may use such interface components of the quantum state measurement logic system 102 to define the number of storage elements in each stage of the quantum state measurement pipeline, to define a particular kernel used in a kernel stage of the quantum state measurement pipeline, to define a particular discriminator used in a discriminator stage of the quantum state measurement pipeline, to define one or more types of data processing functions (e.g., archive functions, reuse functions, etc.) that may be defined for one or more storage elements in at least one stage of the quantum state measurement pipeline, to define a particular data processing function (e.g., archive functions, reuse functions, etc.) for one or more storage elements in at least one stage of the quantum state measurement pipeline, to define one or more memory slots for storing one or more binary values ​​output by the quantum state measurement pipeline, and / or to define another criterion corresponding to the quantum state measurement pipeline. In this example, the stage control register component 108 may generate one or more of the above stage control registers based on such one or more entity-defined criteria, and each of such one or more stage control registers may correspond to a particular stage of the quantum state measurement pipeline.

[0063] The compiler component 110 can generate the quantum state measurement logic based on data processing functions corresponding to storage elements of at least one stage of the quantum state measurement pipeline. For example, the compiler component 110 can generate the quantum state measurement logic based on (e.g., using) data processing functions that can be defined by the stage control register component 108 as described above, where such data processing functions correspond to storage elements of at least one stage of the quantum state measurement pipeline. For example, the compiler component 110 can generate the quantum state measurement logic having one or more stage control registers as described above that can be generated by the stage control register component 108, where each state control register can correspond to a particular stage of the quantum state measurement pipeline, and where each state control register can have at least one data processing function corresponding to at least one storage element of the stage.

[0064] Compiler component 110 can identify one or more quantum backend computing resources that have the capability to capture quantum state measurements based on the quantum state measurement logic described above, which can be generated by compiler component 110. For example, compiler component 110 can identify one or more quantum backend computing resources that have the capability to capture quantum state measurements based on (e.g., using) a data processing function that can be defined by stage control register component 108 as described above, based on (e.g., using) a quantum state measurement logic that can be generated by compiler component 110. In various embodiments, such one or more quantum backend computing resources can include, but are not limited to, quantum-based software, quantum hardware (e.g., quantum processors, superconducting circuits, etc.), quantum devices (e.g., quantum computers, etc.), and / or another quantum backend computing resource. In these embodiments, such one or more quantum backend computing resources can capture quantum state measurements of one or more qubits based on (e.g., using) a quantum state measurement logic that can be generated by compiler component 110 as described above.

[0065] In one embodiment, the compiler component 110 may generate quantum state measurement logic based on a first set of data processing functions or a second set of data processing functions. In this embodiment, the first set of data processing functions has a reuse function corresponding to a single storage element of a bit stage of the quantum state measurement pipeline, and the second set of data processing functions has an archive function corresponding to all storage elements of such bit stage. In this embodiment, the stage control register component 108 may define such a first set of data processing functions and / or such a second set of data processing functions, as described above. It should be appreciated that the generation of such quantum state measurement logic based on (e.g., using) the first set of data processing functions or the second set of data processing functions described above may thereby facilitate a reduction in computational costs associated with one or more quantum backend computing resources that capture quantum state measurements based on the quantum state measurement logic.

[0066] 2 illustrates a block diagram of an exemplary, non-limiting system 200 that can facilitate quantum state measurement logic used in a quantum state measurement back-end process according to one or more embodiments described herein. Repeated descriptions of similar elements and / or processes used in each embodiment are omitted for brevity.

[0067] System 200 may comprise an architecture of a quantum state measurement back-end system that can facilitate a back-end process of capturing the quantum state of one or more qubits. In some embodiments, system 200 may comprise an acquisition channel within the quantum state measurement back-end system that can facilitate a back-end process of capturing the quantum state of one or more qubits.

[0068] The system 200 may include a quantum state measurement pipeline 202. The quantum state measurement pipeline 202 may include a capture array stage 206, a kernel stage 208, a vector-to-value stage 210, a discriminator stage 212, and / or a bit stage 214. As shown in the exemplary embodiment illustrated in FIG. 2, the capture array stage 206 may include a capture array storage element 206a, the kernel stage 208 may include a kernel instance 208a, the vector-to-value stage 210 may include a vector-to-value storage element 210a, the discriminator stage 212 may include a discriminator instance 212a, and / or the bit stage 214 may include a bit storage element 214a.

[0069] System 200 may further comprise a filter 204 that may receive raw data (e.g., voltage values) output by an analog-to-digital converter (ADC), which may have an intermediate frequency (IF) that may be filtered out by filter 204 to generate “level 0” data samples (referred to herein and shown in FIG. 2 as “L0 samples”) that may have complex values ​​represented by (real, imaginary) paired numbers (shown in FIG. 2 as “(re,im)”). In various embodiments, the L0 samples output by filter 204 may be input to quantum state measurement pipeline 202 (e.g., input to capture array stage 206 and / or capture array storage elements 206a) for further processing by various stages of quantum state measurement pipeline 202, as described below.

[0070] It should be understood that while each stage of the quantum state measurement pipeline 202 shown in the exemplary embodiment illustrated in FIG. 2 has only a single component (e.g., a single capture array storage element 206a, a single kernel instance 208a, a single vector-to-value storage element 210a, a single discriminator instance 212a, and a single bit storage element 214a), the subject disclosure is not so limited. For example, as described below with reference to FIGS. 4 and 5, each stage of the quantum state measurement pipeline 202 can have multiple such components (e.g., multiple capture array storage elements, multiple kernel instances, multiple vector-to-value storage elements, multiple discriminator instances, and multiple bit storage elements). The exemplary embodiment illustrated in FIG. 2 illustrates how a first storage element and / or a first instance of each stage of the quantum state measurement pipeline 202 can be automatically selected by the quantum state measurement logic system 102 to store and / or process initial measurement data captured at the start of a qubit measurement. The exemplary embodiments described below and illustrated in Figures 4 and 5 show how subsequent storage elements and / or subsequent instances of each stage of the quantum state measurement pipeline 202 can be used by the quantum state measurement logic system 102 to store and / or process subsequent measurement data captured from one or more qubits.

[0071] As shown in the exemplary embodiment depicted in FIG. 2, at the beginning of a measurement of a qubit, an initial L0 sample output by the filter 204 can be provided to the capture array stage 206 and / or loaded into the capture array storage element 206a. In various embodiments, such L0 samples can have complex values ​​that describe the envelope of the signal coming from the qubit during the measurement. In these embodiments, the L0 sample values ​​may not be raw voltage values ​​from the ADC, since data at this level may still contain intermediate frequencies. Thus, in these embodiments, the filter 204 can remove any intermediate frequencies, as described above, after which each data sample becomes a complex number represented by a (real, imaginary) pair of numbers. While being filtered, in these embodiments, the complex numbers are still data samples taken at a moment in time. In some embodiments, a series of data samples can be used to describe the returned waveform, with the attribute "dtm" defining the time elapsed between the data samples.

[0072] In the exemplary embodiment shown in FIG. 2, the kernel instance 208a of the kernel stage 208 may have a model, algorithm, and / or mathematical function that can convert the L0 samples stored in the capture array storage element 206a into two complex numbers, called “IQ pairs” and referred to herein as “Level 1” data samples and / or “L1 samples” (shown in FIG. 2 as “L1 IQ pairs”). In this exemplary embodiment, such L1 samples may be stored in the vector pair value storage element 210a, as shown in FIG. 2. In various embodiments, passing the L0 samples through the kernel instance 208a of the kernel stage 208 may reduce the waveform to two values, an in-phase (I) value and a quadrature-phase (Q) value, which together may comprise the L1 sample. In these embodiments, the L1 sample may represent a weighted sum of the L0 samples. In some embodiments, the kernel stage 208 may have different kernels, each capable of producing different weights, but the end goal is to convert the L0 samples to a weighted sum of the L0 samples, such that the qubits are in a quantum state.

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[0073] As shown in the exemplary embodiment depicted in FIG. 2, the L1 samples, which may be stored in the vector pair value storage element 210a, may be provided to a discriminator instance 212a of the discriminator stage 212. In various embodiments, the discriminator instance 212a may include models, algorithms, and / or mathematical functions that may reduce the L1 samples (e.g., I and Q values) of a qubit measurement to a single binary value of 0 or 1, referred to herein as “Level 2” data samples and / or “L2 samples” (shown as “L2 bits” in FIG. 2). In these embodiments, such an L2 sample (e.g., a binary value of 0 or 1) may be the most condensed form of a measurement result. In these embodiments, the L2 sample may be a single bit, which may be distributed, combined with other L2 samples, and / or reduced to a single testable binary state.

[0074] The system 200 may further comprise one or more memory slots 216 (depicted in FIG. 2 as “memory_slot”) that may correspond to one or more qubits to be measured, or to a particular qubit to be measured multiple times (e.g., in a test performed by an entity defined herein that implements the quantum state measurement logic system 102 to perform the test). In the exemplary embodiment shown in FIG. 2, each memory slot 216 may be used by the quantum state measurement logic system 102 to provide measurement data of a particular qubit output by the quantum state measurement pipeline 202 to an entity defined herein that may implement the quantum state measurement logic system 102. As shown in the exemplary embodiment shown in FIG. 2, a particular memory slot 216, depicted in FIG. 2 as “2”, may be used by the quantum state measurement logic system 102 to provide an L2 sample value (e.g., an L2 bit value of 0 or 1) to an entity defined herein that may implement the quantum state measurement logic system 102 that may be stored in the bit storage element 214a. In some embodiments, such one or more memory slots 216 may be defined by such an entity that may implement the quantum state measurement logic system 102. For example, such an entity may use an interface component of the quantum state measurement logic system 102 (e.g., a GUI, an API, etc.) to designate a particular memory slot 216 for storing an L2 sample value (e.g., a binary value) output by the quantum state measurement pipeline 202 (e.g., output by a bit storage element 214a of a bit stage 214 of the quantum state measurement pipeline 202).

[0075] 2 may be used by the quantum state measurement logic system 102 to provide L0 samples, L1 samples and / or L2 samples to entities defined herein that may implement the quantum state measurement logic system 102. An exemplary embodiment described below and illustrated in FIG. 3 illustrates how such different types of data (e.g., L0, L1 and / or L2 samples) may be stored in one or more memory slots 216.

[0076] 3 illustrates an exemplary, non-limiting diagram 300 that can facilitate quantum state measurement logic used in a quantum state measurement back-end process according to one or more embodiments described herein. Repetitive descriptions of similar elements and / or processes used in each embodiment are omitted for brevity.

[0077] Diagram 300 may have a memory layout corresponding to the L0, L1 and / or L2 samples described above, illustrating how such different types of data may be stored in one or more memory slots 216 and / or provided to an entity defined herein that may implement the quantum state measurement logic system 102. Currently, the quantum backend hardware of existing quantum state measurement backend systems does not store measurement data between experiments, but the host may store measurement data between experiments and provide such data to an entity that implements such a system. Diagram 300 shown in the exemplary embodiment illustrated in FIG. 3 illustrates how the quantum state measurement logic system 102 may store and / or provide such information via one or more memory slots 216 to an entity defined herein that may implement the quantum state measurement logic system 102. In this exemplary embodiment, diagram 300 further illustrates how the L0, L1 and / or L2 sample information may be presented (e.g., as real and imaginary floating point values, as binary values, etc.) to such an entity that may implement the quantum state measurement logic system 102.

[0078] In the exemplary embodiment shown in FIG. 3, four measurements (denoted as “[0]”, “[1]”, “[2]”, and “[3]” in FIG. 3) may be performed by one or more quantum backend computing resources to capture three L0 samples (denoted as “sample 1”, “sample 2”, and “sample 3” in FIG. 3). In this exemplary embodiment, each L0 sample captured in each measurement may have real and imaginary values ​​that may be represented as floating-point values, as shown in FIG. 3. In this exemplary embodiment, the attribute “dtm” defines the elapsed time between data samples (e.g., the elapsed time between sample 1 and sample 2, and the elapsed time between sample 2 and sample 3). In this exemplary embodiment, the L0 samples captured in each of the four measurements may be averaged (e.g., using a weighted average method) by kernel instance 208a of kernel stage 208, for example, as described above with reference to FIG. 1, to generate a corresponding L1 sample for each of the four measurements. In this exemplary embodiment, the L1 samples may also have real and imaginary values ​​that may be represented as floating-point values, as shown in FIG. 3. In this exemplary embodiment, the L1 samples of each of the four measurements may be reduced by discriminator instance 212a of discriminator stage 212, for example, as described above with reference to FIG. 1, to generate a binary value of 0 or 1 (shown as “Qvalue” and “Binary” in FIG. 3).

[0079] 4 illustrates a block diagram of an exemplary, non-limiting system 400 that can facilitate quantum state measurement logic used in a quantum state measurement back-end process according to one or more embodiments described herein. Repetitive descriptions of similar elements and / or processes used in each embodiment are omitted for brevity.

[0080] The system 400 may include an exemplary, non-limiting alternative embodiment of the system 200 described above with reference to Figure 2. As shown in the exemplary embodiment depicted in Figure 4, the capture array stage 206, the vector-to-value stage 210, and / or the bit stage 214 may each have multiple storage elements that may be used in combination with the kernel instance 208a and the discriminator instance 212a to create multiple quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f. 4, the capture array stage 206 may have capture array storage elements 206a, 206b, 206c, the vector-to-value stage 210 may have vector-to-value storage elements 210a, 210b, 210c, 210d, 210e, 210f, and / or the bit stage 214 may have bit storage elements 214a, 214b, 214c, 214d, 214e, 214f. In this exemplary embodiment, the quantum state measurement pipeline 402a may have the same structure and / or functionality as the quantum state measurement pipeline 202 described above with reference to FIG.

[0081] In the exemplary embodiment shown in FIG. 4, the quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f can be generated by the quantum state measurement logic system 102 using the stage control register component 108. For example, in this exemplary embodiment, the stage control register component 108 can generate a number of stage control registers (e.g., five) corresponding to the capture array stage 206, the kernel stage 208, the vector-to-value stage 210, the discriminator stage 212, and the bit stage 214, respectively. In this exemplary embodiment, as described in more detail below, the stage control register component 108 can generate such stage control registers to respectively define data processing functions corresponding to at least one instance or storage element in each of such stages. For example, the stage control register component 108 can generate such stage control registers to respectively define archive functions or reuse functions corresponding to at least one instance or storage element in each of such stages. In this example, such an archive function can indicate saving the current quantum measurement result, and such a reuse function can indicate overlapping the current quantum measurement result with a subsequent quantum measurement result. For example, at the beginning of an experiment, the first instance or first storage element of each stage can be used by default to process or store the quantum state measurement data. In this exemplary embodiment, as each measurement is made, a bit in each stage control register generated by the stage control register component 108 can determine whether to switch to the next instance or storage element of the stage after the measurement is completed, or to reuse the current instance or storage element (e.g., use the current instance or storage element to process or store subsequent quantum state measurement data captured in a subsequent measurement).

[0082] 4, the stage control register component 108 can generate stage control registers for the capture array stage 206 such that the capture array storage element 206a is used to store the first L0 sample and is reused to store the second L0 sample, the capture array storage element 206b archives the third L0 sample, and the capture array storage element 206c is used to store the fourth L0 sample and is reused to store the fifth and sixth L0 samples. In this exemplary embodiment, the stage control register component 108 can generate stage control registers for the kernel stage 208 such that the kernel instance 208a is used to convert the first L0 sample to the first L1 sample and is reused to convert the second, third, fourth, fifth, and sixth L0 samples to the second, third, fourth, fifth, and sixth L1 samples, respectively. In this exemplary embodiment, the stage control register component 108 may generate stage control registers for the vector-to-value stage 210 such that the vector-to-value storage elements 210a, 210b, 210c, 210d, 210e, 210f archive the first, second, third, fourth, fifth, and sixth L1 samples, respectively. In this exemplary embodiment, the stage control register component 108 may generate stage control registers for the discriminator stage 212 such that the discriminator instance 212a is used to reduce the first L1 sample to the first L2 sample and is reused to reduce the second, third, fourth, fifth, and sixth L1 samples to the second, third, fourth, fifth, and sixth L2 samples, respectively. In this exemplary embodiment, the stage control register component 108 can generate the stage control register for the bit stage 214 such that bit storage element 214a archives the first L2 sample, bit storage element 214b is used to store the second L2 sample and is reused to store the third L2 sample, and bit storage elements 214c, 214d, 214e archive the fourth, fifth, and sixth L2 samples, respectively.As shown in the exemplary embodiment depicted in FIG. 4, each of the first, second, third, fourth, fifth, and sixth L2 samples may be provided via one or more memory slots 216 to an entity defined herein that may implement the quantum state measurement logic system 102.

[0083] In the exemplary embodiment shown in Figure 4, by generating the above-mentioned stage control registers for each stage of the quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f, the quantum state measurement logic system 102 and / or the stage control register component 108 can thereby generate such quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f. Additionally or alternatively, in this exemplary embodiment, based on such generation of the above-mentioned stage control registers for each stage of the quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f, the compiler component 110 can generate the quantum state measurement logic 404 shown in Figure 4. In some embodiments, the compiler component 110 can identify one or more quantum backend computing resources that have the capability to capture quantum state measurements based on (e.g., using) the quantum state measurement logic 404.

[0084] 5 illustrates a block diagram of an exemplary, non-limiting system 500 that can facilitate quantum state measurement logic used in a quantum state measurement back-end process according to one or more embodiments described herein. Repetitive descriptions of similar elements and / or processes used in each embodiment are omitted for brevity.

[0085] The system 500 may include an exemplary, non-limiting alternative embodiment of the system 400 described above with reference to Figure 4. As shown in the exemplary embodiment depicted in Figure 5, the capture array stage 206, the kernel stage 208, the vector-to-value stage 210, the discriminator stage 212, and / or the bit stage 214 may each have multiple instances and / or storage elements that can be used to create multiple quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f. 5, the capture array stage 206 may have capture array storage elements 206a, 206b, 206c, the kernel stage 208 may have kernel instances 208a, 208b, 208c, the vector-to-value stage 210 may have vector-to-value storage elements 210a, 210b, 210c, 210d, 210e, 210f, the discriminator stage 212 may have discriminator instances 212a, 212b, 212c, and / or the bit stage 214 may have bit storage elements 214a, 214b, 214c, 214d, 214e, 214f. In this exemplary embodiment, the quantum state measurement pipeline 502a may have the same structure and / or functionality as the quantum state measurement pipeline 402a described above with reference to FIG.

[0086] In the exemplary embodiment shown in FIG. 5, the quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f can be generated by the quantum state measurement logic system 102 using the stage control register component 108. For example, in this exemplary embodiment, the stage control register component 108 can generate a number of stage control registers (e.g., five) corresponding to the capture array stage 206, the kernel stage 208, the vector-to-value stage 210, the discriminator stage 212, and the bit stage 214, respectively. In this exemplary embodiment, as described in more detail below, the stage control register component 108 can generate such stage control registers to respectively define data processing functions corresponding to at least one instance or storage element in each of such stages. For example, the stage control register component 108 can generate such stage control registers to respectively define archive functions or reuse functions corresponding to at least one instance or storage element in each of such stages. In this example, such an archive function can indicate saving the current quantum measurement result, and such a reuse function can indicate overlapping the current quantum measurement result with a subsequent quantum measurement result. For example, at the beginning of an experiment, the first instance or first storage element of each stage can be used by default to process or store the quantum state measurement data. In this exemplary embodiment, as each measurement is made, a bit in each stage control register generated by the stage control register component 108 can determine whether to switch to the next instance or storage element of the stage after the measurement is completed, or to reuse the current instance or storage element (e.g., use the current instance or storage element to process or store subsequent quantum state measurement data captured in a subsequent measurement).

[0087] As shown in the exemplary embodiment depicted in FIG. 5, the stage control register component 108 can generate stage control registers for the capture array stage 206 such that the capture array storage element 206a is used to store a first L0 sample and is reused to store a second L0 sample, the capture array storage element 206b archives a third L0 sample, and the capture array storage element 206c is used to store a fourth L0 sample and is reused to store a fifth and sixth L0 sample. In this exemplary embodiment, the stage control register component 108 may generate stage control registers for the kernel stage 208 such that kernel instance 208a is used to convert a first L0 sample to a first L1 sample, kernel instance 208b is used to convert a second L0 sample to a second L1 sample and is reused to convert a third L0 sample to a third L1 sample, kernel instance 208c is used to convert a fourth L0 sample to a fourth L1 sample and is reused to convert a fifth and sixth L0 sample to a fifth and sixth L1 sample, respectively. In this exemplary embodiment, the stage control register component 108 may be capable of generating stage control registers for the vector-to-value stage 210 such that vector-to-value storage elements 210a, 210b, 210c, 210d, 210e, 210f archive the first, second, third, fourth, fifth, and sixth L1 samples, respectively.In this exemplary embodiment, the stage control register component 108 can generate stage control registers for the discriminator stage 212 such that the discriminator instance 212a is used to reduce the first L1 sample to a first L2 sample and is reused to reduce the second and third L1 samples to a second and third L2 sample, respectively; and the discriminator instance 212b is used to reduce the fourth L1 sample to a fourth L2 sample and is reused to reduce the fifth and sixth L1 samples to a fifth and sixth L2 sample, respectively. In this exemplary embodiment, the stage control register component 108 may generate the stage control registers of the bit stage 214 such that the bit storage element 214a archives the first L2 sample, the bit storage element 214b is used to store the second L2 sample and is reused to store the third L2 sample, and the bit storage elements 214c, 214d, 214e archive the fourth, fifth, and sixth L2 samples, respectively. As shown in the exemplary embodiment illustrated in FIG. 5, each of the first, second, third, fourth, fifth, and sixth L2 samples may be provided via one or more memory slots 216 to an entity as defined herein that may implement the quantum state measurement logic system 102.

[0088] In the exemplary embodiment shown in Figure 5, by generating the above-mentioned stage control registers for each stage of the quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f, the quantum state measurement logic system 102 and / or the stage control register component 108 can thereby generate such quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f. Additionally or alternatively, in this exemplary embodiment, based on such generation of the above-mentioned stage control registers for each stage of the quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f, the compiler component 110 can generate the quantum state measurement logic 504 shown in Figure 5. In some embodiments, the compiler component 110 can identify one or more quantum backend computing resources that have the capability to capture quantum state measurements based on (e.g., using) the quantum state measurement logic 504.

[0089] 6 illustrates a block diagram of an exemplary, non-limiting system 600 that can facilitate quantum state measurement logic used in a quantum state measurement back-end process according to one or more embodiments described herein. Repetitive descriptions of similar elements and / or processes used in each embodiment are omitted for brevity.

[0090] The system 600 shown in the exemplary embodiment shown in FIG. 6 illustrates logic from a conceptual point of view that may exist between any two of the above-mentioned stages of the quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f and / or the quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f, such two stages being shown in FIG. 6 as “Stage N” and “Stage N+1”. It should be appreciated that by dynamically changing the stage instances and / or storage elements using the above-mentioned stage control registers that may be generated by the stage control register component 108 in the exemplary embodiment described above with reference to FIG. 4 and FIG. 5, the quantum state measurement logic system 102, the system 400 and / or the system 500 may effectively use a selection mechanism between stages to change which instances and / or storage elements are active and may use it as input to the next stage. In the exemplary embodiment shown in FIG. 6, the system 600 may represent such a selection mechanism. The exemplary embodiment shown in FIG. 6 illustrates how system 600 operates the above-mentioned selection mechanisms and stage control registers to precisely define the bounds used to describe the latency through each of the above-mentioned pipelines (e.g., quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f and quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f).

[0091] As described in more detail below, bits of each of the above-mentioned stage control registers, which may be generated by the stage control register component 108, are used to control the above-mentioned selection mechanism, which is represented as system 600 in the exemplary embodiment shown in FIG. 6. As described above with reference to the exemplary embodiments shown in FIGS. 2, 4, and 5, instance 0 and / or storage element 0 of each stage, and bit 0 of the corresponding stage control register generated by the stage control register component 108, may be set as the active entity at the start of each experiment. In these exemplary embodiments and the exemplary embodiment shown in FIG. 6, when an end of measurement (EOM) indication is received by the system 600, different bits may be selected from the stage control register 602 corresponding to a particular stage (denoted as "Stage N SCR Register" in FIG. 6), which may be generated by the stage control register component 108 as described above. In these exemplary embodiments, the selected bit, the EOM, and knowledge of when the active instance and / or active storage element has completed processing the current measurement are used (e.g., by quantum state measurement logic system 102, stage control register component 108, compiler component 110, system 600, stage control register 602 of system 600, and / or selection multiplexer 604) to determine whether to change the active instance and / or active storage element to the next one. Note that in these embodiments, changing the active instance and / or active storage element also changes which one serves as the source of the input for the next stage.

[0092] The exemplary embodiment shown in FIG. 6 also shows where boundaries exist for describing the latency through the above pipeline stages. For example, in this exemplary embodiment, such boundaries for describing the latency are defined to be the starting point of each stage instance. In this exemplary embodiment, using this definition, the delay due to the selection mechanism represented as the system 600 in FIG. 6 can be included in the latency of the driving stage instance, rather than being part of the latency of the next stage. In this exemplary embodiment, such a rule works well because the description of the latency of the first stage (e.g., capture array stage 206) begins after filtering is completed, and the output of the final stage (e.g., L2 samples from active bit storage elements 214a, 214b, 214c, 214d, 214e, or 214f) ends after the selection multiplexer 604 shown in FIG. 6.

[0093] The quantum state measurement logic system 102 can be associated with various technologies, for example, the quantum state measurement logic system 102 can be associated with quantum computing technologies, quantum hardware and / or software technologies, quantum algorithm technologies, quantum simulation technologies, quantum operator sampling technologies, quantum backend computing technologies, quantum state measurement backend technologies, machine learning technologies, artificial intelligence technologies, cloud computing technologies, and / or other technologies.

[0094] The quantum state measurement logic system 102 may provide technical improvements to systems, devices, components, operational steps and / or processing steps associated with the various technologies identified above. For example, the quantum state measurement logic system 102 may define a data processing function corresponding to at least one storage element in at least one stage of the quantum state measurement pipeline. In this example, the quantum state measurement logic system 102 may further define the data processing function based on one or more entity definition criteria corresponding to the quantum state measurement pipeline, and define the data processing function corresponding to the storage element of the at least one stage of the quantum state measurement pipeline to enable a defined amount of quantum backend computing resources to capture quantum state measurements based on the quantum state measurement logic having the data processing function.

[0095] In the above example, by defining one or more data processing functions based on one or more entity definition criteria, quantum state measurement logic system 102 may improve quantum state measurement backend systems and / or processes by enabling a compiler associated with such systems and / or processes to more quickly and more efficiently identify a greater amount of quantum backend computing resources capable of capturing quantum state measurements, since such resources need only support such one or more entity definition criteria. For example, in an embodiment in which an entity defined herein that implements quantum state measurement logic system 102 desires to archive only the L0 samples described above, compiler component 110 may more quickly and / or more efficiently identify a greater amount of quantum backend computing resources capable of capturing quantum state measurements, such that such resources may only be able to facilitate such archiving of only the L0 samples (e.g., as opposed to being able to facilitate archiving of the L0, L1, and L2 samples described above). In another example, in embodiments in which such an entity desires to use a particular kernel instance or a particular discriminator instance, the compiler component 110 may more quickly and / or more efficiently identify a greater amount of quantum backend computing resources that can support such a particular kernel instance or such a particular discriminator instance (e.g., as opposed to being able to support different types of kernel instances or different types of discriminator instances).

[0096] The quantum state measurement logic system 102 may provide technical improvements to a processing unit (e.g., processor 106, etc.) associated with the quantum state measurement logic system 102. For example, by enabling the compiler (e.g., compiler component 110) described above to more quickly and / or more efficiently identify a greater amount of quantum back-end computing resources that only need to support one or more particular entity definition criteria, the quantum state measurement logic system 102 may thereby reduce the number of processing cycles performed by a processing unit (e.g., processor 106) in executing such compiler's software (e.g., instructions, commands, processing threads, etc.) in performing the resource identification process described above. In this example, by reducing the number of processing cycles performed by such a processing unit (e.g., processor 106), the quantum state measurement logic system 102 may thereby facilitate improved performance, improved efficiency, and / or reduced computational costs associated with such a processing unit (e.g., processor 106).

[0097] A practical application of the quantum state measurement logic system 102 is that it can be implemented in a quantum state measurement backend system and / or process to capture quantum state measurements from one or more qubits that can be used to compute (e.g., heuristics, etc.) one or more solutions to a variety of problems (e.g., estimation problems, optimization problems, etc.) spanning the complexity of a variety of fields (e.g., finance, chemistry, medicine, etc.). For example, a practical application of the quantum state measurement logic system 102 is that it can be implemented in a quantum state measurement backend system and / or process to capture quantum state measurements from one or more qubits that can be used to compute (e.g., heuristics, etc.) one or more solutions to optimization problems in the fields of chemistry, medicine, and / or finance, such solutions can be used, for example, to design new chemical compounds, new drugs, and / or new option premiums.

[0098] It should be appreciated that the quantum state measurement logic system 102 provides new approaches conceived by the relatively new quantum computing technology, for example, the quantum state measurement logic system 102 provides new approaches for identifying larger amounts of quantum backend computing resources capable of capturing quantum state measurement data based on one or more specific entity-defining criteria.

[0099] The quantum state measurement logic system 102 may use hardware or software to solve problems that are highly technical in nature, not abstract, and that a human cannot perform as a series of mental actions. In some embodiments, one or more of the processes described herein may be executed by one or more dedicated computers (e.g., dedicated processing units, dedicated classical computers, dedicated quantum computers, etc.) to perform defined tasks associated with the various technologies identified above. The quantum state measurement logic system 102 and / or its components may be used to solve new problems that arise due to advances in the technologies discussed above, quantum computing systems, cloud computing systems, computer architectures, and / or the use of other technologies.

[0100] It should be understood that the quantum state measurement logic system 102, as described herein, may utilize various combinations of electrical components, mechanical components, and circuitry that cannot be replicated in or performed by human thought, as various operations that may be performed by the quantum state measurement logic system 102 and / or its components are operations that are beyond the capabilities of human thought. For example, the amount of data processed by the quantum state measurement logic system 102 over a period of time, the speed at which such data is processed, or the types of data processed may be greater, faster, or of different data types than the human mind can process over the same period of time.

[0101] According to various embodiments, the quantum state measurement logic system 102 may also be fully operational to perform one or more other functions (e.g., fully powered, fully running, etc.) while also performing various operations described herein. It should be understood that such simultaneous multiple operation performance is beyond the capabilities of the human mind. It should also be understood that the quantum state measurement logic system 102 may include information that is not manually obtainable by an entity such as a human user. For example, the type, amount, and / or variety of information included in the quantum state measurement logic system 102, stage control register component 108, and / or compiler component 110 may be more complex than information manually obtained by a human user.

[0102] 7 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method 700 that can facilitate quantum state measurement logic used in a quantum state measurement back-end process according to one or more embodiments described herein. Repetitive descriptions of similar elements and / or processes used in each embodiment are omitted for brevity.

[0103] At 702, the computer-implemented method 700 may include defining, by a system operatively coupled to a processor (e.g., processor 106, quantum processor, etc.) (e.g., via the quantum state measurement logic system 102 and / or the stage control register component 108), a data processing function (e.g., an archive function or a reuse function) corresponding to at least one storage element of at least one stage (e.g., capture array stage 206, kernel stage 208, vector-to-value stage 210, discriminator stage 212, bit stage 214, etc.) of the quantum state measurement pipeline (e.g., quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f and / or quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f). As described above with reference to the exemplary embodiments shown in Figures 2, 4, and 5, such at least one storage element may include, but is not limited to, at least one of capture array storage elements 206a, 206b, 206c, vector pair storage elements 210a, 210b, 210c, 210d, 210e, 210f, and / or bit storage elements 214a, 214b, 214c, 214d, 214e, 214f. In some embodiments, at 702, the computer-implemented method 700 may further include defining, by the system (e.g., via the quantum state measurement logic system 102 and / or the stage control register component 108), a data processing function (e.g., an archive function or a reuse function) corresponding to at least one instance of at least one stage of the quantum state measurement pipeline, where such at least one instance may have, without limitation, at least one of kernel instances 208a, 208b, 208c, and / or discriminator instances 212a, 212b, 212c.

[0104] 8 illustrates a flow diagram of an exemplary, non-limiting, computer-implemented method 800 that can facilitate quantum state measurement logic used in a quantum state measurement back-end process according to one or more embodiments described herein. Repeated descriptions of similar elements and / or processes used in each embodiment are omitted for brevity.

[0105] At 802, the computer-implemented method 800 may include defining, by a system operatively coupled to a processor (e.g., processor 106, quantum processor, etc.) (e.g., via the quantum state measurement logic system 102 and / or the stage control register component 108), a data processing function (e.g., an archive function or a reuse function) corresponding to at least one storage element of at least one stage (e.g., capture array stage 206, kernel stage 208, vector-to-value stage 210, discriminator stage 212, bit stage 214, etc.) of the quantum state measurement pipeline (e.g., quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f and / or quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f). As described above with reference to the exemplary embodiments shown in Figures 2, 4, and 5, such at least one storage element may include, but is not limited to, at least one of capture array storage elements 206a, 206b, 206c, vector pair storage elements 210a, 210b, 210c, 210d, 210e, 210f, and / or bit storage elements 214a, 214b, 214c, 214d, 214e, 214f. In some embodiments, at 802, the computer-implemented method 800 may further include defining, by the system (e.g., via the quantum state measurement logic system 102 and / or the stage control register component 108), a data processing function (e.g., an archive function or a reuse function) corresponding to at least one instance of at least one stage of the quantum state measurement pipeline, where such at least one instance may have, without limitation, at least one of kernel instances 208a, 208b, 208c, and / or discriminator instances 212a, 212b, 212c.

[0106] At 804, the computer-implemented method 800 may include generating, by the system (e.g., via the quantum state measurement logic system 102 and / or the compiler component 110), quantum state measurement logic (e.g., quantum state measurement logic 404 or quantum state measurement logic 504) based on data processing functions corresponding to storage elements of at least one stage of the quantum state measurement pipeline.

[0107] At 806, the computer-implemented method 800 may include identifying, by the system (e.g., via the quantum state measurement logic system 102 and / or the compiler component 110), one or more quantum back-end computing resources (e.g., quantum-based software, quantum hardware, quantum processors, superconducting circuits, quantum computers, etc.) capable of capturing quantum state measurements based on the quantum state measurement logic.

[0108] At 808, the computer-implemented method 800 may include defining, by the system (e.g., via the quantum state measurement logic system 102 and / or the stage control register component 108), the data processing function based on one or more entity definition criteria corresponding to the quantum state measurement pipeline (e.g., one or more entity definition criteria described above with reference to FIG. 1 ).

[0109] At 810, the computer-implemented method 800 may include defining, by the system (e.g., via the quantum state measurement logic system 102 and / or the stage control register component 108), data processing functions corresponding to storage elements of at least one stage of the quantum state measurement pipeline to enable a defined amount (e.g., a larger amount, as described above with reference to FIG. 1 ) of quantum backend computing resources to capture quantum state measurements based on quantum state measurement logic (e.g., quantum state measurement logic 404 or quantum state measurement logic 504) that includes the data processing functions.

[0110] At 812, the computer-implemented method 800 may include generating, by the system (e.g., via the quantum state measurement logic system 102 and / or the stage control register component 108), quantum state measurement logic (e.g., quantum state measurement logic 404 or quantum state measurement logic 504) based on a first set of data processing functions or a second set of data processing functions, the first set of data processing functions having a reuse function corresponding to a single storage element (e.g., bit storage element 214a, 214b, 214c, 214d, 214e, or 214f) of a bit stage (e.g., bit stage 214) of the quantum state measurement pipeline, and the second set of data processing functions having an archive function corresponding to all storage elements (e.g., bit storage elements 214a, 214b, 214c, 214d, 214e, and 214f) of the bit stage, thereby facilitating a reduction in computational costs associated with one or more quantum backend computing resources that capture quantum state measurements based on the quantum state measurement logic.

[0111] In one embodiment, operation 812 of the computer-implemented method 800 described above may be configured to reduce a stage control register, which may be generated by the stage control register component 108, to a single bit that selects "always reuse" or "always advance" (e.g., "always archive"). It should be appreciated that such reduction of the stage control register at operation 812 as described above may facilitate conservation and / or reduction in computational cost of one or more quantum back-end computing resources that capture quantum state measurements based on such a set of first or second data processing functions, as defined above. For example, as defined, the bit stage 214 uses one stage control register bit per data bit, which becomes wasteful as the number of measurements increases. In this example, if individual measurement control is not required by the entity defined herein that implements the quantum state measurement logic system 102, it may be more efficient to refer to a single stage control register bit for control of all storage elements of the bit stage 214.

[0112] 9 illustrates a flow diagram of an exemplary, non-limiting, computer-implemented method 900 that can facilitate quantum state measurement logic used in a quantum state measurement back-end process according to one or more embodiments described herein. Repetitive descriptions of similar elements and / or processes used in each embodiment are omitted for brevity.

[0113] At 902, the computer-implemented method 900 includes a step of: determining whether or not a quantum state measurement pipeline (e.g., quantum state measurement pipeline 402a, 402b, 402c, 402d, 402e, 402f, quantum state measurement pipeline 502a, 502b, 502c, 502d, 502e, 502f, etc.) includes a data processing instance (e.g., capture array stage 206, kernel stage 208, vector-to-value stage 210, discriminator stage 212, bit stage 214, etc.) of a quantum state measurement pipeline (e.g., quantum state measurement pipeline 402a, 402b, 402c, 402d, 402e, 402f, quantum state measurement pipeline 502a, 502b, 502c, 502d, 502e, 502f, etc.) of a data processing instance (e.g., capture array stage 206, kernel stage 208, vector-to-value stage 210, discriminator stage 212, bit stage 214, etc.). f, discriminator instances 212a, 212b, 212c, bit storage elements 214a, 214b, 214c, 214d, 214e, 214f, etc.) as the active data processing instance (e.g., via the quantum state measurement logic system 102, the stage control register component 108, the compiler component 110, the system 600, the stage control register 602 (e.g., a stage control register generated by the stage control register component 108) and / or the selection multiplexer 604)) as the data processing instance that processes a current sample of quantum state measurement data (e.g., the first L0, L1, or L2 sample).

[0114] At 904, the computer-implemented method 900 may include obtaining (e.g., via the quantum state measurement logic system 102, a GUI or API of the quantum state measurement logic system 102, filter 204, system 200, system 400, system 500, system 600, etc.) a current sample of quantum state measurement data (e.g., a first L0, L1, or L2 sample).

[0115] At 906, the computer-implemented method 900 may include processing the current sample of quantum state measurement data using active data processing instances (e.g., via the quantum state measurement logic system 102, capture array storage elements 206a, 206b, 206c, kernel instances 208a, 208b, 208c, vector pair value storage elements 210a, 210b, 210c, 210d, 210e, 210f, discriminator instances 212a, 212b, 212c, bit storage elements 214a, 214b, 214c, 214d, 214e, 214f, etc.).

[0116] At 908, the computer-implemented method 900 may include determining (e.g., via the quantum state measurement logic system 102, the stage control register component 108, the compiler component 110, the system 600, the stage control register 602 (e.g., a stage control register generated by the stage control register component 108)) whether to reuse the active data processing instance to process a subsequent sample of quantum state measurement data (e.g., a second L0, L1, or L2 sample) and / or selecting the multiplexer 604.

[0117] If, at 908, it is determined that the active data processing instance is to be reused to process a subsequent sample of quantum state measurement data (e.g., a second L0, L1, or L2 sample), then, at 910, the computer-implemented method 900 may include obtaining the subsequent sample of quantum state measurement data (e.g., via the quantum state measurement logic system 102, a GUI or API of the quantum state measurement logic system 102, filter 204, system 200, system 400, system 500, system 600, etc.).

[0118] At 912, the computer-implemented method 900 may include overlapping a current sample of quantum state measurement data in the active data processing instance with a subsequent sample of quantum measurement data (e.g., via the quantum state measurement logic system 102, capture array storage elements 206a, 206b, 206c, kernel instances 208a, 208b, 208c, vector pair storage elements 210a, 210b, 210c, 210d, 210e, 210f, discriminator instances 212a, 212b, 212c, bit storage elements 214a, 214b, 214c, 214d, 214e, 214f, etc.).

[0119] If, at 908, it is determined that the active data processing instance will not be reused to process a subsequent sample of quantum state measurement data (e.g., a second L0, L1, or L2 sample), then, at 914, the computer-implemented method 900 may include storing the current sample of quantum state measurement data in the active data processing instance (e.g., archiving via the quantum state measurement logic system 102, capture array storage elements 206a, 206b, 206c, kernel instances 208a, 208b, 208c, vector pair storage elements 210a, 210b, 210c, 210d, 210e, 210f, discriminator instances 212a, 212b, 212c, bit storage elements 214a, 214b, 214c, 214d, 214e, 214f, etc.).

[0120] At 916, the computer-implemented method 900 may include setting another data processing instance (e.g., a next data processing instance) as the active data processing instance (e.g., via the quantum state measurement logic system 102, the stage control register component 108, the compiler component 110, the system 600, the stage control registers 602 (e.g., a stage control register generated by the stage control register component 108), and / or the selection multiplexer 604) in a stage of the quantum state measurement pipeline (e.g., setting capture array storage element 206b or 206c, kernel instance 208b or 208c, vector pair value storage element 210b, 210c, 210d, 210e, or 210f, discriminator instance 212b or 212c, and / or bit storage element 214b, 214c, 214d, 214e, or 214f ​​as the active data processing instance).

[0121] In some embodiments, the computer-implemented method 900 may comprise repeating operations 904, 906, 908, 910, and 912, and / or operations 904, 906, 908, 914, and 916 may be repeated until all quantum state measurements of one or more qubits have been captured by one or more quantum backend computing resources.

[0122] For ease of explanation, the computer-implemented methodologies are depicted and described as a series of acts. It should be understood and appreciated that the subject innovation is not limited by the acts depicted and / or the order of the acts. For example, acts may occur in various orders and / or simultaneously with other acts not presented and described herein. Moreover, not all depicted acts may be necessary to implement a computer-implemented methodology in accordance with the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that a computer-implemented methodology may alternatively be represented as a series of interrelated states via a state diagram or events. Moreover, it should be further appreciated that the computer-implemented methodologies disclosed below and throughout this specification can be stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methodologies to a computer. The term article of manufacture as used herein is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0123] To provide a context for various aspects of the disclosed subject matter, Figure 10 as well as the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. Figure 10 illustrates a block diagram of an exemplary non-limiting operating environment in which one or more embodiments described herein may be facilitated. Repeated descriptions of similar elements used in other embodiments described herein have been omitted for the sake of brevity.

[0124] 10, a suitable operating environment 1000 for implementing various aspects of the disclosure may also include a computer 1012. The computer 1012 may also include a processing unit 1014, a system memory 1016, and a system bus 1018. The system bus 1018 couples system components including, but not limited to, the system memory 1016 to the processing unit 1014. The processing unit 1014 may be any of a variety of processors available. Dual microprocessors and other multi-processor architectures may also be used as the processing unit 1014. The system bus 1018 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), MicroChannel Architecture (MSA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), CardBus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer System Interface (SCSI).

[0125] The system memory 1016 may also include volatile memory 1020 and non-volatile memory 1022. A basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 1012, such as during start-up, is stored in the non-volatile memory 1022. The computer 1012 may also include removable / non-removable, volatile / non-volatile computer storage media. FIG. 10 illustrates, for example, disk storage 1024. The disk storage 1024 may also include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. The disk storage 1024 may also include a storage medium separately or in combination with other storage media. To facilitate connection of the disk storage 1024 to the system bus 1018, a removable or non-removable interface, such as an interface 1026, is typically used. FIG. 10 also illustrates software that acts as an intermediary between a user and the basic computer resources described in the suitable operating environment 1000. Such software may also include, for example, operating system 1028. Operating system 1028, which can be stored on disk storage 1024, acts to control and allocate resources of the computer 1012.

[0126] System applications 1030 take advantage of the management of resources by operating system 1028 through program modules 1032 and program data 1034 stored, for example, in either system memory 1016 or disk storage 1024. It should be appreciated that the present disclosure may be practiced with various operating systems or combinations of operating systems. A user enters commands or information into computer 1012 through input devices 1036. Input devices 1036 include, but are not limited to, pointing devices, such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, television tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to processing unit 1014 through system bus 1018 via interface ports 1038. Interface ports 1038 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 1040 use some of the same types of ports as input devices 1036. Thus, for example, a USB port can be used to provide input to the computer 1012 and to output information from the computer 1012 to an output device 1040. Output adapter 1042 is provided to illustrate that there are some output devices 1040, such as monitors, speakers, and printers, among other output devices 1040, that require dedicated adapters. Output adapters 1042 include, by way of example and not limitation, video cards and sound cards, which provide a means of connection between the output device 1040 and the system bus 1018. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as the remote computer 1044.

[0127] The computer 1012 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1044. The remote computer 1044 can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device or other common network node, and the like, and typically includes many or all of the elements described in conjunction with the computer 1012. For simplicity, only a memory storage device 1046 is shown with the remote computer 1044. The remote computer 1044 is logically connected to the computer 1012 through a network interface 1048, and then physically connected via a communication connection 1050. The network interface 1048 encompasses wired and / or wireless communication networks, such as a local area network (LAN), a wide area network (WAN), a cellular network, and the like. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet-switched networks, and Digital Subscriber Lines (DSL). The communications connection(s) 1050 refers to the hardware / software used to connect the network interface 1048 to the system bus 1018. The communications connection(s) 1050 are illustratively shown internal to the computer 1012 for clarity, but can also be external to the computer 1012. The hardware / software for connecting to the network interface 1048 can also include internal and external technologies such as modems, including ordinary telephone-grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards, for illustrative purposes only.

[0128] 11, an exemplary cloud computing environment 1150 is illustrated. As shown, the cloud computing environment 1150 includes one or more cloud computing nodes 1110 with which local computing devices used by cloud consumers, such as, for example, a personal digital assistant (PDA) or cell phone 1154A, a desktop computer 1154B, a laptop computer 1154C, and / or an automobile computer system 1154N, may communicate. Although not shown in FIG. 11, the cloud computing node 1110 may further have a quantum platform (e.g., quantum computer, quantum hardware, quantum software, etc.) with which the local computing devices used by the cloud consumers may communicate. The nodes 1110 may communicate with each other. They may be grouped (not shown), physically or virtually, into one or more networks, such as the aforementioned private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof. This allows the cloud computing environment 1150 to provide infrastructure, platform, and / or software as a service without the cloud consumer having to maintain resources on the local computing device. It will be understood that the types of computing devices 1154A-N shown in FIG. 11 are intended as examples only, and that the computing node 1110 and cloud computing environment 1150 can communicate with any type of computerized device via any type of network and / or network-addressable connection (e.g., using a web browser).

[0129] Referring now to Figure 12, a set of functional abstraction layers provided by cloud computing environment 1150 (Figure 11) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 12 are for illustrative purposes only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0130] Hardware and software layer 1260 includes hardware and software components. Examples of hardware components include mainframe 1261, RISC (reduced instruction set computer) architecture based servers 1262, servers 1263, blade servers 1264, storage devices 1265, and networks and networking components 1266. In some embodiments, software components include network application server software 1267, database software 1268, quantum platform routing software (not shown in FIG. 12), and / or quantum software (not shown in FIG. 12).

[0131] The virtualization layer 1270 provides an abstraction layer over which the following examples of virtual entities may be provided: virtual servers 1271, virtual storage 1272, virtual networks including virtual private networks 1273, virtual applications and operating systems 1274, and virtual clients 1275.

[0132] In one example, management layer 1280 may provide the functionality described below. Resource provisioning 1281 provides dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 1282 provides cost tracking as resources are utilized within the cloud computing environment and charging or billing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 1283 provides consumers and system administrators with access to the cloud computing environment. Service level management 1284 provides allocation and management of cloud computing resources such that required service levels are met. Service level agreement (SLA) planning and fulfillment 1285 provides advance preparation and procurement of cloud computing resources where future requirements are anticipated according to SLAs.

[0133] Workload tier 1290 provides examples of functions for which a cloud computing environment may be utilized. Non-limiting examples of workloads and functions that may be provided from this tier include mapping and navigation 1291, software development and lifecycle management 1292, virtual classroom instructional delivery 1293, data analytics processing 1294, transaction processing 1295, and quantum state measurement logic software 1296.

[0134] The present invention may be a system, method, apparatus and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to execute aspects of the present invention. The computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage media may also include portable computer diskettes, hard disks, random access memories (RAM), read only memories (ROM), erasable programmable read only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or groove embossed structures having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0135] The computer readable program instructions described herein can be downloaded from a computer readable storage medium to the respective computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing / processing device. The computer readable program instructions for performing the operations of the present invention can be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, or the like, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the invention.

[0136] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general purpose computer, a special purpose computer, or other programmable data processing apparatus to generate a machine, such that the instructions executed via the processor of the computer or other programmable data processing apparatus create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing apparatus, and / or other device to function in a particular manner, such that a computer-readable storage medium having instructions stored therein comprises a product including instructions implementing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operational acts to generate a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0137] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, as well as combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that executes the specified functions or operations, or executes a combination of dedicated hardware and computer instructions.

[0138] Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on one computer and / or multiple computers, those skilled in the art will recognize that the present disclosure can also be combined or implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Furthermore, those skilled in the art will appreciate that the computer-implemented methods of the present invention can be implemented with other computer system configurations, including single-processor or multi-processor computer systems, mini-computing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be implemented in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure can be implemented in stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices. For example, in one or more embodiments, the computer-executable components may execute from a memory that may include or consist of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. Furthermore, one or more embodiments described herein may execute the code of the computer-executable components in a distributed manner, e.g., with multiple processors acting in combination or cooperation to execute the code from one or more distributed memory units. As used herein, the term "memory" may encompass a single memory or memory unit in one location, or multiple memories or memory units in one or more locations.

[0139] As used in this application, the terms "component," "system," "platform," "interface," and the like, can refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. By way of example, both an application running on a server and the server can be components. One or more components can reside within a process and / or thread of execution, and a component can be localized on one computer and / or distributed among two or more computers. In another example, each component can execute from various computer-readable media having various data structures stored thereon. The components can communicate via local and / or remote processes, such as according to signals having one or more data packets (e.g., data from one component interacting with another component via signals with other systems over a network such as a local system, a distributed system, and / or the Internet). As another example, a component may be a device having a particular functionality provided by mechanical parts operated by electrical or electronic circuitry, and operated by a software or firmware application executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application. As yet another example, a component may be a device that provides a particular functionality through electronic components without mechanical parts, and the electronic components may include a processor or other means for executing software or firmware that provides at least part of the functionality of the electronic components.In one aspect, the components can emulate electronic components via virtual machines, for example, in a cloud computing system.

[0140] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise stated or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, if X uses A, if X uses B, or if X uses both A and B, then "X uses A or B" is satisfied in any of the foregoing cases. Furthermore, the articles "a" and "an" as used in the subject specification and the accompanying drawings should generally be construed to mean "one or more" unless otherwise stated or clear from the context to refer to the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, illustration, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Moreover, any aspect or design described herein as "example" and / or "exemplary" should not necessarily be construed as preferred or advantageous over other aspects or designs, nor is it meant to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0141] As used in the subject specification, the term "processor" may refer to, but is not limited to, substantially any computing processing unit or device having a single core processor, a single processor with software multithreaded execution capability, a multicore processor, a multicore processor with software multithreaded execution capability, a multicore processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a processor may leverage nanoscale architectures, such as, but not limited to, molecular and quantum dot based transistors, switches, gates, etc., for area usage optimization or improved performance of user equipment. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component are used to refer to a "memory component," an entity embodied in a "memory," or a component having a memory. It should be understood that the memory and / or memory components described herein may be either volatile or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)).Volatile memory may include, for example, RAM, which may act as external cache memory. By way of example, and not limitation, RAM is available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0142] What has been described above includes merely examples of systems and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many more combinations and permutations of the present disclosure are possible. Moreover, to the extent that "includes," "has," "possesse," and similar terms are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a similar manner to the term "comprising" as they are interpreted as "comprising" when used as transitional words in the claims.

[0143] The description of various embodiments is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond the art found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

Claims

1. a memory for storing computer executable components; A processor for executing the computer-executable components stored in the memory, the computer-executable components comprising: a processor having a stage control register component that defines a data processing function corresponding to at least one storage element of at least one stage of the quantum state measurement pipeline; A system comprising:

2. The system of claim 1 , wherein the data processing functionality includes an archiving functionality that indicates that a current quantum measurement result is to be saved.

3. The system of claim 1 or 2, wherein the data processing functionality has a reuse functionality that indicates overlapping of a current quantum measurement result with a subsequent quantum measurement result.

4. 4. The system of claim 1, wherein the at least one stage is selected from the group consisting of a capture array stage, a kernel stage, a vector pair stage, a discriminator stage, and a bit stage.

5. The computer executable components include: a compiler component that generates quantum state measurement logic based on data processing functions corresponding to storage elements of the at least one stage of the quantum state measurement pipeline, the compiler component identifying one or more quantum backend computing resources that have the capability to capture quantum state measurements based on the quantum state measurement logic. The system of claim 1 , further comprising:

6. 6. The system of claim 1 , wherein the stage control register component defines the data processing functionality based on one or more entity definition criteria corresponding to the quantum state measurement pipeline, and the stage control register component defines data processing functionality corresponding to storage elements of the at least one stage of the quantum state measurement pipeline to enable a defined amount of quantum backend computing resources to capture quantum state measurements based on quantum state measurement logic having the data processing functionality.

7. The computer executable components include: A compiler component that generates quantum state measurement logic based on a first set of data processing functions or a second set of data processing functions, the first set of data processing functions including a reuse function corresponding to a single storage element of a bit stage of the quantum state measurement pipeline, and the second set of data processing functions including an archive function corresponding to all storage elements of the bit stage, thereby facilitating a reduction in computational costs associated with one or more quantum backend computing resources that capture quantum state measurements based on the quantum state measurement logic. Further comprising A system according to any one of claims 1 to 6.

8. A computer-implemented method comprising a system having a processor defining a data processing function corresponding to at least one storage element of at least one stage of a quantum state measurement pipeline.

9. The computer-implemented method of claim 8 , wherein the data processing functionality comprises an archive functionality indicating that a current quantum measurement result is to be saved.

10. 10. The computer-implemented method of claim 8 or 9, wherein the data processing functionality has a reuse functionality that indicates overlapping of a current quantum measurement result with a subsequent quantum measurement result.

11. 11. The computer-implemented method of claim 8, wherein the at least one stage is selected from the group consisting of a capture array stage, a kernel stage, a vector pair stage, a discriminator stage, and a bit stage.

12. generating quantum state measurement logic based on data processing functions corresponding to storage elements of the at least one stage of the quantum state measurement pipeline; the system identifying, based on the quantum state measurement logic, one or more quantum backend computing resources capable of capturing quantum state measurements; The computer-implemented method of claim 8 , further comprising:

13. the system defining the data processing functionality based on one or more entity definition criteria corresponding to the quantum state measurement pipeline; the system defining data processing functionality corresponding to storage elements of the at least one stage of the quantum state measurement pipeline to enable a defined amount of quantum backend computing resources to capture quantum state measurements based on quantum state measurement logic having the data processing functionality; The computer-implemented method of claim 8 , further comprising:

14. 14. The computer-implemented method of claim 8, further comprising: generating quantum state measurement logic based on a first set of data processing functions or a second set of data processing functions, the first set of data processing functions including a reuse function corresponding to a single storage element of a bit stage of the quantum state measurement pipeline, and the second set of data processing functions including an archive function corresponding to all storage elements of the bit stage, thereby facilitating a reduction in computational costs associated with one or more quantum backend computing resources that capture quantum state measurements based on the quantum state measurement logic.

15. 1. A computer program for facilitating a quantum state measurement back-end process, the computer program having program instructions executable by a processor to cause the processor to define a data processing function corresponding to at least one storage element of at least one stage of a quantum state measurement pipeline.

16. 16. The computer program product of claim 15, wherein the data processing functionality comprises an archive functionality indicating that a current quantum measurement result is to be saved.

17. 17. A computer program product as claimed in claim 15 or 16, wherein the data processing functionality comprises a reuse functionality indicating overlap of a current quantum measurement result with a subsequent quantum measurement result.

18. 18. The computer program product of claim 15, wherein the at least one stage is selected from the group consisting of a capture array stage, a kernel stage, a vector pair stage, a discriminator stage, and a bit stage.

19. the program instructions are further executable by the processor; generating, by the processor, quantum state measurement logic based on data processing functions corresponding to storage elements of the at least one stage of the quantum state measurement pipeline; 19. The computer program product of claim 15, further comprising: causing the processor to identify, based on the quantum state measurement logic, one or more quantum backend computing resources that have capability to capture quantum state measurements.

20. the program instructions are further executable by the processor; 20. The computer program product of claim 15, further comprising: causing the processor to generate quantum state measurement logic based on a first set of data processing functions or a second set of data processing functions, the first set of data processing functions including a reuse function corresponding to a single storage element of a bit stage of the quantum state measurement pipeline and the second set of data processing functions including an archive function corresponding to all storage elements of the bit stage, thereby facilitating a reduction in computational costs associated with one or more quantum backend computing resources that capture quantum state measurements based on the quantum state measurement logic.

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