Cryogenic classical superconducting networks for error correction in quantum computing

Abstract

This patent document is directed to the implementation of embodiments of an error correction module or gadget using cryogenic classical superconducting circuits that can be used as a decoder of a quantum error correction code to correct errors in quantum computing. The method and system disclosed herein replaces the classical decoder by a function approximator of the true decoding function. The function approximator is produced by pre-training a model on data generated by the decoder in simulations or in quantum experiments. An example of such a model is a neural network. Such a function approximator can reach a decoding accuracy close to that of a classical decoder, but uses much simpler and faster logic.

Description

[Technical field]

[0001] (Priority claims and related patent applications) This patent document claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 142,375, entitled “CRYOGENIC CLASSICAL SUPERCONDUCTING CIRCUITRY FOR ERROR CORRECTION IN QUANTUM COMPUTING,” filed January 27, 2021 by applicants SeeQC, Inc. and 1QB Information Technologies Inc. under Attorney Docket No. 133858-8007.US00.

[0002] The disclosure of this patent document relates to error correction in the transmission of signals and data in quantum computing systems. [Background technology]

[0003] In digital computing and transmission of digital signals or data in communication systems, the transmitted digital data may be subject to errors during transmission from a sender to a receiver. Error correction codes or error compensation codes (ECC) may be used to encode the digital data to be transmitted in order to control errors in the data passing through a communication channel from a sender to a receiver. The sender encodes the message or data to be transmitted with redundant information, so that errors that may occur in the transmission can be detected and corrected without retransmission.

[0004] In quantum computing, a quantum system for performing quantum computations can be implemented by an ensemble of subsystems that exhibit different quantum states, where the subsystems are mutually correlated or "entangled" due to quantum coherence. In various implementations, each subsystem in the ensemble of subsystems can exhibit two or more different quantum states to operate as an elementary quantum device. Information can be represented, stored, processed, and transmitted by the superposition and correlation of the quantum states of different elementary quantum devices. Such elementary quantum devices with two or more different quantum states can be referred to as "qudits," and two-state devices are often referred to as quantum bits ("qubits"). In quantum computing, in addition to errors that may occur during data transmission in digital computing, quantum information is susceptible to errors due to quantum decoherence and other quantum noise or interference. Quantum error correction is essential to achieve fault-tolerant quantum computing and is an integrated part of quantum computing. Summary of the Invention [Means for solving the problem]

[0005] The disclosure of this patent document is directed to the implementation of embodiments of an error correction module or gadget using cryogenic classical superconducting circuits that can be used as decoders of quantum error correction codes to correct errors in quantum computing.

[0006] The methods and systems disclosed herein replace classical decoders with function approximators of the true decoding function. The function approximators are produced by pre-training a model on data generated by the decoder in simulations or in quantum experiments. An example of such a model is a neural network. Such function approximators can reach decoding accuracy close to that of classical decoders, but use much simpler and faster logic. As a result, the function approximators (1) can be implemented on hardware that can operate within a dilution refrigerator or another cryogenic environment, eliminating latency and potential errors in data transfer to and from the quantum processor, and (2) use much less processing time than classical decoders.

[0007] The disclosed cryogenic classical superconducting circuits may be implemented to use superconducting Josephson junction electronics to process information. The superconducting electronics operate at high speed with low energy dissipation. The disclosed cryogenic classical superconducting circuits may include digital and mixed signal single flux quantum families such as rapid single flux quantum (RSFQ), energy efficient rapid single flux quantum (ERSFQ), energy efficient single flux quantum (eSFQ), inverse quantum logic (RQL), and quantum parametron circuits such as adiabatic quantum flux parametron (AQFP), superconducting quantum interface device (SQUID), Bi-SQUID with two Josephson junctions, SQUID with negative mutual inductance (nSQUID), and analog superconducting circuits based on SQUID.

[0008] In one implementation, the disclosed technology provides a system capable of quantum error correction for quantum computing, comprising a cryogenic device structured to include different cryogenic stages at different cryogenic temperatures, and a quantum processor comprising a plurality of qudits for performing quantum computing, the plurality of qudits comprising data qudits and syndrome qudits for interacting with the data qudits and providing measurements of the syndrome qudits, the plurality of qudits comprising error correction code for correcting quantum errors in quantum computing, and the quantum processor includes a cryogenic device at a desired cryogenic temperature for proper operation of the qudits. In one embodiment, the present invention relates to a quantum computing system that includes a quantum processor coupled to and cooled by the cryogenic device, and a cryogenic classical superconducting circuit coupled to and cooled by the cryogenic device and further coupled to receive information regarding the measurements from the syndrome qudits, the cryogenic classical superconducting circuit including a decoder for the quantum error correction code, processing the received information regarding the measurements from the syndrome qudits, generating recovery operations for the data qudits, and structured to reduce errors in quantum computing, wherein the cryogenic classical superconducting circuit is coupled to the quantum processor as a classical co-processor, reducing communication delays between the quantum processor and the cryogenic classical superconducting circuit.

[0009] In another implementation, the disclosed technology can be implemented to provide a method for implementing a quantum error correction scheme, comprising the steps of preparing at least one syndrome qudit, implementing at least one syndrome extraction circuit comprising at least one data qudit and at least one syndrome qudit, performing at least one measurement on the at least one syndrome qudit of each syndrome extraction circuit, providing a result of the at least one measurement to a function approximator of a decoder, using the function approximator of the decoder to provide a recovery operation comprising a recovery operator, and applying the recovery operation.

[0010] In another implementation, the disclosed technology can be implemented to provide a cryogenic classical superconducting circuit functioning at cryogenic temperatures comprising a function approximator for a decoder of a quantum error correction code, the decoder comprising a plurality of nodes, a plurality of interconnections between the nodes of the plurality of nodes for distributing pulses among the nodes, and a plurality of weights representing function approximator parameters, each node of the plurality of nodes comprising a function approximator comprising a receiver section for receiving at least one pulse comprising a magnetic flux, current, or voltage, a processing core for processing the received pulses, and a transmitter section for transmitting the processed pulses.

[0011] In another implementation, the disclosed technology provides a method for constructing a function approximator for a decoder and can be implemented to perform operations including: collecting data for at least one syndrome qudit and for a corresponding error from an error correction code; and constructing the function approximator using the collected data for the at least one syndrome qudit and the collected data for the corresponding error.

[0012] In yet another implementation, the disclosed technology includes a quantum processor comprising a plurality of physical qudits, each capable of assuming a different quantum state, the plurality of physical qudits being structured to perform quantum computing, the plurality of physical qudits comprising a plurality of data qudits for performing quantum computing, and a plurality of syndrome qudits located between the data qudits to interact with the data qudits and provide a measurement of the quantum state of the syndrome qudits indicative of a quantum error in the quantum computing performed by the quantum processor; a qudit readout circuit coupled to the quantum processor to interact with the syndrome qudits and produce a readout signal representative of the measurement of the quantum state of the syndrome qudits; and a readout signal representative of the measurement of the quantum state of the syndrome qudits. The present invention can be implemented to provide a quantum computing system including: a cryogenic classical superconducting circuit coupled to receive information, the cryogenic classical superconducting circuit being structured to include a decoder that processes the received information, obtains information regarding errors in quantum computing performed by the quantum processor, and generates a recovery operation to reconstruct the quantum information of the qudits, thereby reducing errors in quantum computing; and a cryogenic system coupled to encapsulate the quantum processor, the qudit readout circuit, and the cryogenic classical superconducting circuit, respectively, at a desired cryogenic temperature, the cryogenic classical superconducting circuit and the quantum processor being positioned relative to each other to enable high speed communication between the cryogenic classical superconducting circuit and the quantum processor with reduced communication delays.

[0013] An advantage of one or more embodiments of the disclosed technology is that it eliminates or substantially reduces the latency of data transfer between the quantum processor and the classical coprocessor.

[0014] Another advantage of one or more embodiments of the disclosed technology is that it prevents potential errors in data transfer between the quantum processor and the classical coprocessor.

[0015] Another advantage of one or more embodiments of the disclosed technology is that the function approximator can be implemented on hardware that can be installed and operated in a dilution refrigerator or another cryogenic cooling device.

[0016] Another advantage of one or more embodiments of the disclosed technology is that it can be applied to a variety of quantum processors and a variety of quantum computations.

[0017] Another advantage of one or more embodiments of the disclosed technology is that it can utilize a variety of function approximators, and in particular a variety of neural networks.

[0018] Another advantage of one or more embodiments of the disclosed technology is that it reduces processing time compared to conventional decoders.

[0019] Another advantage of one or more embodiments of the disclosed techniques is that the decoder can be trained in a data-driven manner, using data streams collected from experiments performed on the system.

[0020] Another advantage of one or more embodiments of the disclosed techniques is that the decoder may be retuned or calibrated according to the data stream from an experiment performed over the most recent time window, thus providing maximum performance according to the most recent sources of noise plaguing the qudits of the system.

[0021] These and other features of the disclosed technology are explained in more detail in the drawings, description and claims. The present specification also provides, for example, the following items: (Item 1) 1. A cryogenic classical superconducting circuit operating at cryogenic temperatures comprising a function approximator for a decoder of a quantum error correction code, the decoder comprising a plurality of nodes, a plurality of interconnections between nodes of the plurality of nodes for distributing pulses among the nodes, and a plurality of weights representing the function approximator parameters, each node of the plurality of nodes being: a receiver section for receiving at least one pulse comprising a magnetic flux, a current, or a voltage; a processing core for processing the received pulses; a transmitter section for transmitting the processed pulses; A cryogenic classical superconducting circuit comprising: (Item 2) 2. The cryogenic classical superconducting circuit of claim 1, comprising a mixed-signal digital and analog Josephson junction superconducting electronic device comprising a magnetic junction and a quantum phase slip device. (Item 3) 3. The cryogenic classical superconducting circuit of claim 2, wherein the Josephson junction superconducting electronics comprises digital and mixed-signal quantum flux family, the digital and mixed-signal quantum flux family comprising energy efficient fast single flux quantum (ERSFQ), energy efficient single flux quantum (eSFQ), adiabatic quantum flux parametron (AQFP), inverse quantum logic (RQL), fast single flux quantum (RSFQ), SFQuClass, or superconducting quantum interface device (SQUID, Bi-SQUID, nSQUID). (Item 4) 4. The cryogenic classical superconducting circuit of claim 1, wherein each node is configured to operate in an analog, digital, or analog-digital mode. (Item 5) 5. The cryogenic classical superconducting circuit of item 4, wherein the nodes are arranged in layers, and further wherein a receiver section of the node in a first layer and a transmitter section in a last layer operate in a digital mode, and the nodes in other layers operate in an analog mode. (Item 6) 2. The cryogenic classical superconducting circuit of claim 1, wherein the nodes are coupled by interconnects that are analog, digital, or a hybrid of analog and digital. (Item 7) 2. The cryogenic classical superconducting circuit of claim 1, wherein the nodes are coupled by interconnects that are operated synchronously or asynchronously. (Item 8) 2. The cryogenic classical superconducting circuit of claim 1, wherein the decoder further comprises at least one amplifier for amplifying the signal. (Item 9) 2. The cryogenic classical superconducting circuit of claim 1, wherein at least one of the plurality of weights comprises a fixed coupling comprising a magnetic coupling, a capacitive coupling, or a resistive coupling. (Item 10) 2. The cryogenic classical superconducting circuit of claim 1, wherein at least one of the plurality of weights comprises a variable coupling comprising a magnetic coupling, a capacitive coupling, a galvanic coupling, or a resistive coupling. (Item 11) 10. The cryogenic classical superconducting circuit of item 9, wherein the magnetic coupling comprises a transformer, and different coupling strengths are used for different input pulses at the transformer to represent a weighting of the plurality of weights, and a fixed magnetic coupling is proportional to the weighting. (Item 12) 10. The cryogenic classical superconducting circuit of item 9, wherein the resistive coupling comprises a voltage divider, and further wherein different coupling strengths are used for different input pulses at the voltage divider to represent a weighting of the plurality of weights, and further wherein a fixed resistive coupling is proportional to the weighting. (Item 13) 11. The cryogenic classical superconducting circuit of claim 10, wherein a weighting of the plurality of weights is expressed via at least one of generating a number of the single flux quantum (SFQ) pulses proportional to the weighting, generating a pulse rate proportional to the weighting, and generating a pulse intensity proportional to the weighting. (Item 14) 3. The cryogenic classical superconducting circuit of claim 2, wherein the Josephson junction superconducting electronic device comprises a superconducting quantum interface device (SQUID), and at least one of the number of generated pulses, the pulse rate, or the pulse intensity is varied by varying a bias current or a critical current of the superconducting quantum interface device (SQUID). (Item 15) 10. The cryogenic classical superconducting circuit of claim 9, wherein the processing core comprises at least one storage loop for storing the magnetic flux, and the magnetic flux is erased using a command pulse, which may be a resistor, a SQUID, or a clock. (Item 16) 2. The cryogenic classical superconducting circuit of claim 1, wherein the interconnection between two nodes of the plurality of nodes is electrical, magnetic, or photonic. (Item 17) 2. The cryogenic classical superconducting circuit of claim 1, wherein the interconnection between at least two nodes of the plurality of nodes is in parallel or in series. (Item 18) 2. The cryogenic classical superconducting circuit of claim 1, wherein the interconnection between two nodes of the plurality of nodes is electrical using a Josephson transmission line (JTL) or a passive transmission line (PTL). (Item 19) 2. The cryogenic classical superconducting circuit of claim 1, wherein the pulses between the nodes are generated using line drivers, each of the pulses generating at least one pulse. (Item 20) 2. The cryogenic classical superconducting circuit of claim 1, wherein a function approximator for a decoder of the quantum error correction code comprises a neural network, further wherein the neural network parameters and activations are represented by the decoder nodes and weights, further wherein the neural network activations are implemented using the node processing cores. (Item 21) 21. The cryogenic classical superconducting circuit of claim 20, wherein the activation comprises a sigmoid and a rectified linear unit (ReLU) activation function. (Item 22) 21. The cryogenic classical superconducting circuit of claim 20, wherein the neural network comprises a recurrent neural network, a deep neural network, a feedforward neural network, a convolutional neural network, a Hopfield network, a Boltzmann machine, or a graphical model. (Item 23) 2. The cryogenic classical superconducting circuit of claim 1, wherein the function approximator for the quantum error correction code decoder comprises at least one neural network and at least one linear function approximator. (Item 24) 2. The cryogenic classical superconducting circuit of item 1, wherein at least one of the plurality of weights is programmable. (Item 25) 2. The cryogenic classical superconducting circuit of claim 1, wherein the function approximator is programmable using input from a user. (Item 26) 2. The cryogenic classical superconducting circuit of claim 1, wherein the function approximator for the decoder of the quantum error correction code comprises a regression unit, a classifier, a decision tree, or a random forest. (Item 27) 1. A system capable of quantum error correction for quantum computing, the system comprising: (a) a cryogenic device that is structured to include different cryogenic stages at different cryogenic temperatures; (b) a quantum processor, the quantum processor comprising a plurality of quantum devices with two or more distinct quantum states ("qudits") for performing quantum computing, the quantum processor being coupled to and cooled by the cryogenic devices at a desired cryogenic temperature for proper operation of the qudits, the plurality of qudits comprising data qudits for encoding quantum information for quantum computing and syndrome qudits for interacting with the data qudits and providing measurements, the plurality of qudits providing error correction codes for correcting quantum errors; (c) a cryogenic classical superconducting circuit, the cryogenic classical superconducting circuit coupled to and cooled by the cryogenic device, further coupled to receive information about the measurement from the syndrome qudit, the cryogenic classical superconducting circuit including a decoder for the quantum error correction code, and configured to process the received information about the measurement from the syndrome qudit and generate a recovery operation for a data qudit to reduce errors in the quantum computing, the cryogenic classical superconducting circuit coupled to the quantum processor as a classical coprocessor, reducing communication delays between the quantum processor and the cryogenic classical superconducting circuit; A system comprising: (Item 28) 28. The system of claim 27, wherein the error correction code is a topological error correction code. (Item 29) Item 28. The system of item 27, wherein the error correction procedure on the topological error correction code comprises a parity check operation on the plurality of qudits comprising a plaquette. (Item 30) Item 29. The system of item 28, wherein the topological code comprises a toric code, a surface code, a rotated surface code, a color code, a triangular color code, or a bihexagonal code. (Item 31) 28. The system of claim 27, comprising a plurality of logical qudits, each of the plurality of logical qudits comprising a classical-quantum interface between the cryogenic classical superconducting circuit and the quantum processor, the logical qudit comprising a quantum error correction scheme, the plurality of logical qudits being for performing quantum computing. (Item 32) 28. The system of claim 27, wherein the quantum processor comprises at least one syndrome extraction circuit. (Item 33) 28. A method for implementing a quantum error correction scheme using the system of claim 27, the method comprising: (i) preparing said at least one syndrome qudit; (ii) implementing said at least one syndrome extraction circuit comprising at least one data qudit and at least one syndrome qudit; (iii) performing at least one measurement on at least one syndrome qudit of each said syndrome extraction circuit; (iv) providing a result of the at least one measurement to a function approximator of the detector; and (v) providing a recovery operation using a function approximator of the decoder, the recovery operation comprising a recovery operator; (vi) applying said recovery operation; and A method comprising: (Item 34) Item 34. The method of item 33, wherein the recovery operator is a unitary operator applied to the error-correcting code. (Item 35) Item 34. The method according to item 33, wherein the recovery operator is a change of basis on the Pauli frame. (Item 36) Item 34. The method of item 33, wherein the recovery operator is an equivalence operator. (Item 37) 34. The method of claim 33, wherein steps (ii)-(iv) are repeated at least once. (Item 38) 28. A method for constructing a function approximator for a decoder of the system according to claim 27, the method comprising: (a) collecting data from the error correction code regarding the at least one syndrome qudit and regarding a corresponding error; (b) constructing the function approximator using the collected data for the at least one syndrome qudit and the collected data for the corresponding error; A method comprising: (Item 39) 39. The method of claim 38, wherein (b) includes training a neural network. (Item 40) Item 39. The method of item 38, wherein the data is collected from a simulation of a qudit being beset by a noisy channel. (Item 41) 41. The method of claim 40, wherein the noise channel comprises a Pauli noise channel, and further wherein the Pauli noise channel is depolarizing or dephasing. (Item 42) Item 39. The method of item 38, wherein the data is collected from a simulation of the plurality of qudits performing a logical operation. (Item 43) Item 39. The method of item 38, wherein the data is collected from experimental data, the experimental data comprising data from qudits at rest, data from qudits performing logical measurements, and data from logic gates. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a schematic diagram of an example of a cryogenic classical superconducting circuit with at least one function approximator for a decoder of a quantum error correction code according to one implementation of the disclosed technology.

[0023] [Diagram 2] FIG. 2 is a schematic diagram of a node of the decoder illustrated in FIG.

[0024] [Diagram 3] FIG. 3 is a schematic diagram of an embodiment of a node receiver.

[0025] [Figure 4] FIG. 4 is a schematic diagram showing an embodiment of a variable weight implementation in which the weight is encoded in the number of SFQ pulses generated.

[0026] [Diagram 5] FIG. 5 shows two embodiments of a variable multi-pulse generator.

[0027] [Figure 6] FIG. 6 is a diagram illustrating an embodiment of a node processing core with a threshold-based activation function.

[0028] [Figure 7A] FIG. 7A is a diagram illustrating an embodiment of a node processing core with a rectified linear unit (ReLU) activation function using SQUIDs.

[0029] [Figure 7B] FIG. 7B is a diagram illustrating an embodiment of a node processing core with a rectified linear unit (ReLU) activation function using Bi-SQUIDs.

[0030] [Figure 8] FIG. 8 is a schematic diagram showing two embodiments for clearing the stored magnetic flux and resetting the circuit.

[0031] [Figure 9] FIG. 9 is a schematic diagram showing an embodiment of a direct one-to-one interconnect.

[0032] [Figure 10] FIG. 10 is a diagram illustrating an embodiment of connectivity between nodes of two layers.

[0033] [Figure 11] FIG. 11 is a schematic diagram illustrating an embodiment of connectivity between nodes in two successive layers using parallelizers and serializers to reduce the number of interconnect wires.

[0034] [Figure 12] FIG. 12 is a schematic diagram of an embodiment of a quantum correction gadget.

[0035] [Figure 13] FIG. 13 is a flow chart illustrating an embodiment of a method for implementing a quantum error correction scheme using the system illustrated in FIG.

[0036] [Figure 14] FIG. 14 is a flow chart illustrating an embodiment of a method for constructing a function approximator for a decoder of a quantum error correction code.

[0037] [Figure 15] FIG. 15 is a schematic diagram showing an embodiment of a buffer with coupling and a D flip-flop buffer function for storing an incoming signal.

[0038] [Figure 16] FIG. 16 is a schematic diagram showing an embodiment of a variable bond.

[0039] [Figure 17] FIG. 17 is a schematic diagram showing an embodiment of an amplifier location for a node.

[0040] [Figure 18] FIG. 18 is a schematic diagram showing an embodiment of an amplifier with multiple SQUIDs in series.

[0041] [Figure 19] FIG. 19 is a schematic diagram illustrating an embodiment of an analog node. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] Detailed Description Error correction in quantum computers is desirable for providing fault-tolerant quantum computation and for implementing large-scale quantum algorithms to solve computational problems that may be intractable for classical computers.

[0043] The physical quantum device qubits or qudits in a quantum computer can suffer from continuous errors as a result of various sources such as natural decoherence or interactions with a control device. One approach to overcoming these errors is by using a quantum error correction scheme, where a single logical qubit or qudit is encoded using a combination of (1) the number of physical qubits or qudits for performing the quantum computation, (2) additional syndrome qubits or qudits and error correction circuitry for detecting errors in the quantum states of the physical qubits or qudits for performing the quantum computation, (3) a decoder that prescribes a recovery operation based on the observed syndrome, and (4) a controller for applying the recovery operation to the physical qubits or qudits. Fault tolerance is achieved when errors can be detected and corrected at a faster rate than they occur, thereby preventing errors from compounding over long computations.

[0044] However, engineering such a quantum error correction system presents challenges. Complexity increases exponentially with the increasing number of possible errors to be corrected. Decoding needs to occur in a short period of time to allow for the actions required to correct the errors. Performing the decoding quickly in the decoder and locating the decoder as close as possible to the qubits or qudits can reduce undesired latency caused by error correction operations. The decoding process can be implemented by a classical coprocessor located adjacent to the quantum processor formed by the qubits or qudits to perform the decoding process in the same time frame as the rate at which the errors are generated. For superconducting qubits or qudits with very short decoherence times and very fast gates, this fast decoding time can be difficult or challenging to achieve due to (1) the latency required to transmit the readout information between the quantum processor and the classical coprocessor and (2) the processing time required to perform the decoding.

[0045] The techniques disclosed in this patent document can be implemented in such a way as to provide methods and systems for mitigating certain limitations associated with the accuracy of the physical qubits or qudits, communication delays between the quantum processor and the classical coprocessor, and speed limits of error correction.

[0046] The disclosed technology can be implemented to include a system capable of quantum error correction for performing quantum computing, including, for example, a cryogenic device structured to include different cryogenic stages at different cryogenic temperatures, and a quantum processor with multiple qudits for performing quantum computing, coupled to and cooled by the cryogenic device at a desired cryogenic temperature for proper operation of the qudits. The qudits include (1) data qudits for encoding quantum information for quantum computing, and (2) syndrome qudits for interacting with the data qudits and providing measurements of the syndrome qudits. The combination of the data qudits and syndrome qudits provides or enables a quantum error correction code for correcting quantum errors in quantum computing. The system further includes a cryogenic classical superconducting circuit coupled to and cooled by the cryogenic device. The cryogenic classical superconducting circuit is coupled to receive information about the measurements from the syndrome qudits, includes a decoder of the quantum error correction code, and is structured to process the received information about the measurements from the syndrome qudits and generate recovery operations for the data qudits to reduce errors in quantum computing. The cryogenic classical superconducting circuit is coupled to the quantum processor as a classical co-processor to reduce communication delays between the quantum processor and the cryogenic classical superconducting circuit.

[0047] In implementations, the cryogenic classical superconducting circuit may include a classical circuit that interfaces with the data qudits and the syndrome qudits. A portion of the classical circuit that interfaces with the syndrome qudits includes a decoder to solve the decoding problem and generate a recovery operation for each corresponding data qudit in correcting errors in quantum computing. For example, in some implementations, the decoder may be built based on a neural network.

[0048] As used herein, the term "qubit" generally refers to a unit of quantum information processing whose quantum state is a complex unit vector of dimension 2. These two dimensions are typically referred to as "0" and "1."

[0049] As used herein, the term "qudit" generally refers to a multilevel quantum system or qubit.

[0050] As used herein, the term "physical qubit" generally refers to the physical implementation of a qubit.

[0051] As used herein, the term "physical qudit" generally refers to the physical implementation of a qudit.

[0052] As used herein, the term "logical qubit" generally refers to the abstract concept of a qubit that may be realized by one or more physical qubits. It should be understood that the logical qubits form an abstract Hilbert space used for quantum information processing (e.g., quantum computation), the logical qubits are encoded using various degrees of freedom of the physical qubits, and the physical Hilbert space associated with the physical qubits is often of much higher dimensionality than the logical Hilbert space, thus allowing the physical qubits to protect the logical qubits against various sources of error.

[0053] As used herein, the term "logical qudit" generally refers to the abstract concept of a qudit that may be realized by one or more physical qudits.

[0054] A collection of n qubits has its "quantum state" in a Hilbert space that is the tensor product of the Hilbert spaces of the individual qubits.

[0055] A collection of n qudits has its "quantum state" in a Hilbert space that is the tensor product of the Hilbert spaces of the individual qudits.

[0056] As used herein, the term "quantum gate" generally refers to a unitary operation performed on the collective quantum state of one or more qubits or qudits.

[0057] As used herein, the term “Pauli gate” generally refers to one of the Pauli quantum logic gates X, Y, or Z.

[0058] As used herein, the term “error” generally refers to any undesired transformation of a qubit or qudit, the causes of which may include, but are not limited to, natural qubit or qudit decoherence, thermal interactions, or interactions with a control device.

[0059] As used herein, the term "error rate" when applied to any event (such as a quantum gate, qubit or qudit preparation, qubit or qudit measurement, qubit or qudit waiting time, or error correction gadget) refers to the probability that the event contains an error.

[0060] As used herein, the term "noise channel" generally refers to a mathematical model of the errors that plague a desired circuit when physically implemented. The noise channel is often represented as a CPTP (Conservative Perfect Positive Trace) map, often with error rates for various components as parameters.

[0061] As used herein, the term “quantum error-correcting code” generally refers to a procedure for constructing practical logical qubits or qudits with low error rates from many physical qubits or qudits with high error rates.

[0062] As used herein, the term "data qubit" generally refers to one of the physical qubits used to encode quantum information.

[0063] As used herein, the term "data qudit" generally refers to one of the physical qudits used to encode quantum information.

[0064] As used herein, the term "code space" refers to the Hilbert subspace of the Hilbert space of physical qubits. Given a wavefunction in the code space, the state of a logical qubit can be extracted.

[0065] As used herein, the term "data qubit error rate" refers to the probability of error in each data qubit in a given unit of time.

[0066] As used herein, the term "data qudit error rate" refers to the probability of an error in each data qudit in a given unit of time.

[0067] As used herein, the term "code distance" generally refers to the minimum number of errors required to switch from one encoded state to another. In some embodiments, this translates to the number of qubits or qudits along one side of a patch of data qubits or qudits used to encode a single logical qubit or qudit. This is equal to the smallest possible number of data qubit or qudit errors that can lead to an error in the logical qubit or qudit state.

[0068] As used herein, the term "syndrome qubit" generally refers to one of the physical qubits that is used to detect errors.

[0069] As used herein, the term "syndrome qudit" generally refers to one of the physics qudits that is used to detect errors.

[0070] As used herein, the term "syndrome" generally refers to the combined readout of (potentially many) measurements from a syndrome qudit or qubit.

[0071] As used herein, the term "recovery operation" generally refers to a proposed set of gates to apply to a data qubit or data qudit.

[0072] As used herein, the term “decoder for a quantum error-correcting code” generally refers to methods and systems that take as input a number of syndromes and provide as output a recovery operation that is intended to restore the state of a logical qubit or logical qudit before an error was introduced.

[0073] As used herein, the term "round of error correction" generally refers to one end-to-end pass through a quantum error correction code.

[0074] As used herein, the term "logical error rate" generally refers to the probability of occurrence of a logical error in a logical qubit or qudit in a given unit of time. In one embodiment, this is calculated by finding the frequency at which one round of the entire error correction scheme results in an error in the logical qubit.

[0075] As used herein, the term "neural network" generally refers to a computational graph in which some subset of nodes are designated as "inputs" having only outgoing edges and some subset of nodes are designated as "outputs" having only incoming edges, and for each node with a parameter, the gradient of its associated function with respect to that parameter is itself a readily computable function.

[0076] As used herein, the term "feed-forward neural network" generally refers to a neural network that does not involve any cycles and in which all paths from inputs to outputs have the same length.

[0077] As used herein, the term "input layer" generally refers to a set of input nodes.

[0078] As used herein, the term "layer" generally refers to a set of nodes at a fixed, equal distance from the input layer.

[0079] As used herein, the term "input vector" generally refers to a vector for entering an input node or nodes.

[0080] As used herein, the term "output vector" generally refers to a vector for entering an output node or nodes.

[0081] As used herein, the term "training data" generally refers to a set of (x, y) pairs, where x is an input data point and y is an output data point.

[0082] As used herein, the term “syndrome extraction circuit” generally refers to circuitry used to entangle one or more syndrome qubits or qubits with data qubits or qudits to prepare the syndrome qubits or qubits in a state that (a) can be measured without corrupting the logical state of the quantum computation being protected, and (b) the results of these measurements can be used to extract information about errors afflicting the physical qubits or qudits.

[0083] In the following detailed description, reference will be made to the accompanying drawings in which like numerals typically identify like components, unless the context dictates otherwise.

[0084] Multilevel quantum systems Multilevel quantum systems may be structured in a way that operates based on quantum mechanical processes such as superposition and entanglement of quantum states. Multilevel systems may include systems with two or more energy states of artificial or natural atoms, e.g., the ground (|0>) and the first excited state (|1>) of a superconducting artificial atom. Such multilevel systems may have 0, 1, ..., n energy states. Multilevel quantum systems may be referred to as "qudits" and multiple qudits may be used to implement quantum computing systems. A qudit may be considered as one of n quantum states 0, 1, ..., n-1 or a superposition of any of n states. There is a specific subcategory of qudits that includes systems that consist of only two energy states, namely the ground (|0>) and the first excited state (|1>). These two-state systems are referred to as "qubits". Each qubit can be placed in one of these two states. However, due to the nature of multilevel quantum systems, they can also be placed in a superposition of these two states. Entangled qubit or qudit devices can perform computational tasks.

[0085] Quantum Error Correction Code Quantum error correction codes (QECCs) can be implemented by constructing one or more practical logical qudits with a relatively low error rate from several physical data qudits with relatively higher error rates. A QECC can be characterized by several parameters, including, for example, the number of data qudits (denoted by n), the number of logical qudits (denoted by k), and the number of errors that can occur in a code state and still be corrected (called the code distance, denoted by d).

[0086] In some implementations, QECC may be constructed as a natural extension of classical error correcting codes (ECC), which can encode one or more logical bits using many low-fidelity bits by correcting bit-flip errors.

[0087] A prominent class of QECCs is given by stabilizer codes. The general stabilizer formalism is as follows: An abelian subgroup K of the n-qudit Pauli group is chosen, which is called the stabilizer subgroup. A set of generators A_1, A_2, …, A_k is chosen for K. The code space is the space of states of the data qudits stabilized by A, i.e., the eigenstate with eigenvalue +1. The code space thus encodes nk logical qudits. Simultaneously measuring each of the stabilizers A_1, A_2, …, A_k projects the data state into the code space. For more details, see Gheorghiu, V. "Standard Form of Qudit Stabilizer Groups" https: / / arxiv.org / abs / 1101.1519 and Gottesman, D. "An Introduction to Quantum Error Correction and Fault-Tolerant Quantum Computation" (2009), https: / / arxiv.org / abs / 0904.2557 (incorporated by reference into the specification of this patent document).

[0088] One of the embodiments of the stabilizer code is the CSS code. The CSS code is defined using the Calderbank-Shor-Steane (CSS) construction that produces a single QECC from two nested linear ECCs C’ < C with the same number of data bits. The logical qubit is encoded within the sub-quotient C / C’. The reason this construction produces a QECC is that (1) the ability to correct both Pauli X (bit flip) errors and Pauli Z (phase flip) errors enables full quantum error correction, and (2) the application of the Hadamard gate flips the code to its dual and exchanges the X error for the Z error. For a CSS code, each stabilizer generator is either of type X or type Z. (See, for example, Chapter 10 of “Quantum Computation and Quantum Information” by M. Nielsen and I. Chuang (10th Anniversary Edition, ISBN 978-1-107-00217-3, Cambridge University Press, 2010, http: / / mmrc.amss.cas.cn / tlb / 201702 / W020170224608149940643.pdf), which is incorporated by reference as part of the specification of this patent document.)

[0089] The complete QEC procedure can be implemented as follows. At regular time intervals, a syndrome extraction circuit, which includes data qubits and syndrome qubits, is executed. Such a syndrome extraction circuit operates on a sequence of physical qubit gates, performs a “stabilizer measurement,” and produces a readout value from the syndrome qubits. The set of readout values is referred to as the “syndrome.” This syndrome data provides incomplete information about the errors that occurred and is sent to a classical decoder that infers the most likely error that caused the syndrome. The decoder returns a candidate recovery operation, which is then applied to the data qubits.

[0090] Various classical algorithms have been developed to perform efficient and accurate decoding, depending on the code used. Some examples and their implementation details can be found in "Triangular color codes on trivalent graphs with flag qubits" by C. Chamberland et. al., https: / / arxiv.org / pdf / 1911.00355.pdf (2020), "Efficient color code decoders in d ≧ 2 dimensions from toric code decoders" by Kubica and N. Delfosse, https: / / arxiv.org / pdf / 1905.07393.pdf (2019), "Almost-linear time decoding algorithm for topological codes" by N. Delfosse and N. H. Nickerson, https: / / arxiv.org / pdf / 1709.06218.pdf (2017), and "Fault-tolerant error correction with the gauge color" by Brown et al. code" (2015) (https: / / arxiv.org / abs / 1503.08217), which is incorporated by reference as part of the patent specification of this patent document.

[0091] In some implementations, such algorithms may be implemented on a special purpose classical decoder external to the quantum processor. For example, the special purpose decoder disclosed herein may operate at a sufficiently low cryogenic temperature and may be placed in physical proximity to the quantum processor at a desired low cryogenic temperature that allows for minimization of communication delays. As a specific example, the special purpose decoder may be placed at a suitable cryogenic temperature in the range of tens of mK to a few Kelvin, such as 10 mK, 100 mK, 600 mK, 3 K, or 4 K, where the cryogenic temperature of the quantum processor is tens of mK.

[0092] Further details regarding quantum error correction techniques can be found in "Quantum Error Correction for Beginners" by Devitt, SJ, Munro, WJ, Nemoto K., https: / / arxiv.org / pdf / 0905.2794.pdf (2013) and Chapter 10 "Quantum error-correction" in the above-cited 2010 book by Nielsen, M., Chuang, I., http: / / mmrc.amss.cas.cn / tlb / 201702 / W020170224608149940643.pdf (incorporated by reference as part of the patent specification of this patent document).

[0093] A topological error correction code is a stabilizer code in which the qudits follow a fixed physical layout, and the logical qudit space is identified using the second-order homology group of the surface containing the qudits. In this context, each stabilizer generator corresponds to a two-dimensional facet on the surface, called a plaquette.

[0094] Fault-tolerant quantum computation Quantum computing devices and their operation can be characterized by the logical and physical components of the quantum device. The physical components of the device are the actual hardware, including qubits, gates, etc., while the logical components represent the logical functions of the device, such as logical qubits, gates, etc., and refer to the abstract information that is manipulated in the computations performed on the device. As mentioned above, in various implementations, the construction of one logical qubit according to QECC may use multiple physical qubits and physical gates.

[0095] Gate model quantum computation involves not only logical qubits, but also logical components such as qubit preparation, quantum gates, qubit measurement, and waiting (save the state of the qubit), which all act on logical states. Any of these components may fail in operation and introduce errors into the physical state. In that situation, when the number of errors introduced is too large and such errors in the physical state can no longer be corrected by the QECC, the logical state may be erroneous as well.

[0096] Fault-tolerant quantum computation refers to a protocol that implements all of these components in a way that is tolerant to errors, i.e., the logical result of the quantum computation can be made the same as if no faults had occurred, as long as the number of errors introduced is not too large beyond the error correction capabilities of the device. Some information on fault-tolerant quantum computation can be found in "An Introduction to Quantum Error Correction and Fault-Tolerant Quantum Computation" by Gottesman, D., https: / / arxiv.org / pdf / 0904.2557.pdf (2009). Fault tolerance can be essential for useful quantum computing, and building fault-tolerant devices is desirable in building practical quantum computing systems. To achieve fault-tolerant quantum computation, an error-correcting gadget or module can be used to produce a single fault-tolerant logical qubit, and based on this, fault-tolerant gadgets or modules can be provided to correspond to other components of the quantum circuit, such as fault-tolerant arrangements, fault-tolerant gates, etc. Several schemes for fault-tolerant quantum computation have been proposed that use quantum error-correcting codes in various ways. Building and using fault-tolerant gadgets when each logical qubit is itself encoded in a QECC presents architectural challenges.For further details, see "A Game of Surface Codes: Large-Scale Quantum Computing with Lattice Surgery" by Litinski, D., https: / / arxiv.org / pdf / 1808.02892.pdf (2019), "Surface code quantum computing by lattice surgery" by Horsman, C. et al., https: / / arxiv.org / pdf / 1111.4022.pdf (2013), "Fault-tolerant quantum computing with color codes" by Landahl, AJ, Anderson, JT, Rice, PR, https: / / arxiv.org / pdf / 1108.5738.pdf (2011), and "Surface codes: Towards practical large-scale quantum computation" by Fowler, A. et al., https: / / arxiv.org / ftp / arxiv / papers / 1208 / 1208.0928.pdf (2012), which is incorporated by reference as part of the patent specification of this patent document.

[0097] Fault Tolerant Error Correction A suitable error correction gadget for implementing the disclosed technology can include a syndrome extraction circuit implemented as part of a quantum processor and a decoder implemented as part of a classical processor. This is a consequence of the threshold theorem (see arXiv:0904.2557 (2009) by Gottesman, D.) that if the error rate of the syndrome extraction circuit of the physical component falls below a fixed threshold (determined empirically and varying based on the QECC used) and we have a perfect decoder, the failure rate of the error correction gadget can be made arbitrarily small by increasing the code distance of the QECC. A perfect decoder is likely impossible in practice, and the decoding problem becomes more difficult to solve as the code distance is increased. One way to implement a practical decoder is to build a decoder based on a neural network to solve the decoding problem, as illustrated by several examples of such decoders in the paper entitled "Deep neural decoders for near term fault-tolerant experiments" by Chamberland, C., Ronagh, P., arXiv:1802.06441 (2018) (https: / / arxiv.org / abs / 1802.06441), which is incorporated by reference as part of the patent specification of this patent document.

[0098] Recurrent Neural Networks One of the candidates for the decoder's function approximator is a recurrent neural network. This neural network model can have an architecture that is simple enough to build, yet complex enough to fit the training data and thereby accurately mimic the decoder. Recurrent neural networks are a natural approach to dealing with the time series nature of the syndrome measurements.

[0099] The recurrent neural network maintains an internal state vector, which is initialized as a given vector. A single recursion step can be implemented by passing this internal state vector along with the input vector through a first feedforward neural network, which results in a new internal state vector for the recurrent neural network. The extraction step is performed by passing the internal state vector through a second feedforward neural network, which results in an output vector.

[0100] One complete pass through inference using data points containing N rounds of measurements for each syndrome qubit involves N rounds of recursion steps (each using one of the measurement sets), followed by a single extraction step.

[0101] FIG. 1 shows an example of an embodiment of a cryogenic classical superconducting circuit 100 for implementing a decoder portion of an error correction gadget or module based on the disclosed technology in this patent document. The cryogenic classical superconducting circuit 100 is operated at one or more cryogenic temperatures to maintain proper operating conditions for the superconducting circuit inside. The cryogenic classical superconducting circuit 100 may include a quantum error correction code decoder 102. The quantum error correction code decoder 102 includes one or more function approximator modules 104, 106, and 108. The quantum error correction code decoder includes a plurality of nodes, a plurality of interconnections between the nodes of the plurality of nodes for distributing pulses among the nodes, and a plurality of weights. The cryogenic classical superconducting circuit includes mixed signal, digital, and / or analog Josephson junction superconducting electronics that may include magnetic junctions and / or quantum phase slip devices. In operation, such a cryogenic classical superconducting circuit 100 is provided for interfacing with and receiving measurement data of one or more syndrome qudits.

[0102] In one embodiment, the Josephson junction superconducting electronics includes single flux quantum logic. In another embodiment, the Josephson junction superconducting electronics includes adiabatic quantum flux parametron type circuits. In other embodiments, the Josephson junction superconducting electronics includes SQUIDs or Bi-SQUIDs. The Josephson junction superconducting electronics may be built based on one or more suitable digital and mixed signal quantum flux circuits such as ERSFQ, eSFQ, AQFP, RQL, RSFQ, SFQuClass, nSQUID-based, or analog circuits using SQUIDs and Bi-SQUIDs.

[0103] The function approximators 104, 106, or 108 may be implemented in various configurations, such as the function approximator embodiments disclosed herein. One embodiment of such a function approximator may include a mapping from input vectors to output vectors that appears as a logically computable function, possibly with adjustable parameters that determine the underlying mapping. By adjusting the parameters through a process called training, described elsewhere herein, the function approximator can be fitted to a given training data set of input-output pairs, thereby approximating the true function from which the training data was generated. Once trained, the function approximator mapping approximates the true function by matching its behavior on the training data set.

[0104] In one embodiment, the function approximator includes classical logic circuitry that efficiently computes the correspondence between syndromes and errors. In another embodiment, the classical logic circuitry includes a table for mapping syndromes to errors. In another embodiment, the classical logic circuitry can be implemented by using a hash function that implements or approximates this table.

[0105] In another embodiment, the classical logic circuit can be implemented based on a hardware-efficient combination algorithm for calculating the correspondence between syndromes and errors. In one embodiment, such a combination algorithm may include Minimum Weighted Perfect Match (MWPM) as one or more of its subroutines, as illustrated by the example in the 2012 paper entitled "Topological code Autotune" by AG Fowler, et al., https: / / arxiv.org / abs / 1202.6111 (incorporated by reference into the patent specification of this patent document). In another embodiment, the combination algorithm may include a disjoint set (UF) as a subroutine, as illustrated by the example in the paper entitled "Almost-linear time decoding algorithm for topological codes" by N. Delfosse and NH Nickerson, https: / / arxiv.org / abs / 1709.06218 (2017) (incorporated by reference into the patent specification of this patent document).

[0106] In one embodiment, the function approximator can be implemented by including a neural network, as illustrated by the examples in the 2013 book by Nielsen, M. entitled "Neural Networks and Deep Learning" http: / / neuralnetworksanddeeplearning.com / and the book by James, G., Witten D., Hastie T., Tibshirani R entitled "An Introduction to Statistical Learning: with Applications in R" (https: / / link.springer.com / book / 10.1007 / 978-1-4614-7138-7), which are incorporated by reference as part of the patent specification of this patent document.

[0107] The neural network may be of various types, including but not limited to, a deep neural network, which in some embodiments may include convolutional, recurrent, or feedforward units.

[0108] A neural network may have nodes with activation functions such as rectified linear or sigmoid functions.

[0109] In another embodiment, the neural network may be based on a probabilistic graphical model. In one or more embodiments, the probabilistic graphical model may include a Hopfield neural network or a Boltzmann machine.

[0110] In another embodiment, the function approximator includes at least one linear function. In yet another embodiment, the function approximator includes at least one of a regression unit, a classifier, a decision tree, and a random forest. Further details regarding examples of function approximators can be found in the above-referenced book entitled "An Introduction to Statistical Learning: with Applications in R." It should be understood that if the decoder has weights, such weights represent at least one function approximator parameter. In an embodiment in which the function approximator is a neural network, the adjustable parameters may include coefficients of a linear matrix between layers of the neural network. It should be further understood that the function approximator itself may contain multiple function approximators as components within itself.

[0111] 1, the cryogenic classical superconducting circuit 100 may include a pre-processing unit 110 before the decoder 102 to convert the measurement data from the syndrome qudits or qubits into suitable input for the function approximators 104, 106, or 108 for processing. The cryogenic classical superconducting circuit 100 may further include a post-processing unit 112 to convert the output from the function approximators 104, 106, or 108 into a recovery operation.

[0112] Figure 2 shows a schematic diagram of an example function approximator node of a decoder disclosed herein, such as the example decoder of Figure 1. Such a node may, in some implementations, be a node in a neural network.

[0113] Each node 200 in the decoder receives one or more input signals (in1, in2, ..., in n ), a processing core 204 that processes the input signal, and a transmitter section 206 that generates an output representing an output for a node in another layer or the result of the function approximator based on the results of the processing by the processing core 204. In an embodiment in which the function approximator is a deep neural network, the receiver section 202 receives an input signal from a node in a previous layer or from a syndrome extraction circuit.

[0114] In FIG. 2, each node 200 can be considered as three overlapping sections 202 (receiver), 204 (processing core), and 206 (transmitter) with different functionality. The receiver section 202 collects all signals generated from nodes in the preceding layer or syndrome extraction circuits as part of the cryogenic classical superconducting circuit. Each input to a node in a layer of inputs from nodes in the previous layer may be scaled by a corresponding weight. In one or more embodiments, all weighted inputs from nodes in the previous layer are summed together in the receiver and fed to the processing core. The processing core 204 receives the signal from the receiver 202 and applies activation thereon. The activation is implemented by an activation circuit, which maps the input signal to an output signal. This mapping can be in different forms, but is generally mostly nonlinear. In the implementation, some nonlinearity is introduced into the activation circuit for the signal flow. Different forms of nonlinearity such as ReLU (rectified linear activation function unit), sigmoid, and others can be used. In general, in an activation circuit, an input, which in some cases is the sum of all signals from previous nodes weighted by a corresponding weight, is mapped to an output signal that depends on the details of the activation circuit. This mapping is in most cases non-linear in nature. Depending on the desired functionality, the activation circuit may be as simple as a threshold activation circuit, where an output is produced only if the input is above a threshold. In other implementations, the activation circuit may implement more complex mappings, such as ReLU or other functions.

[0115] In a neural network implementation, the nodes in the input layer that interface with the syndrome qudits each have one input to the node receiver 202, which carries the digital information derived from the syndrome measurements. The single weight for all nodes in the input layer may be assumed to be the same, and in some implementations, one. The processing core 204 converts this digital signal arriving at the node receiver 202 into pulses that are fed to the inner layers of the neural network. Thus, each node in the first layer receives a single digital pulse and converts it into pulses that are fed to multiple nodes in subsequent layers. An embodiment of the converter can be based on the SFQ-DC converter disclosed in "Experimental Study of the RSFQ Logic Circuits" by VK Kaplunenko, VP Koshelets, KK Likharev, VV Migulin, OA Mukhanov, GA Ovsyannikov, VK Semenov, IL Serpuchenko, and AN Vystavkin, Extended Abstracts of International Superconductive Electronics Conference (ISEC'87), Tokyo, pp. 127-130 (August 1987), which is incorporated by reference as part of the disclosure of this patent document. In the SFQ-DC converter, the fast SFQ pulses are converted into slow-varying or fixed-amplitude voltage pulses. The slow-varying voltage pulses are more convenient to be processed in a neural network.

[0116] In implementing the disclosed technology, the decoder may be designed to implement different types of activation circuits for different nodes of a layer or different layers. For example, the activations used in the nodes in the hidden layer may be ReLUs, and the activation circuits on the last layer may be threshold detector circuits. In general, different activation functions using different numbers of components, topologies, and working conditions may be implemented.

[0117] An example of an activation function is ReLU. The output of the processing core 204 is fed to the transmitter 206 and broadcasted to the nodes in the next layer. The transmitter 206 is designed so that the signal is strong enough to be transmitted to the next layer. The output of the transmitter 206 can be a single output or multiple outputs, depending on the interconnections in the network. For example, if the signal is fed serially to the next layer, the output is a single line, or alternatively, it can be a parallel output in case of a parallel feed to the next layer. In the transmitter section, an amplifier can be designed to strengthen the signal if necessary.

[0118]

[0031] Referring now to Figure 3, a schematic diagram of an example embodiment of a node receiver section 202 for implementing the node of Figure 2 is shown. This particular example of a receiver section receives at least one pulse comprising a magnetic flux, a current, or a voltage as an input signal. The receiver sections in this example each include an input buffer for storing the input signal, and a signal combining circuit for applying a signal weighting to the received input signal, respectively.

[0119] In operation, receiver section 202 is structured and operated to apply a corresponding weighting to each individual input signal it receives. In one embodiment, the quantum error correction code decoder weightings are applied using fixed signal coupling, which may be achieved by a magnetic coupling circuit, a capacitive coupling circuit, or a resistive coupling circuit as shown. In one embodiment, the fixed magnetic coupling circuit includes transformers 302, 304, or 306, each formed by a pair of magnetically coupled inductors. In this embodiment, the input signals (in1, in2, ..., inn ) are applied with their corresponding weightings by magnetic coupling through different transformers 302, 304, and 306. In such an embodiment, different coupling strengths are used for different input pulses at the transformers to represent the corresponding weightings, and the fixed magnetic coupling is proportional to the corresponding weightings.

[0120] Now referring to FIG. 15, an example embodiment of an input buffer and D flip-flop buffer function with combination to store the input signal is shown. Such an input buffer is added to store and synchronize the weighted combination of different input signals originating from previous nodes. One function of the buffer is to store the input signals and use their individual clock signals (CLK) to control the timing of the input signals to be applied with the weights so that all weighted combinations occur at the same time.

[0121] In one embodiment, the buffer is a D flip-flop buffer 1500 as shown by the circuit shown on the right side of FIG. 15, which includes Josephson junctions J0, J1, and J2, a transformer formed by inductors L1 and L2, and a current source I b An input signal received by junction J0 switches junction J1, generating a magnetic flux that is stored in inductor L1. The stored magnetic flux is then coupled to an associated weight m n After all the input signals have arrived at their corresponding input buffers, a clock signal CLK is applied to Josephson junction J2 in each buffer, switching Josephson junction J2 and resetting the D flip-flop by removing the magnetic flux, preparing it for the next round of pulses.

[0122] It should be understood that the resistive coupling may include a voltage divider. Different coupling strengths may be used for different input pulses in the voltage divider to represent the weighting of the multiple weights. The fixed resistive coupling is proportional to the weighting.

[0123] In another embodiment, the weights of the decoder of the quantum error correction code are applied using variable coupling, which may be magnetic, capacitive or galvanic.

[0124] In one embodiment, the variable magnetic coupling is implemented using a SQUID interposed inside a two-stage transformer as shown in Figure 16. By varying the adjustable current, the amount of magnetic flux deposited in the SQUID is varied. This means that the effective coupling m between L1 and L2 varies depending on the adjustable current. n would make {overscore (x)} a variadic function.

[0125] Now referring to FIG. 4, another embodiment of variable weight implementation is shown. The weight is encoded in the number of generated SFQ pulses. The variable weight is implemented by varying the number of generated SFQ pulses proportionally to the corresponding weight. Still, in a variable coupling embodiment where multiple numbers of SFQ pulses are generated, the Josephson junction superconducting electronic device may include a SQUID. Herein, the number of generated pulses is varied by changing the bias current or critical current of the SQUID. In this embodiment, the variable multi-pulse generator may be implemented in either the transmitting node, the receiving node, or both the transmitting and receiving nodes.

[0126] Referring now to FIG. 5, two embodiments 502 and 504 of variable multi-pulse generators based on adjustable current sources are shown. The variable multi-pulses generated are SFQ pulses. In the multi-pulse generator 502 with two Josephson junctions J0 and J1, the number of output pulses is controlled by using an adjustable current source. In the multi-pulse generator 504 with Josephson junction J0, a SQUID, and a current source, the number of output pulses is controlled by adjusting the critical current of the SQUID using an external magnetic field from an inductor magnetically coupled to the SQUID.

[0127] It should be appreciated that a variable weighting implementation allows for programmable weighting that can be adjusted as a result of training.

[0128] 2, processing core 204 implements an activation function for node 200. Different activation functions, such as sigmoid and rectified linear unit (ReLU), may be implemented using different values ​​of circuit parameters, including junction shunts and different numbers of Josephson junctions, and different topologies.

[0129] Now referring to FIG. 6, an embodiment of a node processing core 204 with a threshold-based activation function is shown. The activation circuit here functions like a soft binary step function: if the input is above a certain threshold, the output is a digital high, and if the input is below a certain threshold, the output is a digital low. In the decoder, based on the value of the input, the output of each node is a digital pulse that is fed to an error correction circuit. In one embodiment, a simple threshold comparator is used to implement the sigmoid function. In this embodiment, the processing core 204 includes two Josephson junctions J0 and J1 that are coupled to a current source to generate an output pulse based on a threshold. Specifically, in this embodiment, if the combined amplitude of the input pulse and the bias current from the current source exceeds the critical current of the Josephson junction J1, the Josephson junction J1 switches, thus generating one pulse to the output.

[0130] In some embodiments, the processing core 204 includes at least one superconducting storage loop 602 (inductor L coupled to an input) for storing magnetic flux. storage ). The storage loop 602 receives a signal from the receiver section 202 and outputs an associated signal based on the stored values.

[0131] Referring now to FIG. 7A, a rectified linear unit (ReLU) activation function using a SQUID and an adjustable bias current source I bAn embodiment of the node processing core 204 of FIG. 2 is shown with: The transfer function of the SQUID approximates a rectified linear unit (ReLU) function to a first order. Here, Lp represents the effective inductance of the input inductor in the receiver section, and another inductor is coupled to the SQUID with an adjustable critical current I t , from which the signal emanates and enters the processing core of the node through magnetic coupling. b determines the functionality of the rectified linear unit (ReLU) function and adjusts the adjustable critical current I t is used to determine the threshold for the Rectified Linear Unit (ReLU). If the input is less than the given threshold, no output is generated, whereas if the input signal is less than I t When the signal exceeds a threshold set by, a variable number of SFQ pulses are generated depending on the strength of the signal. The number of output pulses per unit time (pulse rate or average output dc voltage) is determined by a rectified linear unit (ReLU) function. b and I t By adjusting , a working curve on the transfer function can be selected.

[0132] Referring now to FIG. 7B, another embodiment of a node processing core with a rectified linear unit (ReLU) activation function is shown, using a Bi-SQUID to replace the SQUID of FIG. 7A to achieve a highly linear flux vs. voltage characteristic. The functionality of the Bi-SQUID is similar to the SQUID, with the difference that it may better approximate the rectified linear unit (ReLU) function. The transfer function of the Bi-SQUID shows a linear region that may be exploited for the linear section of the rectified linear unit (ReLU) function. The functionality of the circuit is similar to the SQUID version above. Here, Lp represents the effective inductance in the receiver section from which the signal emanates and enters the node processing core through magnetic coupling. Adjustable current source I b determines the functionality of the rectified linear unit (ReLU) function and adjusts the adjustable critical current I tis used to determine the threshold for the Rectified Linear Unit (ReLU). If the input is less than the given threshold, no output is generated, whereas if the input signal is less than I t When the signal exceeds a threshold set by, a variable number of SFQ pulses are generated depending on the strength of the signal. The number of output pulses per unit time (pulse rate or average output dc voltage) is determined by a rectified linear unit (ReLU) function. b and I t By adjusting , a working curve on the transfer function can be selected.

[0133] Referring now to FIG. 8, two embodiments of clearing the stored flux and resetting the circuit for the node processing core 204 are shown. Emptying the flux stored in the storage loop resets the circuit and prepares the node for the next input. In embodiment 802, the flux is cleared using a load resistor 806 with a matching impedance, and the stored flux decays with a time constant L1 / R, where L1 is the total inductance in series with the resistor. In another embodiment 804, the flux is cleared by using a SQUID with external flux control. By applying an external flux reset signal, the critical current of the SQUID is reduced, which can drive the SQUID to a normal state. In the normal state, the stored flux decays and prepares the circuit for the next round of decode pulses.

[0134] Referring again to FIG. 2, the transmitter section 206 is responsible for connecting the output of a node to the receiver section of a node in the next layer or to an output representing the function approximator result. Various connection schemes may be implemented, such as the examples in FIGS. 9 and 10. In one embodiment, the interconnection is a direct one-to-one interconnection. In another embodiment, the interconnection is implemented using buses and different methods of parallelization and serialization to reduce the number of interconnections. An example of a full serial interconnection is shown in the example in FIG. 10, where a single line is coupled with multiple inductors that magnetically couple one node in one layer to an inductor implemented in a node in the next adjacent layer. An example of a direct one-to-one interconnection between nodes of two adjacent layers is shown in FIG. 9, where the output of each node in one layer may be distributed to different nodes in the next layer using various methods. In one embodiment of a direct one-to-one connection, the output of each node is distributed using a tree of SFQ pulse splitters to generate enough pulses for all receive modes. The splitters generate identical copies of the input SFQ signal. Binary splitters, which produce two outputs for each input, are the most commonly used splitters. In a full series interconnection, the output current pulse couples to all receiver nodes and terminates to ground through resistors.

[0135] In one embodiment, Josephson transmission lines (JTLs) or passive transmission lines (PTLs) are used for the transfer of SFQ signals between the nodes. JTLs use active Josephson junction elements for the transfer of SFQ pulses. PTLs use passive microwave lines for the transfer of SFQ or current or voltage signals. In another embodiment, the pulse signals can be converted to optical and converted back to electrical signals for interconnection between the nodes. Diodes or other low energy photon generating techniques may be used to convert electrical pulses to photon pulses. Superconducting nanowire single photon detectors (SNSPDs) or other low energy photon detectors may be used to convert photon pulses to electrical pulses. In an embodiment involving photonic interconnects, low loss optical waveguides are used for the propagation of light, and photon sources and detectors are efficiently coupled to the photonic waveguides.

[0136] Various interconnection schemes may be implemented. Referring now to FIG. 10, an embodiment of an interconnection scheme is shown. In this embodiment, each transmitting node includes a driver for all receiving nodes in a fully serial manner using a single PTL line (e.g., magnetic coupling via inductors as shown) that is coupled to different nodes in the next layer. Each receiving node couples to this line using its coupler (fixed or variable). Furthermore, each receiving node couples to all such lines from all transmitting nodes. Multiple received signals from different transmitting nodes are summed at each receiving node. The connections 1010-1026 may be of various types. In one embodiment, the connections 1010-1026 are electrical, such as SFQ splitters. In another embodiment, the connections 1010-1026 are magnetic coupling using transformers. In yet another embodiment, the connections 1010-1026 include capacitive coupling.

[0137] Now referring to FIG. 11, an embodiment of the connectivity between nodes in two successive layers is shown, using parallelizers and serializers to reduce the number of interconnect wires. It should be understood that a combination of direct interconnection between nodes, serialization, and parallelization can be used. The serializer is a serial-to-parallel converter circuit that serially reads the output from each node at the transmitting node where the signal originates. The data output of the serializer is then transmitted serially to the receiving node. At the receiving node, the information is parallelized using a serial-to-parallel converter, which will be fed to the corresponding input with the associated weighted combination. The parallelizer is a parallel-to-serial converter.

[0138] It should be understood that the signals may need to be amplified at different stages of the decoder. For example, in one embodiment, the signal of each node after the activation function may be amplified using an amplifier. In one or more embodiments, the amplifier may be implemented by using multiple Josephson junctions, such as SQUIDs or biSQUIDs. FIG. 17 shows examples of implementations of amplifiers at various locations relative to the node, namely, an amplifier placed at the input of the node receiver 202 of FIG. 2, an amplifier in the node processing core 204 and the node transmitter 206 of FIG. 2. The amplifiers may be of various types. Each amplifier may be single or multiple stages.

[0139] An embodiment of an amplifier with multiple SQUIDs in series is shown in Figure 18. Each SQUID in this example of Figure 18 may be replaced with a biSQUID or other suitable SQUID variant. Feedback mechanisms, such as those illustrated by the example of a feedback circuit of a series inductor coupled to a SQUID in Figure 18, may be designed to change the linearity, dynamic range, and / or other characteristics of the amplifier.

[0140] It should be understood that different operating modes for different nodes and different sections thereof, i.e., analog, digital, and hybrid analog-digital designs, can be envisioned. In one or more embodiments where the nodes are organized in layers, the nodes in the inner layers work in analog mode, while the receiver sections of the nodes in the first (input) layer and the transmitter sections of the nodes in the last (output) layer work in digital mode. In particular, the receiver sections 202 of the nodes in the input layer receive digital signals and convert them to analog signals to be used in the inner layers. The nodes in the output layer receive analog signals and generate and transmit digital signals as the output of the decoder. In one or more alternative embodiments, the nodes in the inner layers work in digital mode or analog-digital hybrid mode. It should be understood that the decoder can be of various types, such as the decoder 102 described elsewhere herein with respect to FIG. 1. In one or more embodiments, the output of the decoder is fed to a post-processing unit 112, which converts the output from the function approximator into a recovery operation.

[0141] It should be understood that the interconnections between the nodes can be analog or digital (i.e., patterns of SFQ signals). In one or more embodiments, the signals between the nodes are converted to digital and then transmitted digitally between the nodes. In other embodiments, the signals are analog voltage or current signals. In alternative embodiments, hybrid combinations may be envisioned. The information communicated between the nodes may be encoded in the number of SFQ pulses (digital) or in the shape of pulses of different amplitudes and lengths (analog).

[0142] In the analog embodiment shown in Figure 19, the inputs from the nodes in the previous layer are summed with different weights and magnetically coupled to an activation function circuit, which may be a SQUID, biSQUID, or a variation thereof. The activation function circuit is designed such that the voltage is modulated by the magnetic flux generated at the node receiver section. The output resistor R out This voltage acting on generates an output current that can be fed to a node in the next layer.

[0143] The decoder system may be operated synchronously and asynchronously depending on whether the system is analog, digital or hybrid in design.

[0144] In one or more embodiments, the signal propagates between nodes, and at each node the signal is processed with different weights and then passed through an activation function, and the resulting signal also propagates asynchronously to the next layer. Synchronous or asynchronous operation may be used for different components. For example, the receiver section of the node in the input layer that receives the digital signal and the transmitter section of the node in the output layer that generates the digital signal may be operated synchronously, while the nodes in the inner layers may operate asynchronously.

[0145] Referring now to FIG. 12, an embodiment of a quantum correction gadget or module 1200 is shown. The quantum correction gadget 1200 may include one or more syndrome extraction circuits designed to perform quantum error correction operations. The quantum processor 1210 also includes physical qubits or qudits for performing quantum computation operations, for which the quantum error correction operations are provided. The quantum correction gadget 1200 further includes a separate cryogenic classical superconducting circuit 1214 that contains a decoder as shown in FIG.

[0146] The quantum processor 1210 may be of various types. In some implementations, such quantum processors use the properties of entangled qudit or qubit devices to perform computational tasks. In certain regions where quantum mechanics operates, particles of matter can exist simultaneously in multiple states, known as a superposition of states. Two or more qudits or qubits that exist in a superposition of states can be entangled together. In embodiments where the qudits include qubits with two quantum states 0 and 1, respectively, entanglement means that the qubits in the superposition can be correlated with each other in a non-classical way, i.e., the state of one (whether it is 1 or 0 or both) can depend on the state of another, and there is more information that can be ascertained about two qubits when they are entangled than when they are treated individually. A system of two or more entangled qudits can be manipulated via quantum interference as part of quantum processing. Where binary computing is limited to using only on and off states (equivalent to 1 and 2 in binary code), the quantum processor utilizes these quantum states of matter to output signals that are usable in data computing. The quantum processor 1210 may include a plurality of qudits, comprising at least one data qudit and at least one syndrome qudit that represents an error-correcting code. The plurality of qudits includes an error-correcting code. The error-correcting code may be of different types, such as any of the types described herein. In one embodiment, the error-correcting code includes a topological error-correcting code, such as a toric code, a surface code, a rotated surface code, a color code, or a triangular color code.

[0147] 12, a qudit readout circuit is provided that is coupled to a quantum processor 1210 to interact with the qudits, perform measurements on the qudits, and provide measurement data. Such a qudit readout circuit may be implemented in a variety of configurations, including the readout circuit disclosed in U.S. Patent No. 9,692,423, entitled "System and method for circuit quantum electrodynamics measurement," by inventors McDermott et al., https: / / patents.google.com / patent / US9692423B2 / en?oq=9692423 (which is incorporated by reference into the specification of this patent document).

[0148] In connection with the operation of quantum correction gadget 1200, a portion of the qudit readout circuitry that is coupled to interact with the syndrome qudits in quantum processor 1210 is used to perform measurements on the syndrome qudits without directly performing measurements on the data qudits to provide measurement data for quantum error correction operations. Cryogenic classical superconducting circuitry 1214 includes the decoder of FIG. 1 that receives the measurement data from reading out the syndrome qudits, processes the received information in the measurement data, obtains information regarding errors in the quantum computing performed by the quantum processor, and generates recovery operations to reconstruct the quantum information of the qudits and reduce errors in the quantum computing.

[0149] The quantum correction gadget 1200 may include a cryogenic device 1212 designed to provide different cryogenic stages at different cryogenic temperatures. The quantum processor 1210 is cooled by the cryogenic device 1212 at a desired or suitable low cryogenic temperature for operating the qudits. In some implementations, the cryogenic classical superconducting circuit 1214 containing the decoder may be separated from the quantum processor 1210 and kept in the cryogenic device 1212 at a higher cryogenic temperature than that of the quantum processor 1210, such as 100 mK, 600 mK, 3 K, or 4 K. In other implementations, the cryogenic classical superconducting circuit 1214 containing the decoder may be kept in the cryogenic device 1212 at the same cryogenic temperature (e.g., tens of mK) in the same cryogenic stage as the quantum processor 1210. The cryogenic device 1212 may be of various types. In one embodiment, the cryogenic device 1212 includes a cryogenic platform capable of reaching the required low temperatures for the operation of the qudits. In another embodiment, the cryogenic device 1212 includes a dilution refrigerator system with different cryogenic stages at different temperatures.

[0150] In another embodiment, the cryogenic device 1212 includes a cryocooler system. In another embodiment, the cryogenic device 1212 includes an adiabatic demagnetizing refrigerator.

[0151] The cryogenic classical superconducting circuit 1214 with one or more decoders as part of the quantum correction gadget 1200 may be implemented by a variety of suitable cryogenic classical superconducting circuits, including, for example, the cryogenic classical superconducting circuit 100 of FIG. 1.

[0152] The cryogenic classical superconducting circuit 1214 may be structured and coupled to the quantum processor 1210 to act as a classical co-processor to the quantum processor 1210. The cryogenic classical superconducting circuit 1214 is cooled by an identical cryogenic device 1212, which allows for minimization of communication delays (or latency) between the quantum processor 1210 and the cryogenic classical superconducting circuit 1214. It should be understood that information travels at the speed of electromagnetic waves in a medium that is a finite value. Reducing the travel distance between modules reduces communication delays.

[0153] The cryogenic classical superconducting circuit 1214 includes at least one function approximator for at least one decoder 1216 of the quantum error correction code. The function approximator for the decoder 1216 of the quantum error correction code may be of various types, such as any function approximator disclosed elsewhere herein. The decoder 1216 of the quantum error correction code may be of various types, such as any decoder disclosed elsewhere herein.

[0154] The quantum correction gadget 1200 may include logical qudits. The logical qudits include a classical quantum interface between the cryogenic classical superconducting circuit 1214 and the quantum processor 1210. It should be understood that the logical qudits include a quantum error correction scheme including at least one data qudit and at least one syndrome extraction circuit. Each syndrome extraction circuit includes at least one syndrome qudit. The operation of the error correction scheme includes at least (1) at least one iteration of each syndrome extraction circuit, which includes preparing a syndrome, executing a gate, and measuring the syndrome, (2) communicating the measurement readout to a decoder, (3) the decoder proposing a recovery operation, and (4) the recovery operation can either be immediately applied to the data qudit or stored for later use.

[0155] Quantum corrector gadget 1200 may include n copies of the logical qudits disclosed herein.

[0156] In an embodiment of the topological error correction code, the data qudits are laid out on a surface that includes one or more faces, called a plaquette, with each plaquette including one or more syndrome extraction circuits.

[0157] 13, a flow chart of an embodiment of a method for implementing a quantum error correction scheme using the quantum correction gadget 1200 illustrated in FIG 12 is shown. The method includes the operation of logical qudits as disclosed herein.

[0158] According to process step 1302, at least one syndrome qudit is provided and prepared to perform a quantum measurement for a quantum error correction operation. It should be understood that the at least one syndrome qudit may be prepared in various ways. In an embodiment in which the at least one syndrome qudit includes at least one syndrome qubit, the preparation includes applying energy to the qudit, e.g., via microwave photons, to place it in a superposition of two or more of its states. The qubit in this state can then be entangled with other qudits in the processor, e.g., one or more data qudits. Entanglement between qudits can be induced by having them interact together in such a way that the final states of the qudits are mutually dependent. For example, entanglement between two superconducting qudits can be induced by frequency tuning the qudits to resonate with each other and coupling via capacitance for a fixed time, resulting in a state-dependent relative phase shift. In embodiments in which the at least one syndrome qudit comprises at least one multilevel quantum system, the preparation may include the same methods as described above.

[0159] According to the processing operation 1304, a syndrome extraction circuit is implemented. The syndrome extraction circuit includes at least one data qudit and at least one syndrome qudit. The operation of each syndrome extraction circuit includes at least (1) preparation of one or more syndrome qudits in a desired initial state, (2) application of a two-qudit gate such as CNOT (in a qubit embodiment) between pairs of data qudits and syndrome qudits, and (3) measurement of the syndrome in a desired basis. Figure 3 of arXiv:1802.06441 (2018) by Chamberland, C., Ronagh, P. depicts a syndrome extraction circuit for a rotating surface code. Figure 3 of arXiv:1911.00355 (2020) by Chamberland, C. et al. depicts a syndrome extraction circuit for a triangle color code.

[0160] Still referring to FIG. 13, according to process step 1306, at least one measurement is performed on at least one syndrome qudit for each of the at least one syndrome extraction circuit.

[0161] According to process step 1308, if the stopping criterion is met, the method proceeds to process step 1310. If the stopping criterion is not met, process steps 1304 and 1306 are repeated. It should be understood that the stopping criterion can be of various types. In one embodiment, the stopping criterion is that process steps 1304 and 1306 have been repeated a fixed predetermined number of times.

[0162] 13, in accordance with process step 1310, a result of the at least one measurement is provided to a function approximator of a decoder of a quantum error correction code. A cryogenic classical superconducting circuit is operated to implement the function approximator to obtain a result corresponding to the at least one measurement.

[0163] According to process step 1312, a recovery operation is provided using the function approximator. The recovery operation includes a recovery operator.

[0164] In accordance with processing step 1314, a recovery operation is applied. It should be understood that the recovery operator can be of various types. In one embodiment, the recovery operator is a unitary operator that is applied to the error-correcting code. The recovery operator may include a separate unitary operation on each individual data qubit, for example a single-qubit Pauli X, Y, or Z operation. In an alternative embodiment, the recovery operator additionally includes a change of basis on the Pauli frame. Subsequent gates are passed through this change of basis before being applied, until some future time step when the unitary operator is applied.

[0165] 14, an embodiment of a method for constructing a function approximator for a decoder of a quantum error correction code is shown. It should be understood that the function approximator can be of various types, such as any of the function approximators disclosed elsewhere herein. The function approximator may be any suitable function approximator, such as any of the function approximators described herein with respect to FIG.

[0166] In accordance with process step 1402, data is collected for at least one syndrome qudit and for a corresponding error from the error correction code. It is understood that the data may be collected from a simulation of the qudit being plagued by a noise channel. It is further understood that the noise channel may include a Pauli noise channel (in a qubit embodiment), which may be depolarizing or dephasing. In one embodiment, the data is collected from a simulation of a plurality of qudits performing a logical operation. In an alternative embodiment, the data is collected from experimental data, which includes data from qudits at rest, data from qudits performing logical measurements, and data from logical gates.

[0167] Still referring to FIG. 14, according to processing step 1404, a function approximator is constructed using collected data for at least one syndrome qudit and collected data for the corresponding error. In embodiments where the function approximator comprises a neural network, it is understood that constructing the function approximator comprises training the neural network. It is understood that constructing the function approximator may include modifications to accurately model hardware constraints. In one or more embodiments, the modifications may include digitizing input and output signals, activation functions such as rectified linear units (ReLUs) and sigmoids, and converting tunable parameters to 8-bit precision. In embodiments where the function approximator comprises a neural network, specialization techniques exist for training neural networks with such modifications.(For further details, see Courbariaux, M., Hubara, I., Soudry, D., El-Yaniv, R., and Bengio, Y., "Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1," arXiv:1602.02830 (2016); Courbariaux, M., Bengio, Y., and David JP, "Training deep neural networks with low precision multiplications," arXiv:1412.7024 (2015); Gupta, S., Agrawal, A., Gopalakrishnan, K., and Narayanan, P., "Deep Learning with Limited Numerical Precision," arXiv:1502.02551; and Jacob, B. et al., "Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference” arXiv:1712:05877 (2017), which is incorporated by reference as part of the patent specification of this patent document.

[0168] Example of Collecting Data Data points are generated via simulation for the purpose of training the function approximator and benchmarking the theoretical error rate of the QEC procedure. The generation of a single data point is as follows. The process for a Z-stabilizer type syndrome extraction circuit and measurement circuit is described below, which is similar for an X-stabilizer circuit. Herein, the code distance d is fixed. Every qubit measurement results in a 0 or 1 readout, so the input coordinates are two-dimensional 0-1 arrays of size (N_rounds, #syndrome qubits), while the output coordinates are one-dimensional 0-1 arrays of size (#data qubits). A parameter N_rounds is chosen. A quantum circuit is constructed in a simulation, which in turn includes: Preparation of a data qubit in the |0> state. · N_ round iterations of the Z stabilizer circuit as shown in Figures 3 and 4 of the Chamberland paper referenced above. The quantum circuit above is passed through a depolarized noise channel to generate a noisy version of the circuit. The depolarized noise channel is given five separate parameters for the noise strength associated with the qubit preparation, the one-qubit gate, the two-qubit gate, the idle qubit, and the qubit measurement. This noisy circuit is then run in a simulation, resulting in a sequence of N_round measurement readouts for each syndrome qubit. This array of size (N_rounds, #syndrome qubits) is the input coordinates of the data points. · The data qubits are fully measured at the end of the noisy circuit. A readout vector of size (#data qubits) is the output coordinates of the data points.

[0169] The above process is repeated multiple times with different random number seeds used for the depolarization noise channel and different random number seeds used for the circuit implementation to obtain a large number of data points.

[0170] Thus, various implementations of the features of the disclosed technology can be made based on the above disclosure, including the examples listed below.

[0171] Example 1. A cryogenic classical superconducting circuit operating at cryogenic temperatures including a function approximator for a decoder of a quantum error correction code, the decoder comprising a plurality of nodes, a plurality of interconnections between the nodes of the plurality of nodes for distributing pulses among the nodes, and a plurality of weights representing function approximator parameters, each node of the plurality of nodes comprising a receiver section for receiving at least one pulse comprising a magnetic flux, current, or voltage, a processing core for processing the received pulses, and a transmitter section for transmitting the processed pulses.

[0172] Example 2. A cryogenic classical superconducting circuit as described in Example 1 including mixed-signal digital and analog Josephson junction superconducting electronics with magnetic junctions and quantum phase slip devices.

[0173] Example 3. Josephson junction superconducting electronics include cryogenic classical superconducting circuits as described in Example 2, including digital and mixed-signal quantum flux families, including energy efficient fast single flux quantum (ERSFQ), energy efficient single flux quantum (eSFQ), adiabatic quantum flux parametron (AQFP), inverse quantum logic (RQL), fast single flux quantum (RSFQ), SFQuClass, or superconducting quantum interface devices (SQUID, Bi-SQUID, nSQUID).

[0174] Example 4. The cryogenic classical superconducting circuit of examples 1-3, wherein each node is configured to operate in an analog, digital, or analog-digital mode.

[0175] Example 5. The cryogenic classical superconducting circuit of example 4, wherein the nodes are arranged in layers, and further wherein the receiver sections of the nodes in the first layer and the transmitter sections in the last layer operate in a digital mode, and the nodes in the other layers operate in an analog mode.

[0176] Example 6. The cryogenic classical superconducting circuit of example 1, wherein the nodes are coupled by interconnects that are analog, digital, or hybrid analog and digital.

[0177] Example 7. The cryogenic classical superconducting circuit of example 1, wherein the nodes are coupled by interconnects that are operated synchronously or asynchronously.

[0178] Example 8. The cryogenic classical superconducting circuit of example 1, wherein the decoder further comprises at least one amplifier for amplifying the signal.

[0179] Example 9. The cryogenic classical superconducting circuit of example 1, wherein at least one of the plurality of weights comprises a fixed coupling, comprising a magnetic coupling, a capacitive coupling, or a resistive coupling.

[0180] Example 10. The cryogenic classical superconducting circuit of example 1, wherein at least one of the plurality of weights comprises a variable coupling, comprising a magnetic coupling, a capacitive coupling, a galvanic coupling, or a resistive coupling.

[0181] Example 11. The cryogenic classical superconducting circuit of example 9, wherein the magnetic coupling comprises a transformer, and further wherein different coupling strengths are used for different input pulses at the transformer to represent a weighting of a plurality of weights, and further wherein the fixed magnetic coupling is proportional to the weighting.

[0182] Example 12. The cryogenic classical superconducting circuit of example 9, wherein the resistive coupling comprises a voltage divider, and further wherein different coupling strengths are used for different input pulses at the voltage divider to represent a weighting of the multiple weights, and further wherein the fixed resistive coupling is proportional to the weighting.

[0183] Example 13. The cryogenic classical superconducting circuit of example 10, wherein the weighting of the plurality of weights is expressed via at least one of the steps of generating a number of single flux quantum (SFQ) pulses proportional to the weighting, generating a pulse rate proportional to the weighting, and generating a pulse intensity proportional to the weighting.

[0184] Example 14. The cryogenic classical superconducting circuit of example 2, wherein the Josephson junction superconducting electronic device comprises a superconducting quantum interface device (SQUID), and at least one of the number of generated pulses, the pulse rate, or the pulse intensity is varied by varying the bias current or the critical current of the superconducting quantum interface device (SQUID).

[0185] Example 15. The cryogenic classical superconducting circuit of example 9, wherein the processing core comprises at least one storage loop for storing the magnetic flux, and the magnetic flux is erased using a command pulse, which may be a resistor, a SQUID, or a clock.

[0186] Example 16. The cryogenic classical superconducting circuit of example 1, wherein an interconnection between two nodes of the plurality of nodes is electrical, magnetic, or photonic.

[0187] Example 17. A cryogenic classical superconducting circuit as described in any of claims 1-16, wherein the interconnection between at least two nodes of the plurality of nodes is in parallel or in series.

[0188] Example 18. The cryogenic classical superconducting circuit of any of Examples 1-16, wherein an interconnection between two nodes of the plurality of nodes is electrical using a Josephson transmission line (JTL) or a passive transmission line (PTL).

[0189] Example 19. The cryogenic classical superconducting circuit of example 1, wherein the pulses between the nodes are generated using line drivers, each generating at least one pulse.

[0190] Example 20. The cryogenic classical superconducting circuit of example 1, wherein the function approximator for a decoder of a quantum error correction code comprises a neural network, further wherein the neural network parameters and activations are represented by decoder nodes and weights, further wherein the neural network activations are implemented using node processing cores.

[0191] Example 21. The cryogenic classical superconducting circuit of example 20, wherein the activation comprises sigmoid and rectified linear unit (ReLU) activation functions.

[0192] Example 22. The cryogenic classical superconducting circuit of example 20, wherein the neural network comprises a recurrent neural network, a deep neural network, a feedforward neural network, a convolutional neural network, a Hopfield network, a Boltzmann machine, or a graphical model.

[0193] Example 23. The cryogenic classical superconducting circuit of example 1, wherein the function approximator for the decoder of the quantum error correction code comprises at least one neural network and at least one linear function approximator.

[0194] Example 24. The cryogenic classical superconducting circuit of example 1, wherein at least one weighting of the plurality of weightings is programmable.

[0195] Example 25. The cryogenic classical superconducting circuit of example 1, wherein the function approximator is programmable using input from a user.

[0196] Example 26. The cryogenic classical superconducting circuit of example 1, wherein the function approximator for the decoder of the quantum error correction code comprises a regression unit, a classifier, a decision tree, or a random forest.

[0197] Example 27. A system capable of quantum error correction for quantum computing, comprising a cryogenic device structured to include different cryogenic stages at different cryogenic temperatures, and a quantum processor comprising a plurality of qudits for performing quantum computing, coupled to and cooled by the cryogenic device at a desired cryogenic temperature for proper operation of the qudits, the plurality of qudits comprising data qudits for encoding quantum information for quantum computing, and syndrome qudits for interacting with the data qudits and providing measurements, the plurality of qudits comprising a plurality of qudits for correcting quantum errors, and a cryogenic classical superconducting circuit coupled to and cooled by a cryogenic device, further coupled to receive information about the measurements from the syndrome qudits, the cryogenic classical superconducting circuit including a decoder for the quantum error correction code, processing the received information about the measurements from the syndrome qudits, and generating recovery operations for the data qudits, and structured to reduce errors in quantum computing, wherein the cryogenic classical superconducting circuit is coupled to the quantum processor as a classical co-processor, reducing communication delays between the quantum processor and the cryogenic classical superconducting circuit.

[0198] Example 28. The system of example 27, wherein the error correction code is a topological error correction code.

[0199] Example 29. The system of example 27, wherein the error correction procedure on the topological error correction code comprises a parity check operation on a plurality of qudits comprising a plaquette.

[0200] Example 30. The system of example 28, wherein the topological code comprises a toric code, a surface code, a rotated surface code, a color code, a triangular color code, or a bihexagonal code.

[0201] Example 31. The system of example 27, wherein the cryogenic device comprises a cryogenic platform capable of reaching the required temperature for operation of the qudits.

[0202] Example 32. The system of example 27, wherein the cryogenic device comprises a dilution refrigerator system, a cryocooler system, or an adiabatic demagnetization refrigerator.

[0203] Example 33. A method for implementing a quantum error correction scheme using the system described in Example 27, comprising: (i) preparing at least one syndrome qudit; (ii) implementing at least one syndrome extraction circuit comprising at least one data qudit and at least one syndrome qudit; (iii) performing at least one measurement on the at least one syndrome qudit of each syndrome extraction circuit; (iv) providing a result of the at least one measurement to a function approximator of a detector; (v) providing a recovery operation comprising a recovery operator using the function approximator of a decoder; and (vi) applying the recovery operation.

[0204] Example 34. The method of example 33, wherein the recovery operator is a unitary operator applied to the error-correcting code.

[0205] Example 35. The method of example 33, wherein the recovery operator is a change of basis on the Pauli frame.

[0206] Example 36 The method of example 33, wherein the recovery operator is an equivalence operator.

[0207] The method of Example 33, wherein steps (ii)-(iv) in Example 37 are repeated at least once.

[0208] Example 38. A method for constructing a function approximator for a decoder of the system described in Example 27, comprising the steps of collecting data for at least one syndrome qudit and for a corresponding error from an error correction code, and constructing the function approximator using the collected data for the at least one syndrome qudit and the collected data for the corresponding error.

[0209] Example 39.(b) is the method of example 38, further comprising training a neural network.

[0210] Example 40. The method of example 38, wherein the data is collected from a simulation of a qudit beset by a noisy channel.

[0211] Example 41. The method of example 40, wherein the noise channel comprises a Pauli noise channel, and further wherein the Pauli noise channel is depolarized or dephasing.

[0212] Example 42. The method of example 38, wherein the data is collected from a simulation of a plurality of qudits performing a logical operation.

[0213] Example 43. The method of example 38, wherein the data is collected from experimental data, the experimental data comprising data from qudits at rest, data from qudits performing logical measurements, and data from logic gates.

[0214] Example 44. The system of Example 27 for fault-tolerant quantum computing, comprising a plurality of logical qudits, each of which comprises a classical-quantum interface between a cryogenic classical superconducting circuit and a quantum processor, the logical qudits comprising a quantum error correction scheme, and the plurality of logical qudits are for performing quantum computing.

[0215] Example 45. The system of example 27, wherein the quantum processor comprises at least one syndrome extraction circuit.

[0216] Example 46. The system of example 27, wherein the cryogenic classical superconducting circuit and the quantum processor are coupled to different cryogenic stages of a cryogenic device and are therefore cooled at different cryogenic temperatures.

[0217] Example 47. The system of example 27, wherein the cryogenic classical superconducting circuit and the quantum processor are coupled to a common cryogenic stage of a cryogenic device and are therefore cooled at a common cryogenic temperature.

[0218] Example 48. A quantum computing system comprising: a quantum processor comprising a plurality of physical qudits, each capable of assuming a different quantum state, the plurality of physical qudits being structured to perform quantum computing, the plurality of physical qudits comprising a plurality of data qudits for performing quantum computing, and a plurality of syndrome qudits located between the data qudits to interact with the data qudits and provide measurements of the quantum states of the syndrome qudits indicative of quantum errors in the quantum processor; a qudit readout circuit coupled to the quantum processor to interact with the syndrome qudits and produce a readout signal representative of the measurements of the quantum states of the syndrome qudits; and 1. A quantum computing system comprising: a cryogenic classical superconducting circuit coupled to receive information in a readout signal representing a measurement of a quantum state of a qudit, the cryogenic classical superconducting circuit being structured to include a decoder that processes the received information, obtains information regarding quantum errors in the quantum processor, and generates a recovery operation to reconstruct the quantum information of the qudit and reduce the quantum errors; and a cryogenic system coupled to encapsulate the quantum processor, the qudit readout circuit, and the cryogenic classical superconducting circuit, respectively, at a desired cryogenic temperature, the cryogenic classical superconducting circuit and the quantum processor being positioned relative to each other to enable high speed communication between the cryogenic classical superconducting circuit and the quantum processor with reduced communication delays.

[0219] Example 49. The system of example 27 or 48, comprising a neural network, wherein the decoder in the cryogenic classical superconducting circuit includes a plurality of nodes coupled to form different layers of nodes as part of the neural network, and a plurality of interconnections between the nodes of the different layers of nodes to provide signaling between the nodes of the different layers of nodes, each node structured to apply a weighting to the signaling between the nodes of the different layers of nodes.

[0220] Example 50. The system of example 27 or 48, wherein the cryogenic classical superconducting circuit is configured as described in any one of examples 1-26.

[0221] Example 51. The system of example 48, wherein the quantum processor is operable to prepare syndrome qudits in a desired initial state and induce quantum mechanical interactions between the data qudits and the syndrome qudits, and the qudit readout circuitry is operated to obtain measurements of the syndrome qudits in a desired basis.

[0222] Example 52. The system of example 48, wherein the cryogenic classical superconducting circuit and the quantum processor are coupled to different cryogenic stages of the cryogenic device and are therefore cooled at different cryogenic temperatures.

[0223] Example 53. The system of example 48, wherein the cryogenic classical superconducting circuit and the quantum processor are coupled to a common cryogenic stage of a cryogenic device and are therefore cooled at a common cryogenic temperature.

[0224] Publications, patents, and patent applications cited in this patent document are incorporated herein by reference to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference. To the extent that the publications and patents or patent applications incorporated by reference conflict with the disclosure contained herein, the present specification is intended to supersede and / or have priority over any such conflicting material.

[0225] Although this patent document contains many details, these should not be interpreted as limitations on the scope of any subject matter or content that may be claimed, but rather as descriptions of features that may be specific to certain embodiments of a particular technique. Certain features described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Also, although features may be described above as acting in a combination and even initially claimed as such, one or more features from a claimed combination may in some cases be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0226] Only some implementations and examples have been described; other implementations, enhancements, and variations can be made based on what is described and illustrated in this patent document.

Claims

1. 1. A cryogenic classical superconducting circuit operating at cryogenic temperatures comprising a function approximator for a decoder of a quantum error correction code, the decoder comprising a plurality of nodes, a plurality of interconnections between nodes of the plurality of nodes for distributing pulses among the nodes, and a plurality of weights representing the function approximator parameters, each node of the plurality of nodes being: a receiver section for receiving at least one pulse comprising a magnetic flux, a current, or a voltage; a processing core for processing the received pulses; a transmitter section for transmitting the processed pulses; Equipped with 11. The cryogenic classical superconducting circuit, wherein at least one of the plurality of weights comprises a magnetic coupling, a capacitive coupling, a galvanic coupling, or a resistive coupling.

2. The cryogenic classical superconducting circuit of claim 1, comprising a mixed-signal digital and analog Josephson junction superconducting electronic device comprising at least one of a conventional Josephson junction, a magnetic junction, and a quantum phase slip device.

3. 3. The cryogenic classical superconducting circuit of claim 2, wherein the Josephson junction superconducting electronics comprises digital and mixed-signal quantum flux families, the digital and mixed-signal quantum flux families comprising energy efficient fast single flux quantum (ERSFQ), energy efficient single flux quantum (eSFQ), adiabatic quantum flux parametron (AQFP), inverse quantum logic (RQL), fast single flux quantum (RSFQ), SFQuClass, or superconducting quantum interface devices (SQUID, Bi-SQUID, nSQUID).

4. The cryogenic classical superconducting circuit of claims 1-3, wherein each node is configured to operate in an analog, digital, or analog-digital mode.

5. 5. The cryogenic classical superconducting circuit of claim 4, wherein the nodes are arranged in layers, and further wherein a receiver section of the node in a first layer and a transmitter section in a last layer operate in a digital mode, and the nodes in other layers operate in an analog mode.

6. 10. The cryogenic classical superconducting circuit of claim 1, wherein the nodes are coupled by interconnects that are analog, digital, or hybrid analog and digital.

7. 10. The cryogenic classical superconducting circuit of claim 1, wherein the nodes are coupled by interconnects that are operated synchronously or asynchronously.

8. The cryogenic classical superconducting circuit of claim 1 , wherein the decoder further comprises at least one amplifier for amplifying a signal.

9. 10. The cryogenic classical superconducting circuit of claim 1, wherein at least one weight of the plurality of weights comprises a fixed coupling comprising a magnetic coupling, a capacitive coupling, or a resistive coupling.

10. 10. The cryogenic classical superconducting circuit of claim 1, wherein at least one weight of the plurality of weights comprises a variable coupling comprising a magnetic coupling, a capacitive coupling, a galvanic coupling, or a resistive coupling.

11. 10. The cryogenic classical superconducting circuit of claim 9, wherein the magnetic coupling comprises a transformer, and different coupling strengths are used for different input pulses at the transformer to represent weightings of the plurality of weights, and a fixed magnetic coupling is proportional to the weightings.

12. 10. The cryogenic classical superconducting circuit of claim 9, wherein the resistive coupling comprises a voltage divider, and further wherein different coupling strengths are used for different input pulses at the voltage divider to represent weightings of the plurality of weights, and further wherein a fixed resistive coupling is proportional to the weightings.

13. 11. The cryogenic classical superconducting circuit of claim 10, wherein a weighting of the plurality of weights is expressed via at least one of generating a number of single flux quantum (SFQ) pulses proportional to the weighting, generating a pulse rate proportional to the weighting, and generating pulses of intensity proportional to the weighting.

14. A mixed-signal digital and analog Josephson junction superconducting electronic device comprising at least one of a conventional Josephson junction, a magnetic junction, and a quantum phase slip device, 14. The cryogenic classical superconducting circuit of claim 13, wherein the Josephson junction superconducting electronic device comprises a Superconducting Quantum Interface Device (SQUID), and at least one of the number of SFQ pulses, the pulse rate, or the intensity of pulses is varied by varying a bias current or a critical current of the Superconducting Quantum Interface Device (SQUID).

15. 10. The cryogenic classical superconducting circuit of claim 9, wherein the processing core comprises at least one storage loop for storing the magnetic flux, and wherein the magnetic flux is erased using a command pulse, which may be a resistor, a SQUID, or a clock.

16. 10. The cryogenic classical superconducting circuit of claim 1, wherein the interconnection between two nodes of the plurality of nodes is electrical, magnetic, or photonic.

17. 10. The cryogenic classical superconducting circuit of claim 1, wherein the interconnection between at least two nodes of the plurality of nodes is in parallel or in series.

18. 2. The cryogenic classical superconducting circuit of claim 1, wherein the interconnection between two nodes of the plurality of nodes is electrical using a Josephson transmission line (JTL) or a passive transmission line (PTL).

19. 2. The cryogenic classical superconducting circuit of claim 1, wherein the pulses between the nodes are generated using line drivers, each of the pulses producing at least one pulse.

20. 2. The cryogenic classical superconducting circuit of claim 1 , wherein the function approximator for the quantum error correction code decoder comprises a neural network, further wherein the neural network parameters and activations are represented by decoder nodes and weights, and further wherein the neural network activations are implemented using the decoder nodes and processing cores.

21. 21. The cryogenic classical superconducting circuit of claim 20, wherein the neural network activations comprise sigmoid and rectified linear unit (ReLU) activation functions.

22. 21. The cryogenic classical superconducting circuit of claim 20, wherein the neural network comprises a recurrent neural network, a deep neural network, a feedforward neural network, a convolutional neural network, a Hopfield network, a Boltzmann machine, or a graphical model.

23. 10. The cryogenic classical superconducting circuit of claim 1, wherein a function approximator for the quantum error correction code decoder comprises at least one neural network and at least one linear function approximator.

24. 10. The cryogenic classical superconducting circuit of claim 1, wherein at least one weight of said plurality of weights is programmable.

25. The cryogenic classical superconducting circuit of claim 1 , wherein the function approximator is programmable using input from a user.

26. 10. The cryogenic classical superconducting circuit of claim 1, wherein a function approximator for the quantum error correction code decoder comprises a regression unit, a classifier, a decision tree, or a random forest.

27. 1. A system capable of quantum error correction for quantum computing, the system comprising: (a) a cryogenic device structured to include different cryogenic stages at different cryogenic temperatures; (b) a quantum processor, the quantum processor comprising a plurality of quantum devices with two or more distinct quantum states ("qudits") for performing quantum computing, the quantum processor being coupled to and cooled by the cryogenic devices at a desired cryogenic temperature for proper operation of the qudits, the plurality of qudits comprising data qudits for encoding quantum information for quantum computing and syndrome qudits for interacting with the data qudits and providing measurements, the plurality of qudits providing error correction codes for correcting quantum errors; (c) a cryogenic classical superconducting circuit, the cryogenic classical superconducting circuit coupled to and cooled by the cryogenic device, further coupled to receive information relating to the measurement from the syndrome qudit, the cryogenic classical superconducting circuit including a decoder for the quantum error correction code, and configured to process the received information relating to the measurement from the syndrome qudit and generate a recovery operation for a data qudit to reduce errors in the quantum computing, the cryogenic classical superconducting circuit coupled to the quantum processor as a classical co-processor, reducing communication delays between the quantum processor and the cryogenic classical superconducting circuit; Equipped with 11. The system of claim 1, wherein the decoder is configured to operate with a function approximator, the decoder comprising a plurality of weights representing the function approximator parameters, and at least one weight of the plurality of weights comprising magnetic coupling, capacitive coupling, galvanic coupling, or resistive coupling.

28. 28. The system of claim 27, wherein the error-correcting code is a topological error-correcting code.

29. 30. The system of claim 28, wherein the error correction procedure on the topological error correction code comprises a parity check operation on the plurality of qudits comprising a plaquette.

30. 30. The system of claim 28, wherein the topological error correction code comprises a toric code, a surface code, a rotated surface code, a color code, a triangular color code, or a bihexagonal code.

31. 28. The system of claim 27, comprising a plurality of logical qudits, each of the plurality of logical qudits comprising a classical-quantum interface between the cryogenic classical superconducting circuit and the quantum processor, the logical qudit comprising a quantum error correction scheme, the plurality of logical qudits for performing quantum computing.

32. 30. The system of claim 27, wherein the quantum processor comprises at least one syndrome extraction circuit.

33. 33. A method for implementing a quantum error correction scheme using the system of claim 32, the method comprising: (i) preparing at least one syndrome qudit; (ii) executing the at least one syndrome extraction circuit, the at least one syndrome extraction circuit comprising at least one data qudit and at least one syndrome qudit; (iii) performing at least one measurement on at least one syndrome qudit of the at least one syndrome extraction circuit; (iv) providing a result of the at least one measurement to a function approximator of a decoder; and (v) providing a recovery operation using a function approximator of the decoder and comprising a recovery operator; (vi) applying said recovery operation; and A method comprising:

34. 34. The method of claim 33, wherein the recovery operator is a unitary operator applied to the error-correcting code.

35. 34. The method of claim 33, wherein the restoration operator is a change of basis on the Pauli frame.

36. The method of claim 33, wherein the recovery operator is an equivalence operator.

37. 34. The method of claim 33, wherein steps (ii)-(iv) are repeated at least one time.

38. 28. A method for constructing a function approximator for a decoder of the system of claim 27, the method comprising: (a) collecting data from the error-correcting code regarding at least one syndrome qudit and regarding a corresponding error; (b) constructing the function approximator using the collected data for the at least one syndrome qudit and the collected data for the corresponding error; A method comprising:

39. 40. The method of claim 38, wherein (b) comprises training a neural network.

40. 40. The method of claim 38, wherein the data is collected from a simulation of a qudit being beset by a noisy channel.

41. 41. The method of claim 40, wherein the noise channel comprises a Pauli noise channel, and further wherein the Pauli noise channel is depolarizing or dephasing.

42. 40. The method of claim 38, wherein the data is collected from a simulation of the plurality of qudits performing a logical operation.

43. 40. The method of claim 38, wherein the data is collected from experimental data, the experimental data comprising data from qudits at rest, data from qudits performing logical measurements, and data from logic gates.

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