Scalable and programmable coherent waveform generator

Abstract

To provide scalable and programmable digital-to-analog converter (DAC) cards implemented for quantum information processing (QIP) systems, and a network.SOLUTION: A DAC card used by a network of a QIP system includes a clock divider / replicator device with an input SYNC pin, a digital logic component, and one or more DAC components 470. Each output of the DAC components is used to control optical beams for a separate qubit of the QIP system. The network also includes a first distribution network to provide a clock signal to the clock divider / replicator device and a second distribution network to provide a start signal to the DAC card. The start signal is used by the digital logic component to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 877,979, filed July 24, 2019, the disclosure of which is incorporated herein by reference in its entirety.

[0002] Aspects of the present disclosure relate generally to waveform or signal generators, and more particularly to scalable, programmable coherent waveform generators implemented for quantum information processing (QIP) systems. [Background technology]

[0003] Trapped atoms (or atomic ions) are one of the primary implementations of quantum information processing, with superconducting devices being another possible implementation. Atom-based qubits can be used as quantum memories, as quantum gates in quantum computers and simulators, and can act as nodes in quantum communication networks. These atoms or atomic ions are controlled in QIP systems, at least in part, by applying modulated light beams during various operations, including running quantum algorithms / calculations and quantum simulations. These light beams are controlled, at least in part, by radio frequency (RF) signals provided to acousto-optic modulators (AOMs) that are used to modulate the light beams. To ensure correct operation among multiple qubits in the system, it is important that the electronics driving the RF signals are well synchronized and have tightly controlled phase relationships. As the number of trapped atoms or atomic ions available in a QIP system scales up (e.g., increases), the QIP system must be able to maintain the synchronization and phase relationships of the RF signals by applying additional RF signals and light beams to increase the number of trapped atoms or atomic ions, even when more electronics are required to process them.

[0004] Additionally, these electronics must operate in an efficient manner to ensure that the RF signal has the proper waveform to be applied to the trapped atoms or atomic ions using the optical beam. Because the RF signal waveform is typically generated by digital-to-analog converters (DACs), it is desirable that these DACs be configured to operate not only for scalability but also to overcome delays such as those introduced by having the waveform information streamed from a network host.

[0005] It would therefore be desirable to develop and implement techniques that would enable scalable and programmable coherent waveform or signal generators (such as DDS) for use in various types of systems, including QIP systems. Summary of the Invention [Problem to be solved by the invention]

[0006] The following presents a simplified summary of one or more aspects to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is not intended to identify key or critical elements of all aspects or to delineate the scope of any or all aspects. Its purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0007] This disclosure describes techniques related to scaling and programming waveform or signal generators (e.g., Direct Digital Synthesizers (DDS)). More specifically, this disclosure describes techniques related to scaling and programming waveform or signal generators for quantum information processing (QIP) systems. [Means for solving the problem]

[0008] In one aspect of the disclosure, a network for synchronizing a plurality of digital-to-analog converter (DAC) cards in a QIP system is described. The network includes DAC cards, each DAC card having a clock divider / duplicator device having an input SYNC pin, a digital logic component, and one or more DAC components, each of whose outputs is used to control one or more light beams for separate quantum bits of the QIP system. The network further includes a first distribution network for providing a clock signal to the clock divider / duplicator device of each of the plurality of DAC cards, and a second distribution network for providing a central wake-up signal to each of the plurality of DAC cards. For each of the plurality of DAC cards, the central wake-up signal is used by a digital logic component within the DAC card to assert an input SYNC pin of the clock divider / duplicator device of the DAC card in response to the central wake-up signal being asserted, unless the central wake-up signal is masked by the digital logic component.

[0009] Another aspect of the disclosure describes a DAC card for controlling quantum bits in a QIP system. The DAC card can include a digital logic component having one or more direct digital synthesizers (DDS) for each output of the DAC card, each DDS controlling one or more light beams for a separate quantum bit of the QIP system, and a pair of tables collectively providing commands to the one or more DDSs, a first table of the pair of tables being a function table and a second table of the pair of tables being an instruction table, the function table defining a parameterized function generated by the one or more DDSs, and the instruction table defining a subroutine call to the function table or a conditional loop instruction of the function table. The DAC card can further include one or more DAC components, each DAC component providing one or more outputs of the DAC card, each DAC component receiving a parameterized function generated by the one or more DDSs and generating one or more outputs, the parameterized function being in digital form and the one or more outputs being in analog form.

[0010] Described herein are methods, apparatus, and computer-readable storage media for various aspects relating to the implementation of techniques for scaling and programming a waveform or signal generator. [Brief description of the drawings]

[0011] The accompanying drawings depict only some embodiments and therefore should not be considered limiting of the scope.

[0012] [Figure 1A] 1 shows a diagram of a vacuum chamber housing electrodes for trapping atomic ions in a crystal according to an aspect of the present disclosure. [Figure 1B] 1 is a diagram illustrating an example of a reduced energy level diagram illustrating application of laser radiation (e.g., a light beam) for state initialization in accordance with an aspect of the present disclosure. [Figure 1C]1 is a diagram illustrating an example of a reduced energy level diagram illustrating application of laser radiation (e.g., a light beam) for qubit state detection via fluorescence, in accordance with an aspect of the present disclosure. [Figure 2A] 1 is a diagram illustrating an example of a Raman beam geometry according to an aspect of the present disclosure. [Figure 2B] 1 is a diagram illustrating an energy level diagram showing coherent stimulated Raman transitions coupling qubit states in accordance with an aspect of the present disclosure. [Diagram 3] 1 is a diagram illustrating an example of the frequency dependence of a diffractive laser or light beam using an acousto-optic modulator (AOM) according to an embodiment of the present disclosure. [Figure 4A] 1 illustrates an example of a digital-to-analog conversion (DAC) card according to an embodiment of the present disclosure. [Figure 4B] 1 illustrates an example of implementing multiple direct digital synthesizers and instructions and spline tables on a DAC card in accordance with an aspect of the present disclosure. [Figure 4C] 1 illustrates an example of using multiple DAC cards to control the operation of trapped atomic ions used as quantum bits, according to an aspect of the present disclosure. [Figure 5A] 1 illustrates an example of a startup signal distribution network for multiple DAC cards according to an aspect of the disclosure. [Figure 5B] 1 illustrates an example of a clock distribution network for multiple DAC cards according to an aspect of the present disclosure. [Figure 6] 1 illustrates an example of the operation of combining an instruction table with a function or spline table in accordance with an aspect of the present disclosure. [Figure 7] 1 is a diagram illustrating an example of a computing device according to an aspect of the present disclosure. [Figure 8] FIG. 1 is a block diagram illustrating an example of a QIP system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The detailed description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known components are shown in block diagram form in order to avoid obscuring such concepts.

[0014] As mentioned above, trapped ions may be used to implement quantum information processing systems. Atomic-based qubits can be used as various types of devices, such as quantum memories, quantum gates in quantum computers and simulators, and nodes in quantum communication networks. Qubits based on trapped atomic ions can have very good coherence properties, can be prepared and measured with nearly 100% efficiency, and can be easily entangled with each other by modulating the Coulomb interaction with appropriate external control fields, such as optical and microwave fields. As used in this disclosure, the terms "atomic ion," "atom," and "ion" may be used interchangeably to describe particles that will be or are actually confined in a trap to form a crystal or similar arrangement or configuration, and that are used as qubits in quantum computing and simulations. This disclosure describes techniques that can make coherent waveform or signal generators (e.g., DDS) scalable and programmable for use in different types of systems based on atomic qubits, including QIP systems.

[0015] A typical ion trap geometry or structure used for quantum information and metrology purposes is the linear radio frequency (RF) Paul trap (also called RF trap, surface trap, or simply Paul trap), where nearby electrode layers hold static and dynamic potentials that lead to effective non-uniform harmonic confinement of ions. RF Paul traps are a type of trap that uses an electric field to trap or confine charged particles to a specific region, position, or location. When atomic ions are laser cooled to very low temperatures in such a trap, they form a stationary crystal of qubits (e.g., a structured array of qubits) where Coulomb repulsion balances the external confinement forces. For sufficient trap anisotropy, ions can form crystals along the weak confinement direction, which is the arrangement typically adopted for applications in quantum information and metrology.

[0016] FIG. 1A shows a diagram 100 illustrating the trapping of atomic ions in a crystal 110 (using electrodes in a vacuum chamber) using a linear trap, such as, for example, a linear RF Paul trap. The crystal 110 can be, for example, a linear crystal or a linear lattice. In the example shown in FIG. 1A, the vacuum chamber of the quantum system traps N (N≧1) atomic Ytterbium ions (e.g., 171 Yb + The trapped atomic ions 120 may include a set of electrodes and may be laser cooled to near stationary. The number of trapped atomic ions may be configurable. The atoms may be 171 Yb + The atomic ions are illuminated with laser radiation tuned to the resonance of the nucleus, and the fluorescence of the atomic ions is imaged on a camera. In one example, the atomic ions are separated from each other by a distance 215 of about 5 micrometers (μm), which can be seen by the fluorescence. The separation of the atomic ions is determined by the balance between the external confinement forces and the Coulomb repulsion forces.

[0017] The strong fluorescence of individual trapped atomic ions depends on efficient cycling of photons, and therefore the atomic structure of the ions must have strong closed optical transitions that allow laser cooling of the motion, initialization of qubit states, and efficient qubit readout. This allows the alkaline earth (Be) + , Mg + , Ca + , Sr + , B.A. + ) and certain transition metals (Zn + , Hg + , Cd + , and Yb + Many atomic ions can be excluded, except for simple atomic ions with only one outer electron, such as ). Within these atomic ions, the qubits are represented by two stable electronic levels, often characterized by effective spins of two states |↑> and |↓>, or equivalently, |1> and |0>. Figures 1B and 1C show the quantum bit structure of an atomic ion. 171 Yb + 13, where the qubit levels |↑> and |↓> 130 are represented by stable hyperfine levels in the ground electronic state and are separated by a frequency ω0 / 2π=12.64 GHz. 171 Yb + The excited electronic states |e> and |e'>140 of are themselves split by smaller hyperfine couplings and are separated from the ground state by an optical interval having an energy corresponding to an optical wavelength of 369.53 nm.

[0018] Laser radiation tuned just below resonance in these optical transitions can confine atomic ions near the bottom of the trap by Doppler laser cooling. Other, more sophisticated forms of laser cooling can hold atomic ions nearly still within the trap.

[0019] When a dichroic laser or light beam (e.g., a light beam with two tones generated by sidebands resulting from optical modulation) is applied to the atom in resonance with both the │↑>⇔│e> and │↓>⇔│e'> transitions, it quickly falls to the state │↓> and no longer interacts with the optical field, allowing the initialization of the qubit with essentially 100% fidelity (see, e.g., Figure 1B).

[0020] When a single laser beam resonant with the │↑>⇔│e> transition is applied, ions in the │↑> state fluoresce strongly due to a closed-cycle optical transition, while ions in the │↓> state remain dark because the laser frequency is away from its resonance (see, for example, Figure 1C). Collection of even a small fraction of this fluorescence allows detection of the atomic qubit state with nearly perfect efficiency or precision. Other atomic species can have similar initialization / detection schemes.

[0021] 1B and 1C, all allowed transitions from the excited electronic states |e> and |e'>140 are shown as downward wavy arrows, while applied laser radiation (shown as upward straight arrows) drives these transitions to initialize the state |↓> as shown in Fig. 1B, and detects the fluorescence of the qubit state (|↑>=fluorescence, |↓>=no fluorescence) as shown in Fig. 1C.

[0022] To perform quantum processing using qubits of the type described in Figures 1A-1C, it is necessary to use lasers or light beams to control the phase, frequency, amplitude, and / or polarization of the quantum information in the qubits.

[0023] For entangled multi-qubit operations, the motions of many trapped ions are coupled through Coulomb interactions, like an array of pendulums connected by springs. A natural way to entangle quantum logic gates between atomic ions in a crystal is to use their motion as an intermediary, as shown in FIG. 2A. FIG. 2A shows a diagram 200 illustrating an example of a Raman beam geometry and where motion is generated in the qubits by application of a light beam. In diagram 200, there are light beams 210 and 220 directed at a linear lattice or crystal 110 with atomic ion qubits. Light beams in the same direction are sometimes referred to as co-propagating light beams, and light beams in opposite directions are sometimes referred to as non-co-propagating or counter-propagating light beams. Beam 210 (which is co-propagating) is a focused beam or an individually addressed beam, while beam 220 (which is counter-propagating to beam 210) is a non-focused global beam. As used herein, the terms laser beam, laser radiation, light beam, light radiation, beam, light field, and field may be used interchangeably. 1A-1C and 2B, diagram 230 in FIG. 2B illustrates that the qubit levels are separated in energy and that there may be different approaches to enabling qubit level transitions.

[0024] Acousto-optical modulators (AOMs) are used in quantum computing and simulation applications to manipulate or control the frequency, phase, amplitude, and / or polarization of the optical beams described above. One or more RF signals and a laser beam are applied to the AOM, and the RF signal is imprinted onto a portion of the laser beam. That portion can be deflected ("diffracted") by the AOM from the unaffected beam and spatially separated.

[0025] To generate the required manipulation of quantum information, pairs of modulated beams often need to be irradiated simultaneously on the same atom. An AOM can generate multiple manipulated laser beams by applying the sum of two or more RF signals, each associated with a specific frequency (e.g., f1, f2, etc.) of the RF signal. However, if the two or more laser beams have different frequencies, the two modulated beams will not overlap after being diffracted by the AOM. The laser beams can be "refocused" (or reimaged) onto the atom or ion such that both beams overlap at the atom.

[0026] 3 shows a diagram 300 illustrating an example of the frequency dependence of the diffractive laser or light beam described above. In this example, a first RF signal (e.g., a modulating signal) is generated by RF generator 310a based on a frequency or tone f1, and a second RF signal is generated by RF generator 310b based on a frequency or tone f2. These two signals are combined by summer 2315 and applied to AOM 320a. The RF control signals (first RF signal and second RF signal) are typically analog signals generated by an analog-to-digital converter (DAC) that converts a digital waveform into an analog waveform represented in the RF control signal.

[0027] The AOM 320a receives an incident laser beam 325, some of which is not diffracted (e.g., the non-diffracted laser beam 330 generated by the zero-order diffraction). Meanwhile, two modulated laser beams are generated from the incident laser beam 325 by diffraction at the AOM 320a (e.g., the diffracted laser beam 335a for tone f1 and the diffracted laser beam 335b for tone f2, both of which can be spatially filtered to produce higher-order diffracted beams generated by the first-order diffraction). The two diffracted laser beams diffract at different angles and do not co-propagate. Therefore, the two diffracted laser beams need to be focused by optical elements 340 (e.g., the focused laser beam 345a for f1 and the focused laser beam 345b for f2) onto the respective ions or atoms 120 in the lattice or crystal 110 formed in the ion trap for quantum processing (see, e.g., FIG. 1A). Techniques can be applied such that the refocused laser beams may not reach the ions or atoms 120 in the same propagation direction (eg, do not co-propagate), which does not introduce errors into the quantum state operation.

[0028] As quantum information processing systems scale up, i.e., as the number of atoms or ions 120 increases, it is important to be able to maintain synchronization and phase relationships of RF signals (e.g., RF control signals) within the various atoms or ions 120, such that synchronization and phase relationships are maintained when manipulating or controlling the frequency, phase, amplitude, and / or polarization of the light beam described above.

[0029] 1A-3, a trapped ion quantum information processing system, such as a quantum computer, requires two non-parallel Raman laser beams to impinge on each of the atoms or atomic ions 120 in a crystal or lattice 110, with a known and stable phase relationship to similar laser beams impinging on other atoms or atomic ions 120 in the same trap. As described above, the laser beams are aligned in a direction such that the atomic species used for the qubits are 171 Yb +, it may be 355 nanometers. One global beam (eg, global beam 220 in diagram 200 of FIG. 2A) is shared by all qubits.

[0030] Lasers or light beams can have the phase imprinted on them from an electronic signal (e.g., the RF control signal of diagram 300 of FIG. 3) by using an AOM, which brings the phase control from the purely optical domain to a mostly electronic domain. 171 Yb + In the case of , a 355 nm (e.g., ultraviolet) light source can be used to generate the laser or light beam. In some cases, the light source can be a light source used for commercial semiconductor photolithography and adapted or repurposed for trapped ion quantum information processing. The original laser or light beam generated by the light source can be split into a single global beam (e.g., global beam 220 of diagram 200 of FIG. 2A) and multiple individual beams (e.g., beam 210 of diagram 200 of FIG. 2A) to address each of the atoms or atomic ions 120 separately. These light beams can then be passed through one or more AOMs, as shown in diagram 300 of FIG. 3, where an optical system can be used to spread the total global beam so that the individual beams can be aimed or focused on their respective atoms or atomic ions 120. In some examples, the crystal or lattice 110 can contain 32 or more atoms or atomic ions 120 (e.g., up to 100 or more atoms or atomic ions 120), and the number of light beams required (and their respective electronic signals, e.g., RF control signals) is proportional to the number of atoms or atomic ions 120. Although the example shown in diagram 300 of FIG. 3 is for one AOM for each light beam, it is also possible to use a multi-channel AOM, in which case a single set of optics may be sufficient to manipulate the light beams generated by the multi-channel AOM. 171 Yb+ If a typical AOM is used, the required electronic signal will have a frequency between, for example, 150 MHz and 250 MHz.

[0031] As mentioned above, it is important that the electronics used to generate the RF signals that drive the electrical inputs to the AOM (e.g., signal generators for control signals) have a tightly controlled phase relationship. These electronics do not need to have a specific phase (e.g., 16° or 567 picoseconds) with respect to one another, but the phase needs to be substantially fixed for the duration of a set of experiments or calculations so that the calibration applied does not change. In preferred operation, a calibration that occurs before the signal generator is finally powered off or reset will remain valid at a later point when the same signal generator is powered back on or the reset is released.

[0032] An aspect described in this disclosure to achieve a tightly controlled phase relationship is that when multiple signal generators are used to provide RF control signals to several AOMs (or multi-channel AOMs), the signal generators are configured to derive their digital clocks from a common source, so that their outputs can remain at a predetermined phase for a longer period of time, since even good oscillators that start out at the same frequency tend to drift different amounts over the same period of time.

[0033] In another aspect of the present disclosure, during the course of an experiment (e.g., a quantum computation or algorithm) or simulation with a quantum information processing system, it may be necessary to individually change one or more parameters of the electrical signals (e.g., waveforms) that are generated to control each quantum bit in a crystal or lattice (see, e.g., crystal or lattice 110 in diagram 100 of FIG. 1A). The statements or instructions for a particular quantum algorithm or quantum simulation that indicate how the quantum bits should interact and proceed need to be compiled into a specific set of commands for the signal generator to vary the parameters accordingly.

[0034] In a trapped ion quantum information processing system, there can be several different types of lasers or light beams that need to be used and controlled: (1) pulsed lasers to convey motion to information; 171 Yb + For qubits, this may include ultraviolet (UV) light (e.g., 355 nm); (2) continuous wave (CW) lasers (Doppler cooled) for scanning or erasing information; 171 Yb + For qubits, this may include 369 nm + 14 GHz UV light), (3) a CW laser to prepare the qubit state; 171 Yb + For qubits, this may include 369 nm + 2.105 GHz light, and (4) a CW laser to detect the qubit state; 171 Yb + For quantum bits, this may include light at 369 nm. In one example, a 369 nm (or about 370 nm) laser or light beam is 2 S 1 / 2 and 2 P 1 / 2 may be used in the transition shown in diagram 230 of FIG. 2B between

[0035] Furthermore, in a trapped ion quantum information processing system, the algorithm or simulation typically includes one or more of the following phases: (1) coarse Doppler cooling, (2) fine (sideband) cooling by alternating between pulsed and CW lasers, (3) preparation of all atoms or atomic ions (qubits) into a known state, (4) qubit entanglement for the algorithm or simulation using a pulsed laser (which may include multiple steps), and (5) state detection. In such an algorithm or simulation, the term "shot" can refer to performing each of the above-mentioned phases, the term "experiment" can refer to performing a large number of shots, e.g., anywhere between 100 shots and 10,000 shots, the term "pulse" can refer to the operation of a signal generator during qubit entanglement in the algorithm or simulation to cause single qubit or multi-qubit coherent operations, the term "pulse duration" can refer to a duration of about 10 microseconds (μs) for single qubit operations and about 100 μs for two-qubit operations (and possibly longer if more than two qubits are involved), and the term "entangled" can refer to having two or more qubits interacting, such that as long as only coherent operations are performed on the qubits, they will still be connected such that an operation on one qubit affects the operation of the other qubit.

[0036] During state detection (phase (5) above), atoms or atomic ions (qubits) that can be in any superposition of |0> and |1> states are collapsed into a classical state of "0" or "1" (light or dark). The probability of detecting a "0" or "1" is controlled by the original quantum superposition, but because each shot provides only one sample per qubit, an experiment requires many shots to obtain a statistical population large enough to estimate the original superposition with the desired level of accuracy.

[0037] As mentioned above, signal generators are used to provide electrical signals (e.g., RF signal control signals) that control lasers or light beams used in quantum operations (e.g., algorithms / calculations or simulations). These electrical signals can control lasers or light beams by using AOMs. Signal generators of the type described in this disclosure may be used, for example, in conjunction with phases (2) and (4) (fine (sideband) cooling and entanglement) discussed above.

[0038] In some experiments, the behavior of the signal generator over the course of the experiment (e.g., the waveform or signal generated / provided, or the parameters used to generate the waveform or signal) is known even before the experiment begins. Other types of experiments may require the behavior of the signal generator to change during the experiment based on feedback from the experiment itself. Quantum information processing systems may be configured to handle both types of experiments.

[0039] Arbitrary waveform generators (AWGs) have been used as signal generators in quantum information processing systems. AWGs are typically configured to store all of the outputs that their corresponding digital-to-analog converters (DACs) output over time for as long as the experiment is run. This can be a lot of data, so it can consume a long time to transfer the samples from the computer to the AWG. This "upload time" can govern the experiment time, whether the experiment may be repeated many times in succession, or whether each run of the experiment is short or limited. Systems relying on AWGs can therefore be limited in their speed of operation, especially when the information to generate the samples provided to the AWG is streamed from a host or network into the system.

[0040] Another approach has been proposed (see for example the Artiq project, https: / / m-labs.hk / artiq / ), in which instead of generating each sample of the waveform or signal to be used, the waveform or signal parameters are explicitly specified. That is, rather than specifying each analog voltage to be generated, several parameters are specified to describe the signal or waveform over a period of time. The advantage of this is that less data is needed to specify the parameters than the instantaneous analog voltages. If the parameters do not need to change in a given interval (e.g. changing the amplitude dominantly does not change the frequency), they can be omitted from the description to save space, since the signal generator hardware knows how to run that frequency at will without any external help.

[0041] Additionally, predictable changes to signal parameters (e.g., frequency increase by NHz every Tμs, or amplitude increase by M thousandths of full-scale amplitude every Tμs) can also be succinctly described. Thus, the signal generator can do the right thing for a period of time without any new input. It is unlikely that these types of changes will be sufficient to completely describe the desired behavior of the signal generator for a given time interval, and therefore additional parameters may need to be provided, but the advantage is that these additional parameters / changes do not often need to be provided, so again, less data needs to be pushed into the signal generator.

[0042] Generally, a change indicated by a statement such as "Variation parameter P with N steps over time T" conveys a linear equation to the signal generator. Depending on the shape that needs to be described in the waveform or signal, more complex equations with higher order terms such as squared or cubed, or even higher, are also useful. These methods of describing parameter changes are called or referred to as "splines." In the case of cubic equations, they are called or referred to as "cubic splines."

[0043] One example of a type of hardware (e.g., signal generator) that can be used to control a waveform or signal by exhibiting signal parameters and / or changes in signal parameters is a direct digital synthesis device, also called a direct digital synthesizer or DDS. For example, a DDS can generate any desired frequency infinitely. A DDS allows the frequency and / or phase to be specified at any time, and very quickly changes the samples that can be fed to the DAC to match the newly specified parameters. Amplitude may not be a parameter that a DDS inherently allows to change (as it may typically operate at full-scale amplitude), but amplitude parametric modulation can be easily handled outside of the DDS by inserting a digital multiplication unit between the output of the DDS and the input of the DAC. Internally, a DDS may include a look-up table (LUT) of sinusoidal DAC samples and some mathematical capabilities to increase accuracy. Some examples of mathematical capabilities of a DDS include, but are not necessarily limited to, Taylor series (expansion), linear interpolation, and low-pass filtering. Further details regarding DDS devices or the typical operation of a DDS are publicly available (see, for example, https: / / www.analog.com / en / analog-dialogue / articles / all-about-direct-digital-synthesis.html, https: / / en.wikipedia.org / wiki / Direct_digital_synthesis).

[0044] DDS can be implemented as a standalone integrated circuit ("chip") or as an intellectual property (IP) block for insertion into an integrated circuit with other processing blocks, typically feeding an internal or external DAC with the DDS digital logic. Such IP blocks can be used, for example, in field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs) to implement a system-on-chip (SOC) solution. For example, the Artiq project mentioned above offers free use of DDS soft IP. In addition, FPGA manufacturers such as Xilinx and Intel / Altera also sell DDS IP blocks, and chip manufacturer Analog Devices also has an open source DDS IP block.

[0045] In some cases, it is desirable to run the digital logic in the FPGA (or ASIC) at a slower clock rate than the samples output by the DAC. For example, a DAC channel may be capable of accepting 1 billion samples per second from the digital logic (e.g., a DDS), but it may be desirable to implement and operate the digital logic on an FPGA such that it runs no faster than, say, 250 MHz.

[0046] One approach could be to run parallel copies of the DDS at a slower clock rate. For example, instead of a single DDS, four instances of the DDS (or sub-DDS) could be implemented and used to generate 1 billion samples per second, but each DDS would actually be clocked at 250MHz. The sub-DDSs would start with phase offsets of 0, 90, 180, and 270 degrees, all giving the same frequency. They would then each sweep a different quadrant of the waveform, using a small part of an FPGA or ASIC, usually designed specifically to feed data off-chip at high speeds, such as a serializer-deserializer (SERDES), so that four samples (one from each sub-DDS) are fed to the DAC per clock.

[0047] In this example, there are four instances of the DDS (e.g., four DDS IP blocks) that use about four times the logic, random access memory (RAM), and clock resources inside the FPGA or ASIC, so it may be preferable to run fewer instances at a faster clock rate. Again, using the example of 1 billion DAC samples per second, instead of using four sub-DDSs, it may be preferable to use three instances at 333 MHz, or two instances at 500 MHz. The approach described above is still used, with different phase offsets of (0, 120, 240) degrees for the three instances and (0, 180) degrees for the two instances. Note that fewer gates using a clock domain often run faster than the entire chip. A dual rate first-in, first-out (FIFO) can be used to communicate data between a small, fast rate domain and the majority of the chip running at a slower clock rate (perhaps 250 MHz).

[0048] Another problem that may arise in the context of quantum information processing systems is that it may not be possible to find a single FPGA or ASIC that can drive enough DAC chips to generate enough signals to control all the qubits in the crystal or lattice 110 in the diagram 100 of FIG. 1A, for example. Alternatively, if one such FPGA is available, its cost may be prohibitively high. Furthermore, the time or cost required to build a board using such an FPGA may also be prohibitive. In all of these cases, it may be desirable to use many separate FPGAs, possibly on separate boards, to control the entirety of the atoms or atomic ions (qubits) in the system. Having a modular or scalable approach may allow the system to be easily deployed, since the system may be scalable (e.g., the number of qubits may be increased). The outputs of all DACs across all boards need to be synchronized, so that the relative phase of these outputs is preferably kept static between power-up and reset.

[0049] In view of the above problems, this disclosure describes various aspects or techniques of synchronizing clocks across physically separate DAC cards for use in a QIP system to control a scalable number of quantum bits. In one such aspect, a central or common clock is run through a passive splitter (e.g., a 1:N splitter) and distributed to each DAC card in the QIP system so that the DAC cards see the rising edge of the clock at the same time (see, e.g., FIG. 5B). A DAC card may also be referred to as a DAC board and may include one or more DAC components (e.g., DAC integrated circuits or modules) that provide a DAC output (e.g., an analog electrical signal) that is used to control a laser or light beam to manipulate quantum bits. One way to achieve the simultaneous appearance of the rising edge of the clock to all DAC cards is to use a coaxial cable that is all the same length. In another such embodiment, on the DAC card, the clock runs through a clock divider / duplicator device so that an associated clock (e.g., a local clock on the DAC card) can reach both the DAC components and the connected digital logic, such as an FPGA or ASIC, in which one or more DDSs may be implemented (see, e.g., FIG. 4A and FIG. 4B). The clock divider / duplicator device has an input SYNC pin that holds all outputs at a known value and clears a counter that may drive some of its outputs. In yet another such embodiment, a central or common start-up signal is also distributed to all DAC cards in the QIP system. This start-up signal is used to drive the DAC components, and therefore it is desirable for the DAC cards to get the start-up signal at the same time. One way to distribute the start-up signal with good signal integrity and fast rise time is to use low-voltage differential signaling (LVDS) over a shielded twin-axial cable (see, e.g., FIG. 5A). One example is the Samtec C28S cable (see, for example, https: / / www.samtec.com / rf / components / original / bayonet-twinax).In yet another such embodiment, the SYNC input pin of the divider / duplicator device can be driven from the output of digital logic (such as an FPGA / ASIC) that is programmed to assert whenever the wake-up signal asserts (unless the wake-up signal is masked) (see, e.g., FIG. 4A). The FPGA / ASIC in this case may be the same one in which the DDS is implemented.

[0050] One reason to prefer a slower clock in the digital logic (such as an FPGA or ASIC) that contains a DDS is that after reducing the input clock rate from 1 GHz to 250 MHz, it is easier to have many divider / duplicator devices all cleared on the same clock cycle (and therefore have zero phase between their outputs).

[0051] The above aspects and techniques relating to synchronizing DAC cards and their outputs are described in further detail below in conjunction with FIGS. 4A-5B.

[0052] FIG. 4A shows a diagram 400a illustrating an example of a DAC board or card 410 according to an embodiment of the disclosure. A QIP system, or any other similar system in which individual operations, devices, or elements may be controlled using a DAC card, may include one or more of the DAC cards 410. Each of the outputs 480 of the DAC card 410 is used to control a separate laser or light beam used with a particular qubit in the QIP system. For example, each of the outputs 480 may include one or more waveforms or signals, such as an RF control signal applied to an AOM, as described above in the diagram 300 of FIG. 3. The DAC card 410 in this example provides eight outputs 480, such that this single DAC card 410 may be used to manipulate or control up to eight qubits in a QIP system. For a larger number of qubits, additional DAC cards 410 may be added to the system.

[0053] Each DAC card 410 includes a divider / duplicator device 420 with a SYNC input, a digital logic component 430, an interface logic 460, and one or more DAC components 470 (e.g., DAC-1, ..., DAC-n). Each of the DAC components 470 is configured to receive samples, i.e., digital voltages representing a digital waveform or signal, and convert the samples to analog voltages representing a corresponding analog waveform or signal (e.g., an RF control signal). The digital waveform or signal is generated by the digital logic component 430 based on a parameterized function and adapted by the interface logic component 460 for compatibility with the input to the DAC components 470.

[0054] Divider / duplicator device 420 is configured to receive a clock signal 421, which may correspond to the central or common clock discussed above. Divider / duplicator device 420 may be configured to divide the rate of change of clock signal 421 (e.g., operate as a clock divider), or may be configured to simply replicate or maintain the rate of change of clock signal 421 when generating local clock signal 425. Local clock signal 425 is provided to digital logic component 430, interface logic 460, and / or DAC component 470 for synchronous operation.

[0055] Digital logic component 430 may be configured to generate samples that are provided to DAC component 470 via interface logic component 460. Digital logic component 430 may include an asynchronous logic component 435, a DDS component 440, and a table component 450.

[0056] The asynchronous logic component 435 may receive a wake-up signal 436, which may correspond to the central wake-up signal or common wake-up signal described above, and may use the wake-up signal 436 to assert the input SYNC pin of the clock divider / duplicator device 420 in response to the wake-up signal 436 being asserted, unless the wake-up signal 436 is masked by the asynchronous logic component 435. The wake-up signal 436 is also used to synchronize the DAC components 470 across multiple DAC cards 410. In other words, the wake-up signal 436 serves two purposes, providing a coordinated wake-up for all DAC cards 410 in the system, in which case the wake-up signal 436 is masked by the asynchronous logic component 435 and not provided to the divider / duplicator device 420, or it may be used to assert the input SYNC pin of the clock divider / duplicator device 420, in which case the wake-up signal 436 is not masked from the clock divider / duplicator device 420 by the asynchronous logic component 435. The asynchronous logic component 435 may generate a separate signal to assert the input SYNC pin of the clock divider / duplicator device 420 based on the wake-up signal 436 .

[0057] The DDS component 440 is configured to implement one or more direct digital synthesis or synthesizers (DDS) for each output 480 of the DAC card 410 (see, e.g., FIG. 4B). As mentioned above, a DDS may be a type of signal generator that can construct samples infinitely once phase and frequency parameters are given. Each of the DDSs for a particular output 480 generates a parameterized function that corresponds to a digital version of the waveform or signal to be provided in analog form by the output 480. For example, the output 480 may provide two RF control signals associated with two tones (f1, f2) applied to the AOM, as illustrated in diagram 300 of FIG. 3. In such a case, the DDS component 440 may include two DDSs for each output 480, i.e., one DDS that generates a parameterized function that is converted to an RF control signal related to the first tone (f1) and another DDS that generates a parameterized function that is converted to an RF control signal related to the second tone (f2). Different sets of DDSs may also be implemented for different outputs 480 of the DAC card 410.

[0058] The table component 450 is configured to store a pair of tables for each output of the DAC card 410, which collectively provide commands to one or more DDSs in the DDS component 440 for that output 480. The pair of tables includes a first table that is a function table and a second table that is an instruction table, where the function table defines the parameterized function (e.g., digital samples of a waveform or signal) generated by each DDS, and the instruction table defines subroutine calls to the function table or conditional loop instructions for the function table. In some aspects, the parameterized function defined by the function table is a spline curve. Various parameters can be used to define or characterize each of multiple segments of the spline curve, including one or more of amplitude, phase, or frequency. As shown in diagram 400a of FIG. 4A, the digital logic component 430 can receive parameter / configuration information 431, which can be used to populate and / or update parameters in the various tables stored in the table component 450 and used as a basis for generating the parameterized function by the DDS.

[0059] Although the digital logic component 430 is described above as being implemented using an FPGA or ASIC, it should be understood that some of the parts or components of the DAC card 410 may be implemented within the same integrated circuit (e.g., FPGA or ASIC). For example, the digital logic component 430 may be implemented within a single integrated circuit along with one or more of the divider / duplicator device 420, the interface logic component 460, or the DAC component 470. The entire DAC card 410 may also be implemented on a single integrated circuit, and in some cases, two or more DAC cards 410 may be implemented on a single integrated circuit.

[0060] 4B shows a diagram 400b illustrating an example of implementing multiple DDSs and command and spline tables within a DAC card such as DAC card 410. In this example, DAC card 410 is assumed to include two DAC components 470 (e.g., DAC-1 and DAC-2), each of which provides four outputs 480 for a total of eight outputs 480 to DAC card 410. DDS components 440 within digital logic component 430 include multiple DDSs to support the eight outputs 480. For example, a first set of DDSs 441 can include eight DDSs, two for each of the four outputs 480 of the first DAC component 470, and a second set of DDSs 442 can also include eight DDSs, two for each of the four outputs 480 of the second DAC component 470. Subsets 443 within set 441 correspond to one of the four outputs 440 of the first DAC component 470. The subset 443 includes a first DDS 444 (DDS1A) for generating a parameterized function used to generate a first RF control signal associated with a first tone (f1), and a second DDS 445 (DDS1B) for generating a parameterized function used to generate an RF control signal associated with a second tone (f2). Similarly, DDS2A and DDS2B are used with different outputs 480 of the first DAC component, as are DDS3A and DDS3B, as well as DDS4A and DDS4B. A similar configuration as above is used for the second set of DDS 442, which includes pairs DDS5A and DDS5B, DDS6A and DDS6B, DDS7A and DDS7B, and DDS8A and DDS8B. These pairs generate parameterized functions used to generate RF control signals at the four outputs 480 of the second DAC component 470.

[0061] Table component 450 in digital logic component 430 includes multiple tables to support the DDS in DDS component 440. For example, a first set of tables 451 can include eight tables, two for each pair of DDS associated with the four outputs 480 of first DAC component 470, and a second set of tables 452 can also include eight tables, two for each pair of DDS associated with the four outputs 480 of second DAC component 470. Subset 453 in set 451 corresponds to two tables used with subset 443 of DDS (DDS1A and DDS1B) in DDS component 440. In this example, subset 453 includes a first table 454 (Table 1A) and a second table 455 (Table 1B), where first table 454 is a function table and second table 455 is an instruction table. Similarly, for the remaining tables in set 451, Table 2A (function table) and Table 2B (instruction table) are used with DDS2A and DDS2B, Table 3A (function table) and Table 3B (instruction table) are used with DDS3A and DDS3B, and Table 4A (function table) and Table 4B (instruction table) are used with DDS4A and DDS4B. A similar arrangement is used for a second set of tables 452, which includes Table 5A (function table) and Table 5B (instruction table) used with DDS5A and DDS5B, Table 6A (function table) and Table 6B (instruction table) used with DDS6A and DDS6B, Table 7A (function table) and Table 7B (instruction table) used with DDS7A and DDS7B, and Table 8A (function table) and Table 8B (instruction table) used with DDS8A and DDS8B. The parameterized functions defined by the function table may be spline curves, so the function table may be referred to as, for example, a spline table.

[0062] Each of the DDSs shown in DDS component 440 may be a separate and distinct instantiation of a DDS IP block in an FPGA or ASIC, while each of the tables in table component 450 may be implemented in a separate and distinct portion of memory in an FPGA or ASIC.

[0063] FIG. 4C shows a diagram 400c illustrating an example of using multiple DAC cards 410 to control the operation of trapped atoms or atomic ions (e.g., atoms or atomic ions 120 in diagram 100 of FIG. 1A) used as quantum bits according to an embodiment of the disclosure. In this example, there are N DAC cards 410 (e.g., DAC card 410-1, ..., DAC card 410-N) used in the QIP system, where N > 1. Each of the DAC cards 410 may be implemented or configured as shown in diagram 400a of FIG. 4A, and each of the DAC cards 410 may have eight outputs 480. The outputs 480 are then fed to a respective AOM or multi-channel AOM to modulate a laser or light beam applied to the atoms or atomic ions 120. If the QIP system supports up to 32 atoms or atomic ions 120, four DAC cards 410 (N = 4) can be used to provide the required 32 outputs 480. If the QIP system is scalable and the number of atoms or atomic ions 120 increases, additional DAC cards 410 can be used to provide the appropriate number of outputs 480 .

[0064] As mentioned above, each of the DAC cards 410 receives a clock signal 421 (also referred to as a central or common clock signal) and a wake-up signal 436 (also referred to as a central or common wake-up signal). To enable proper synchronization across multiple DAC cards 410, these signals are provided by a distribution network that is part of the overall QIP system.

[0065] 5A shows a diagram 500a illustrating an example of a start-up signal distribution network for multiple DAC cards 410 according to an aspect of the disclosure. Diagram 500a shows a master control system 510 at the top of the start-up signal distribution network exchanging master control signals 512 with a digital logic component 515. The master control signals 512 include START1 and START2 signals from the master control system 510 to the digital logic component 515 and a DONE signal from the digital logic component 515 to the master control system 510. The START1 and START2 signals are used by the digital logic component 515 to generate a differential start signal 436 having a START+ signal and a START- signal. The digital logic component 515 may be implemented using an FPGA. In one example, the digital logic component 515 may be implemented using a Xilinx Kintex7 FPGA.

[0066] The wake-up signal 436 is provided by the digital logic component 515 to a splitter 520, which is configured to split the wake-up signal 436 and further provide it to each of the DAC cards 410 (e.g., DAC card 410-1, ..., DAC card 410-N) used in the QIP device, where N > 1. The wake-up signal 436 is provided to each of the DAC cards 410 as depicted in diagram 400a of FIG. 4A. Since there may be up to N DAC cards 410 in a QIP system, the splitter 520 may be referred to as a 1:N splitter. As mentioned above, one way to distribute the wake-up signal 436 with good signal integrity and fast rise time is to use LVDS cabling, such as LVDS over a shielded twinaxial cable. Each of the cables 530 (dashed lines) shown in diagram 500a may be an LVDS-based cable to achieve the type of signal integrity and rise time required to ensure that the activation signals 436 arrive at the various DAC cards 410 simultaneously.

[0067] 5B shows a diagram 500b illustrating an example of a clock distribution network for multiple DAC cards 410 according to an embodiment of the disclosure. Diagram 500b shows a reference clock source 540 at the top of the clock distribution network that provides a reference clock signal 541 to a multiplier component 545. Reference clock source 540 may not be part of the clock distribution network, but may be connected to the clock distribution network to provide reference clock signal 541.

[0068] The multiplier component 545 may be configured to receive the reference clock signal 541 and generate the clock signal 421 from the reference clock signal 541 using one or more multiplier stages. In one example, the multiplier component 545 may be a Wenzel Associates Golden Multiplied Crystal Oscillator (GMXO-PLD) with one or more low noise multiplier stages to generate a signal in the range of, for example, 200 MHz to 12 GHz.

[0069] In one example, reference clock source 540 is an atomic clock source, reference clock signal 541 is a 10 MHz signal, and clock signal 421 generated by multiplier component 545 is a 250 MHz signal.

[0070] The clock signal 421 is provided by the multiplier component 515 to a splitter 550, which is configured to split and further provide the clock signal 421 to each of the DAC cards 410 (e.g., DAC card 410-1, ..., DAC card 410-N) used in the QIP system, where N > 1. The clock signal 421 is provided to a divider / duplicator device 420 of each of the DAC cards 410, as depicted in diagram 400a of FIG. 4A. Because there may be up to N DAC cards 410 in a QIP system, the splitter 550 may be referred to as a 1:N splitter. As mentioned above, one way to achieve the simultaneous appearance of the rising edge of the clock signal 421 on all DAC cards 410 is through the use of coaxial cables that are all the same length. Each of the cables 560 (dashed lines) shown in diagram 500b may be a coaxial cable of the same length.

[0071] In addition to the above aspects and techniques related to synchronizing DAC cards and their outputs, this disclosure also describes aspects and techniques for enhancing the representation of spline curves, which are then used by the DDS to generate parameterized functions. This enhanced spline curve representation can be achieved in two ways by reusing sequences: (1) through subroutine calls; and (2) through conditional loop instructions.

[0072] To accomplish this, instead of using one table, two tables are used as described above (a spline or function table and an instruction table) (see, for example, FIG. 4B). The columns in the spline or function table specify parameters such as amplitude, phase, frequency and the relative times at which they should occur. The columns in the instruction table typically act as "subroutine calls" to some subsection of the spline table, but can alternatively act as loop iterators.

[0073] To save space, a single spline row (e.g., a single row in a spline table) cannot specify all parameters. Each row has an opcode field to describe which of a set of known parameters it includes, e.g., frequency slope, initial phase, or amplitude acceleration. In the spline table, a "spline node" consists of many consecutive spline rows. A row that is not the last of a spline node is marked in some way, perhaps with a special bit that is always present, or a special value in a field that usually has some other purpose, e.g., all "1's" in a relative timestamp field. Furthermore, not all fields are typically specified in most spline nodes. Fields that are not specified either default to a static value such as zero ("0"), or retain the value they had at the end of the previous spline node. This helps achieve space compression. For example, when one only wants to specify nonzero values ​​for the zeroth and second order coefficients of an amplitude spline, and the first and third order coefficients are completely fine as they are zero ("0"), the two first and third order coefficients can be omitted. In another example, if a single spline opcode can specify two or more parameters on the same line, space can be saved if the parameters are commonly used.

[0074] In another aspect, it is sometimes useful for a command line (eg, a row in a command table) to have additional information, such as modifiers to the amplitude or phase that the spline line can specify.

[0075] In another aspect, the instructions in the instruction table can have an alternative "jump" variant that compares one of N counters to a constant. If it is greater than or equal to the constant, the operation proceeds to the next instruction. Otherwise, the counter is incremented and then a jump is made to a user-defined row in the instruction table. A jump instruction does not cause a "subroutine call" to the spline table. Additionally, jump instructions can be distinguished from non-jump instructions by having a reserved bit in all instructions for that purpose or by using a special value.

[0076] In yet another aspect, there may be two kinds of timestamps used in conjunction with the function or spline table and the instruction table. For example, each instruction line may use a global timestamp (e.g., a timestamp related to tracking time since the experimental shot began), while each spline line has a narrower relative timestamp (e.g., a timestamp related to tracking time since the spline subroutine began). However, only the last line's timestamp can be used to control execution time. Lines other than the last line may use the timestamp field to indicate something else, such as not being the last line. The sum of the global and relative timestamps must correspond exactly to the current time, which is when the wide counter is cleared when the experimental shot begins in order for the first part of the spline subroutine to be executed.

[0077] The techniques described above provide a level of indirection when generating spline functions by using, in addition to the spline or function table, an instruction table that indicates how to reuse the spline table.

[0078] 6 illustrates a diagram 600 illustrating an example of a combined operation of an instruction table 610 and a function or spline table 620 according to an aspect of the disclosure. The instruction table 610 may correspond to an instruction table in table component 450 (see, e.g., diagram 400a in FIG. 4A and diagram 400b in FIG. 4B), while the spline table 620 may correspond to a spline table in table component 450.

[0079] The instruction table 610 in this example has two parameters, "call" and "jump." As mentioned above, "jump" is used to iterate through the instruction table and any number of counters can be compared to values ​​found in the instruction and incremented when jumping and repeating. In this example, there is one "call," one "jump," and one "end" in the program instructions. "End" is indicated by a "0" in the timestamp field (e.g., absolute timestamp), although other fields or special values ​​could be used to indicate "end" in the instruction table 610.

[0080] The difference between a "call" and a "jump" is indicated by a special value in a field. The field may be called a "jump to" field and may be, for example, a 12-bit field. In one example, the maximum value of the "jump to" field may be reserved to indicate a "jump" rather than a "call".

[0081] The "call" in this example is intended to call location "123" in spline table 620 and then return from spline table 620 three rows later. Therefore, rather than using an explicit return in spline table 620, it is possible to indicate in the "call" in instruction table 610 how long the subroutine is.

[0082] On the right side of the instruction table 610, there is a corresponding timestamp (absolute timestamp), which is the time when the "call" occurs. If it is not the current time, in this example, a large counter waits until it is the value "11". This value "11" is not the value that is used; rather, the engine performing the operations of these tables uses the value "11" in the instruction table 610 and fetches the corresponding value from the relative timestamp field in the spline table 620 (e.g., the third or right column in the spline table 620). The number "4" in the third column of the spline table 620 is added to "11" to get "15", which is the combined time value given by the absolute timestamp and the relative timestamp, and is the value that is used by the system to start execution (e.g., execution starts in "15" ticks).

[0083] Spline table 620 has an "Op Code" field (first or left column of spline table 620) that indicates which parameter is specified. This approach is in contrast to having a spline function or waveform defined by streaming from the host, which requires a large amount of memory. The intention here is to compress the content in the table as much as possible so that fewer bits of memory are used to represent common operations, parameters, etc. For example, in the first row shown for spline table 620 (e.g., line "123"), a single row can be used to specify a frequency value, in this case "200 MHz". In another example, in the second row shown for spline table 620 (e.g., line "124"), a single row can be used to specify the zeroth and third order values ​​of a gain parameter. For the gain parameter, the zeroth order is called the starting point, the first order is called the slope, the second order is called the acceleration, and the third order is called the jerk. In this example, the second row identifies the zero order or starting point value as "32k" and the third order or jerk as "0" (e.g., no jerk). In another example, the third row of spline table 620 is also specified with a phase value of "48°". The "-1" in the right column (e.g., relative timestamp) of the first and second rows of spline table 620 indicates that these rows are not the last rows of the subroutine. A bit field or some special value could also be used to indicate that a row is not the last row.

[0084] In general, there are many row groups that are done together and are part of something that happens simultaneously in the spline table 620. That is, multiple modifications done on the same row group are done in the same clock cycle, so all the commands are flattened into a final command.

[0085] The only one of these lines that is relevant in terms of timing is the last line (e.g., line "125"), which has a value of "4". The engine running the table operations runs through the various lines until it reaches line "125", the one line without a "-1" in the relative timestamp. The engine accumulates all the commands up to the last line and unpacks all the command operations that occur at the appropriate time. Parameters that are not specified in the various lines may default to zero values ​​and / or previous values ​​depending on how the system is configured to operate.

[0086] In addition to the various aspects described above, another aspect of the present disclosure includes adding functions to the instruction table that allow for fine-grained resetting of an embedded DDS (e.g., a DDS in DDS component 430). This can be useful when implementing pulse boundaries. For example, each non-jump instruction position can have a bit flag (e.g., a "resynchronize" bit flag) that causes the DDS to be instructed to reset its internal phase accumulator when the instruction's global and relative timestamps match the current time.

[0087] In this regard, the instruction table 610 may include another column, e.g., a single bit field, that may be renumbered by the engine executing the table when execution time is reached, and one of the things that may be done is to clear the phase accumulator for the DDS. That is, when execution time finally arrives (e.g., in the example diagram 600 of FIG. 6, the accumulated value is "15"), the engine may not only instruct each DDS to clear its internal phase to "0°", but may also instruct it to set it to the phase shown on line "125", i.e., to set its phase to "48°" instead.

[0088] In yet another embodiment, it may be possible to modify some parameters outside of the spline mechanism outlined above so that the parameters can be scaled globally without the need to download or update new splines for a particular atom or atomic ion signal generator (e.g., DDS). One example of such a modification may be to calibrate the optical power seen by the atom or atomic ion. It may be desirable to change the electrical amplitude every "shot" of every experiment so that changes to the brightness can be tracked with as little delay as possible. Techniques that increase the bandwidth in the control loop can be used to reduce latency so that rapid changes in brightness can be tracked without missing anything.

[0089] For example, since a DDS typically operates at full scale, any smaller values ​​can be achieved by multiplication or scaling after the parameterization function is provided by the DDS. If the DDS is implemented in an FPGA or ASIC, the DDS may include multipliers to perform such functions. Otherwise, external multipliers may be required. In either case, a multiplier may be used to adjust the parameters in the instruction table 610, a different multiplier may be used to adjust the parameters in the spline table 620, and / or a global multiplier may be used to adjust the parameters from either or both tables.

[0090] 6A has been described with reference to parameters for a waveform or parameterized function generated by a DDS, each pair of tables (e.g., command table 610 and spline table 620) may be used to control the operation of more than one DDS. In such cases, additional fields or columns may be used to indicate which of multiple supported DDSs is being controlled.

[0091] FIG. 7 is a diagram 700 illustrating an example of a computing device 705 according to an aspect of the disclosure. The computing device 705 may be used to implement aspects of a scalable, programmable coherent waveform generator for a QIP system. In one example, the computing device 700 may include a processor 710 for performing processing functions associated with one or more of the features described herein. For example, the computing device 705 may be used to control and / or manage the operation of the DAC card 410, the distribution network of diagrams 500a and 500b, and / or tables 610 and 620 described above in connection with FIGS. 4A-6. The processor 710 may include a single or multiple sets of processors or multi-core processors. Additionally, the processor 710 may be implemented as an integrated processing system and / or a distributed processing system. The processor 710 may include a central processing unit (CPU), a quantum processing unit (QPU), a graphics processing unit (GPU), or a combination of these types of processors. In one aspect, the processor 710 may refer to a general processor of the computing device 700, which may also include additional processors 710 that perform more specific functions.

[0092] In one example, computing device 705 may include memory 720 that stores instructions executable by processor 710 to perform functions described herein. In one implementation, for example, memory 720 may correspond to a computer-readable storage medium that stores code or instructions for performing one or more functions or operations described herein. In one example, memory 720 may include instruction tables and spline tables. As with processor 710, memory 720 may refer to the general memory of computing device 705, which may also include additional memory 720 that stores instructions and / or data for more specific functions.

[0093] Additionally, computing device 705 may include a communications component 730 that provides for establishing and maintaining communications with one or more parties that utilize the hardware, software, and services. Communications component 730 may effect communications both among components on computing device 705 and between computing device 705 and external devices, such as devices located over a communications network and / or devices serially or locally connected to computing device 705. For example, communications component 730 may include one or more buses and may further include transmit chain and receive chain components associated with transmitters and receivers, respectively, operable to interface with external devices.

[0094] Additionally, computing device 705 may include data store 740, which may be any suitable combination of hardware and / or software that provides mass storage of information, databases, and programs used in connection with the implementations described herein. For example, data store 740 may be a data repository for operating system 760 (e.g., Classic OS or Quantum OS). In one implementation, data store 740 may include memory 720.

[0095] The computing device 705 may also include a user interface component 750 operable to receive input from a user of the computing device 705 and further operable to generate output for presentation to the user or to provide (directly or indirectly) to a different system. The user interface component 750 may include one or more input devices. The input devices include, but are not limited to, a keyboard, a number pad, a mouse, a touch-sensitive display, a digitizer, navigation keys, function keys, a microphone, a voice recognition component, any other mechanism capable of receiving input from a user, or any combination thereof. Additionally, the user interface component 750 may include one or more output devices. The output devices include, but are not limited to, a display, a speaker, a haptic feedback mechanism, a printer, any other mechanism capable of presenting output to a user, or any combination thereof.

[0096] In one implementation, user interface component 750 can send and / or receive messages corresponding to the operation of operating system 760. Additionally, processor 710 can execute, and memory 720 or data store 740 can store, operating system 760 and / or applications, programs, or algorithms.

[0097] When computing device 705 is implemented as part of a cloud-based infrastructure solution, user interface component 750 may be used to enable a user of the cloud-based infrastructure solution to interact with computing device 705 remotely.

[0098] 8 is a block diagram illustrating an example of a QIP system 605 according to an aspect of the disclosure. The QIP system 805 may also be referred to as a quantum computing system, a quantum computer, a computing device, etc. In one aspect, the QIP system 805 may correspond to portions of a quantum computing implementation of the computing device 705 of FIG.

[0099] The QIP system 805 may include a source 860 that provides atomic species (e.g., a flux of neutral atoms) to a chamber 850 having an ion trap 870 that traps the atomic species once ionized (e.g., photoionized) by the optical controller 820. The ion trap 870 may be used to trap ions in a crystal (as illustrated in diagram 100a of FIG. 1A). The light source 830 in the optical controller 820 may include one or more laser or light beam sources that may be used for ionization of atomic species, control (e.g., phase control) of atomic ions, fluorescence of atomic ions that may be monitored and tracked by image processing algorithms operating in an imaging system 840 in the optical controller 820, and / or to perform other optical control functions associated with the techniques described above. In one aspect, the light source 830 may be implemented separately from the optical controller 820.

[0100] The imaging system 840 may include a high resolution imager (e.g., a CCD camera) for monitoring the atomic ions while they are provided to the ion trap or after they are provided to the ion trap 870. In one aspect, the imaging system 840 may be implemented separately from the optical controller 820, although the use of fluorescence to detect, identify, and label the atomic ions using image processing algorithms may need to be coordinated with the optical controller 820.

[0101] An acousto-optic modulator (AOM) 845 may be used to perform modulation of a laser or light beam generated by light source 830. In this regard, optical controller 820 may also include a DAC card 846, which may be an example of DAC card 410 described above, which may be used to generate an output to drive a radio frequency (RF) source 847 to modulate AOM 845.

[0102] QIP system 805 may also include an algorithm component 810, which may operate with other parts of QIP system 805 (not shown) to perform quantum algorithms or operations, including single-qubit or multi-qubit operations and extended quantum computation. As such, algorithm component 810 may provide instructions to various components of QIP system 805 (e.g., optical controller 820) to enable implementation of quantum algorithms or operations, which may in turn implement the various techniques described herein.

[0103] QIP system 805 may also include a distribution network 880, which may include a clock signal network 882 corresponding to the distribution network described above in connection with diagram 500b of Figure 5B, and a wake-up signal network 883 corresponding to the distribution network described above in connection with diagram 500a of Figure 5A. Distribution network 880 may be used to provide a common signal to multiple DAC cards 486 and / or other portions of QIP system 805.

[0104] Although the present disclosure has been provided according to the illustrated implementation, those skilled in the art will readily recognize that there may be variations in the embodiments and that these variations are also within the scope of the present disclosure. Accordingly, those skilled in the art may make many modifications without departing from the scope of the appended claims.

Claims

1. 1. A digital-to-analog converter (DAC) card for controlling quantum bits in a quantum information processing (QIP) system, comprising:

1. A digital logic component comprising: one or more direct digital synthesizers (DDS) for each output of the DAC card, each output controlling one or more light beams for separate quantum bits of the QIP system; a pair of tables that collectively provide commands to one or more DDSs, a first table of the pair of tables being a function table and a second table of the pair of tables being an instruction table, the function table defining a parameterized function generated by the one or more DDSs, and the instruction table defining a subroutine call to the function table or a conditional loop instruction of the function table; a digital logic component having one or more DAC components, each providing one or more of the outputs of the DAC card, each DAC component receiving a parameterized function generated by the one or more DDSs and generating the one or more outputs, the parameterized function being in digital form and the one or more outputs being in analog form; Equipped with the parameterized function defined by the function table is a spline curve, and parameters of each segment of the spline curve include one or more of amplitude, phase, or frequency; The amplitude is defined by one or more of an onset or zero order, a slope or first order, an acceleration or second order, or a jerk or third order.

2. 2. The DAC card of claim 1, wherein the parameterized function defined by the function table is a spline curve, the function table including a plurality of spline nodes, each spline node including parameters for defining a respective segment of the spline curve.

3. 3. The DAC card of claim 2, wherein each spline node includes one or more consecutive rows, each row specifying different parameters of the respective segment of the spline curve.

4. 4. The DAC card of claim 3, wherein each row has an identifier that identifies the different parameters defined by the row.

5. The DAC card of claim 4 , wherein the identifier identifies two or more different parameters defined by the row.

6. 3. The DAC card of claim 2, wherein an end of each spline node is explicitly identified in a last row of one or more consecutive rows of said spline nodes.

7. 7. The DAC card of claim 6, wherein each row of a spline table includes a timestamp field, and the explicit identification of the last row is made in the timestamp field of each of the last rows.

8. 3. The DAC card of claim 2, wherein one or more different parameters of the respective segments of the spline curve that are not specified in one or more rows of the spline node default to a static value or retain a value from the end of the previous spline node.

9. the parameterized function defined in the function table is a spline curve, and parameters of each segment of the spline curve include one or more of amplitude, phase, or frequency; the instruction table includes instructions for modifying one or both of the amplitude or phase parameters; 2. The DAC card of claim 1.

10. 2. The DAC card of claim 1, wherein the instruction table includes one or more jump instructions, each of which compares one of N counters to a constant and, if greater than or equal to the constant, falls through to a next instruction and, if less than the constant, increments the counter and jumps to a user-defined row of the instruction table.

11. 11. The DAC card of claim 10, wherein the one or more jump instructions are distinguishable from other instructions in the instruction table by having a reserved bit or by using a special value.

12. 2. The DAC card of claim 1, wherein the rows of the instruction table include a global timestamp field for tracking operations since the start of an experimental shot, and the rows of the function table include relative timestamps for tracking operations associated with spline nodes defining respective segments of the parameterized function.

13. 13. The DAC card of claim 12, wherein the current time at which the spline node is executed is the sum of a global timestamp value and the relative timestamp value.

14. 2. The DAC card of claim 1, wherein for instructions in the instruction table that are different from a jump instruction, a bit flag resynchronization is configured to cause the one or more DDSs associated with the instruction table to reset an internal phase accumulator at a boundary of the parameterized function.

15. 15. The DAC card of claim 14, wherein the reset of the internal phase accumulator occurs when a value of a global timestamp field in the instruction table and a value of a relative timestamp field in the function table match a current time.

16. The DAC card of claim 1 , further comprising one or more amplifiers configured to control an amplitude of the one or more outputs of each DAC component.

17. 2. The DAC card of claim 1, wherein the digital logic components are implemented in a programmable integrated circuit, and the function table and the instruction table are implemented in separate memories within the programmable integrated circuit.

18. the DAC card has two or more outputs; For each output of the digital logic component of the DAC card, there is a pair of DDSs; For each pair of DDS, there is a pair of tables, 2. The DAC card of claim 1.

19. 2. The DAC card of claim 1, wherein each distinct quantum bit of the QIP system being controlled corresponds to an atom or atomic ion in a trap of the QIP system.

20. The DAC card of claim 1 , further comprising: interface logic connecting the digital logic component to the one or more DAC components.

21. 2. The DAC card of claim 1, further comprising a clock divider / duplicator device having an input SYNC pin, the digital logic component configured to receive a wake-up signal, the wake-up signal being used to assert the input SYNC pin of the clock divider / duplicator device unless the wake-up signal is masked by the digital logic component.

22. 22. The DAC card of claim 21, wherein the digital logic component includes an asynchronous logic component configured to receive the wake-up signal and generate another signal to assert the input SYNC pin of the clock divider / duplicator device.

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