Quantum operation device and method for manufacturing the same

Abstract

A quantum computing device (10) comprises: a layered plurality of substrates (20, 30, 40) that includes a substrate (20) provided with a quantum bit element (11); and through vias (35A, 35B, 45A, 45B) that are provided to, of the plurality of substrates (20, 30 ,40), at least the substrate (40) which is disposed in the uppermost layer and the substrate (30) which is disposed in the lowermost layer, and that are electrically connected to the substrate (20) which is disposed in an adjacent layer.

Description

[Technical field]

[0001] The disclosed technology relates to a quantum processing device and a method for manufacturing a quantum processing device. [Background technology]

[0002] The following techniques are known as techniques related to quantum computing devices. For example, a quantum computer system is known that includes a plurality of quantum bit elements arranged in a two-dimensional layout, and at least one internal quantum bit element of the plurality of quantum bit elements includes a signal line extending outside the two-dimensional layout of the plurality of quantum bit elements. The internal quantum bit element includes a plurality of layers, and an upper layer of the plurality of layers includes a through hole to a bottom layer, and a signal line is placed in the through hole to connect the bottom layer to the upper layer.

[0003] Also known is a quantum device including a first set of bumps formed on a substrate and a second set of bumps formed on a qubit chip, the quantum device including a set of bumps formed on an interposer, the set of bumps being formed of a material having a ductility above a threshold in the room temperature range, a first subset of the set of bumps configured to be cold welded to the first set of bumps, and a second subset of the set of bumps configured to be cold welded to the second set of bumps. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2019 / 287946 [Patent Document 2] US Patent Application Publication No. 2020 / 259064 Summary of the Invention [Problem to be solved by the invention]

[0005] A quantum computing device including a quantum bit element (Qubit) may include a control port for controlling the quantum bit element from the outside. The quantum computing device may also include a read port for reading out a bit signal indicating the state of the quantum bit element to the outside. The quantum computing device may also include a ground port for applying a ground potential to an arithmetic circuit including the quantum bit element. The quantum computing device is maintained at an extremely low temperature in a vacuum chamber, and input / output of signals related to arithmetic processing and supply of potentials are performed via probes that are abutted against access ports such as the control port, read port, and ground port. The probes are housed inside the dilution refrigerator together with the quantum computing device.

[0006] The number of required probes increases with the number of bits in the quantum computing device. As quantum bit devices become more multi-bit and more compact, the port density increases, and the probe density increases accordingly. This can cause poor contact between each port and the probe, or signal crosstalk between the ports.

[0007] The disclosed technology aims to suppress the increase in density of access ports that accompanies increased bit counts and miniaturization in quantum processing devices. [Means for solving the problem]

[0008] A quantum computing device according to the disclosed technology includes a plurality of stacked substrates including a substrate having a quantum bit element provided thereon, a first through via provided through a first substrate arranged in an uppermost layer among the plurality of substrates and electrically connected to a substrate arranged in a layer adjacent to the first substrate, and a second through via provided through a second substrate arranged in the lowermost layer among the plurality of substrates and electrically connected to a substrate arranged in a layer adjacent to the second substrate. Effect of the Invention

[0009] According to the disclosed technology, it is possible to suppress the increase in density of access ports that accompanies the increase in bit count and miniaturization in a quantum processing device. [Brief description of the drawings]

[0010] [Figure 1] 1 is a partial equivalent circuit diagram of a quantum processing device according to an embodiment of the disclosed technique. [Diagram 2] FIG. 1 is a diagram illustrating an example of a connection configuration between quantum bit elements according to an embodiment of the disclosed technique. [Diagram 3] 1 is a schematic cross-sectional view showing an example of a configuration of a quantum processing device according to an embodiment of the disclosed technique. [Figure 4] 2 is an exploded view showing first to third substrates constituting a quantum processing device according to an embodiment of the disclosed technique. FIG. [Figure 5A] 1 is a diagram showing an example of a state in which a probe is in contact with a quantum processing device according to an embodiment of the disclosed technique; [Figure 5B] 1 is a diagram showing an example of a state in which a probe is in contact with a quantum processing device according to an embodiment of the disclosed technique; [Figure 6A] 1 is a plan view showing an example of a configuration of a seal member according to an embodiment of the disclosed technique; [Figure 6B] 1 is a plan view showing a state in which a through hole constituting a through via according to an embodiment of the disclosed technique is blocked by an electrode. [Figure 7] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 8] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 9] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 10] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 11] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 12] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 13]1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 14] 1 is a cross-sectional view showing an example of a manufacturing method of a quantum processing device according to an embodiment of the disclosed technique; [Figure 15] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 16] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 17] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 18] 1A to 1C are cross-sectional views showing an example of a manufacturing method for a quantum processing device according to an embodiment of the disclosed technique. [Figure 19] 11 is a cross-sectional view showing an example of the configuration of a quantum processing device according to another embodiment of the disclosed technology. [Figure 20] 11 is a cross-sectional view showing an example of the configuration of a quantum processing device according to another embodiment of the disclosed technology. [Figure 21A] 11 is a cross-sectional view showing an example of the configuration of a quantum processing device according to another embodiment of the disclosed technology. [Figure 21B] 11 is a cross-sectional view showing an example of the configuration of a quantum processing device according to another embodiment of the disclosed technology. [Figure 22] 11 is a cross-sectional view showing an example of the configuration of a quantum processing device according to another embodiment of the disclosed technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and duplicated descriptions will be omitted.

[0012] [First embodiment] 1 is a partial equivalent circuit diagram of a quantum processing device 10. The quantum processing device 10 has a quantum bit element (Qubit) 11, a resonator 12, a read port 13, a ground port 14, and a control port 15.

[0013] The quantum bit element 11 is an element that forms a coherent two-level system using superconductivity, and includes a transmon quantum bit circuit in which a superconducting Josephson element 201 and a capacitor 202 are connected in parallel. The superconducting Josephson element 201 includes a pair of superconductors that exhibit superconductivity at a temperature equal to or lower than a predetermined critical temperature, and an extremely thin insulator having a thickness of about several nm sandwiched between the pair of superconductors. The superconductor may be, for example, aluminum, and the insulator may be, for example, aluminum oxide.

[0014] As shown in Fig. 2, in a quantum computing device 10, a plurality of quantum bit elements 11 are connected to adjacent quantum bit elements 11 via inter-bit wiring 221. A capacitor 222 is provided on the path of the inter-bit wiring 221. As a result, each of the quantum bit elements 11 creates a quantum entangled state with the adjacent quantum bit elements 11 to perform quantum computing. Fig. 1 shows only the peripheral configuration of one quantum bit element 11.

[0015] The resonator 12 interacts with the quantum bit element 11 to read out a bit signal indicating the state of the quantum bit element 11. The resonator 12 is connected to the quantum bit element 11 via a capacitor 16. The resonator 12 includes a resonant circuit in which a superconducting inductor 211 and a capacitor 212 are connected in parallel.

[0016] The readout port 13, the ground port 14, and the control port 15 are access ports for externally accessing the quantum operation circuit including the quantum bit element 11 and the resonator 12. The readout port 13 is connected to the resonator 12 via a capacitor 17. The readout port 13 is used to externally extract a bit signal read out by the resonator 12. The ground port 14 is connected to the quantum bit element 11 and the resonator 12. The ground port 14 is used to externally apply a ground potential to the quantum bit element 11 and the resonator 12. The control port 15 is connected to the quantum bit element 11 via a capacitor 18. The control port 15 is used to externally control the quantum bit element 11.

[0017] FIG. 3 is a schematic cross-sectional view showing an example of the configuration of the quantum processing device 10. FIG. 3 shows only the configuration around one quantum bit element 11. The quantum processing device 10 has a configuration in which a first substrate 30, a second substrate 40, and a third substrate 50 are stacked. In this embodiment, the second substrate 30 is disposed in the bottom layer, the third substrate 40 is disposed in the top layer, and the first substrate 20 is disposed in an intermediate layer between the top layer and the bottom layer. FIG. 4 is a view showing the first substrate 20, the second substrate 30, and the third substrate 40 in an exploded manner to facilitate understanding of the configurations of these substrates.

[0018] A quantum bit element 11 is provided on the lower surface of the first substrate 20, and a resonator 12 is provided on the upper surface of the second substrate 30. The resonator 12 is formed by patterning a conductive film 50A. The second substrate 30 is bonded to the lower surface side of the first substrate 20 via a sealing member 60 so that its upper surface faces the lower surface of the first substrate 20. The quantum bit element 11 and the resonator 12 are connected to each other via a wiring 21 and bumps 22 and 32. The sealing member 60 is configured to include a laminated film in which a conductive film 50A and a conductive film 50B are laminated. The wiring 21 is configured by the conductive film 50A, and the bumps 22 and 32 are each configured by the conductive film 50B.

[0019] A control electrode 70 is provided on the upper surface of the first substrate 20, to which a control signal for controlling the quantum bit element 11 is supplied. The control electrode 70 is disposed directly above the quantum bit element 11, and the control signal supplied to the control electrode 70 is transmitted to the quantum bit element 11 via the base material of the first substrate 20. The third substrate 40 is joined to the upper surface side of the first substrate 20 via a seal member 60 so that the lower surface of the third substrate 40 faces the upper surface of the first substrate 20.

[0020] The first substrate 20 is provided with through vias 25A and 25B, the second substrate 30 is provided with through vias 35A and 35B, and the third substrate 40 is provided with through vias 45A and 45B. Each of these through vias includes a through hole 51 penetrating the substrate and a conductive film 50B covering the inner wall of the through hole 51. These through vias are electrically connected to an electrode 71 or a control electrode 70 provided on a substrate arranged in an adjacent layer. The control electrode 70 and the other electrodes 71 are each configured to include a laminated film in which the conductive film 50A and the conductive film 50B are laminated.

[0021] The through via 35A of the second substrate 30 functions as a ground port 14. That is, when the quantum computing device 10 is used, as shown in FIG. 5A, a probe 300A fixed to a ground potential is abutted against the through via 35A. The ground potential supplied from the probe 300A is provided to each element provided on the upper and lower surfaces of the second substrate 30 by the through via 35A. The ground potential is also provided to the resonator 12. The through via 35A is electrically connected to the through via 25A of the first substrate 20, and the ground potential is provided to each element provided on the upper and lower surfaces of the first substrate 20. The ground potential is also provided to the quantum bit element 11. The through via 25A is electrically connected to the through via 45A of the third substrate 40, and the ground potential is provided to each element provided on the upper and lower surfaces of the third substrate 40.

[0022] Both the through via 35A of the second substrate 30 and the through via 45A of the third substrate 40 may function as the ground port 14. That is, when the quantum processing device 10 is in use, a probe 300A fixed to the ground potential may be brought into contact with each of the through vias 35A and 45A as shown in FIG.

[0023] The through via 35B of the second substrate 30 is electrically connected to the resonator 12. The through via 35B functions as a read port 13 for reading out a bit signal indicating the state of the quantum bit element 11. That is, when the quantum computing device 10 is in use, as shown in Figures 5A and 5B, a probe 300B is brought into contact with the through via 35B, and the bit signal is extracted to the outside by the probe 300B.

[0024] The through via 45B of the third substrate 40 is electrically connected to the control electrode 70 provided on the first substrate 20. The through via 45B functions as a control port 15 for controlling the quantum bit element 11 from the outside. That is, as shown in FIG. 5A and FIG. 5B, when the quantum processing device 10 is used, the probe 300C is abutted against the through via 45B, and a control signal for controlling the quantum bit element 11 supplied from the probe 300C is given to the control electrode 70 through the through via 45B. The quantum processing device 10 is used in a vacuum chamber in a state where it is kept at an extremely low temperature. The probes 300A, 300B, and 300C can be accommodated inside the dilution refrigerator together with the quantum processing device 10.

[0025] The through vias 25B of the first substrate 20 are used as paths for introducing gas for removing the protective film covering the surface of the quantum bit element 11 in the manufacturing process of the quantum processing device 10. The manufacturing process of the quantum processing device 10 will be described later.

[0026] A space 80 is formed between the first substrate 20 and the second substrate 30, and between the first substrate 20 and the third substrate 40. A space 80 is also formed around the quantum bit element 11. A through hole 51 constituting the through via 25B of the first substrate 20 used as a gas introduction path communicates with the space 80 extending around the quantum bit element 11.

[0027] Here, FIG. 6A is a plan view showing an example of the form of a seal member 60 forming a joint between the first substrate 20 and the second substrate 30 and a joint between the first substrate 20 and the third substrate 40. As shown in FIG. 6, the seal member 60 is ring-shaped and surrounds a space 80 formed between the substrates. In this way, the space 80 is sealed by joining the substrates via the ring-shaped seal member 60 surrounding the space 80. In addition, the opening ends of the through holes 51 constituting the through vias 35A and 35B of the second substrate 30 are blocked by an electrode 71 provided on the lower surface of the first substrate 20. Similarly, the opening ends of the through holes 51 constituting the through vias 45A and 45B of the third substrate 40 are blocked by an electrode 71 and a control electrode 70 provided on the upper surface of the first substrate 20. 6B is a plan view showing a state in which the through holes 51 constituting the through vias 35A, 35B, 45A, and 45B are respectively blocked by the electrode 71 or the control electrode 70. In this manner, by blocking the open ends of the through holes 51 constituting the through vias 45A and 45B of the third substrate 40 and the through vias 35A and 35B of the second substrate 30 with the electrode 71 or the control electrode 70 provided on the first substrate 20, the space 80 is brought into a completely sealed state.

[0028] It is preferable that the sealed space 80 is a vacuum. By making the space 80 a vacuum, it is possible to suppress the adsorption of substances to the quantum bit element 11 without forming a protective film that causes dielectric loss on the surface of the quantum bit element 11, and it is possible to always keep the surface of the quantum bit element 11 clean. Note that the vacuum is not limited to a complete vacuum, and includes a low-pressure state that has an effect of substantially suppressing the adsorption of substances to the quantum bit element 11.

[0029] The conductive films 50A and 50B constituting the elements provided on the first to third substrates are preferably made of a metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature. Although not particularly limited, the conductive film 50A can be preferably made of, for example, titanium nitride (TiN), and the conductive film 50B can be preferably made of, for example, aluminum (Al).

[0030] The following describes a method for manufacturing the quantum processing device 10. First, an example of a method for manufacturing the first substrate 20 will be described with reference to FIGS.

[0031] A base material 20a constituting the first substrate 20 is prepared. For example, a silicon substrate can be used as the base material 20a (FIG. 7). Next, a conductive film 50A is formed on each of the upper and lower surfaces of the base material 20a by, for example, a vapor deposition method. For example, TiN (titanium nitride) can be suitably used as the conductive film 50A (FIG. 8). Next, the conductive film 50A is patterned using a known photolithography technique to form wiring 21 and the like (FIG. 9).

[0032] Next, the quantum bit element 11 is formed on the surface of the substrate 20a (FIG. 10). The superconducting Josephson element constituting the quantum bit element 11 is formed, for example, by a process of forming a first electrode (not shown) containing Al (aluminum) on the surface of the substrate 20a by a vapor deposition method, a process of forming an extremely thin oxide film (not shown) with a thickness of about several nm on the surface of the first electrode using O2 gas, and a process of forming a second electrode (not shown) containing Al (aluminum) on the surface of the oxide film by a vapor deposition method. The patterning of the first electrode and the second electrode may be performed, for example, by a lift-off method using a patterned resist (not shown). In this case, the opening pattern of the resist may be a cross shape including a first straight portion along the first direction and a second straight portion along a second direction perpendicular to the first direction, and the first electrode may be formed in a portion corresponding to the first straight portion by performing vapor deposition while tilting the first direction as the rotation axis. Subsequently, the second electrode may be formed in a portion corresponding to the second straight portion by performing vapor deposition while tilting the second direction as the rotation axis. According to the above method, the first electrode and the second electrode can be patterned using a single resist.

[0033] Next, a protective film 90 made of an insulator such as SiO2 is formed on the surface of the base material 20a by, for example, a CVD (chemical vapor deposition) method. The quantum bit element 11 is covered with the protective film 90. Next, the protective film 90 is patterned using a known photolithography technique. The protective film 90 is removed except for the portion covering the quantum bit element 11 (FIG. 11).

[0034] Next, a resist (not shown) is formed on the surface of the base material 20a, and the resist is patterned. Using the patterned resist as a mask, through-holes 51 are formed in the base material 20a by, for example, deep RIE (Reactive Ion Etching) (FIG. 12).

[0035] Next, a conductive film 50B is formed on the upper and lower surfaces of the base material 20a by, for example, a vapor deposition method. The surface of the conductive film 50A and the inner wall of the through hole 51 are covered with the conductive film 50B. For example, Al (aluminum) can be suitably used as the conductive film 50B. The conductive film 50B is patterned by, for example, a lift-off method (FIG. 13). On the surface of the base material 20a, a control electrode 70 including a laminated film obtained by laminating the conductive film 50A and the conductive film 50B, other electrodes 71, a ring-shaped seal member 60, and the like are formed. In addition, the inner wall of the through hole 51 is covered with the conductive film 50B, thereby forming the through vias 25A and 25B.

[0036] The first substrate 20 is completed through the above steps. The second substrate 30 and the third substrate 40 are manufactured in a similar manner to the first substrate 20, and therefore the manufacturing methods for these substrates will not be described.

[0037] An example of a method for forming the quantum processing device 10 by combining the first substrate 20, the second substrate 30, and the third substrate 40 will be described below with reference to FIGS.

[0038] The first substrate 20 and the second substrate 30 are accommodated in a vacuum chamber (not shown), and in the vacuum chamber, the lower surface of the first substrate 20 and the upper surface of the second substrate 30 are irradiated with an ion beam (FIG. 14). As a result, elements that hinder bonding, such as an oxide film, hydroxyl groups, and water molecules, present on the surface of the conductive film 50B that forms the bonding portion between the first substrate 20 and the second substrate 30 are removed, and the surface of the conductive film 50B is activated. In addition, resist residues and adsorbed substances present on the surfaces of the first substrate 20 and the second substrate 30 are removed, and the surfaces of the first substrate 20 and the second substrate 30 are cleaned. An inert gas such as argon is used for the ion beam. Since the quantum bit element 11 is covered with a protective film 90, damage to the quantum bit element 11 caused by the ion beam irradiation is suppressed.

[0039] Next, the first substrate 20 and the second substrate 30 are bonded in a vacuum chamber. That is, the seal member 60 of the first substrate 20 and the seal member 60 of the second substrate 30 are bonded, the electrode 71 of the first substrate 20 and the through vias 35A and 35B of the second substrate 30 are bonded, and the bump 22 of the first substrate 20 and the bump 32 of the second substrate 30 are bonded. Since the surface of the conductive film 50B constituting each of these elements is activated by ion beam irradiation, it is possible to obtain a strong bond at room temperature (about 25°C). This method is called surface activation room temperature bonding. By performing the bonding between the substrates at room temperature, the characteristic fluctuation due to heating of the quantum bit element 11 is suppressed. The open ends of the through holes 51 constituting the through vias 35A and 35B of the second substrate 30 are blocked by the electrode 71 of the first substrate 20. The first substrate 20 and the second substrate 30 are joined with a gap therebetween, and a space 80 is formed around the quantum bit device 11 (FIG. 15).

[0040] Next, an etching gas such as vapor HF gas is introduced into the space 80 around the quantum bit element 11 from the through hole 51 constituting the through via 25B of the first substrate 20. This removes the protective film 90 covering the quantum bit element 11 and also removes the silicon oxide film (SiO2) formed on the surfaces of the first substrate 20 and the second substrate 30, cleaning the surfaces of the first substrate 20 and the second substrate 30 (FIG. 16).

[0041] Next, the first substrate 20 and the second substrate 30 bonded together and the third substrate 40 are housed in a vacuum chamber (not shown), and an ion beam is irradiated onto the upper surface of the first substrate 20 and the lower surface of the third substrate 40 in the vacuum chamber (FIG. 17). This removes elements that hinder bonding, such as oxide films, hydroxyl groups, and water molecules, present on the surface of the conductive film 50B that forms the bonding portion between the first substrate 20 and the third substrate 40, and activates the surface of the conductive film 50B. In addition, resist residues and adsorbed substances present on the surfaces of the first substrate 20 and the third substrate 40 are removed, and the surfaces of the first substrate 20 and the third substrate 40 are cleaned.

[0042] Next, the first substrate 20 and the third substrate 40 are bonded in a vacuum chamber. That is, the seal member 60 of the first substrate 20 and the seal member 60 of the third substrate 40 are bonded, the electrode 71 of the first substrate 20 and the through via 45A of the third substrate are bonded, the control electrode 70 of the first substrate 20 and the through via 45B of the third substrate 40 are bonded, and the through via 25B of the first substrate 20 and the electrode 71 of the third substrate 40 are bonded (FIG. 18). The surface of the conductive film 50B constituting each of these elements is activated by ion beam irradiation, so that it is possible to obtain a strong bond at room temperature (about 25° C.). The through via 25B of the first substrate 20 is blocked by the electrode 71 of the third substrate 40. Furthermore, the through vias 45A and 45B of the third substrate 40 are respectively blocked by the electrode 71 and the control electrode 70 of the first substrate 20. Through the above steps, the quantum processing device 10 is completed.

[0043] As described above, the quantum computing device 10 according to the embodiment of the disclosed technique includes the first substrate 20 on which the quantum bit elements are provided, the second substrate 30 laminated on the lower surface side of the first substrate 20, and the third substrate 40 laminated on the upper surface side of the first substrate 20. Among these substrates, the second substrate 30 arranged in the lowest layer is provided with the through via 35A functioning as the ground port 14 and the through via 35B functioning as the read port 13. The third substrate 40 arranged in the highest layer is provided with the through via 45B functioning as the control port 15. The through via 45A of the third substrate 40 can also be used as the ground port 14. These through vias 35A, 35B, 45A, and 45B are each electrically connected to the first substrate 20 arranged in the middle layer.

[0044] When the quantum processing device 10 is in use, as shown in Fig. 5A and Fig. 5B, the probes 300A-300C are brought into contact with the through vias 35A, 35B, 45A, and 45B, thereby making it possible to access the quantum processing circuit including the quantum bit element 11 and the resonator 12. The number of probes required increases with an increase in the number of bits of the quantum processing device 10. As the quantum processing device 10 becomes more multi-bit and more compact, the density of the ports increases, and the density of the probes increases accordingly. This may cause poor contact between each port and the probe, or signal crosstalk between the ports.

[0045] In the quantum processing device 10 according to this embodiment, the through vias 35A, 35B, 45A, and 45B that function as access ports to which the probes come into contact are distributed on both sides of the quantum processing device 10. This makes it possible to suppress the density of the access ports associated with the multi-bit and miniaturization, compared to a case in which the through vias 35A, 35B, 45A, and 45B are provided only on one side. In addition, by using both the through via 35A of the second substrate 30 and the through via 45A of the third substrate 40 as the ground port 14, the ground potential supplied to each part of the quantum processing device 10 can be made uniform and stable.

[0046] Here, the time during which the quantum bit element 11 can continue quantum operations is called the coherence time. The coherence time is sensitive to the state around the quantum bit element 11. For example, if a dielectric such as an oxide film is present around the quantum bit element 11, the coherence time is shortened due to dielectric loss. For this reason, it is preferable not to form an insulating film such as a protective film on the surface of the quantum bit element 11. The quantum operation device 10 is kept at an extremely low temperature in a vacuum chamber, but adsorbates that are adsorbed in the atmosphere and cause decoherence are cooled and remain there. Since the coherence time is shortened by the adsorbates adsorbed on the surface of the quantum bit element 11, it is necessary to always keep the surface of the quantum bit element 11 clean. In the quantum operation device 10 according to this embodiment, the space 80 formed around the quantum bit element 11 is in a vacuum sealed state. This makes it possible to suppress the adsorption of substances to the quantum bit element 11 without forming a protective film that causes dielectric loss on the surface of the quantum bit element 11, and to always keep the surface of the quantum bit element 11 clean.

[0047] The characteristics of the superconducting Josephson element 201 constituting the quantum bit element 11 may vary due to heating. According to the manufacturing method of the quantum computing device 10 of this embodiment, the first substrate 20 and the second substrate 30 are bonded together, and the first substrate 20 and the third substrate 40 are bonded together by surface activation room temperature bonding. Therefore, it is possible to avoid the characteristic variation caused by heating the quantum bit element 11. In the surface activation room temperature bonding, an ion beam is irradiated onto the surface of each substrate. According to the manufacturing method of the quantum computing device 10 of this embodiment, the quantum bit element 11 is covered with a protective film 90 during the ion beam irradiation. This makes it possible to suppress damage to the quantum bit element 11 caused by the ion beam irradiation.

[0048] Furthermore, according to the manufacturing method of the quantum processing device 10 of this embodiment, the protective film 90 covering the quantum bit element 11 is removed after bonding the first substrate 20 and the second substrate 30. This makes it possible to eliminate factors that shorten the coherence time.

[0049] Furthermore, according to the manufacturing method of the quantum computing device 10 of this embodiment, the protective film 90 is removed by introducing an etching gas from the through hole 51 communicating with the space 80 formed around the quantum bit element 11 after the first substrate 20 and the second substrate 30 are bonded together. This makes it possible to efficiently remove the protective film 90 and clean the surfaces of the first substrate 20 and the second substrate 30.

[0050] In the present embodiment, the quantum processing device 10 has a three-layer structure in which the first substrate 20, the second substrate 30, and the third substrate 40 are stacked. However, the quantum processing device 10 may have a two-layer structure or may have four or more layers. FIG. 19 is a schematic cross-sectional view showing an example of the configuration of a two-layer quantum processing device 10A. The quantum processing device 10A differs from the quantum processing device 10 shown in FIG. 3 and the like in that it does not have a third substrate 40. That is, in the quantum processing device 10A, the first substrate 20 is disposed in the uppermost layer, the control electrode 70 functions as the control port 15, and the probe 300C is abutted against the control electrode 70. In the quantum processing device 10A, the space 80 around the quantum bit element 11 is open to the atmosphere through the through hole 51 constituting the through via 25B.

[0051] In addition, in the present embodiment, the quantum bit element 11 is provided on the first substrate 20, and the resonator 12 is provided on the second substrate 30, but the quantum bit element 11 and the resonator 12 may be provided on the same substrate. Fig. 20 is a schematic cross-sectional view showing an example of the configuration of a quantum processing device 10B in which the quantum bit element 11 and the resonator 12 are provided on the first substrate 20.

[0052] In the present embodiment, the through via having the through hole 51 communicating with the space 80 around the quantum bit element 11 is provided in the first substrate 20, but the through via having the through hole 51 communicating with the space 80 may be provided in a substrate other than the first substrate 20. For example, as in the quantum processing device 10C shown in FIG. 21A, the through hole 51 constituting the through via 35C provided in the second substrate 30 may communicate with the space 80 around the quantum bit element 11. In this case, as in the quantum processing device 10D shown in FIG. 21B, the third substrate 40 may be joined to the lower surface side of the second substrate 30, and the opening end of the through hole 51 of the second substrate 30 communicating with the space 80 may be blocked by the electrode 71 of the third substrate 40. In the quantum processing device 10D, the through via 25A of the first substrate 20 arranged in the uppermost layer and the through via 45A of the third substrate 40 arranged in the lowermost layer each function as the ground port 14. The through via 45B of the third substrate 40 arranged in the bottom layer functions as the read port 13. The control electrode 70 of the first substrate 20 arranged in the top layer functions as the control port 15.

[0053] [Second embodiment] 22 is a schematic cross-sectional view showing an example of the configuration of a quantum processing device 10E according to the second embodiment of the disclosed technology. In the quantum processing device 10E, the second substrate 30 arranged in a layer adjacent to the first substrate 20 on which the quantum bit element 11 is provided has a recess 95A recessed in the thickness direction of the second substrate 30 at a portion facing the quantum bit element 11. The first substrate 20 arranged in a layer adjacent to the second substrate 30 on which the resonator 12 is provided has a recess 95B recessed in the thickness direction of the first substrate 20 at a portion facing the resonator 12. The surfaces of the recesses 95A and 95B are covered with a conductive film 50B.

[0054] In this way, since the second substrate 30 has the recess 95A, it is possible to suppress the capacitive coupling between the quantum bit element 11 and the second substrate 30. Similarly, since the first substrate 20 has the recess 95B, it is possible to suppress the capacitive coupling between the resonator 12 and the first substrate 20. This makes it possible to stabilize the operations of the quantum bit element 11 and the resonator 12. Furthermore, since the surfaces of the recesses 95A and 95B are covered with the conductive film 50B, it is possible to suppress the external noise that affects the operations of the quantum bit element 11 and the resonator 12 and to suppress the diffusion of the electromagnetic noise radiated from the quantum bit element 11 and the resonator 12. [Explanation of symbols]

[0055] 10, 10A, 10B, 10C, 10D, 10E quantum computing device 11 Quantum bit element 12 resonator 13 Read Port 14 Grand Port 15 Control Port 20 First Substrate 25A, 25B Through Via 30 Second board 35A, 35B, 35C Through Via 40 Third Board 45A, 45B Through Via 50A, 50B conductive film 51 Through hole 60 Sealing material 70 Control Electrode 71 Electrode 80 space 90 Protective film 95A, 95B recess

Claims

1. A plurality of stacked substrates including a substrate on which a quantum bit element is provided; a first through via provided through a first substrate arranged in a top layer among the plurality of substrates and electrically connected to a substrate arranged in a layer adjacent to the first substrate; a second through via provided through a second substrate arranged in a lowermost layer among the plurality of substrates and electrically connected to a substrate arranged in a layer adjacent to the second substrate; A quantum computing device comprising:

2. The first through via is formed in a first through hole penetrating the first substrate, and the second through via is formed in a second through hole penetrating the second substrate, An opening end of the first through hole is closed by a substrate disposed in a layer adjacent to the first substrate, and an opening end of the second through hole is closed by a substrate disposed in a layer adjacent to the second substrate. The quantum computing device according to claim 1 .

3. a space is formed around the quantum bit element; A third substrate other than the first substrate and the second substrate among the plurality of substrates is provided with a third through via formed in a third through hole penetrating the third substrate and communicating with the space. The quantum computing device according to claim 1 or 2.

4. The space is sealed and evacuated. The quantum computing device according to claim 3 .

5. The substrate disposed in a layer adjacent to the substrate on which the quantum bit element is provided has a recess in a portion facing the quantum bit element. The quantum computing device according to any one of claims 1 to 4.

6. The recess further includes a conductive film covering the surface of the recess. The quantum computing device according to claim 5 .

7. A fourth through via that functions as a read port for reading out a bit signal indicating a state of the quantum bit element, a fifth through via that functions as a ground port for applying a ground potential to the quantum bit element, and a sixth through via that functions as a control port for controlling the quantum bit element are provided in at least one of the first substrate and the second substrate among the plurality of substrates. The quantum computing device according to claim 1 .

8. cleaning a surface of a first substrate on which a quantum bit element is provided, the surface of the first substrate being covered with a protective film; cleaning the surface of the second substrate; a step of cleaning a surface of the first substrate and a surface of the second substrate, and then bonding the first substrate and the second substrate to each other so as to form a space around the quantum bit element; removing the protective film by introducing an etching gas into the space through a through hole provided in at least one of the first substrate and the second substrate; A method for manufacturing a quantum computing device comprising the steps of:

9. The method further includes a step of bonding a third substrate that closes an open end of the through hole to the first substrate or the second substrate. The method according to claim 8.

10. The bonding between the first substrate, the second substrate, and the third substrate is performed in a vacuum, and the space is sealed. The method of claim 9.

11. forming a through via in each of two of the plurality of substrates including the first substrate and the second substrate; and stacking the plurality of substrates such that the two substrates in which the through vias are formed are disposed in the uppermost layer and the lowermost layer, respectively. Further comprising: The through vias are electrically connected to substrates disposed in layers adjacent to the two substrates. The method according to any one of claims 8 to 10.

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