STORAGE DEVICE AND METHOD FOR OPERATION OF STORAGE DEVICE - Patent application

Abstract

To provide a storage device and a method of operating the storage device.SOLUTION: A method of operating a storage device includes the steps of: storing program and erase counts of a non-volatile memory as metadata in units of super blocks including a plurality of blocks of the non-volatile memory; performing a read operation on a first block included in a first super block based on a first read level; storing the first read level as a history read level of the first super block in a history buffer when the read operation on the first block is successful; receiving a read request for a second block of the first super block and an address of the second block from a host; and performing a read operation on the second block based on the history read level stored in the history buffer.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to memory devices, and more particularly to storage devices including non-volatile memory and methods of operating the storage devices. [Background technology]

[0002] Flash memory is a non-volatile memory that can retain stored data even when power is cut off. The flash memory can be electrically reprogrammed and erased. Recently, storage devices including flash memory, such as solid static drivers (SSDs) and memory cards, have been widely used. The flash memory includes a number of memory cells. The flash memory can store data by changing a threshold voltage of the memory cells. Data can be read from the flash memory by sensing the threshold voltage and comparing the sensed voltage with one or more read data using a predefined read level. However, degradation of the memory cells can change the threshold voltage of the memory cells, which can cause read errors. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem that the present invention aims to solve is to provide a storage device that can reduce the number of read retry operations and the capacity of the history buffer, thereby preventing performance degradation, and a method of operating the storage device. [Means for solving the problem]

[0004] A method of operating a storage device according to the technical idea of ​​the present disclosure includes a step of storing the number of times a non-volatile memory is programmed and erased as metadata in units of a superblock including a plurality of blocks of the non-volatile memory; a step of reading a first block included in the first superblock based on a first read level; if the read operation on the first block is successful, a step of storing the first read level in a history buffer as a history read level of the first superblock; a step of receiving a read request and address for a second block of the first superblock from a host; and a step of reading the second block based on the history read level stored in the history buffer.

[0005] A storage device according to the technical idea of ​​the present disclosure includes a non-volatile memory including a plurality of physical blocks, and a controller that controls the non-volatile memory to group the plurality of physical blocks into a plurality of groups, store the number of times each of the plurality of groups has been programmed and erased as metadata, store the read level for each of the plurality of groups in a history buffer, and, when a read command and address are received from a host, perform a read on the physical block corresponding to the address based on the corresponding read level among the plurality of read levels stored in the history buffer.

[0006] An operating method of a storage device including a non-volatile memory according to the technical idea of ​​the present disclosure includes a step of performing a read on a first block included in a first memory group among a plurality of memory groups of the non-volatile memory based on a first read level; if the read operation on the first block is successful, storing the first read level in a history buffer as a read level related to the first memory group; receiving a read request and address for a second block included in the first memory group from a host; determining a second read level based on the first read level stored in the history buffer and an offset indicating a characteristic difference between the first block and the second block; and performing a read on the second block based on the second read level.

[0007] A method for operating a storage device including a non-volatile memory according to the technical idea of ​​the present disclosure includes a step of grouping a plurality of physical blocks of the non-volatile memory into a plurality of memory groups based on characteristic information of each of the physical blocks; receiving a read request from a host for a first physical block included in a first memory group among the plurality of memory groups; confirming whether a read level corresponding to the first memory group is stored in a history buffer; if the read level is not stored in the history buffer, reading the first physical block based on a default read level; and if the first read level is stored in the history buffer, reading the first physical block based on the read level, and the degree of deterioration can be managed for each of the plurality of memory groups. Effect of the Invention

[0008] According to the technical concept of the present disclosure, by managing the history buffer in memory group units corresponding to the degradation management units of non-volatile memory, the number of read retries can be reduced, the performance of the storage device can be improved, and the capacity of the history buffer can be reduced. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating a storage system according to an exemplary embodiment of the present disclosure. [Figure 2A] 2 is a circuit diagram illustrating an example of a block of the non-volatile memory of FIG. 1 according to an exemplary embodiment of the present disclosure. [Figure 2B] 2 is a circuit diagram illustrating an example of a block of the non-volatile memory of FIG. 1 according to an exemplary embodiment of the present disclosure. [Figure 3A] 2 is a block diagram illustrating grouping of superblocks in the non-volatile memory of FIG. 1 according to an exemplary embodiment of the present disclosure. [Figure 3B] 2 is a block diagram illustrating grouping of superblocks in the non-volatile memory of FIG. 1 according to an exemplary embodiment of the present disclosure. [Figure 4A] 1 is a diagram illustrating an example of a metadata table stored in a metadata buffer, according to an exemplary embodiment of the present disclosure. [Figure 4B] 1 is a diagram illustrating an example of a metadata table stored in a metadata buffer, according to an exemplary embodiment of the present disclosure. [Diagram 5] 1 is a diagram showing an example of a distribution change due to deterioration of a memory cell included in a nonvolatile memory; [Figure 6A] 6 shows an example implementation of a read history table corresponding to the distribution change of FIG. 5 according to an exemplary embodiment of the present disclosure. [Figure 6B] 6 shows an example implementation of a read history table corresponding to the distribution change of FIG. 5 according to an exemplary embodiment of the present disclosure. [Figure 6C] 6 shows an example implementation of a read history table corresponding to the distribution change of FIG. 5 according to an exemplary embodiment of the present disclosure. [Figure 7] 2 is a block diagram illustrating an example of a controller of FIG. 1 in accordance with an exemplary embodiment of the present disclosure. [Figure 8A] 1 illustrates an address mapping table according to an exemplary embodiment of the present disclosure. [Figure 8B]1 illustrates a superblock mapping table according to an exemplary embodiment of the present disclosure. [Figure 9A] 1 is a diagram illustrating device offsets of a non-volatile memory according to an exemplary embodiment of the present disclosure. [Figure 9B] 1 is a diagram illustrating block offset according to an exemplary embodiment of the present disclosure. [Figure 10] 4 is a flow chart that generally illustrates a method of operating a storage device, according to an exemplary embodiment of the present disclosure. [Figure 11] 11 is a flowchart illustrating in further detail a method of operation of the storage device of FIG. [Figure 12] 4 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. [Figure 13] 4 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. [Figure 14A] 1 is a diagram illustrating the operation of a controller and a non-volatile memory of a storage device according to an exemplary embodiment of the present disclosure. [Figure 14B] 1 is a diagram illustrating the operation of a controller and a non-volatile memory of a storage device according to an exemplary embodiment of the present disclosure. [Figure 15] 4 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. [Figure 16] 4 is a flowchart illustrating a method for updating a history buffer of a storage device, according to an exemplary embodiment of the present disclosure. [Figure 17] 1 is a flowchart illustrating an example of a super-block grouping method for a storage device according to an exemplary embodiment of the present disclosure. [Figure 18] 4 is a flowchart illustrating a method for supergroup regrouping of storage devices according to an exemplary embodiment of the present disclosure. [Figure 19A] 19 is a diagram showing an example of regrouping of FIG. 18; [Figure 19B] 19 is a diagram showing an example of regrouping of FIG. 18; [Figure 20] 4 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. [Figure 21] 21 is a diagram illustrating an example of the operation method of FIG. 20. [Figure 22] 1 is a block diagram illustrating an SSD and an SSD system including the same, according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] FIG. 1 is a block diagram illustrating a storage system 10 in accordance with an exemplary embodiment of the present disclosure.

[0011] 1, the storage system 10 includes a storage device 100 and a host 200 (e.g., a host device), and the storage device 100 may include a controller 110 (e.g., a control circuit or memory controller) and a non-volatile memory (NVM) 120. The controller 110 may output a command CMD, an address ADDR, and a control signal CTRL to the non-volatile memory 120 and exchange data DATA with the non-volatile memory 120. The host 200 may communicate with the storage device 100 through various interfaces and may transmit a read request, a write request, and the like to the storage device 100. In one embodiment, the host 200 may be embodied by an application processor (AP) or a system-on-a-chip (SoC).

[0012] The non-volatile memory 120 includes a plurality of memory blocks BLK, which are also grouped into a plurality of super blocks SB. Each of the plurality of memory blocks includes a plurality of memory cells. The memory block BLK means a physical block, and hereinafter, the memory block BLK is also referred to as a block or a physical block. The super block SB is also a logical memory area unit for the controller 110 to manage the non-volatile memory 120, and each of the plurality of super blocks SB may include a plurality of memory blocks BLK. In one embodiment, each of the plurality of super blocks SB includes the same number of memory blocks BLK, and the number is adjusted according to need.

[0013] The block BLK may also be embodied by a memory cell array having a two-dimensional or three-dimensional array structure, and the memory cells may include single-level cells programmed with one bit, or multi-level cells (e.g., double-level cells, triple-level cells, or quadruple-level cells) programmed with two or more bits. The memory cells may be NAND flash memory cells. However, the memory cells may be resistive memory cells such as resistive random access memory (ReRAM), phase change random access memory (PRAM), and magnetic random access memory (MRAM).

[0014] A block BLK includes a plurality of pages. Memory cells connected to the same word line may constitute a page. For example, a block BLK is a unit of erasure, and a page is a unit of programming and reading.

[0015] The controller 110 (also referred to as a storage controller) may control the overall operation of the storage device 100, and may control the non-volatile memory 120 to read data DATA stored in the non-volatile memory 120 in response to a read request from the host 200, and to program data DATA in the non-volatile memory 120 in response to a write request from the host 200. The controller 110 may also control the non-volatile memory 120 to perform internal management operations or background operations of the storage device 100, regardless of a request from the host 200.

[0016] In this embodiment, the controller 110 includes a metadata buffer MB and a history buffer HB, and the controller 110 can manage the metadata buffer MB and the history buffer HB in units of a predetermined memory group, for example, a superblock SB. In one embodiment, the controller 110 can group a plurality of blocks BLK into a plurality of superblocks SB based on the positions of the blocks BLK in a memory device in which the blocks BLK are included, or can group the plurality of blocks BLK into a plurality of superblocks SB based on electrical characteristics of the blocks BLK (for example, threshold-voltage distribution characteristics when the same test program voltage is applied).

[0017] Various kinds of metadata may be stored in the metadata buffer MB. Here, the metadata may be user data stored in the non-volatile memory 120 or data generated by the controller 110 to manage the non-volatile memory 120. For example, the metadata may include mapping information used to convert a logical address of the host 200 into a physical address of the non-volatile memory 120, or may include information for managing the memory space of the non-volatile memory 120, such as wear leveling and garbage collection, such as program cycles and erase cycles (P / E cycles) (also called program count and erase count), deterioration level information, etc. For example, the wear leveling process may include distributing writes evenly to extend the life of the memory device. For example, the garbage collection process may include erasing the first memory block to secure space after moving valid pages of the first memory block to the second memory block.

[0018] The metadata may continue to be available if storage device 100 is powered off and then powered on, but may be stored in non-volatile memory 120 during runtime of storage device 100 or when storage device 100 is powered off. For example, the metadata may be maintained even after storage device 100 is powered off.

[0019] The controller 110 controls the non-volatile memory 120 such that a plurality of memory blocks BLK included in a superblock SB perform a program operation and / or an erase operation at the same time, and metadata related to the degradation degree management of the non-volatile memory 120 may be managed (stored and updated) in units of the superblock SB. For example, a different degradation degree may be stored or updated for each superblock SB. The degradation degree may indicate how the superblocks are degraded relative to each other. For example, if a first degradation degree of a first superblock is higher than a second degradation degree of a second superblock, the first superblock is considered to be more degraded than the second superblock. For example, the first superblock has been programmed and / or erased more than the second superblock to be considered to have a higher degradation degree.

[0020] For example, when the controller 110 converts a logical address received from the host 200 together with a write request into a physical address, the controller 110 can map the physical address to the logical address so that multiple blocks BLK of the superblock SB can be simultaneously programmed in an interleaving manner. As a result, the deterioration levels of the multiple blocks BLK of the superblock SB can be the same or similar. Here, the deterioration of a memory cell means that the physical characteristics of the memory cell change due to repeated program and erase cycles, and the deterioration of the memory cell reduces endurance and retention characteristics. Since the deterioration levels of the multiple blocks BLK of the superblock SB are the same or similar, metadata related to the deterioration level can be managed for each superblock SB.

[0021] In one embodiment, the controller 110 may manage program cycles and erase cycles (P / E cycles) in units of superblocks SB, and may store the number of program cycles and the number of erase cycles for each superblock SB in the metadata buffer MB. Alternatively, the controller 110 may detect the degree of deterioration for each superblock SB, and store the detected degree of deterioration in the metadata buffer MB. By managing metadata in units of superblocks SB in this manner, the storage capacity of the metadata buffer MB required for storing metadata may be reduced.

[0022] Furthermore, the controller 110 may store a read level in the history buffer HB for each superblock SB during runtime of the storage device 100. For example, the read level may be a specific voltage or current. When a read request is received from the host 200, data may be read from the block BLK for which the read request is made based on the read level stored in the history buffer HB. Hereinafter, in this disclosure, the read level stored in the history buffer HB is referred to as a "history read level" and a read operation based on the history read level is referred to as a "history read".

[0023] For example, the controller 110 may perform a read on one memory block BLK (first block) of the first superblock based on the first read level, and if the read operation is successful, may store the first read level in the history buffer HB as a history read level for the first superblock. Thereafter, if a read request is received from the host 200 for the first block of the first superblock or another block, the controller 110 may perform a history read based on the history read level for the first superblock stored in the history buffer HB.

[0024] The controller 110 may perform a read retry operation if the read operation fails. Hereinafter, a read operation performed by modifying a read level when a previous read operation fails and then using the modified read level is referred to as a "read retry operation". In one embodiment, the read operation includes reading a cell voltage of a memory block, converting the read voltage into a codeword (e.g., data and redundancy information), and performing an error correction code (ECC) operation on the codeword, and if the ECC operation fails, the read operation fails. For example, an ECC operation failure may indicate that the codeword has a certain number of errors that exceed the error correction capability of the ECC operation. The read level may be used to convert the read voltage into the codeword. If the ECC operation fails, the read level used may be raised or lowered to the modified read level, the codeword may be modified using the previously read cell voltage and the modified read level, and an ECC operation may be performed on the modified codeword.

[0025] If the history read operation fails, the controller 110 can execute a defensive code in firmware to derive a corrected read level and perform a read retry based on the corrected read level. If the read retry operation is successful, the controller 110 can update the history read level by saving the corrected read level in the history buffer HB as the history read level.

[0026] When a read operation is performed based on a default read level that does not reflect the deterioration level of the block BLK, the read operation has a high probability of failing. However, the storage device 100 according to the embodiment of the present disclosure manages the history read level in units of superblocks SB, and when performing a read operation on a block BLK for which a read is requested, performs a history read based on the history read level of the corresponding superblock SB, thereby increasing the probability of a successful read. As described above, if a read operation fails, a defense code can be executed, but the execution of the defense code requires a considerable amount of time. The storage device 100 according to the embodiment of the present disclosure can minimize the number of times the defense code is executed, and therefore the performance of the storage device 100 can be improved.

[0027] On the other hand, if too much time has passed since the history read level was stored in the history buffer HB, there is a high probability that the read operation will fail even if a history read is performed based on the history read level. When the storage device 100 is powered off, the time that has passed until the storage device 100 is powered on again cannot be known, and the time that has passed is quite long. Therefore, unlike metadata, when the storage device 100 is powered off, the data stored in the history buffer HB, in other words, the history read level of each superblock SB, does not need to be stored in the non-volatile memory 120. When the storage device 100 is powered on, if a normal read operation, for example, a read operation performed based on a default read level, is successful, the read level is stored in the history buffer HB as the history read level, and can be used and further updated during the runtime of the storage device 100. In one embodiment, the history read level is stored in a volatile memory of the storage device 100, and the default read level is used initially after the storage device 100 is powered on, and can continue to be used until each history read level is newly calculated.

[0028] In one embodiment, when performing a history read, the controller 110 adds an offset to the history read level to generate an adjusted read level to compensate for characteristic differences between multiple blocks BLK included in the same superblock SB or characteristic differences between multiple memory devices each including multiple blocks BLK, calculates an adjusted read level from the adjusted history read level, and performs a history read based on the adjusted read level.

[0029] A plurality of blocks BLK included in the same superblock SB may have electrical characteristic differences due to a manufacturing process (i.e., manufacturing stage). For example, the threshold voltage distribution characteristics (e.g., threshold voltage distribution width and threshold voltage level, etc.) of a first block may be different from the threshold voltage distribution characteristics of a second block, and thus the retention characteristics may be different even if the degradation levels of the first and second blocks are the same or similar.

[0030] Therefore, when performing a history read, the controller 110 performs the history read based on an adjusted read level in which an offset that reflects the characteristic differences between multiple blocks BLK is added to the history read level, thereby increasing the read success rate and reducing the number of times (or time) the defense code is executed.

[0031] In one embodiment, the controller 110 may perform a background read in units of superblocks SB to update the history buffer HB. In this case, the "background read operation" refers to an operation in which the controller 110 independently issues a read command CMD and an address ADDR without receiving a read request from the host 200, and reads data DATA from the non-volatile memory 120 in response to the read command CMD and the address ADDR. In one embodiment, the "background read operation" performed to update the history buffer is also performed on one block BLK of the superblock SB, for example, a representative block, based on the history read level stored in the history buffer HB. For example, immediately after the storage device 100 is powered on, the controller 110 may perform one or more background read operations to update the history buffer HB.

[0032] In one embodiment, the controller 110 performs a background read on a block BLK basis, and may regroup the superblock SB or replace a defective block BLK included in the superblock SB with another block based on characteristics detected based on the result of the background read, in other words, characteristics of a plurality of blocks BLK. For example, if it is determined that a defect occurs in one of the blocks BLK assigned to the superblock SB, another block of the non-volatile memory 120 is also assigned to the superblock SB.

[0033] The storage system 10 may be embodied as, for example, a personal computer (PC), a data server, a network-attached storage (NAS), an internet of things (IoT) device, or a portable electronic device, such as a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable device, or the like.

[0034] In some embodiments, storage device 100 is an internal memory built into an electronic device. For example, storage device 100 is an SSD, an embedded universal flash storage (UFS) memory device, or an embedded multi-media card (eMMC). In some embodiments, storage device 100 is an external memory that is removable from an electronic device. For example, storage device 100 is a UFS memory card, compact flash (CF), secure digital (SD), micro secure digital (micro-SD), mini secure digital (mini-SD), extreme digital (xD), or a memory stick.

[0035] 2A and 2B are circuit diagrams illustrating an example of a block of the non-volatile memory of FIG. 1, according to an exemplary embodiment of the present disclosure.

[0036] 2A, the block BLKa is also a horizontal structure NAND flash memory, and includes a plurality of NAND strings STR, a plurality of word lines WL1 through WL8, a plurality of bit lines BL1 through BLd, a ground selection line GSL, a string selection line SSL, and a common source line CSL, where the number of the NAND strings, the number of the word lines, the number of the bit lines, the number of the ground selection lines, and the number of the string selection lines may be variously changed according to the embodiment.

[0037] Memory cells MC connected to one word line, for example, the fifth word line WL5, may constitute a page PAGE, and program and read operations may be performed in units of pages. At this time, the page PAGE shown in FIG. 2A indicates a physical page, and if the memory cells MC are multi-level cells, a plurality of logical pages may be programmed in the page PAGE. Programming and reading are performed in units of pages PAGE corresponding to each of the word lines WL1 to WL8, and an erase operation may be performed on the entire block BLKa.

[0038] 2B, the block BLKb is also a vertical structure NAND flash memory. The block BLKb may include a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be variously changed according to the embodiment.

[0039] NAND strings NS11, NS21, and NS31 are provided between a first bit line BL1 and a common source line CSL, NAND strings NS12, NS22, and NS32 are provided between a second bit line BL2 and the common source line CSL, and NAND strings NS13, NS23, and NS33 are provided between a third bit line BL3 and the common source line CSL. For example, the NAND string NS11 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST, which are connected in series.

[0040] The string selection transistors SST are connected to string selection lines SSL1 through SSL3. A plurality of memory cells MC1 through MC8 are connected to corresponding word lines WL1 through WL8, respectively. The ground selection transistors GST are connected to ground selection lines GSL1, GSL2, and GSL3. The string selection transistors SST are connected to corresponding bit lines BL, and the ground selection transistors GST are connected to a common source line CSL.

[0041] In the plurality of NAND strings NS11 to NS33, word lines connected to memory cells located at the same height are commonly connected, and the string selection lines SSL1 to SSL3 are separated from each other. For example, when programming memory cells connected to the first word line WL1 and belonging to the NAND strings NS11, NS12, and NS13, the first word line WL1 and the first string selection line SSL1 may be selected. As shown in the figure, the ground selection lines GSL1, GSL2, and GSL3 may be separated from each other. However, the present invention is not limited thereto, and the ground selection lines GSL1, GSL2, and GSL3 may be connected to each other.

[0042] Programming and reading are performed in units of pages PAGE corresponding to the word lines WL1 to WL8 and the NAND strings NS11 to NS33, and an erase operation can be performed on the entire block BLKb.

[0043] 3A and 3B are block diagrams illustrating grouping of superblocks in the non-volatile memory of FIG. 1 according to an exemplary embodiment of the present disclosure.

[0044] 1 and 3A, the non-volatile memory 120 includes a plurality of memory devices D1 to D8, which can communicate with the controller 110 via at least one channel CH. Each of the memory devices D1 to D8 is a semiconductor chip or a semiconductor die, and each of the memory devices D1 to D8 includes a plurality of blocks BLK. For example, as shown in the figures, each of the memory devices D1 to D8 may include n blocks B11 to B1n, B21 to B2n, ..., B81 to B8n (n is a natural number equal to or greater than 2). Although not shown, each of the memory devices D1 to D8 may further include peripheral circuits for performing program operations, read operations, and erase operations, such as a voltage generator, an address decoder, and an input / output circuit.

[0045] In multiple memory devices D1 to D8, blocks BLK arranged at the same position (or blocks BLK assigned the same number) are also grouped into one superblock. For example, in FIG. 3A, blocks B11 to B81 are grouped as a first superblock SB1, blocks B12 to B82 are grouped as a second superblock SB2, and blocks B1n to B8n are also grouped as a k-th superblock SBk (k is a natural number equal to or greater than 2 and is equal to or smaller than n).

[0046] 3A, for convenience of explanation, the first device D1 through the eighth device D8 are illustrated as being connected in parallel to one channel CH and communicating with the controller 110 through one channel CH, but is not limited thereto, and the non-volatile memory 120 may include multiple channels each connected to multiple memory devices. The multiple memory devices D1 through D8 connected to the same channel CH may perform program, read, and erase operations in an interleaving manner.

[0047] 3B, a plurality of blocks B11 to B8n are also grouped into a plurality of super-blocks SB1 to SBk based on their electrical characteristics. For example, blocks B11, B21, ..., B81 have the same or similar electrical characteristics and are grouped into a first super-block SB1, blocks B12, B22, ..., B82 have the same or similar electrical characteristics and are grouped into a second super-block SB2, and blocks B1n, B2n, ..., B8n have the same or similar electrical characteristics and are also grouped into a k-th super-block SBk.

[0048] In addition to the grouping methods described with reference to Figures 3A and 3B, the blocks BLK of the non-volatile memory 120 may also be grouped into a plurality of superblocks based on various conditions. In addition, for convenience of description, in Figures 3A and 3B, the first device D1 to the eighth device D8 are illustrated as being connected in parallel to one channel CH and communicating with the controller 110 through one channel CH, but the present invention is not limited thereto, and the non-volatile memory 120 may include a plurality of channels, each of which is connected to a plurality of memory devices. The memory devices D1 to D8 connected to the same channel CH may perform program, read, and erase operations in an interleaving manner.

[0049] 4A and 4B show example metadata tables stored in a metadata buffer according to an exemplary embodiment of the present disclosure.

[0050] Referring to FIG. 4A, the P / E cycles associated with each of the multiple super-blocks SB1 to SBn are also stored in the metadata buffer MB (FIG. 1) as a counting table CTB.

[0051] For example, the counting table CTB includes a super block number (SBN) which is a super block address of the non-volatile memory 120, and a counting value CV which indicates a P / E cycle. The counting table CTB can store a plurality of counting values ​​CV1 to CVn corresponding to a plurality of super blocks SB1 to SBn, respectively. For example, the controller 110 can count the P / E cycles (or the number of times program and erase operations are repeated) for a plurality of super blocks of a first super block SB1, and store the counting result in the counting value CV as a first counting value CV1. For example, the super block address SBN includes a physical address of each block BLK assigned to the super block SB. For example, the counting value associated with the super block SB is increased every time a block BLK assigned to the super block SB is programmed or erased.

[0052] 4B, a degradation value DV indicating a degradation degree associated with each of the superblocks SB1 to SBn may be stored in the metadata buffer MB as a degradation degree table DTB. In this case, the degradation degree may indicate a degree of degradation of each of the superblocks SB1 to SBn due to repeated programming and erasing. For example, the degradation degree table DTB may include SBN, which is a superblock address of the non-volatile memory 120, and a degradation value DV. The degradation degree table DTB may store a plurality of degradation values ​​DV1 to DVn corresponding to each of the superblocks SB1 to SBn. For example, the controller 110 may periodically or non-periodically detect the degradation degree of the superblocks SB1 to SBn, and store the degradation degree or a processing value calculated based on the degradation degree in the degradation degree table DTB as the degradation value DV.

[0053] FIG. 5 shows an example of a change in distribution due to degradation of a memory cell included in a nonvolatile memory.

[0054] 1 and 5, in an initial distribution 51 and a modified distribution 52, the horizontal axis indicates the threshold voltage Vth and the vertical axis indicates the number of memory cells.

[0055] For example, if the memory cell is a multi-level cell programmed with two bits, the memory cell may have an erased state E and one of a first programmed state P1 through a third programmed state P3. The initial distribution 51 is also a distribution within a predetermined time after the memory cell is programmed. The storage device 100 may use a first default read level DRL1 through a third default read level DRL3 to determine the first programmed state P1 through the third programmed state P3, respectively.

[0056] The changed distribution 52 is also a distribution after a certain time after the program of the memory cell is completed. If the retention time is extended, the amount of charge trapping in the memory cell is reduced, and the distribution changes and moves. As a result, the threshold voltage of the memory cell is changed compared to the initial distribution 51. Specifically, if the retention time is extended, the charge stored in the charge storage layer of the memory cell leaks to the substrate, and the threshold voltage of the memory cell is reduced. The change and movement of the distribution may be affected not only by the elapsed time after the program is completed (i.e., retention time), but also by the repetition of program and / or erase (e.g., P / E cycles). For example, even if the elapsed time after the program of the first word line and the second word line is the same, if the P / E cycle of the first word line and the P / E cycle of the second word line are different, the change and movement of the first word line distribution may be different from the change and movement of the second word line distribution.

[0057] At this time, when the memory cells are read using the first default read level DRL1 to the third default read level DRL3, respectively, a read error may occur in some of the memory cells programmed in the first program state P1 to the third program state P3. Here, the read error occurs when the number of failed bits in the read data is equal to or greater than a reference number correctable by ECC, and thus the read error may be called UECC (uncorrectable ECC). To remove the read error, it is necessary to correct the read level by performing a read retry.

[0058] If a read error occurs during a normal read operation using a default read level (DRL), the storage device 100 can correct the read level, perform a read retry based on the corrected read level, and obtain an appropriate read level at which the read operation can be successful, for example, corrected read levels CRL1 to CRL3. The controller 110 can execute a recovery code by firmware to correct the read level. At this time, a considerable amount of time is required to execute the recovery code, which causes a performance degradation of the storage device 100.

[0059] During a history read operation using the history read level, the probability of a read error occurring may be reduced. However, when the history read level is managed (stored and updated) in units of blocks, a read retry operation must be performed to obtain the history read level for each of the multiple blocks, and the storage capacity of the history buffer HB required to store the history read level for each of the multiple blocks increases. However, according to an embodiment of the present disclosure, the controller 110 manages the history read level in units of superblocks SB, and only a read retry operation is required to be performed to obtain the history read level for each of the multiple superblocks, and a read retry operation does not need to be performed for each of the multiple blocks, but the number of times (or time) the protection code is executed is reduced, and the storage capacity of the history buffer HB required to store the history read level may be reduced.

[0060] 6A, 6B, and 6C show implementations of read history tables corresponding to the distribution changes of FIG. 5, according to exemplary embodiments of the present disclosure.

[0061] 1 to 6A, the read history table RHTa is also stored in the history buffer HB. The read history table RHTa can store history read levels HRL1 to HRL3 corresponding to a plurality of superblocks SB1 to SBn, respectively. For example, read levels CRL1a, CRL2a, and CRL3a modified for the first superblock SB1 are also stored as history read levels HRL1 to HRL3. Read levels CRL1b, CRL2b, and CRL3b modified for the second superblock SB2 are also stored as history read levels HRL1 to HRL3, and read levels CRL1c, CRL2bc, and CRL3c modified for the n-th superblock SBn are also stored as history read levels HRL1 to HRL3. The history read levels HRL1 to HRL3 associated with the plurality of superblocks SB1 to SBn, respectively, are updated over time. The operation of generating the read history table RHTa will be described below.

[0062] The memory controller 110 may perform a normal read on one block of the first superblock SB, for example, a first block on which a read operation is performed for the first time during runtime of the storage device 100 among a plurality of blocks of the first superblock SB, based on the default read levels DRL1, DRL2, and DRL3. If a read error occurs, the memory controller 110 may perform a read retry on the first block using the corrected read levels CRL1a, CRL2a, and CRL3a. If no read error occurs, the memory controller 110 may store the corrected read levels CRL1a, CRL2a, and CRL3a in the read history table RHT as the history read levels corresponding to the first superblock SB. Similarly, the memory controller 110 may store the corrected read levels CRL1b, CRL2b, and CRL3b in the read history table RHTa through the normal read operation and / or the read retry operation for the second superblock SB2 through the n-th superblock SBn.

[0063] Meanwhile, if the normal read operation is successful based on the default read levels DRL1, DRL2, DEL3, the controller 110 may update the history read levels HR1, HR2, HR3 associated with the first superblock SB1 to the default read levels DRL1, DRL2, DEL3, respectively. If the read retry operation based on the modified read levels CRL1a, CRL2a, CRL3a fails, the controller 110 may adjust the modified read levels CRL1a, CRL2a, CRL3a and re-execute the read retry operation based on the adjusted read levels. If the read retry operation is successful after re-executing the read retry operation based on the adjusted read levels, the controller 110 may update the history read levels HR1, HR2, HR3 associated with the first superblock SB1 to the adjusted read levels in the read history table RHTa, respectively.

[0064] In some embodiments, when the memory cell is a single-level cell programmed with one bit, the memory cell may have one of an erased state and a programmed state, and in that case, the read history table may store the modified read levels corresponding to the plurality of superblocks SB1 to SBn as history levels. The operation of generating the read history table is also substantially the same as that described with reference to FIG. 6A.

[0065] 6B, the read history table RHTb may store history read levels HRL1 to HRL3 corresponding to the plurality of superblocks SB1 to SBn, respectively, as described with reference to FIG. 6A, and may also store a device number DN indicating an address of a memory device (hereinafter, also referred to as a device). For example, the device number DN indicates a device including a block on which a read operation (or a read retry operation) was performed when the history read levels HRL1 to HRL3 related to the superblock were acquired. For example, as shown in FIG. 6B, the first superblock SB1 may be located on a first memory chip having a second device number DN2, and the n-th superblock SB2 may be located on a second memory chip having a third device number DN3. In an exemplary embodiment, the device number may be stored in each memory chip of the non-volatile memory 120, or the device number may be stored inside or outside all memory chips of the non-volatile memory 120. In an exemplary embodiment, the device number may be queried by the controller 110. For example, the controller 110 can transmit a request for a device number of a memory chip to the non-volatile memory 120, and the non-volatile memory 120 can respond to the controller 110 with the corresponding device number.

[0066] For example, in FIG. 3A, when a read retry operation is performed on block B21 among blocks B11 to B81 included in the first superblock SB1, and corrected read levels CRL1a, CRL2a, and CRL3a are obtained, the second device D2 including block B21 is also stored as device number DN. As described with reference to FIG. 1, there may be differences in electrical characteristics between devices. The electrical characteristics of each of the devices D1 to D8 may be detected during the manufacturing process, for example, during a device test stage, and stored in the device. For example, the electrical characteristics may be stored in one of the blocks included in the device, or may also be stored in a peripheral circuit of the device.

[0067] For example, when performing a history read based on the corrected read levels CRL1a, CRL2a, and CRL3a for blocks B11 and B81 other than block B21, the memory controller 110 checks from which device the corrected read levels CRL1a, CRL2a, and CRL3a are obtained, i.e., whether they are obtained from the second device D2, adjusts the corrected read levels CRL1a, CRL2a, and CRL3a based on an offset reflecting an electrical characteristic difference between the second device D2 and a device including a block on which the history read operation is performed, and performs a history read based on the adjusted read levels. For example, the memory controller 110 can generate the adjusted read levels by adding an offset to each of the corrected read levels CRL1a, CRL2a, and CRL3a. For example, if a history read operation was previously performed on block B21 of the second device D2, the corresponding entry in the read history table RHTb may be temporarily stored in a buffer of the controller 110, and when the next history read operation is performed on a block of the third device D3, an offset may be added to the read level of the buffer to derive the read level for the block of the third device D3.

[0068] 6C, the read history table RHTc can store history read levels HRL1 to HRL3 corresponding to a plurality of superblocks SB1 to SBn, respectively, as described with reference to FIG. 6A, and can also store block numbers BN corresponding to addresses of blocks (hereinafter, also referred to as blocks). For example, the block numbers BN indicate blocks on which a read operation (or a read retry operation) was performed when the history read levels HRL1 to HRL3 related to the superblocks were obtained. For example, in FIG. 3, in blocks B11 to B81 included in the first superblock SB1, when a read retry operation is performed on block B21 to obtain corrected read levels CRL1a, CRL2a, and CRL3a, B21 is also stored as the block number BN.

[0069] For example, electrical characteristics of each of the blocks included in each of the devices D1 to D8 are detected during the manufacturing process, for example, during a device test stage, and are also stored in the device. For example, the characteristics of each of the blocks in the device are stored in the block, a specific block, or a peripheral circuit of the device.

[0070] For example, when performing a history read based on the modified read levels CRL1a, CRL2a, and CRL3a for blocks B11 and B81 other than block B21, the memory controller 110 confirms from which block the modified read levels CRL1a, CRL2a, and CRL3a are obtained, i.e., whether they are obtained from block B21 or not, adjusts the modified read levels CRL1a, CRL2a, and CRL3a based on an offset reflecting the electrical characteristic difference between block B21 and the block on which the history read operation is performed, and performs a history read based on the adjusted read levels.

[0071] FIG. 7 is a block diagram illustrating an example of the controller of FIG. 1 according to one embodiment of the present disclosure.

[0072] 7, the controller 110a includes a processor 111, a memory 112, a host interface 113 (e.g., an interface circuit), a read only memory (ROM) 114, an ECC module 115, and a non-volatile memory interface 116 (e.g., an interface circuit), which may communicate with each other via a bus 117. The processor 111 may include a central processing unit, a microprocessor, or the like, and may control the overall operation of the controller 110a. The processor 111 may include one or more processor cores capable of executing a set of instructions of a program code configured to perform a specific operation. For example, the processor 111 may execute instruction codes of firmware stored in the ROM 114.

[0073] The memory 112 operates under the control of the processor 111, and is also used as an operating memory, a buffer memory, a cache memory, etc. The memory 112 includes a read controller RC, a metadata buffer MB, and a history buffer HB. For example, the memory 112 may be realized by a volatile memory such as a DRAM or an SRAM, or a non-volatile memory such as a PRAM or a flash memory.

[0074] The read controller RC may also be embodied in firmware or software and loaded into the memory 112. In one embodiment, the read controller RC is embodied as part of a flash translation layer (FTL) and is also loaded into the memory 112. However, without being limited thereto, the read controller RC may also be embodied in hardware.

[0075] The history buffer HB may store, for example, one of the read history tables RHTa, RHTb, and RHTc of FIG. 6A, 6B, and 6C, and may be embodied as a part of the memory 112. In one embodiment, the read controller RC and the history buffer HB may be embodied in the same chip. However, without being limited thereto, the read controller RC and the history buffer HB may be embodied in different chips. For example, the history buffer HB may be embodied as a part of a separate DRAM chip.

[0076] The metadata buffer MB can store, for example, the counting table CTB of Fig. 4A and / or the degradation table DTB of Fig. 4B, and can be embodied as part of the memory 112 or a separate DRAM chip. The metadata buffer MB can also store an address mapping table AMT (Fig. 8A) including mapping information between logical addresses and physical addresses, and a superblock mapping table SMBT (Fig. 8B) including information on blocks mapped to superblocks.

[0077] FIG. 8A illustrates an address mapping table according to an embodiment of the present disclosure, and FIG. 8B illustrates a superblock mapping table according to an embodiment of the present disclosure.

[0078] Referring to Fig. 8A, the address mapping table AMT can store a plurality of mapping data for converting logical addresses to physical addresses, and is used even when loaded into the metadata buffer MB of Fig. 6. Each mapping data indicates a physical page number (PPN) corresponding to a logical page number (LPN). For example, the third physical page PPN3 corresponding to the third page of the block BLK11 is mapped to the first logical page LPN1, and the ninth physical page PPN9 corresponding to the first page of the block BLK12 is also mapped to the second logical page LPN2.

[0079] 8B, the superblock mapping table SBMT indicates block numbers (BNs) for blocks corresponding to the superblocks SB1 to SBb, i.e., blocks grouped into each of the superblocks SB1 to SBb. For example, blocks BLK11, BLK21 to BLK81 may correspond to the first superblock SB1. In one embodiment, the superblock mapping table SBMT may include device numbers (e.g., D1, D2, ..., D8) in which the blocks are included, along with the BNs associated with the blocks, as shown.

[0080] When a read request and a logical address are received from the host 200, the controller 110a may refer to the address mapping table AMT to determine a physical address corresponding to the received logical address. The controller 110a may then check the superblock mapping table SBMT to determine a superblock corresponding to the physical address, and determine whether the history read level of the superblock is stored in the read history tables RHTa, RHTb, and RHTc (FIGS. 6A, 6B, and 6C).

[0081] For example, when the first logical page LPN1 is received from the host 200, the controller 110a can refer to the address mapping table AMT to confirm the third physical page PPN3 corresponding to the first logical page LPN1. Next, the controller 110a can refer to the superblock mapping table SBMT to determine that the third physical page PPN3 corresponds to the first superblock SB1, and can confirm whether the history read level corresponding to the first superblock SB1 is stored in the history buffer HB (FIGS. 1 and 7) (in other words, the read history tables RHTa, RHTb, and RHTc (FIGS. 6A, 6B, and 6C)). Since the history read levels corresponding to the first superblock SB1, for example, the corrected read levels CRL1a, CRL2a, and CRL3a, are stored in the history buffer HB, a history read can be performed on the third physical page PPN3 based on the history read levels.

[0082] Meanwhile, for example, when the second logical page LPN2 is received from the host 200, the controller 110a may refer to the address mapping table AMT and determine the ninth physical page PPN9 corresponding to the second logical page LPN2. Next, the controller 110a may refer to the superblock mapping table SBMT to confirm that the ninth physical page PPN9 corresponds to the second superblock SB2, and may confirm whether the history read level corresponding to the second superblock SB2 is stored in the history buffer HB (FIGS. 1 and 7) (in other words, in the read history tables RHTa, RHTb, and RHTc (FIGS. 6A, 6B, and 6C)). Since the history read level corresponding to the second superblock SB2 is not stored in the read history tables RHTa, RHTb, and RHTc (FIGS. 6A, 6B, and 6C), a read operation, for example, a normal read, for the ninth physical page PPN9 may be performed using a default read level. When the normal read operation is successful, the default read level is also stored as the history read level for the second superblock SB2. When the normal read operation is unsuccessful, a read retry is performed, and the corrected read level at the time of the read success is also stored as the history read level for the second superblock SB2.

[0083] Continuing with reference to FIG. 7, the host interface 113 may provide an interface between the host 200 and the controller 110a, and may provide interfaces such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect-express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), small computer system interface (SCSI), serial attached SCSI (SAS), enhanced small disk interface (ESDI), integrated drive electronics (IDE), etc.

[0084] The ROM 114 may store various information required for the operation of the controller 110a. Exemplarily, the ROM 114 may store operation algorithms of the controller 110a, such as a metadata buffer (MB) management algorithm and a history buffer (HB) management algorithm, or an operation algorithm of the read controller RC, in the form of firmware.

[0085] The ECC module 115 may perform ECC operations on data (e.g., codewords) received from the non-volatile memory 120 to detect error bits in the data and correct the detected error bits. In one embodiment, the ECC module 115 may be implemented in hardware. In one embodiment, the ECC module 115 may be implemented in software or firmware and may be loaded into the memory 112.

[0086] The non-volatile memory interface 116 can provide an interface between the controller 110a and the non-volatile memory 120. For example, metadata, write data, and read data can be transmitted and received between the controller 110a and the non-volatile memory 120 via the non-volatile memory interface 116.

[0087] FIG. 9A illustrates device offsets for a non-volatile memory according to an embodiment of the present disclosure, and FIG. 9B illustrates block offsets according to an embodiment of the present disclosure.

[0088] 1 and 9A, the non-volatile memory 120 can store device offsets DO corresponding to a plurality of devices, for example, the first device D1 to the 21st device D21, for example, the first device offset DO1 to the 21st device offset DO21. The device offsets DO are calculated based on electrical characteristic differences between the plurality of devices during the manufacturing stage of the storage device 100, and are also stored in the devices. When the storage device 100 is powered on, the controller 110 reads the first device offsets DO1 to the 21st device offset DO21 from the first device D1 to the 21st device D21, configures the first device offsets DO1 to the 21st device offset DO21 as an offset table OTa, stores the offset table, and can refer to the offset table. For example, the offset table OTa is also stored in the metadata buffer MB.

[0089] 9B, the offset of the block included in each of the plurality of devices of the non-volatile memory 120, for example, the first device D1 to the twenty-first device D21, i.e., the block offset BOs, may be stored in each of the plurality of devices. The block offset BOs is calculated based on the electrical characteristic difference of the plurality of blocks of the plurality of devices during the manufacturing stage of the storage device 100, and is also stored in the device. For example, if the first device D1 includes the first block to the eighth block, the first device D1 may store the first block offset BO11 to the eighth block offset BO18 corresponding to the first block to the eighth block. When the storage device 100 is powered on, the controller 110 reads the block offset BOs from the first device D1 to the twenty-first device D21, configures and stores the block offset BOs as an offset table OTb, and can refer to it. For example, the offset table OTa is also stored in the metadata buffer MB. The offset table OTb including the block offset BOs may store the block offset BOs on a device-by-device basis. For example, block offsets BO11 to BO1n corresponding to blocks of the first device D1 may be stored in block offset BO_D1 of the first device, and block offsets BO21 to BO2n corresponding to blocks of the second device D2 may be stored in block offset BO_D1 of the first device.

[0090] The device offset DO or block offset BOs described with reference to Figures 9A and 9B is also used when performing a history read operation. As described with reference to Figure 1, the controller 110 may add the device offset DO or block offset BO to the history read level to compensate for differences in characteristics of multiple blocks BLK included in the same superblock SB or differences in characteristics of multiple memory devices included in each of the multiple blocks BLK, calculate an adjusted read level, and perform a history read based on the adjusted read level.

[0091] Fig. 10 is a flow chart that shows a schematic operation method of the storage device according to an embodiment of the present disclosure, and Fig. 11 is a flow chart that shows in more detail the operation method of the storage device of Fig. 10. The operation methods of Fig. 10 and Fig. 11 are also performed in time series in the storage device 100 of Fig. 1. The contents described with reference to Figs. 1 to 9B are also applied to this embodiment.

[0092] 1 and 10, the storage device 100 manages degradation of the nonvolatile memory in units of superblocks (S10), and also manages a history buffer in units of superblocks and controls a read operation for the nonvolatile memory 120 (S20). The superblock may include multiple memories. For example, the controller 120 may group at least one block included in each of multiple memory devices constituting the nonvolatile memory 120 into a superblock, or may group multiple blocks in the nonvolatile memory 120 having similar electrical characteristics into a superblock, and control degradation management, history buffer management, and read operation of the nonvolatile memory 120 in units of superblocks. Steps S10 and S20 may be performed continuously during runtime of the storage device 100.

[0093] 11, the storage device 100 performs a program operation and an erase operation (S11), and can store and update the program count and erase count for each of a plurality of super-blocks as metadata (S12). For example, the controller 120 can store a counting table CTB (FIG. 4A) including the program count and erase count corresponding to each of a plurality of super-blocks in the metadata buffer MB, and can update the program count and erase count in super-block units as program operations and erase operations are successively performed. In this way, the storage device 100 can manage degradation of the non-volatile memory in super-block units.

[0094] The storage device 100 may perform a normal read on the first block of the superblock (S21). For example, the first block is the block on which a read operation is first performed among the multiple blocks of the superblock after the storage device 100 is powered on. The storage device 100 may perform a normal read on the first block based on a default read level, and if the read operation performed based on the default read level fails, may perform a read retry based on a modified read level.

[0095] When a read operation on the first block of the superblock is successful, the storage device 100 may store the read level in the history buffer as a history read level (S22). For example, when a read operation performed based on a default read level is successful, the controller 110 may store the default read level in the history buffer HB as a history read level related to the superblock. Alternatively, when a read retry operation performed based on a modified read level is successful, the controller 110 may store the modified read level in the history buffer HB as a history read level related to the superblock.

[0096] The storage device 100 may perform a history read on a plurality of blocks of the superblock based on the history read level stored in the history buffer (S23). After the history level of the superblock is stored in the history buffer HB in step S22, a history read operation may be performed on the superblock. For example, the controller 110 may perform a history read based on the history read level when performing a read operation (hereinafter, also referred to as a host read operation) on the first block at the read request of the host 200 or performing a host read on another block of the superblock. Alternatively, the controller 110 may perform a history read based on the history read level even when performing a background read operation for updating the history read level.

[0097] In this way, the storage device 100 according to the exemplary embodiment of the present disclosure can manage degradation by managing the program count and erase count of the non-volatile memory 120 in superblock units, manage the history read level stored in the history buffer in superblock units, and further control the read operation. In the storage device 100 according to the embodiment of the present disclosure, the durability and retention characteristics of a plurality of blocks included in a superblock are similar due to program and erase operations, and therefore, the history read level is stored and updated in the history buffer HB in superblock units, thereby minimizing the number of times the defense code is executed, improving the performance of the storage device 100, and reducing the capacity of the history buffer HB.

[0098] 12 is a flowchart showing a method of operating a storage device according to an exemplary embodiment of the present disclosure, which exemplarily describes step S20 of FIG.

[0099] 1 and 12, the storage device 100 may be powered on (S31). After the storage device 100 is powered on, if a read operation is performed in the non-volatile memory 120, a history read level may be stored and updated in the history buffer HB.

[0100] The storage device 100 may receive a read request for the first block of the first superblock from the host 200 (S32). For example, a logical address, e.g., a logical page, received together with the read command from the host 200 may indicate a physical address, e.g., a physical page, corresponding to the first block of the first superblock.

[0101] The storage device 100 can perform a normal read on the first block of the first superblock (S33). The storage device 100 can perform a normal read based on a default read level set for the first superblock, and when the read fails, can perform a read retry based on a read level corrected by executing the defense code.

[0102] When the storage device 100 successfully reads the first block of the first superblock, the read level can be stored in the history buffer HB as the history read level of the first superblock (S34). The default read level or the modified read level is also stored as the history read level. For example, the read level of the successful read operation is also stored as the history read level.

[0103] Thereafter, the storage device 100 may receive a read request for the second block of the first superblock from the host 200 (S35). The storage device 100 may perform a history read for the second block based on the history read level of the first superblock stored in the history buffer HB (S36). Although the history read level has not been acquired for the second block, the history read level is managed on a superblock basis, and the history read level for the superblock is also used during a read operation for a plurality of blocks included in the superblock. However, there is no need to perform a read retry to acquire the history read level for the second block, and the number of times (or time) the defense code is executed may be reduced.

[0104] In one embodiment, if the history read operation involving the second block fails, the storage device 100 performs a read retry on the second block based on the modified read level, and if the read retry is successful, the storage device 100 can update the history read level by storing the modified read level in the history buffer HB as the history read level of the first superblock.

[0105] Meanwhile, in steps S32 and S33 of this embodiment, the storage device 100 is described as performing a normal read on the first block in response to receiving a read request from the host 200, but is not limited thereto. In another embodiment, the storage device 100 may perform a background read (also called a patrol read) without a read request from the host 200, and when the background read on the first block, i.e., a normal read performed based on a default read level or a read by a read retry performed based on a modified read level, is successful, the read level may be stored in the history buffer HB as the read level of the first superblock.

[0106] For example, when the storage device 100 is powered on, it may perform a background read on a plurality of blocks in the non-volatile memory 110, and may store a read level when the first block of the first superblock is successfully read in the history buffer HB as a history read level for the first superblock. As another example, when the storage device 100 is powered on, it may perform a background read on a block selected from each of a plurality of superblocks among a plurality of blocks in the non-volatile memory 110. For example, the controller 110 may perform a background read on a first block among blocks included in the first superblock, and may store a read level when the first block is successfully read in the history buffer HB as a history read level for the first superblock.

[0107] 13 is a flowchart illustrating an operation method of the storage device 100 according to an exemplary embodiment of the present disclosure. FIG 13 provides a detailed explanation of the history read operation of step S36 of FIG 12, which is also performed in a time-sequential manner in the storage device 100 of FIG 1.

[0108] 1 and 13, the storage device 100 may receive a read request for the second block of the first superblock from the host 200 (S41). The storage device 100 may access the history buffer HB and retrieve (or read out) the history read level of the first superblock (S42). For example, the history read level may be the read level obtained when the first block was successfully read, which was stored in step 34 of FIG. 12.

[0109] The storage device 100 can calculate the adjusted read level by adding an offset indicating the characteristic difference between the first block and the second block to the history read level (S43). For example, when the first block and the second block are included in the first device and the second device, respectively, the controller 110 can calculate the adjusted read level by referring to an offset table OTa (FIG. 9A) including device offsets and adding the difference between the first device offset DO1 and the second device offset DO2 to the history read level as an offset. Alternatively, the controller 110 can calculate the adjusted read level by referring to an offset table OTb (FIG. 9B) including block offsets and adding the difference between the offset of the first block and the offset of the second block to the history read level as an offset.

[0110] The storage system 100 can perform a history read on the second block based on the adjusted read level (S44).

[0111] 14A and 14B illustrate the operation of a controller and a non-volatile memory of a storage device according to an embodiment of the present disclosure.

[0112] Referring to FIG. 14A, the controller 110 may issue a read command (S111) and transmit the read command to the non-volatile memory 120 (S1120). The controller 110 may issue a read command in response to a read request from the host 200 (FIG. 1), or may issue the read command autonomously by performing a background read operation. The controller 110 may transmit, together with the read command, an address associated with the physical area where the read is to be performed, e.g., a physical page, and a default read level as a control signal to the non-volatile memory 120.

[0113] The non-volatile memory 120 may perform a normal read based on a default read level (S121). For example, during a normal read operation, data retrieved (or read) from the non-volatile memory 120 may also correspond to read data. The non-volatile memory 120 may transmit the read data to the controller 120 (S122).

[0114] The controller 110 can determine whether the normal read operation has failed (S113). Specifically, the ECC module 115 (FIG. 7) can perform an ECC operation on the received data and determine whether the number of fail bits (e.g., the number of error bits) detected from the received data exceeds the error correction capability of the ECC module 115. If the number of fail bits does not exceed the error correction capability or the data does not include fail bits, it is determined that the normal read operation has been successful, and the controller 110 can store a read level, for example, a default read level, as a history read level in the history buffer HB (S118).

[0115] On the other hand, if the number of fail bits exceeds the error correction capability, it is determined that the normal read operation has failed, and the controller 110 can execute a protection code (S114). The controller 110 can issue a read retry command by executing the protection code (S115). The controller 110 can also issue an address related to the physical area where the read has failed, and determine the read retry voltage as the corrected read level. The controller 110 can transmit the read retry command to the non-volatile memory 120 (S116). The controller 110 can transmit the address together with the read retry command to the non-volatile memory 120, and transmit the read retry voltage, i.e., the corrected read level, as a control signal.

[0116] The non-volatile memory 120 performs a read retry based on the corrected read level (S123), and is able to transmit the data read by the read retry to the controller 110 (S124).

[0117] The controller 110 can determine whether the read retry has failed (S117). As described in step S113, the ECC module 115 performs an ECC operation on the received data, and can determine whether the read has failed based on the result. If the read has failed, the controller 110 further executes step S114, and if the read is successful, the controller 110 can store the read level, in other words, the corrected read level, as the history read level in the history buffer HB (S118). Thus, the history read level of the superblock can be stored in the history buffer HB.

[0118] FIG. 14B shows the operation of the controller 110 and the non-volatile memory 120 by a history read after the operation of FIG. 14A.

[0119] 14B, the controller 110 may receive a read request from the host 200 (S211). The controller 110 may receive the read request and an address from the host 200.

[0120] The controller 110 can retrieve (or read) the history read level from the history buffer (S212). The controller 110 can read the history read level of the superblock that includes the address received in the history buffer HB, i.e., the physical page corresponding to the logical page.

[0121] The controller 110 can transmit a read command to the non-volatile memory 120. The controller 110 can transmit the history read level as a control signal to the non-volatile memory 120 together with the read command.

[0122] The non-volatile memory 120 may perform a history read based on the history read level (S221). For example, the non-volatile memory 120 may perform a read operation on a block of a superblock using the history read level to search for read data. The non-volatile memory 120 may transmit data read by the history read to the controller 110 (S214).

[0123] Thereafter, the controller 110 can determine whether the read has failed by performing an ECC operation on the received data (S214). If the read is successful, the controller 110 can transmit the data to the host 200 (S220).

[0124] When the read fails, the controller 110 may execute a protection code and perform a read retry. For example, the read level may be adjusted by executing the protection code, and a read retry operation may be performed.

[0125] Steps S215 to S218 performed by the controller 110 are the same as steps S114 to S117 in Fig. 14A, and steps S223 and S224 performed by the non-volatile memory 120 are the same as steps S123 and S124 in Fig. 14A, so redundant description will be omitted.

[0126] Meanwhile, when the read is successful in step S218, the controller 110 may update the history read level of the history buffer (S218). The controller 110 may update the history read level based on the modified read level determined by the execution of the defense code in step S215. The controller 110 may also transmit the data to the host 200 (S220).

[0127] 15 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. FIG. 15 illustrates a host read operation that is performed when a read request is received from a host. The operation of FIG. 15 is also performed in the storage device 100 of FIG. 1. Therefore, the description will be made with reference to FIG. 1.

[0128] The storage device 110 may receive a read request and an address from the host 200 (S310). The address includes an address related to a logical area, i.e., a logical address, and the storage device 110 may determine a physical area, e.g., a physical page, corresponding to the logical area, and may determine a block and a superblock in which the physical area is included.

[0129] The storage device 110 can check whether the history buffer HB is free (S320). Here, the history buffer HB being free means that the history read level of the superblock corresponding to the block to be read is not stored in the history buffer HB. For example, if the history read level of a superblock other than the superblock corresponding to the block to be read is stored in the history buffer HB, it can be determined that the history buffer HB is free.

[0130] If the history buffer HB is empty, in other words, if the history read level of the superblock corresponding to the physical area to be read does not exist in the history buffer HB, the storage device 110 can perform a normal read based on the default read level (S330). Conversely, if the history buffer HB is not empty, in other words, if the history read level of the superblock corresponding to the physical area to be read exists in the history buffer HB, the storage device 110 can perform a history read based on the history read level (S340).

[0131] After performing a normal read or a history read, the storage device 110 determines whether the read was successful (S350). If the read fails, a read retry may be performed (S360). The storage device 110 may update the history read level of the history buffer based on the corrected read level when the read retry is successful (S380). The storage device 110 may transmit the read data to the host (S390).

[0132] 15, the history buffer is updated in step S360 by a host read operation. However, the present invention is not limited to this, and the history buffer may also be updated by a background read operation of the storage device 100. This will be described with reference to FIG.

[0133] 16 is a flowchart illustrating a method for updating a history buffer in a storage device according to an exemplary embodiment of the present disclosure. The operations in FIG. 16 are also performed in time sequence in the storage device 100 of FIG.

[0134] 1 and 16, the storage device 100 may perform a background read on a representative block of each of a plurality of superblocks in the non-volatile memory 120 (S410). The storage device 100 may preliminarily set one block as a representative block for each of a plurality of superblocks and perform a background read on the representative blocks in sequence. The storage device 100 may perform the background read periodically or aperiodically. For example, the storage device 100 may perform the background read of step S410 based on the history read level already stored in the history buffer HB if a predetermined time has elapsed after a read operation on the superblock is performed. For example, the background read operation may also be performed to ensure that each superblock has the latest read level stored in the history buffer HB.

[0135] The storage device 100 determines whether the read has failed (S420). If the read has failed, the storage device 100 may perform a read retry (S430). The read retry operation includes a step of modifying a read level applied to the representative block, and determining a codeword by comparing a voltage indicating data of the representative block with the modified read level. If the read retry is successful, the storage device 100 may update the history buffer HB based on the modified read level (S440). For example, if the ECC operation performed on the codeword is successful, the read retry operation may be successfully performed. The storage device 110 may store the modified read level in the history buffer HB as a history read level of a superblock corresponding to the representative block for which the background read was performed in step S410. On the other hand, if it is determined that the read is successful in step S420, the storage device 100 may end the background read without updating the history buffer.

[0136] FIG. 17 is a flowchart illustrating an example of a super-block grouping method of a storage device according to an exemplary embodiment of the present disclosure.

[0137] 1 and 17, the storage device 100 may be initialized (S510). For example, the storage device 100 may be initialized while in use or after the manufacturing stage. For example, the initialization of the storage device 110 may include setting characteristic information in the storage device 100.

[0138] The controller 110 of the storage device 100 can read characteristic information related to each of the multiple blocks from the non-volatile memory 120 (S520). During the manufacturing stage or a subsequent test stage, the characteristics of each of the multiple blocks can be detected and the characteristic information can be stored in the device. The controller 110 can read the characteristic information of the corresponding blocks from the multiple devices.

[0139] The controller 110 may group a plurality of blocks into a plurality of superblocks based on the characteristic information (S530). The controller 110 may group blocks having similar characteristics into one superblock. The controller 110 may then manage the metadata and history buffers as described above on a superblock basis.

[0140] FIG. 18 is a flowchart illustrating a method for regrouping a supergroup of a storage device according to an exemplary embodiment of the present disclosure, and FIGS. 19A and 19B illustrate a specific example of the regrouping of FIG.

[0141] 18, the storage device 110 performs a background read on each of the blocks of the non-volatile memory 120 (S610). The storage device 110 may calculate characteristic values ​​for each of the blocks based on the background read results (S620). For example, the characteristic values ​​may include a width of a threshold voltage distribution, a minimum level of a threshold voltage, etc.

[0142] The storage device 110 can regroup multiple blocks based on the characteristic values ​​(S630).

[0143] In one embodiment, the storage device 110 may regroup multiple blocks such that blocks with the same or similar characteristic values ​​are included in the same superblock, as shown in Figure 19A. In Figure 19A, before regrouping, blocks at the same location in multiple devices D1 to D8 are also grouped into one superblock. The storage device 110 performs regrouping based on the characteristic values ​​of multiple blocks detected by background read, and blocks with the same or similar characteristic values ​​are also grouped into one superblock, regardless of the location of each block.

[0144] In one embodiment, the storage device 110 may determine a block in which a defect occurs based on the characteristic value, and may replace the block in which a defect occurs in the superblock with another block. For example, referring to FIG. 19B, if blocks B12 to B82 are also grouped into a second superblock SB, and a background read determines that a defect occurs in block B82, block B82 may be replaced with block Bd8. Thereafter, blocks B12, B22, and Bd8 are also grouped into a second superblock SB2.

[0145] Continuing with reference to FIG. 18, the storage device 110 may manage the metadata and history buffers in units of regrouped superblocks (S640).

[0146] FIG. 20 is a flowchart showing a method of operating a storage device according to an exemplary embodiment of the present disclosure, and FIG. 21 exemplarily explains the method of operating FIG.

[0147] Referring to FIG. 20, the storage device 100 can manage degradation of non-volatile memory on a memory group basis including multiple blocks (S10a), and can manage history buffers and read operations on a subgroup basis of the memory group (S20).

[0148] 21, a plurality of devices D1 to D8 constitute the non-volatile memory 120, and at least one block of the plurality of devices D1 to D8 is also grouped into a superblock. For example, the first blocks of each of the plurality of devices D1 to D8, for example, blocks B11 to B81, are also grouped into a first superblock SB. Meanwhile, within a superblock, for example, the first superblock SB1, blocks having similar characteristics are also grouped into subgroups. For example, in the first superblock SB1, blocks B11, B21, B31, and B51 may be included in a first subgroup SG1, and blocks B41, B61, B71, and B81 may be included in a second subgroup SG1 because they have similar electrical characteristics.

[0149] The storage device 100 can manage the degradation of the non-volatile memory 120 on a superblock basis by counting and storing the number of times the program and erase operations are performed for each of the multiple superblocks SB1 to SBk, and can manage the history buffer and read operations on a subgroup basis by storing and updating the history read level for each subgroup, for example, the first subgroup SG1 and the second subgroup SG2.

[0150] FIG. 22 is a block diagram illustrating an SSD according to an exemplary embodiment of the present disclosure, and an SSD system including the SSD.

[0151] 22, the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may communicate with the host 1100 and exchange signals, such as commands, addresses, and data, with the host 1100. The SSD 1200 may receive power from the host 1100 to operate.

[0152] The SSD 1200 may include an SSD controller 1210, a plurality of nonvolatile memory devices 1220, 1230, 1240, and a buffer memory 1300. The storage device 100 and the controller 110 described with reference to FIG. 1 to FIG. 21 may be applied to the SSD 1200 and the SSD controller 1210, respectively. The plurality of nonvolatile memory devices 1220, 1230, 1240 may also be realized by a plurality of semiconductor chips. The SSD controller 1210 may communicate with the plurality of nonvolatile memory devices 1220, 1230, 1240 through a plurality of channels CH1, CH2, CHn. For example, at least one memory block included in each memory chip constituting the nonvolatile memory devices 1220, 1230, 1240 constitutes a superblock, and the SSD 1200 may manage metadata (e.g., deterioration level, program count, and erase count) and a history buffer (e.g., history read level) in units of superblocks.

[0153] The buffer memory 1300 may be embodied with a volatile memory or a resistive memory, for example, the buffer memory 1300 may be a DRAM. The buffer memory 1300 may temporarily store data received from the host 1100 and stored in the plurality of non-volatile memory devices 1220, 1230, 1240, or may temporarily store data read from the plurality of non-volatile memory devices 1220, 1230, 1240 and transmitted to the host 1100. In one embodiment, a history buffer may also be embodied as part of the buffer memory 1300.

[0154] The storage system according to the above-described embodiment of the present disclosure can be installed or applied not only to the SSD system 1000 but also to a memory card system, a universal flash storage (UFS), an embedded storage, and the like.

[0155] As described above, the exemplary embodiment has been disclosed with the drawings and the specification. In this specification, the present embodiment has been described using specific terms, but these terms are used only for the purpose of describing the technical idea of ​​the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person skilled in the art will understand that various modifications and other equivalent embodiments are possible. Therefore, the true technical scope of protection of the present disclosure is defined by the technical idea of ​​the claims. [Explanation of symbols]

[0156] 10 Storage Systems 100 Storage Device 110,110a Controller 111 Processor 112 Memory 113 Host Interface 114 ROM 115 ECC Module 116 NVM Interface 120 Non-volatile memory 200 Host

Claims

1. A method for operating a storage device including a non-volatile memory, comprising: the non-volatile memory includes a plurality of superblocks, each superblock including at least two blocks; performing a read on a first block included in a first superblock of the plurality of superblocks based on a first read level; if the read operation for the first block is successful, storing the first read level in a history buffer as a history read level of the first superblock; in response to receiving a read request for a second block of the first superblock, calculating an adjusted read level by adding a characteristic offset indicating a characteristic difference between the first block and the second block to the history read level; and performing a read on the second block based on the adjusted read level.

2. generating a modified read level from the first read level if the read operation for the second block fails; performing a read retry on the second block using the modified read level; 2. The method of claim 1, further comprising: updating the read level of the first superblock stored in the history buffer based on the modified read level. determining whether the history read level associated with the first superblock exists in the history buffer; performing a normal read on the second block based on a default read level when it is determined that the history read level does not exist in the history buffer; 2. The method of claim 1, wherein the steps of calculating the adjusted read level and reading the second block based on the adjusted read level occur only if it is determined that the history read level exists in the history buffer.

4. When a read fails, a read retry is performed on the second block based on a corrected read level; 4. The method of claim 3, further comprising: updating the history buffer by storing the modified read level as the history read level of the first superblock.

5. the non-volatile memory is composed of a plurality of memory devices, each of the plurality of memory devices stores a device offset indicating an electrical characteristic of the memory device; 2. The method of claim 1, wherein the first block and the second block are included in a first memory device and a second memory device of the plurality of memory devices, and the characteristic offset is calculated based on a device offset of the first memory device and a device offset of the second memory device.

6. The method of claim 1, further comprising grouping the plurality of blocks into the plurality of superblocks based on characteristics of the plurality of blocks.

7. performing a background read on at least one block selected from the first superblock based on a history read level; generating a modified read level based on the history read level when the background read fails; performing a read retry on the selected at least one block based on the modified read level; 2. The method of claim 1, further comprising: updating the history buffer by saving the modified read level as the history read level of the first superblock.

8. performing a background read on each of the superblocks; calculating a characteristic value of each of a plurality of blocks of the superblock based on the background read; detecting a defective block for a selected one of the super-blocks based on the characteristic value; The method of claim 1 , further comprising: replacing the block in which the defect occurs with another block.

9. 2. The method of claim 1, wherein the step of reading from the first block is performed based on a default read level in response to a read request received from a host.

10. a non-volatile memory including a plurality of physical blocks; a controller for controlling the non-volatile memory to group the plurality of physical blocks into a plurality of groups, store a program count and an erase count for each of the plurality of groups as metadata, store a read level for each of the plurality of groups in a history buffer, and, when a read command and an address are received from a host, perform a read on a selected physical block among the physical blocks corresponding to the address based on a corresponding read level among the plurality of read levels stored in the history buffer; The controller: if the corresponding read level is determined based on other physical blocks of a group including the selected physical block, determining an adjusted read level by adding an offset based on a characteristic difference between the selected physical block and the other physical blocks to the read level, and transmitting the adjusted read level to the non-volatile memory to be used when performing a read on the selected physical block. Storage device.

11. The controller: The storage device of claim 10, further comprising: if a read performed on the selected physical block is determined to be unsuccessful based on the corresponding read level, the read level is modified; and a read retry is performed on the selected physical block based on the modified read level.

12. The controller:

12. The storage device of claim 11, further comprising: updating the read level stored in the history buffer to the modified read level if the read retry performed on the selected physical block is determined to be successful based on the modified read level.

13. The controller:

11. The storage device according to claim 10, further comprising: controlling the non-volatile memory so that a background read is performed on the plurality of physical blocks; and regrouping the plurality of physical blocks based on characteristic values ​​of each of the plurality of physical blocks calculated based on the background read.

14. 1. A method for operating a storage device including a non-volatile memory including a plurality of memory blocks divided into a plurality of memory groups, comprising: reading a first block included in a first memory group among the plurality of memory groups based on a first read level; if the read operation for the first block is successful, storing the first read level in a history buffer as a read level for the first memory group; receiving a read request and an address for a second block included in the first memory group from a host; determining a second read level based on the first read level stored in the history buffer and a characteristic offset indicating a characteristic difference between the first block and the second block; and performing a read on the second block based on the second read level.

15. The method of claim 14 , wherein the first read level is a preset default read level for the first memory group.

16. 15. The method of claim 14, further comprising counting the number of program and erase cycles of the non-volatile memory for each of the plurality of memory groups and storing the counted number of program and erase cycles as metadata.

17. the non-volatile memory is composed of a plurality of memory devices, and a device offset indicating an electrical characteristic of the memory device is stored in each of the plurality of memory devices; 15. The method of claim 14, wherein the first block and the second block are located in a first memory device and a second memory device of the plurality of memory devices, and the characteristic offset is calculated based on a device offset of the first memory device and a device offset of the second memory device.

18. 20. The method of claim 17, wherein an order of the first blocks in the first memory device is the same as an order of the second blocks in the second memory device.

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