Hardware assisted dynamic random access memory (DRAM) row merging.

Abstract

Hardware-assisted dynamic random access memory (DRAM) row merging involves a memory controller identifying multiple rows in a DRAM module that store identical data, storing data in a mapping table that maps one or more of the multiple rows to another row, and excluding one or more rows from refreshing the DRAM module.

Description

[Background technology]

[0001] To ensure data integrity, dynamic random access memory (DRAM) rows must be refreshed. Refreshing dynamic random access memory accounts for a significant portion of the power used by a memory module. In some environments, multiple rows of dynamic random access memory store the same value. [Brief description of the drawings]

[0002] [Figure 1] 1 is a block diagram of an example system for hardware-assisted DRAM row merging in accordance with some embodiments. [Diagram 2] 4 is a flowchart of an example method for hardware-assisted DRAM row merging in accordance with some embodiments. [Diagram 3] 4 is a flowchart of an example method for hardware-assisted DRAM row merging in accordance with some embodiments. [Figure 4] 4 is a flowchart of an example method for hardware-assisted DRAM row merging in accordance with some embodiments. [Diagram 5] 4 is a flowchart of an example method for hardware-assisted DRAM row merging in accordance with some embodiments. [Figure 6] 4 is a flowchart of an example method for hardware-assisted DRAM row merging in accordance with some embodiments. [Figure 7] 4 is a flowchart of an example method for hardware-assisted DRAM row merging in accordance with some embodiments. [Figure 8] 4 is a flowchart of an example method for hardware-assisted DRAM row merging in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0003] In some embodiments, hardware assisted dynamic random access memory (DRAM) row merging includes, among other things, a memory controller identifying multiple rows in a DRAM module that store identical data, and further includes mapping one or more of the multiple rows to another row in a mapping table and excluding one or more rows from refreshing the DRAM module.

[0004] In some embodiments, the hardware assisted DRAM row merging further includes updating a bitmap to indicate that one or more rows are excluded from refresh. In such embodiments, excluding one or more rows from refresh includes the memory controller providing the bitmap to the DRAM module. In some embodiments, the other row includes any of the multiple rows. In other embodiments, the other row includes a reserved row included in one or more reserved rows of the DRAM module. In some embodiments, the hardware assisted DRAM row merging further includes determining that the single row is mapped to the reserved row. In response to such determination, the memory controller stores data stored in the reserved row in the single row and updates the mapping table to remove the mapping of the single row to the reserved row. In some embodiments, the hardware assisted DRAM row merging further includes maintaining a counter indicating a number of rows mapped to the reserved row. In such embodiments, determining that the single row is mapped to the reserved row is based on the counter. In some embodiments, the hardware assisted DRAM row merging further includes maintaining a mapping table cache that stores a portion of the mapping table. In some embodiments, the hardware assisted DRAM row merging further includes receiving a read request for any of the one or more rows. In response to receiving the read request, the memory controller determines, based on the mapping table, that the row is mapped to another row and provides the data stored in the other row. In some embodiments, the hardware-assisted DRAM row merging further includes receiving a write request for a particular row of the one or more rows. In response to the write request, the memory controller stores the data stored in the reserved row in the particular row of the one or more rows. The memory controller then executes the write request and updates the mapping table to remove the mapping of the particular row to the reserved row.

[0005] In some embodiments, a memory controller for hardware assisted DRAM row merging performs steps including, inter alia, the memory controller identifying, within a DRAM module, a plurality of rows that store identical data, the steps further including mapping one or more of the plurality of rows to another row in a mapping table, and excluding one or more rows from refreshing the DRAM module.

[0006] In some embodiments, the process further includes updating the bitmap to indicate that the one or more rows are excluded from the refresh. In such embodiments, excluding the one or more rows from the refresh includes the memory controller providing the bitmap to the DRAM module. In some embodiments, the another row includes any of the plurality of rows. In other embodiments, the another row includes a reserved row included in the one or more reserved rows of the DRAM module. In some embodiments, the process further includes determining that the single row is mapped to the reserved row. In response to such determination, the memory controller stores the data stored in the reserved row in the single row and updates the mapping table to remove the mapping of the single row to the reserved row. In some embodiments, the process further includes maintaining a counter indicating a number of rows mapped to the reserved row. In such embodiments, determining that the single row is mapped to the reserved row is based on the counter. In some embodiments, the process further includes maintaining a mapping table cache that stores a portion of the mapping table. In some embodiments, the process further includes receiving a read request for any of the one or more rows. In response to receiving the read request, the memory controller determines, based on the mapping table, that the row is mapped to another row and provides the data stored in the other row. In some embodiments, the process further includes receiving a write request for a particular row of the one or more rows. In response to the write request, the memory controller stores the data stored in the reserved row in the particular row of the one or more rows. The memory controller then executes the write request and updates the mapping table to remove the mapping of the particular row to the reserved row.

[0007] In some embodiments, an apparatus for hardware assisted DRAM row merging includes a memory controller that performs steps including, among other things, the memory controller identifying a plurality of rows in a DRAM module that store identical data, the steps further including mapping one or more of the plurality of rows to another row in a mapping table, and excluding one or more rows from refreshing the DRAM module.

[0008] In some embodiments, the process further includes updating the bitmap to indicate that one or more rows are excluded from refresh. In such embodiments, excluding one or more rows from refresh includes the memory controller providing the bitmap to the DRAM module.

[0009] 1 is a block diagram of a non-limiting exemplary system 100. The exemplary system 100 can be implemented in a variety of devices, including a central processing unit (CPU), a graphics processing unit (GPU), etc. The system 100 includes a memory controller 102 and one or more dynamic random access memory (DRAM) modules 104. Each of the DRAM modules 104 includes multiple rows 106 for storing data. The memory controller 102 processes read and write requests issued to the DRAM modules 104. For example, the memory controller 102 maintains a queue of read and write requests and issues the queued requests to the particular DRAM module 104 to which the request is directed.

[0010] The rows 106 are volatile memory for storing data. Because the rows 106 are volatile, the rows 106 must be periodically refreshed to maintain the integrity of the stored data. These refreshes account for a significant portion of the power utilized by the DRAM module 104. In many environments, multiple rows 106 in the same DRAM module 104 store identical data; that is, each value in one row 106 is identical to each value in one or more other rows 106. For example, in an environment where multiple virtual machines run on the same hardware, and the virtual machines are running the same software or operating system, the data stored in the allocated portion of the DRAM for each virtual machine will be at least partially identical.

[0011] Existing solutions for addressing identical data across rows of DRAM include software modules managed by a hypervisor or other agent that deduplicate data from identical rows. However, to reduce the bottleneck involved in deduplication of DRAM content, these modules typically run only when the total available memory in the system is below a threshold. Furthermore, because these solutions are software-based, computational overhead and resources are required to deduplicate data stored in DRAM.

[0012] Instead of utilizing a software-based solution that requires significant computational overhead and is executed only when the total system memory falls below a threshold, the system 100 uses a hardware-based approach to merge rows 106 that store identical data within the DRAM module 104. The memory controller 102 identifies multiple rows within the DRAM module 104 that store identical data. For example, each of the multiple rows may include a row 106 of the DRAM module 104. As another example, the multiple rows may include one or more rows 106 that share identical data with a reserved row 108. The reserved row 108 is a row of memory within the DRAM module 104 that is reserved for storing data from the row 106 identified as storing the identical data. In other words, the row 106 is used to accommodate read and write operations from other processes or agents, while the reserved row 108 is used only to store data from the row 106 identified as storing the identical data.

[0013] In some embodiments, identifying multiple rows that store the same data is performed at a predetermined interval or in response to another event. For example, the memory controller 102 identifies two or more rows 106 that store the same data within the rows 106 in response to the occurrence of an event. As another example, the memory controller 102 identifies one or more rows 106 that store the same data within the rows 106 in response to the occurrence of an event. In some embodiments, identifying multiple rows is performed in response to a read request or a write request issued to the row 106. For example, the memory controller 102 compares data read from or written to the row 106 with data from another row 106 or the reserved row 108. In some embodiments, this includes comparing a checksum 110 or hash of the data read from or written to the row 106 with one or more stored checksums 110, as described in more detail below.

[0014] The memory controller 102 then stores data mapping one or more of the multiple rows to another row in a mapping table 112. Each entry in the mapping table 112 maps a row 106 to another row within the DRAM module 104, where the other row stores the same data as was last stored in the row 106 to which it is mapped. Although the mapping table 112 is shown as being stored in the DRAM module 104, it will be understood that in some embodiments the mapping table 112 is stored in the memory controller 102 instead.

[0015] In some embodiments, storing data mapping one or more rows to another row includes storing data mapping one or more rows 106 of the plurality of identified rows 106 to another row 106 of the plurality of identified rows 106. For example, assume that memory controller 102 identifies rows 106A, 106B, 106C, and 106D as each storing identical data. In such an example, memory controller 102 stores an entry in mapping table 112 that maps rows 106A, 106B, and 106C to row 106D. In this example, row 106D is considered a "representative row" if the remaining rows are mapped to it. Further, in this example, row 106D is arbitrarily selected as the representative row, and it will be understood that the other rows 106 are also possible representative rows.

[0016] As another example, assume that memory controller 102 identifies rows 106A, 106B, 106C, and 106D as each storing identical data. Memory controller 102 then stores data in reserved row 108 equal to that stored in rows 106A, 106B, 106C, and 106D, and stores entries in mapping table 112 that map rows 106A, 106B, 106C, and 106D to reserved row 108. As a further example, assume that memory controller 102 identifies rows 106A, 106B, and 106C as storing data equal to data already stored in reserved row 108. Memory controller 102 then stores entries in mapping table 112 that map rows 106A, 106B, and 106C to reserved row 108.

[0017] The memory controller 102 then excludes one or more rows 106 (e.g., rows 106 that are mapped to another row in the mapping table 112) from refreshing the DRAM module 104. For example, the memory controller 102 provides the DRAM module 104 with an indication of which rows 106 will or will not be refreshed during the next refresh operation. In some embodiments, the memory controller 102 maintains a refresh bitmap 114. Each row 106 corresponds to a bit in the refresh bitmap 114. When a row 106 is mapped to another row (e.g., to a representative row or a reserved row 108), the bit corresponding to the mapped row 106 is set (e.g., set to “1”) to indicate that the mapped row 106 will be skipped during the next refresh. For example, when an entry in the mapping table 112 is generated to map a particular row 106, the bit in the refresh bitmap 114 corresponding to the particular row 106 is set to indicate that the particular row 106 will be excluded from the next refresh. Thus, in some embodiments, excluding one or more rows 106 from refresh includes providing a refresh bitmap 114 to the DRAM module 104. The DRAM module 104 then performs a refresh operation based on the refresh bitmap 114.

[0018] According to the above approach, one or more rows 106 that store data identical to another row (e.g., representative row or reserved row 108) are excluded from the refresh operation, saving energy compared to refreshing these rows 106. Such rows 106 are hereinafter referred to as "merge rows 106." Read operations for these merge rows 106 are performed by accessing the mapping table 112 to determine the location to which the mapped row 106 is mapped (e.g., the target of the mapping), and then loading the corresponding data from the target of the mapping.

[0019] As described above, merged rows 106 are mapped to either a representative row (contained in rows 106) or to a reserved row 108. Because the representative row can still be the target of a write request, mapping to a representative row presents a risk of significant overhead when written to. For example, when writing to a representative row, the data stored in the representative row must be copied to another row, and any mapping table 112 entries that map to the representative row should be updated to a mapping to this other row. Thus, because the reserved row 108 is written only to store the data of the merged row 106, in a preferred embodiment, the merged row 106 is mapped to the reserved row 108.

[0020] In some embodiments, the memory controller 102 maintains, for each reserved row 108, a corresponding counter 116 that indicates the number of merge rows 106 that are mapped to the reserved row 108. For example, when an entry in the mapping table 112 is created that maps a merge row 106 to a reserved row 108, the memory controller 102 increments the counter 116 that corresponds to the reserved row 108. When the merge row 106 stops being mapped to the reserved row 108 (e.g., in response to a write on the merge row 106), the counter 116 that corresponds to the reserved row 108 is decremented. In some embodiments, the counters 116 are maintained in the same data structure as the checksums 110 of each reserved row 108. For example, each entry in the data structure corresponds to a reserved row 108. Each entry in the data structure indicates, for the corresponding reserved row 108, the checksum 110 of the data stored in the reserved row 108 (if any) and a counter 116 that indicates the number of merge rows 106 that are mapped to the reserved row 108.

[0021] Thus, in some embodiments, the memory controller 102 determines when the single row 106 is mapped to the reserved row 108. For example, the memory controller 102 determines when the counter 116 corresponding to the reserved row 108 is set to "1." As another example, the memory controller 102 accesses an entry in the mapping table 112 that maps to the reserved row 108 and determines that the single mapping table 112 is mapped to the reserved row 108.

[0022] In response to determining that the single row 106 is mapped to the reserved row 108, the memory controller 102 stores the data stored in the reserved row 108 in the single row 106. For example, the memory controller 102 issues a command to the DRAM module 104 to copy or replicate the data stored in the reserved row 108 to the single row 106 mapped to the reserved row 106. This ensures that the single row 106 stores correct data in the event that data previously stored in the single row 106 becomes corrupted due to lack of refresh. The memory controller 102 then updates the mapping table 112 to remove the mapping of the single row 106 to the reserved row 108. In some embodiments, the memory controller 102 decrements a counter corresponding to the reserved row 108 to zero. In some embodiments, this indicates that the reserved row 108 is unallocated and available for storage of other data to map other rows 106 for merging purposes. In some embodiments, the memory controller 102 updates the refresh bitmap 114 to indicate that the next refresh should include a single row 106 that is not currently mapped to any reserved row 108.

[0023] As described above, in some embodiments, the memory controller 102 maintains a checksum 110 of the data stored in each reserved row 108. The checksum 110 facilitates determining whether data read from or written to a row 106 matches the reserved row 108. For example, in response to a write request to a row 106, the memory controller 102 determines that the data to be written matches the reserved row 108. Instead of executing the write request, the memory controller 102 generates an entry in the mapping table 112 that maps the row 106 targeted by the write request to the reserved row 108. In some embodiments, the memory controller 102 updates the refresh bitmap 114 to indicate that the row 106 targeted by the write request, here the merge row 106, is excluded from refreshing the DRAM module 104. As another example, in response to a read request to a row 106, the memory controller 102 determines that the read data matches the data stored in the reserved row 108 based on the checksum 110. The memory controller 102 then generates an entry in the mapping table 112 that maps the read row 106 to the reserved row 108 and updates the refresh bitmap 114 to exclude the read row 106 from refreshing the DRAM module 104 .

[0024] In some embodiments, the memory controller 102 maintains a mapping table cache 118 that stores the most recently or most frequently used mappings in the mapping table 112. For example, the memory controller 102 accesses the mapping table 112 to determine whether a row 106 targeted by a read or write request is mapped to another row (e.g., the representative row or the reserved row 108). If the memory controller 102 finds a match in the mapping table 112, the memory controller 102 updates the mapping table cache 118 to include the matching mapping table 112 entry. Thus, a read or write request is first compared to entries in the mapping table cache 118 before accessing the mapping table 112, reducing the number of accesses to the DRAM module 104 required to determine whether a particular row 106 has been merged and mapped to another row.

[0025] In response to a read request for a column 106 in the DRAM module 104, the memory controller 102 determines whether the row 106 has been merged and mapped to another row (e.g., the representative row or the reserved row 108). For example, the memory controller 102 accesses the mapping table cache 118 to determine whether an entry exists that maps the row 106. If an entry is not found or if the mapping table cache 118 is not implemented, the memory controller 102 accesses the mapping table 112 to determine whether an entry exists that maps the row 106. If an entry exists in the mapping table cache 118 or the mapping table 112, the row targeted by the mapping indicated in the accessed entry and the stored data are retrieved. This data is then returned in response to the read request. In some embodiments, the identified entry of the mapping table 112 is added to the mapping table cache 118.

[0026] In response to a write request for row 106 in DRAM module 104, memory controller 102 determines whether row 106 has been merged and mapped to reserved row 108. For example, memory controller 102 accesses mapping table cache 118 to determine whether an entry exists that maps row 106 to reserved row 108. If no entry is found or if mapping table cache 118 is not implemented, memory controller 102 accesses mapping table 112 to determine whether an entry exists that maps row 106 to reserved row 108.

[0027] If an entry exists in the mapping table cache 118 or mapping table 112, the reserved row 108 is accessed and the contents of the reserved row 108 are copied to the row 106 targeted by the write request. The write request is then applied to row 106. The entry in the mapping table 112 (and the entry in the mapping table cache 118, if present) that maps row 106 to the reserved row 108 is removed. In some embodiments, the counter 116 corresponding to the reserved row 108 is decremented.

[0028] 2 illustrates a flow chart depicting an exemplary method for hardware-assisted DRAM row merging that includes identifying 202 multiple rows within a DRAM module 104 (e.g., by the memory controller 102) that store identical data. For example, each of the multiple rows includes a row 106 of the DRAM module 104. As another example, the multiple rows include one or more rows 106 and a reserved row 108, where one or more rows 106 share identical data with the reserved row 108. For example, in some embodiments, the reserved row 108 stores data by pre-merging other rows 106 and mapping them to the reserved row.

[0029] In some embodiments, identifying 202 the multiple rows storing the same data is performed at a predetermined interval or in response to another event. For example, the memory controller 102 identifies two or more rows 106 that store the same data within the rows 106 in response to the occurrence of an event. As another example, the memory controller 102 identifies one or more rows 106 within the rows 106 that store the same data as the reserved row 108. In some embodiments, identifying the multiple rows is performed in response to a read request or a write request issued to the row 106. For example, the memory controller 102 compares the data read from or written to the row 106 with the data of another row 106 or the reserved row 108.

[0030] 2 also includes storing 204 data in the mapping table 112 that maps one or more of the rows 106 to another row. Each entry in the mapping table 112 maps a row 106 to another row in the DRAM module 104, where the other row stores the same data as was last stored in the row 106 to which it is mapped. In some embodiments, the other row includes the row 106 of the DRAM module 104 (e.g., the row 106 that can be targeted by read and write requests). In other embodiments, the other row to which the row 106 is mapped includes a reserved row 108 that is reserved for storing data and is mapped to the row 106. Although the mapping table 112 is shown as being stored in the DRAM module 104, it will be understood that in some embodiments, the mapping table 112 is instead stored in the memory controller 102.

[0031] In some embodiments, storing 204 data mapping one or more rows 106 to another row includes storing data mapping one or more rows 106 of the plurality of identified rows 106 to another row 106 of the plurality of identified rows 106. For example, assume that memory controller 102 identifies rows 106A, 106B, 106C, and 106D as each storing the same data. In such an example, memory controller 102 stores an entry in mapping table 112 that maps rows 106A, 106B, and 106C to row 106D. In this example, row 106D is considered a "representative row" if the remaining rows 106 are mapped to it. Further, in this example, row 106D is arbitrarily selected as the representative row, the other rows 106 are possible representative rows, and it will be understood that the representative row can be selected according to various criteria.

[0032] As another example, assume that memory controller 102 identifies rows 106A, 106B, 106C, and 106D as each storing identical data. Memory controller 102 then stores data in reserved row 108 equal to that stored in rows 106A, 106B, 106C, and 106D, and stores entries in mapping table 112 that map rows 106A, 106B, 106C, and 106D to reserved row 108. As a further example, assume that memory controller 102 identifies rows 106A, 106B, and 106C as storing data equal to data already stored in reserved row 108. Memory controller 102 then stores entries in mapping table 112 that map rows 106A, 106B, and 106C to reserved row 108.

[0033] 2 further includes (e.g., by the memory controller 102) excluding 206 one or more rows 106 (e.g., rows 106 that are mapped to another row in the mapping table 112) from refreshing the DRAM module 104. A row 106 that has an entry in the mapping table 112 and is excluded from refreshing is considered a "merged row" 106. In some embodiments, excluding 206 the one or more rows 106 from refreshing includes providing to the DRAM module 104 an indication of the row 106 that will or will not be refreshed during the next refresh operation. The DRAM module 104 then performs the refresh according to the received indication.

[0034] For further explanation, Figure 3 illustrates a method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure. The method of Figure 3 is similar to that of Figure 2 in that it includes identifying 202 multiple rows that store identical data, storing 204 data in a mapping table 112 that maps one or more rows 106 of the multiple rows to another row, and excluding 206 one or more rows 106 from refreshing the DRAM module 104.

[0035] FIG. 3 differs from FIG. 2 in that it includes updating 302 a bitmap (e.g., refresh bitmap 114) to indicate that one or more rows 106 are excluded from refresh. For example, in some embodiments, memory controller 102 maintains refresh bitmap 114. Each row 106 corresponds to a bit in refresh bitmap 114. When a row 106 is mapped to another row (e.g., to a representative row or a reserved row 108), the bit corresponding to the mapped row 106 (e.g., the row 106 having a mapping table 112 entry) is set (e.g., set to “1”) to indicate that the mapped row 106 is to be skipped during the next refresh. For example, when an entry in mapping table 112 is generated to map a particular row 106, the bit in refresh bitmap 114 corresponding to the particular row 106 is set to indicate that the particular row 106 is to be excluded from the next refresh.

[0036] The method of Figure 3 further differs from Figure 2 in that, except for excluding 206 one or more rows 106 from refresh, it includes providing 304 a bitmap (e.g., refresh bitmap 114) to the DRAM module 104. The DRAM module 104 then performs a refresh operation based on the received bitmap.

[0037] For further explanation, Figure 4 illustrates a method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure. The method of Figure 4 is similar to that of Figure 2 in that it includes identifying 202 multiple rows that store identical data, storing 204 data in a mapping table 112 that maps one or more rows 106 of the multiple rows to another row, and excluding 206 one or more rows 106 from refreshing the DRAM module 104.

[0038] Assume that the other row to which one or more rows 106 are mapped is a reserved row 108. The method of FIG. 4 differs from FIG. 2 in that it includes determining 402 that a single row 106 is mapped to the reserved row 108. Assume that after multiple rows 106 are mapped to the reserved row 108, the mapping of all rows except these rows 106 to the reserved row 108 is stopped. For example, a write operation is performed that targets a mapped row 106 other than the single row 106. As a result, the row 106 targeted by the write operation stores a different value than the mapped reserved row 108 and requires not to be mapped to the reserved row 108.

[0039] In some embodiments, determining 402 that the single row 106 is mapped to the reserved row 108 includes determining that a counter 116 indicating the number of rows 106 mapped to the reserved row 108 is set to “1.” As another example, determining 402 that the single row 106 is mapped to the reserved row 108 includes accessing an entry in the mapping table 112 that maps to the reserved row 108 to determine that the single mapping table 112 is mapped to the reserved row 108.

[0040] 4 further includes storing 404 the data stored in the reserved row 108 to the single row 106. For example, the memory controller 102 issues a command to the DRAM module 104 to copy or replicate the data stored in the reserved row 108 to the single row 106 mapped to the reserved row 108. This ensures that the single row 106 stores the correct data in the event that data previously stored in the single row 106 becomes corrupted due to lack of refresh.

[0041] 4 further includes updating 406 the mapping table 112 to remove the mapping of the single row 106 to the reserved row 108. In some embodiments, the memory controller 102 decrements 406 the counter 116 corresponding to the reserved row 108 to zero. In some embodiments, this indicates that the reserved row 108 is unallocated and available for storing other data to which other rows 106 can be mapped for merging purposes. In some embodiments, the memory controller 102 updates the refresh bitmap 114 to indicate that the next refresh will include the single row 106 that is not currently mapped to any reserved row 108.

[0042] For further explanation, Figure 5 illustrates a method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure. The method of Figure 5 is similar to Figure 4 in that it includes identifying 202 a plurality of rows storing identical data, storing 204 data mapping one or more rows 106 of the plurality of rows to another row in a mapping table 112, excluding 206 one or more rows 106 from refreshing the DRAM module 104, determining 402 that a single row 106 is mapped to a reserved row 108, storing 404 the data stored in the reserved row 108 in the single row 106, and updating 406 the mapping table 112 to remove the mapping of the single row 106 to the reserved row 108.

[0043] The method of FIG. 5 differs from FIG. 4 in that it includes maintaining 502 a counter 116 indicative of the number of rows 106 mapped to the reserved rows 108. For example, the memory controller 102 maintains, for each reserved row 108, a corresponding counter 116 indicative of the number of merge rows 106 mapped to the reserved row 108. For example, when an entry in the mapping table 112 is created that maps a merge row 106 to a reserved row 108, the memory controller 102 increments the counter 116 corresponding to the reserved row 108. When the merge row 106 stops being mapped to the reserved row 108 (e.g., in response to a write on the merge row 106), the counter 116 corresponding to the reserved row 108 is decremented. In some embodiments, the counters 116 are maintained in the same data structure as the checksums 110 of each reserved row 108. For example, each entry in the data structure corresponds to a reserved row 108. Each entry in the data structure indicates, for a corresponding reservation row 108, a checksum 110 of the data stored in the reservation row 108 (if any) and a counter 116 indicating the number of merge rows 106 mapped to the reservation row 108.

[0044] The method of Figure 5 further differs from Figure 4 in that determining 402 that the single row 106 is mapped to the reserved row 108 includes determining 504 that the single row 106 is mapped to the reserved row 108 based on the counter 116. For example, the memory controller 102 accesses the counter 116 of the reserved row 108 and determines that the counter 116 is set to "1."

[0045] For further explanation, Figure 6 illustrates a method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure. The method of Figure 6 is similar to that of Figure 2 in that it includes identifying 202 multiple rows that store identical data, storing 204 data in a mapping table 112 that maps one or more rows 106 of the multiple rows to another row, and excluding 206 one or more rows 106 from refreshing the DRAM module 104.

[0046] FIG. 6 differs from FIG. 2 in that it includes maintaining 602 (e.g., by the memory controller 102) a mapping table cache 118 that stores a portion of the mapping table 112. The mapping table cache 118 stores the most recently or most frequently used mappings to the mapping table 112. For example, the memory controller 102 accesses the mapping table 112 to determine whether a row 106 targeted by a read or write request is mapped to another row (e.g., the representative row or the reserved row 108). If the memory controller 102 finds a match in the mapping table 112, the memory controller 102 updates the mapping table cache 118 to include the matching mapping table 112 entry. Thus, the read or write request is first compared to the entries in the mapping table cache 118 before accessing the mapping table 112, reducing the number of accesses to the DRAM module 104 required to determine whether a particular row 106 has been merged and mapped to another row.

[0047] For further explanation, Figure 7 illustrates a method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure. The method of Figure 7 is similar to Figure 2 in that it includes identifying 202 multiple rows that store identical data, storing 204 data in a mapping table 112 that maps one or more rows 106 of the multiple rows to another row, and excluding 206 one or more rows 106 from refreshing the DRAM module 104.

[0048] 2 in that it includes receiving 702 (e.g., by the memory controller 102) a read request for a row 106 in one or more rows 106 (e.g., a merged row 106 that was previously mapped to another row and excluded from refresh). For example, assume that rows 106A, 106B, and 106C have been identified 202 as storing identical data and mapped to the reserved row 108. Further assume that the read request is for data stored in row 106A. Once the data stored in row 106A is excluded from refresh, the data stored in row 106A is subject to a loss of integrity.

[0049] The method of FIG. 7 further includes determining 704 that row 106 is mapped to other rows based on the mapping table 112. Continuing with the above example, the memory controller 102 determines that row 106A is mapped to its corresponding reserved row 108 based on the mapping table 112. For example, in some embodiments, the memory controller 102 accesses the mapping table 112 from the DRAM module 104 and identifies an entry in the mapping table 112 for row 106A. The entry indicates the corresponding reserved row 108. In other embodiments, the memory controller 102 first accesses the mapping table cache 118 to determine whether an entry for row 106A is stored. If an entry is stored, the memory controller identifies the corresponding reserved row 108 based on the entry in the mapping table cache 118. If no entry is found for row 108A, the memory controller 102 accesses the mapping table 112 from the DRAM module 104 as described above.

[0050] 7 further includes providing 706 data stored in the other row (e.g., the row identified in mapping table 112 to which merge row 106 is mapped) in response to the read request. For example, memory controller 102 reads from the row identified in mapping table 112 and provides the requested data in response to the read request. Thus, a read request targeting merge row 106 accordingly receives data stored in the row identified in mapping table 112 as the target of the mapping of merge row 106.

[0051] For further explanation, Figure 8 illustrates a method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure. The method of Figure 8 is similar to that of Figure 2 in that it includes identifying 202 multiple rows that store identical data, storing 204 data in a mapping table 112 that maps one or more rows 106 of the multiple rows to another row, and excluding 206 one or more rows 106 from refreshing the DRAM module 104.

[0052] Assume that one or more rows 106 are mapped to the reserved row 108. Figure 8 differs from Figure 2 in that it includes receiving 802 a write request for any row 106 of the one or more rows 106 (e.g., a merge row 106 mapped to the reserved row 108 and excluded from refresh). For example, assume that rows 106A, 106B, and 106C have been identified 202 as storing identical data and mapped to the reserved row 108. Further assume that a read request is for data stored in row 106A. If the data stored in row 106A is excluded from refresh, then the data stored in row 106A is susceptible to loss of integrity.

[0053] The method of FIG. 8 also includes storing 804 the data stored in the reserved row 108 in one of the one or more rows 106. Continuing with the above example, the memory controller 102 determines that row 106A is mapped to its corresponding reserved row 108 based on the mapping table 112. For example, in some embodiments, the memory controller 102 accesses the mapping table 112 from the DRAM module 104 and identifies an entry in the mapping table 112 for row 106A. The entry indicates the corresponding reserved row 108. In other embodiments, the memory controller 102 first accesses the mapping table cache 118 to determine whether an entry for row 106A is stored. If an entry is stored, the memory controller identifies the corresponding reserved row 108 based on the entry in the mapping table cache 118. If an entry is not found for row 108A, the memory controller 102 accesses the mapping table 112 from the DRAM module 104 as described above. The memory controller 102 then loads the data stored in the identified reserved row 108 and stores this data in row A.

[0054] 8 also includes executing 806 the write request. For example, the memory controller 102 issues the write request to the DRAM module 104 for application. Thus, any operation of the write request is applied to the row 106 indicated in the write request that stores data for the corresponding reserved row 108.

[0055] 8 also includes updating 808 the mapping table 112 to remove the mapping of row 106 to reserved row 108. Because row 106 has been written to, it no longer stores identical data as reserved row 108. Thus, the mapping of row 106 to reserved row 108 is removed from the mapping table 112. If a mapping table cache 118 is implemented, the mapping of row 106 to reserved row 108 is also removed from the mapping table cache 118.

[0056] In view of the above discussion, the reader will appreciate that hardware assisted DRAM row merging includes the following advantages: · Inhibiting refresh of refresh selected rows with identical data improves manufacturing of computing systems by reducing the energy required to perform DRAM refresh. Improved performance of computing systems due to reduced computational overhead required compared to software-based solutions for data deduplication in DRAM.

[0057] The advantages and features of the present disclosure may be further explained by the following description. 1. A method for hardware-assisted dynamic random access memory (DRAM) row merging, comprising: a memory controller identifying, within a DRAM module, multiple rows that store identical data; storing data in a mapping table that maps one or more of the multiple rows to another row; and excluding one or more rows from refreshing the DRAM module. 2. The method of claim 1, further comprising updating a bitmap to indicate that one or more rows are excluded from refresh, and excluding one or more rows from refresh comprises a memory controller providing the bitmap to a dynamic random access memory (DRAM) module. 3. A method according to any one of claims 1 to 2, wherein the other line includes any one of the multiple lines. 4. The method of any of claims 1-3, wherein the separate row includes a reserved row included in one or more reserved rows of a dynamic random access memory (DRAM) module. 5. A method as described in any of claims 1 to 4, further comprising determining that the single row is mapped to the reserved row, storing data stored in the reserved row in the single row, and updating the mapping table to remove the mapping of the single row to the reserved row. 6. The method of any of claims 1 to 5, further comprising maintaining a counter indicating the number of rows mapped to the reservation row, and determining that a single row is mapped to the reservation row based on the counter. 7. The method of any of claims 1 to 6, further comprising maintaining a mapping table cache that stores a portion of the mapping table. 8. A method as described in any of claims 1 to 7, further comprising receiving a read request for any one of the one or more rows, determining based on a mapping table that the row is mapped to another row, and providing data stored in the other row in response to the read request. 9. A method as described in any of claims 1 to 8, further comprising: receiving a write request for a particular row of the one or more rows; storing data stored in the reserved row in the particular row of the one or more rows; and updating the mapping table to remove mapping of the particular row to the reserved row. 10. A memory controller for hardware-assisted dynamic random access memory (DRAM) row merging, the memory controller being configured to perform steps including: identifying multiple rows within a DRAM module that store identical data; storing data in a mapping table that maps one or more of the multiple rows to another row; and excluding one or more rows from refreshing the DRAM module. 11. The memory controller of claim 10, wherein the process further includes updating a bitmap to indicate that one or more rows are excluded from refresh, and excluding one or more rows from refresh includes the memory controller providing the bitmap to the DRAM module. 12. The memory controller according to any one of claims 10 to 11, wherein the other row includes any one of the multiple rows. 13. The memory controller of any of claims 10-12, wherein the separate row includes a reserved row included in one or more reserved rows of a dynamic random access memory (DRAM) module. 14. A memory controller as described in any of claims 10 to 13, wherein the steps include determining that the single row is mapped to the reserved row, storing data stored in the reserved row in the single row, and updating the mapping table to remove the mapping of the single row to the reserved row. 15. The memory controller of any of claims 10-14, wherein the steps further include maintaining a counter indicating the number of rows mapped to the reserved row, and determining that a single row is mapped to the reserved row is based on the counter. 16. The memory controller of any of statements 10-15, wherein the steps further include maintaining a mapping table cache that stores a portion of the mapping table. 17. The controller of any of statements 10-16, wherein the steps further include receiving a read request for any one of the one or more rows, determining that the row is mapped to another row based on the mapping table, and providing data stored in the other row in response to the read request. 18. A controller as described in any of statements 10-17, wherein the steps further include receiving a write request for a particular row of the one or more rows, storing data stored in the reserved row to the particular row of the one or more rows, and updating the mapping table to remove mapping of the particular row to the reserved row. 19. An apparatus for hardware assisted dynamic random access memory (DRAM) row merging, the apparatus comprising: a memory controller configured to perform steps including identifying a plurality of rows within a DRAM module that store identical data; storing data in a mapping table that maps one or more of the plurality of rows to another row; and excluding one or more rows from refreshing the DRAM module. 20. The apparatus of claim 19, wherein the process further includes updating a bitmap to indicate that one or more rows are excluded from refresh, and excluding one or more rows from refresh includes the memory controller providing the bitmap to the DRAM module.

[0058] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a particular logical function. In some alternative implementations, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, as well as combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs a particular function or act, or a combination of dedicated hardware and computer instructions.

[0059] It will be understood from the above description that modifications and changes may be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. A method for hardware assisted dynamic random access memory (DRAM) row merging, comprising: A memory controller identifying multiple rows in the DRAM module that store identical data; storing data mapping one or more of the plurality of rows to another row in a mapping table; and excluding the one or more rows from refreshing the DRAM module. method.

2. updating a bitmap to indicate that the one or more rows are excluded from the refresh; excluding the one or more rows from the refresh includes the memory controller providing the bitmap to the dynamic random access memory (DRAM) module.

2. The method of claim 1.

3. The another row includes any one of the plurality of rows.

2. The method of claim 1.

4. the other row includes a reserved row included in one or more reserved rows of the dynamic random access memory (DRAM) module; 2. The method of claim 1.

5. determining that a single row is mapped to the reserved row; storing the data stored in the reserved row in the single row; updating the mapping table to remove the mapping of the single row to the reservation row. The method of claim 4.

6. maintaining a counter indicating a number of rows that are mapped to the reserved row, and determining that the single row is mapped to the reserved row is based on the counter. The method of claim 5.

7. and maintaining a mapping table cache that stores a portion of the mapping table.

2. The method of claim 1.

8. receiving a read request for a row of the one or more rows; determining, based on the mapping table, that the any row is mapped to another row; and providing the data stored in the other row in response to the read request.

2. The method of claim 1.

9. receiving a write request for a particular row of the one or more rows; storing the data stored in the reserved row in the particular row of the one or more rows; executing the write request; updating the mapping table to remove the mapping of the particular row to the reservation row. The method of claim 4.

10. 1. An apparatus for hardware assisted dynamic random access memory (DRAM) row merging, comprising: A memory controller is provided. The memory controller includes: Identifying a plurality of rows within a DRAM module which store identical data; storing data mapping one or more of the plurality of rows to another row in a mapping table; excluding the one or more rows from refreshing the DRAM module; [0023] Device.

11. The memory controller includes: configured to update a bitmap such that the one or more rows are excluded from the refresh; excluding the one or more rows from the refresh includes the memory controller providing the bitmap to the DRAM modules.

11. The apparatus of claim 10.

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