Flux-tunable qubit architecture for multiplexing qubit control lines

Abstract

A method for multiplexing control lines of a qubit array includes applying a qubit control signal to a single drive line. The qubit control signal is split on the single drive line between a first resonator and a second resonator. The first drive line is operable to control a first qubit, a second tunable qubit, a third qubit, and a fourth tunable qubit. The first qubit is coupled to the second tunable qubit by the first resonator. The third qubit is coupled to the fourth tunable qubit by the second resonator. Variations in the amplitude of the qubit control signal are compensated for by adjusting the frequency of the second tunable qubit and the frequency of the fourth tunable qubit.

Description

[Technical Field]

[0001] This disclosure relates, in general terms, to superconducting devices, and more specifically, to qubit control. [Background technology]

[0002] Superconducting quantum computing is the implementation of quantum computers in superconducting electronic circuits. Quantum computing studies the application of quantum phenomena for information processing and communication. Various models of quantum computing exist, the most common of which involve the concepts of qubits and quantum gates. A qubit is a generalization of a bit with two possible states, but can be a quantum superposition of both states. A quantum gate is a generalization of a logic gate, however, a quantum gate describes the transformations that one or more qubits will encounter after the gate is applied to them, given their initial states. Various quantum phenomena such as superposition and entanglement have no analogues in the world of classical computing and therefore may involve special structures, techniques, and materials. [Overview of the project]

[0003] According to various embodiments, methods and systems are provided for multiplexing control lines of a qubit array. A qubit control signal is applied to a single drive line. The qubit control signal on the single drive line is split between a first resonator and a second resonator, where the first drive line is operable to control a first qubit, a second adjustable qubit, a third qubit, and a fourth adjustable qubit. The first qubit is coupled to the second adjustable qubit by the first resonator. The third qubit is coupled to the fourth adjustable qubit by the second resonator. Variations in the amplitude of the qubit control signal are compensated by adjusting the frequency of the second adjustable qubit or the frequency of the fourth adjustable qubit, or a combination thereof. Failures may be, without limitation, variations in the frequency of the first qubit or variations in the pulse amplitude, or a combination thereof.

[0004] In one embodiment, the control line is configured to drive a resonator-induced phase (RIP) gate, where the first resonator is a RIP resonator and the second resonator is a RIP resonator.

[0005] In one embodiment, calibration of the RIP gate between the first qubit and the second qubit is provided by maximizing the fidelity of the gate while varying the RIP frequency.

[0006] In one embodiment, the second and fourth tunable qubits are flux-tunable Ancilla qubits that can operate to correct the frequency difference between the corresponding RIP resonators by changing a quantum state-dependent frequency shift χ on the corresponding RIP resonators of the first and second RIP resonators. The RIP resonator frequencies may depend on quantum states such as the ancilla and data qubits. If both qubits are in the ground state, then the RIP resonator frequencies will not shift. If one or both qubits are in an excited state, the RIP resonator frequencies will shift by χ.

[0007] The magnitude of the chi-shift depends on the different frequencies between the anciracubit and the RIP resonator.

[0008] In one embodiment, the magnitude of the frequency shift χ of the first qubit and the second adjustable qubit depends on the frequency difference between the second adjustable qubit and the first qubit.

[0009] In one embodiment, a second variation in the amplitude of the qubit control signal is compensated by adjusting the frequency of the fourth adjustable qubit.

[0010] In one embodiment, the qubit control signal is a radio frequency (RF) pulse having a fixed drive amplitude and a fixed frequency.

[0011] In one embodiment, the splitting step is performed by a resistive power splitter, a reactive power splitter, or a multiport coupler.

[0012] In one embodiment, the splitting step is performed by a Wilkinson-type resistive power splitter, a Wi-Power splitter, or a delta power splitter.

[0013] In one embodiment, error correction is performed on the surface code architecture by cyclically performing at least one of X - parity and Z - parity.

[0014] In one embodiment, the first resonator is detuned from the second resonator. The drive frequency of the qubit control signal is shifted to a frequency at which the gate rates for the first qubit and the second adjustable qubit are the same as the gate rates for the third qubit and the fourth adjustable qubit.

[0015] According to one embodiment, a quantum structure includes a first qubit, a second adjustable qubit coupled to the first qubit via a first resonator, a third qubit, a fourth adjustable qubit coupled to the third qubit via a second resonator, and a fixed drive line coupled to the first resonator and the second resonator. The second adjustable qubit is configured to be adjusted to compensate for variations in the amplitude of the qubit control signal of the fixed drive line.

[0016] In one embodiment, the control line drives a resonator - induced phase (RIP) gate by carrying a signal to the resonator. The first resonator is a RIP resonator. The second resonator is a RIP resonator.

[0017] In one embodiment, the second and fourth adjustable qubits are flux - adjustable ancilla qubits configured to correct the frequency shift χ that is dependent on the quantum state of their corresponding RIP resonators.

[0018] In one embodiment, the correction of χ for at least one of the first or third resonators is operable to mitigate impairments in the pulse amplitude of the qubit control signal.

[0019] In one embodiment, the adjustment of the frequency of the fourth adjustable qubit is operable to compensate for a second variation in the amplitude of the qubit control signal.

[0020] In one embodiment, the qubit control signal is a radio frequency (RF) pulse having a fixed drive amplitude and a fixed frequency.

[0021] In one embodiment, the splitting step is performed by a resistive power splitter, a reactive power splitter, or a multiport coupler.

[0022] In one embodiment, there exists an RF splitter configured to split the qubit control signal on the fixed single drive line.

[0023] According to one embodiment, the quantum structure includes a first qubit, a second tunable qubit coupled to the first qubit via a first resonator, a third qubit, a fourth tunable qubit coupled to the third qubit via a second resonator, and a shared drive line coupled to the first and second resonators. The first resonator is detuned from the second resonator. The drive frequency of the qubit control signal is at a frequency where the gate rates for the first qubit and the second tunable qubit are the same as the gate rates for the third qubit and the tunable fourth qubit. Detuning of the first resonator from the second resonator can be performed by fabricating resonators having different dimensions.

[0024] These and other features will become apparent from the following detailed description of their exemplary embodiments, which will be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0025] The drawings are illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or as substitutes. Details that may be obvious or unnecessary may be omitted for space saving or for more effective illustration. Some embodiments may be carried out with additional configurations or steps, or combinations thereof, without all of the components or steps shown. If the same number appears in different drawings, it refers to the same or similar component or step.

[0026] [Figure 1A] This shows an exemplary architecture of a quantum computing system consistent with an exemplary embodiment.

[0027] [Figure 1B] This provides an exemplary graphic representation of the number of wires used in a quantum system with respect to logical qubit size, consistent with exemplary embodiments.

[0028] [Figure 2] The basic elements of a flux-adjustable qubit architecture, consistent with an exemplary embodiment, are shown.

[0029] [Figure 3] An enlarged view of the basic elements of Figure 2 is provided, consistent with the exemplary embodiment.

[0030] [Figure 4A] The changes in θZZ are shown as functions of the changes in χ and the changes in ε0, respectively.

[0031] [Figure 4B] This shows the change in χ as a function of the change in detuning Δ.

[0032] [Figure 5] A conceptual diagram illustrating how the cubit is adjusted is provided, consistent with an exemplary embodiment.

[0033] [Figure 6A] A diagram is provided relating to the use of RIP frequency as a knob for multiple access to multiple qubits, consistent with an exemplary embodiment. [Figure 6B] A diagram is provided relating to the use of RIP frequency as a knob for multiple access to multiple qubits, consistent with an exemplary embodiment.

[0034] [Figure 7] Figure 6A shows the gate rate versus drive frequency of an example consistent with an exemplary embodiment.

[0035] [Figure 8] This provides an overview of an exemplary architecture having 17 qubits, 8 of which are adjustable and 9 of which are fixed, consistent with exemplary embodiments.

[0036] [Figure 9] A multiplexed RIP bus is shown driving a first entangling gate consistent with an exemplary embodiment.

[0037] [Figure 10] A multiplexed RIP bus driving a second entangling gate, consistent with an exemplary embodiment, is shown.

[0038] [Figure 11] A multiplexed RIP bus driving a third entangling gate, consistent with an exemplary embodiment, is shown.

[0039] [Figure 12] A multiplexed RIP bus driving a fourth entangling gate is shown, consistent with an exemplary embodiment.

[0040] [Figure 13A] This provides a different method for performing a power split of a qubit control signal, consistent with exemplary embodiments. [Figure 13B] This provides a different method for performing a power split of a qubit control signal, consistent with exemplary embodiments. [Figure 13C] This provides a different method for performing a power split of a qubit control signal, consistent with exemplary embodiments. [Figure 13D] This provides a different method for performing a power split of a qubit control signal, consistent with exemplary embodiments.

[0041] [Figure 14] We present an exemplary process for reading a signal from a quantum processor, consistent with an exemplary embodiment.

[0042] [Figure 15] This provides an illustration of a functional block diagram of a computer hardware platform that can be used to implement a specifically configured computing device capable of hosting a qubit control engine, consistent with an exemplary embodiment. [Modes for carrying out the invention]

[0043] [overview] In the following detailed explanation, many specific details are provided as examples to provide a complete understanding of the relevant teachings. However, it should be clear that these teachings can be carried out without such details. In other instances, well-known methods, procedures, components, or circuits or combinations thereof are described at a relatively high level without detail, in order to avoid unnecessarily obscuring the nature of these teachings.

[0044] In the discussion of this technology, this may be helpful in explaining various important terms. As used herein, a qubit represents a quantum bit, and a quantum gate is an operation performed on a qubit, such as controlling the superpositioning between two qubits.

[0045] As used herein, a resonator-induced phase (RIP) gate is a multi-qubit entangling gate. This is suitable for quantum computation in large-scale architectures by allowing a high degree of flexibility in qubit frequencies. The advantage of RIP gates is their ability to couple qubits even when they are substantially detuned from one another. Accordingly, RIP gates can overcome challenges arising from constraints on the frequency arrangement of qubits that can hinder scalability to larger quantum architectures. A RIP gate is a CZ gate that uses a strong coupling between qubits and a resonator in a quantum system. This can be achieved by applying a detuned pulsed microwave drive to a shared bus cavity.

[0046] As used herein, the term "C-phase" refers to a controlled phase gate, where the Z rotation of one qubit is defined by the state of another qubit. ZZ refers to a state-dependent qubit interaction that can be used to form a C-phase gate.

[0047] As used herein, the term "flux-tunable" refers to a device whose frequency depends on magnetic flux.

[0048] As used herein, an ancila qubit relates to a qubit that can be used in error correction protocols to store entangled quantum states. An ancila can be used in parity circuits to extract the parity of an entangled state. A parity circuit relates to a quantum circuit used to determine the parity of an entangled state of a data qubit.

[0049] As used herein, a transmon is a type of superconducting qubit, where the charging energy Ec is much smaller than the Josephson energy Ej.

[0050] As used herein, a driveline refers to a qubit control line that carries signals to a qubit. The term "multiplexing" includes the meaning of a single control line capable of carrying signals to multiple qubits.

[0051] Terms such as “first,” “second,” and “third” may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the terms “and / or” include all any combination of one or more of the relevant enumerated items.

[0052] Exemplary embodiments are described herein with reference to schematic drawings of idealized or simplified embodiments (and intermediate structures). Therefore, variations from the illustrated shapes may be expected, for example, as a result of manufacturing techniques, tolerances, or combinations thereof. Accordingly, the areas shown in the figures are essentially schematic, and their shapes do not necessarily represent, nor do they limit, the actual shapes of the areas of the device.

[0053] It should be understood that other embodiments may be used, and structural or logical modifications may be made without departing from the spirit and scope defined by the claims. The description of embodiments is not limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0054] As used herein, certain terms such as “lossless,” “superconductor,” “superconducting,” and “absolute zero” are used to describe what may be considered idealized behavior, which may not be exactly ideal but are intended to cover functionality that is within acceptable error limits for a given application. For example, certain levels of loss or tolerance may be acceptable, and consequently, the resulting materials and structures may still be described by these “idealized” terms.

[0055] This disclosure relates, in general, to efficient interaction with superconducting devices, more specifically with lattice arrays containing multiple qubits. The electromagnetic energy associated with a qubit can be stored within a so-called Josephson junction, within capacitive and inductive elements used to form the qubit. In one example, to read out a qubit state, a microwave signal is applied to a microwave readout cavity coupled to the qubit at the cavity frequency. The transmitted (or reflected) microwave signal passes through several thermal isolation stages and a low-noise amplifier used to block or reduce noise and improve the signal-to-noise ratio. Alternatively or in addition, a microwave signal (e.g., a pulse) can be used to entangle one or more qubits. Much of this process is performed in a low-temperature environment (e.g., a cryogenic chamber), while the microwave signal of the qubit is ultimately measured at room temperature. The amplitude or phase, or a combination thereof, of the returned / output microwave signal carries information about the qubit state, such as whether the qubit has dissipated phase to the ground state or an excited state. The microwave signals carrying quantum information about qubit states are typically weak (e.g., only a few microwave photons). To measure these weak signals using room-temperature electronic equipment (i.e., outside a refrigerated environment), low-noise quantum-limited amplifiers (QLAs), such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs), can be used as preamplifiers (i.e., first amplification steps) at the output of a quantum system to boost the quantum signal, while adding a minimum amount of noise defined by quantum mechanics to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, Josephson mixers, Josephson isolators, and certain Josephson microwave components that use Josephson mixers, such as Josephson amplifiers or Josephson circulators, can be used in scalable quantum processors.

[0056] A qubit system may include one or more readout resonators coupled to the qubit. The readout resonator may be a transmission line that either includes a capacitive connection to ground on one side and is short-circuited to ground on the other side (e.g., a quarter-wavelength resonator), or it may have a capacitive connection to ground, such as a half-wavelength resonator, which results in vibrations in the transmission line, the resonant frequency of which is close to the frequency of the qubit. For example, the readout resonator affects a pulse coming from a control / measurement instrument at the readout resonator frequency. This pulse causes decoherence in the qubit and collapses it to a "1" or "0" state, thereby acting as a measurement that imparts a phase shift to the measurement pulse.

[0057] Between qubits, there may be a coupling resonator, sometimes referred to herein as a coupler resonator or RIP bus, which allows different qubits to be coupled together to realize quantum logic gates. Such a coupling resonator is typically structurally similar to a readout resonator; however, more complex designs are possible. When qubits are implemented as transmons, each side of the coupling resonator is coupled (e.g., capacitively or inductively) to the corresponding qubit by being appropriately close to the qubit (e.g., its capacitor). Since each side of the coupling resonator has a coupling with its respective different qubit, two qubits are coupled together through the coupling resonator (e.g., RIP bus). Thus, there is an interdependence between the states of the coupled qubits, allowing the coupling resonator to use the state of one qubit to control the state of another. Entanglement occurs when the interaction between two qubits is such that the two states cannot be specified independently, but only in relation to the entire system. In this way, the states of the two cubits are linked together such that a measurement of one cubit disrupts the state of the other cubit.

[0058] The ability to contain more qubits is crucial to realizing the potential of quantum computers. Generally, performance increases as temperature decreases, for example by reducing the remaining thermally excited qubit population and decreasing the thermal extension of qubit transition frequencies. Accordingly, the lower the temperature, the better for quantum processors.

[0059] To enhance the computational power and reliability of quantum computers, improvements along two main dimensions are deemed necessary. The first is the qubit count itself. The more qubits there are in a quantum processor, the more states can be manipulated and stored in principle. The second is a low error rate, which relates to accurately manipulating qubit states and performing a series of operations that provide consistent results, not just unreliable data. Therefore, to improve the fault tolerance of quantum computers, a large number of physical qubits should be used to store logical qubits. In this way, local information is delocalized, and as a result, quantum computers become less susceptible to the effects of local errors and the performance of measurements in the equanimatic basis of qubits, similar to parity checks in classical computers, thereby leading to qubits that are more fault-tolerant.

[0060] In one embodiment, the teachings herein are based on the applicant's insight that directly applying conventional integrated circuit techniques for interacting with computing elements to superconducting quantum circuits may not be effective due to unique challenges presented by quantum circuits that are not presented in classical computing architectures. Accordingly, embodiments of the herein further are based on the recognition that quantum circuit-specific problems were taken into consideration when evaluating the applicability of conventional integrated circuit techniques for constructing superconducting quantum circuits, in particular for selecting methods and architectures used to efficiently interact with qubits. [Example architecture]

[0061] Figure 1A shows an exemplary architecture 100 of a quantum computing system consistent with an exemplary embodiment. Architecture 100 includes a quantum processor 112 containing a plurality of qubits 114. The quantum processor 112 is housed in a refrigeration device 110, which may be a dilution refrigeration device. A dilution refrigeration device is a cryogenic device that typically provides continuous cooling to a temperature of around 10 mK. Most of the physical volume of architecture 100 is due to the large size of the refrigeration device 110. To reach a temperature near absolute zero in which the system operates, the refrigeration device 110 may use liquid helium as a coolant.

[0062] Outside the refrigeration unit 110, there is a measurement and control unit 130. The measurement and control unit 130 can communicate with a quantum processor through an opening 116, which may be referred to as the bulkhead of the dilution refrigeration unit 110, and further forms a sealed enclosure that separates the ambient atmospheric pressure from the vacuum pressure of the cryostat under operation. A practical challenge in known refrigeration devices housing cubits 114 is that the number of cubits that can be housed in the refrigeration unit is limited due to the number of wires between the measurement and control unit 130 and the cubits 114 that are measured / controlled by it.

[0063] As the number of qubits 114 increases, for example, to hundreds, thousands, or larger, the opening 116 may not be large enough to accommodate all the lines 120 supporting the quantum processor 112 within the dilution refrigerator 110. Alternatively, access to the vacuum environment of the dilution refrigerator 110 is limited to the number of connectors that can be fitted through the bulkhead opening 116. Known architectures in which the bus is driven to generate two qubit gates typically include twice as many control lines as the cross-resonance gate discussed herein, thereby making higher scaling impractical.

[0064] Accordingly, in one embodiment, provided herein is an architecture that substantially reduces the number of lines between a measurement and control unit 130 housed in a refrigerated environment and a quantum processor 112. Multiple qubits 114 of the quantum processor 112 may be accessed by multiplexing drive lines, which reduces the number of qubit control lines for executing error correction protocols. The concepts discussed herein provide an architecture and method for minimizing the number of drive lines used to control the quantum processor 112. In one embodiment, two qubits are coupled together by a resonator. Driving the resonator with an RF pulse drives the two qubit C-phase gates. One of these two qubits is flux-tunable, which facilitates tuning of the qubit frequency and aligns that frequency with a radio frequency (RF) pulse driving a two-qubit gate.

[0065] As described above, the teachings herein facilitate a substantial reduction in the number of wires used between the refrigerated environment 110 and the measuring and control equipment 130. In this regard, Figure 1B provides an exemplary graphic representation of the number of wires used in a quantum system with respect to logical qubit size, consistent with an exemplary embodiment. A drawback of architectures in which buses include drive tones (e.g., RIP) is the existence of extra drive lines used for each bus, represented by dashed lines in Figure 1B. For example, the number of bus lines for a surface code of distance d is given by the following formula:

[0066]

number

[0067] Accordingly, for a 1000-cubit system d~23, the total number of lines is >3000 in the case of a conventional system. In contrast, by using an ancilla based on the teachings herein, additional lines are provided for the degree of adjustment, but the total number of RIP lines, represented by dashed lines in Figure 1B, is only four.

[0068] In one embodiment, the calculation of the number of RIP lines is based on the size of the logical qubit d. The following equations provide several relationships for different parameters.

[0069] The number of physical cubits is

[0070]

number

[0071] The number of ancilacbits is

[0072]

number

[0073] The number of data qubits is

[0074]

number

[0075] The number of bus connections is

[0076]

number

[0077] In practice, there are many more bus connections, and each bus includes its own RIP drive line. In this exemplary architecture, the total number of bus connections is reduced to 4. However, the number of ancilla drive lines doubles. Each ancilla cubit includes a single cubit RF drive line, which includes a drive line for flux adjustment. There are significantly more bus connections than ancilla cubits.

[0078] The number after multiplexing the drive lines is

[0079]

number

[0080] Therefore, even after doubling the number of ancilla lines, the number of drive lines is still fewer than when there is one drive line per bus. By using the teachings herein, there is one drive line per cubit, represented by the solid lines in Figure 1B, thereby substantially reducing the number of lines to the refrigerated environment.

[0081] In one embodiment, the concepts discussed herein are scalable in that the architecture enables the division of an RF tone, which may be referred to herein as a flux pulse or qubit control signal, and the driving of multiple resonators using the same RF tone. Variations in the RF tone can be mitigated by adjusting the flux-tunable qubit frequency. These concepts are discussed in more detail below. [Example Basic Elements]

[0082] Herein, we refer to Figure 2, which shows the basic elements of a flux-adjustable qubit architecture consistent with an exemplary embodiment. In particular, Figure 2 shows a fixed-frequency qubit 202, as well as an adjustable ancilla qubit 204, which may be referred to herein simply as an adjustable qubit. Figure 2 also shows a fixed-frequency qubit Q coupled together by a RIP bus 214 having a first frequency f1. d 211 and adjustable Ancilla Q tune The base flux adjustable cubit element 206, including 213, is shown. First cubit Q d and the second adjustable cubit Q tune This can be entangled by pulse 220. For example, a fixed-frequency RIP (e.g., radio frequency (RF)) pulse 220 can be entangled via a RIP bus 214 having a first frequency f1, with a fixed-frequency qubit Q d (211) and adjustable cubit Q tune (213) can drive two qubit gates. In this way, the first qubit Q d 211 and the second adjustable cubit Q tune 213 can be entangled. The theory for RIP devices can be better understood by considering the following equation, which assumes that the x of each qubit is the same.

[0083]

number

number

number

number

[0084] The applicant has determined that two of these basic elements 206 can be combined to provide a multiplexed underlying flux-adjustable qubit element 208. The adjustable qubit Q tune (e.g., 221 or 219 or a combination thereof) is an adjustable ancilla. Variations in the RIP pulse frequency or the frequency of the fixed-frequency qubit Q d (e.g., 209) or a combination thereof can be compensated for the adjustable qubit Q tune (e.g., 221). Stated differently, the adjustable qubit Q tune can be adjusted to calibrate the gate to the fixed RIP pulse 222.

[0085] In the proposed architecture of the multiplexed underlying flux-adjustable element 208, the flux-adjustable qubit Q tune (e.g., 221 or 219 or a combination thereof) can be used to vary the χ of Equation 1 above by applying a flux pulse 222 to the ancilla qubit Q tune 221 or 219 or a combination thereof. This adjusts the ancilla qubit Q tune (e.g., 221) to obtain a specific desired frequency difference between the two qubits. This sequence changes the χ of Equation 1 above and enables calibration of the fixed drive amplitude

Number

[0086] The multiplexed base flux adjustable element 208 is less susceptible to various types of interference caused by the Qtune's flux adjustment degree. An example of interference mitigated by the multiplexed base flux adjustable element 208 is RIP drive.

number

[0087] Here, we refer to Figure 3, which provides an enlarged view of the basic elements of Figure 2, consistent with an exemplary embodiment. The base flux adjustable cubit element 206 and the multiplexed base flux adjustable cubit element 308 are repeated in Figure 3 as reference to a structure extended thereon to provide multiplex functionality. More specifically, Figure 3 shows an exemplary element for a single parity check 306, which includes a plurality of fixed cubits 322 to 328 coupled to a common adjustable cubit 310. In structure 306, each fixed frequency cubit (e.g., 322 to 328) is coupled to the adjustable cubit 310 via a RIP bus (sometimes referred to herein as a coupled resonator) having different frequencies (e.g., f1 to f4). For example, cubit Q d 322 is coupled to a RIP bus having a first frequency f1, and qubit Q d 324 is coupled to a RIP bus having a second frequency f2, and qubit Q d 326 is coupled to a RIP bus having a third frequency f3, and qubit Q d 328 is coupled to a RIP bus having a fourth frequency f4. In one embodiment, the difference between the frequencies of RIP buses f1 to f4 is 100 MHz or greater.

[0088] Cubit Q dExecute the gate with 322, then the qubit Q d The gate with 324 is retuned to execute, and then the cubit Q d The tunable qubit 310 can be sequentially tuned so that it is readjusted to execute a gate having 328, and so on. Although four fixed-frequency qubit devices are shown in basic element 306 as an example, any number of fixed-frequency qubits can be tuned to the tunable qubit Q tune It will be understood that these can be coupled together, each having a RIP bus of a different frequency. The basic elements for a single parity check 306 can be extended to multiple parity checks while maintaining a certain number of RIP buses. In this regard, Figure 3 shows an enlarged view of the multiplexing elements for multiple parity checks 310, where a further fixed-frequency qubit Q d 330 and Q d 332 and shared Q tune It is included in the array via 352. Fixed frequency qubit Q d 324 and Q d Both 328 and Q are adjustable cubic Q. tune 310 and Q tune It is shared (e.g., accessible) by both 352 and 352. Accordingly, multiple qubits having the same qubit frequency can be accessed simultaneously. For example, qubits coupled to a RIP bus having a first frequency f1 can all be accessed simultaneously because they share the same RF line, thereby substantially reducing the number of wires used in a refrigerated environment. For the sake of brevity and to avoid complexity, there are six fixed qubits Q. d and two adjustable cubic Q tune A grid is shown in structure 310. It will be understood that grids of any size are supported by the teachings herein. [Example graph]

[0089] As described above, the teachings herein can mitigate various obstacles. For this purpose, Figures 4A and 4B show how a 1% change in RIP pulse amplitude can be compensated by a 40% change in chi. If the control lines leading to each RIP resonator have slightly different transmission characteristics, then each resonator will encounter different amplitude electric fields. More specifically, Figure 4A shows θ as a function of the change in χ and the change in ε0, respectively. ZZ This shows the changes in the RIP resonator. The frequency of the RIP resonator depends on the quantum states, such as the ancilla and data qubits. If both qubits are in the ground state, then the frequency of the RIP resonator will not shift. If one or both qubits are in an excited state, the RIP resonator frequency will shift by χ. The magnitude of the chi-shift depends on the different frequencies between the anciracubit and the RIP resonator.

[0090] Figure 4B shows the change in χ as a function of the change in detuning Δ. For example, the detuning is changed by only 30%. For example, a flux-tunable cubit is detuned from the frequency of the RIP resonator. This change is related to detuning (i.e., a change in frequency). Accordingly, Figures 4A and 4B provide the operating range.

[0091] Figure 5 provides a conceptual diagram illustrating how the qubit is tuned, consistent with an exemplary embodiment. More specifically, graph 500 shows the normalized tunable qubit frequency. There is a RIP pulse 504 applied during the tuning stage of the tunable qubit 502 that compensates for the faults described herein, including faults from the qubit frequency, resonator, pulse amplitude when divided, etc. The RIP pulse entangles a fixed-frequency qubit having two qubit gates (e.g., an ancilla) applied to perform the tunable qubit. Considering waveform 502, this shows the change in the frequency of the qubit over time. While the qubit is being tuned to a higher frequency, there is a window in which entanglement can be generated by applying the RIP pulse shown in 504. The change in the frequency of the qubit shown in waveform 502 can actually be realized by applying magnetic flux to the tunable qubit. Accordingly, the dashed line between 502 and 500 indicates that these changes in frequency are linked to changes in magnetic flux. [Further embodiments]

[0092] Figures 6A and 6B provide illustrations relating to the use of RIP frequency as a knob for multiple access to multiple qubits, consistent with exemplary embodiments. In Figure 6A, two different RIP resonant buses (i.e., R1 and R2) connecting qubits Q1 through Q4, respectively, are driven using a shared drive line 602. Figure 6B shows that RIP resonators R1 and R2 are intentionally detuned from each other. Thus, they can be driven between the two resonators 610. In other words, a two-qubit gate can be applied simultaneously between Q1 and Q2, and between Q3 and Q4. Thus, an RF pulse can be applied simultaneously to both RIP resonators between the frequencies of the two resonators, thereby accelerating phase accumulation.

[0093] This concept can be better understood by considering Figure 7, which shows the gate rate versus drive frequency in the example of Figure 6A, consistent with an exemplary embodiment. Curve 702 represents qubits Q1 and Q2 in Figure 6A, while curve 704 represents qubits Q3 and Q4 in Figure 6A. For example, curve 702 represents the gate rate, or entanglement generation rate, between qubits Q1 and Q2, and curve 704 represents the gate rate between qubits Q3 and Q4 as a function of the RIP drive frequency applied simultaneously to R1 and R2. Since the gate rate decreases with detuning, by shifting the drive frequency, we can find the configuration represented by point 706 at approximately 7.11 GHz in Figure 7, where the gate rates of Q1 and Q2 are the same as those of Q3 and Q4.

[0094] As shown, the ZZ rate as a function of the drive frequency is plotted on R1 at 6 GHz and on R2 at 6.2 GHz. Around 6.11 GHz, the gate velocities of R1 and R2 are equal. Accordingly, the two gates can be driven in parallel. Note that in scenarios where you want to execute only the gates on Q1 and Q2 (but not Q3 and Q4), you can eliminate the ZZ accumulation on Q3 and Q4 by splitting the gate into two parts and using an echo sequence. As mentioned above, ZZ is C phasegate This represents a state-dependent qubit interaction that can be used to form a qubit. Note that, as used herein, the terms “ZZ rate,” “gate rate,” or “rate of entanglement generation” are all interchangeable. The two-qubit operation to be realized occurs over a period of time. The reciprocal of the time required to complete the operation is the “rate” of the operation. [Example Embodiments]

[0095] Figure 8 shows eight adjustable cubits (represented by cubits annotated with Qa) and nine fixed cubits (Qa), consistent with an exemplary embodiment. dThe diagram provides an overview of an exemplary architecture having 17 qubits (represented by qubits annotated with ). In one embodiment, the architecture of Figure 8 may be used in the context of a surface code type device in which X parity check 802 and Z parity check 804 are performed. For example, X parity check 802 checks the phase, while Z parity check 804 checks the state (e.g., up or down).

[0096] Figure 8 shows an architecture supporting four separate RIP buses f1 to f4. All RIP buses having the same frequency can be driven simultaneously during an error correction cycle. For this purpose, Figures 9 to 12 show different RIP buses that are activated at different stages (e.g., periods) during parity checking. More specifically, Figures 9 to 12 show multiplexed RIP buses driving the first, second, third, and fourth entangling gates, respectively, consistent with an exemplary embodiment. For example, referring to Figure 9, when a RIP pulse 904 of the first frequency f1 is generated on a fixed drive line 906, all RIP buses having the same frequency f1 can be driven simultaneously during an error correction cycle. Similarly, in Figure 10, when a RIP pulse 1004 of the second frequency f2 is generated on another fixed drive line 1006, all RIP buses having the same frequency f2 can be driven simultaneously during an error correction cycle. The operations of the multiplexed RIP buses in Figures 11 and 12, which drive the third and fourth entangling gates respectively, are substantially similar to those in Figures 9 and 10, and are therefore not repeated here for brevity. In one embodiment, the operations illustrated in Figures 9 to 12 may be repeated within a cycle in the context of performing X parity checks and Z parity checks. [Example Power Splitter]

[0097] As described above, the functionality relating to the multiplexing of RIP drive signals includes splitting the qubit control signal into two or more paths. For that purpose, Figures 13A to 13D provide different methods of performing power splitting that can be used to split the qubit control signal. More specifically, Figure 13A shows a 2-way Wilkinson power splitter, Figure 13B shows a 3-way Wilkinson power splitter, and Figure 13C shows an N-way Wilkinson power splitter. In some embodiments, the power is not split immediately in the first stage but in a progressive stage as shown in Figure 13D. [Example processing]

[0098] The above overview of the exemplary architecture may make it useful to consider a higher-level discussion of the exemplary process here. For that purpose, Figure 14 presents an exemplary process relating to reading a signal from a quantum processor. Process 1400 is shown as a set of blocks in a logical flowchart representing a sequence of operations that may be implemented in hardware, software, or a combination thereof. In a software context, the blocks represent computer executable instructions that perform the described operations when executed by one or more processors. Generally, computer executable instructions may include routines, programs, objects, components, and data structures that perform functions or implement abstract data types. In each process, the order in which the operations are described is not intended to be interpreted as limiting, and any number of described blocks may be combined in any order, executed in parallel, or in any combination thereof to implement the process. For the purposes of discussion, the process is described with reference to the architecture of the multiplexed basic elements 208 in Figure 2.

[0099] In block 1402, the qubit control signal 222 is applied to a single drive line 223.

[0100] In block 1404, the qubit control signal on a single drive line is divided between a first resonator 216 and a second resonator 218, where the single drive line 223 is operable to control a first qubit 209, a second adjustable qubit 211, a third qubit 217, and a fourth adjustable qubit 219.

[0101] In block 1406, the first cubit 209 is coupled to the second adjustable cubit 211 by the first resonator 216.

[0102] In block 1408, the third cubit 217 is coupled to the fourth adjustable cubit 219 by the second resonator 218.

[0103] In block 1410, fluctuations in the amplitude of the qubit control signal are compensated by adjusting the frequency of the second adjustable qubit 211.

[0104] In one embodiment, block 1412 provides further compensation for varying the amplitude of the qubit control signal by adjusting the frequency of the fourth adjustable qubit 219.

[0105] In some embodiments, the flow of process 1400 may be repeated cyclically. [Example of a computer platform]

[0106] As described above, the functions relating to interaction with the qubit via measurement and control signals may include a measurement and control unit, as shown in Figure 1A. Figure 15 provides an illustration of a functional block diagram of a computer hardware platform 1500 that may be used to implement a specifically configured computing device capable of hosting the qubit control engine 1540. In particular, Figure 15 shows a network or host computer platform 1500 that may be used to implement a appropriately configured computing device such as the measurement and control block 130 in Figure 1A.

[0107] The computer platform 1500 may include a central processing unit (CPU) 1504, a hard disk drive (HDD) 1506, random access memory (RAM) or read-only memory (ROM) or both 1508, a keyboard 1510, a mouse 1512, a display 1514, and a communication interface 1516, all connected to a system bus 1502.

[0108] In one embodiment, the HDD 1506 has the ability to include a procedure for storing a program capable of performing various processes, such as a qubit control engine 1540, in the manner described herein. The qubit control engine 1540 may have various modules configured to perform different functions. For example, there may be a control module 1542 capable of transmitting control signals to a qubit. There may be a measurement module 1544 capable of performing the function of receiving feedback from the qubit described herein. There may be a multiplexing module 1548 configured to provide the multiplexed control signals described herein.

[0109] In one embodiment, a program such as Apache® may be stored to operate the system as a web server. In one embodiment, HDD1506 may store an executable application that includes one or more library software modules, such as one for a Java® runtime environment program to implement a JVM (Java® Virtual Machine). [Conclusion]

[0110] While various embodiments of this teaching have been presented for illustrative purposes, they are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, practical applications, or technical improvements beyond the technology available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0111] While the above describes what is considered to be the best-case scenario, other examples, or both, it should be understood that various modifications are possible therein, that the subject matter disclosed herein can be implemented in various forms and examples, and that the teachings can be applied to many uses, with only a portion of those uses described herein. The following claims are intended to claim all uses, modifications, and variations that fall within the true scope of these teachings.

[0112] The components, steps, features, objects, benefits, and advantages described herein are for illustrative purposes only. None of them, nor any of the descriptions relating to them, are intended to limit the scope of protection. While various advantages have been described herein, it will be understood that not all embodiments necessarily include all of these advantages. Unless otherwise stated, all measurements, values, ratings, locations, sizes, dimensions, and other specifications described herein, including the following claims, are approximate and not precise. They are intended to be within a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they relate.

[0113] Many other embodiments are also contemplated. These include embodiments having fewer, additional, different, or combinations of components, steps, features, objects, benefits, and advantages. These also include embodiments in which components or steps or combinations thereof are configured, ordered, or combined in a different manner.

[0114] Aspects of the present disclosure are described herein with reference to flowcharts or block diagrams, or combinations thereof, of methods, apparatus (systems), and computer program products described herein. It will be understood that each block in a flowchart or block diagram or combination thereof, and any combination of blocks in a flowchart or block diagram or combination thereof, can be implemented by computer-readable program instructions.

[0115] These computer-readable program instructions may be provided to a processor of a computer, a dedicated computer, or other programmable data processing device appropriately configured to generate machines, and as a result, such instructions executed via the processor of the computer or other programmable data processing device create means for implementing a specified function / operation in one or more blocks or combination of blocks of a flowchart or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing device, or other device or combination of devices to function in a certain manner, and as a result, a computer-readable storage medium having instructions stored therein includes a product containing instructions that implement a mode of function / operation specified in one or more blocks or combination of blocks of a flowchart or block diagram.

[0116] Computer-readable program instructions can also be loaded onto a computer, other programmable device, or other device to perform a series of operational steps on that computer, other programmable device, or other device to generate a computer implementation process, and as a result, the instructions executed on the computer, other programmable device, or other device implement the functions / operations specified by one or more blocks in a flowchart or block diagram or a combination thereof.

[0117] The call flows, flowcharts, and block diagrams in the drawings herein illustrate the architecture, functionality, and operation of possible implementations of the systems, methods, and computer program products described in various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions that implement a specified logical function. In some alternative implementations, the functions described in a block may occur out of the order shown in the diagram. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions they may involve. It should also be noted that each block in a block diagram or flowchart, or combination thereof, and combinations of blocks in a block diagram or flowchart, or combination thereof, may be implemented by a dedicated hardware-based system that performs a specified function or operation, or a combination of dedicated hardware and computer instructions.

[0118] While the above has been explained in conjunction with exemplary embodiments, it should be understood that the term “exemplary” means merely an example, not the best or optimal. Except as stated immediately above, nothing described or illustrated is intended to provide to the public any component, step, feature, subject matter, benefit, advantage, or equivalent, whether or not it is described in the claims, and should not be construed as such.

[0119] The terms and expressions used herein will be understood to have the ordinary meanings given to such terms and expressions in relation to their respective fields of study and research, unless otherwise stated herein. Relative terms such as "first" and "second" may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof are intended to cover non-exclusive inclusions such that a process, method, article, or apparatus containing a list of elements may contain not only those elements but also other elements that are not specific to or expressly described in such process, method, article, or apparatus. The element preceded by "a" or "an" does not, unless further constraints apply, exclude the presence of additional identical elements in a process, method, article, or apparatus containing that element.

[0120] An abstract of this disclosure is provided to allow readers to quickly confirm the nature of the technical disclosure. The abstract is submitted with the understanding that it is not to be used to interpret or limit the scope or meaning of the claims. Furthermore, it is found that in the modes for carrying out the invention described herein, various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than those explicitly described in each claim. Rather, as represented by the following claims, the subject matter of the invention lies in fewer features than all the features of the single embodiment disclosed. Accordingly, the following claims are incorporated herein into the modes for carrying out the invention, and each claim stands alone as separately claimed subject matter.

Claims

1. applying a qubit control signal to a single drive line; splitting the qubit control signal on the single drive line between a first resonator and a second resonator, wherein the single drive line is operable to control a first qubit, a second tunable qubit, a third qubit, and a fourth tunable qubit; coupling the first qubit to the second tunable qubit by the first resonator; coupling the third qubit to the fourth tunable qubit by the second resonator; and compensating for variations in the amplitude of the qubit control signal by adjusting the frequency of at least one of the second tunable qubit or the fourth tunable qubit.

1. A method for multiplexing control lines of a qubit array, comprising:

2. The control line is configured to drive a resonator-induced phase (RIP) gate; the first resonator is a RIP resonator; and The second resonator is a RIP resonator. The method of claim 1.

3. 3. The method of claim 2 , further comprising providing calibration of the RIP gate between the first qubit and the second tunable qubit by maximizing the fidelity of the gate while varying a RIP frequency.

4. 4. The method of claim 2 or 3, wherein the second tunable qubit and the fourth tunable qubit are flux-tunable ancyla qubits operable to modify a frequency difference between corresponding RIP resonators of the first and second resonators by changing a quantum-state-dependent frequency shift χ on the corresponding RIP resonators.

5. 5. The method of claim 4, wherein the magnitude of the frequency shift χ of the first qubit and the second tunable qubit depends on the difference in frequency between the second tunable qubit and the first qubit.

6. 6. The method of claim 1, further comprising compensating for a second variation in the amplitude of the qubit control signal by adjusting the frequency of the fourth tunable qubit.

7. 7. The method of claim 1, wherein the qubit control signal is a radio frequency (RF) pulse having a fixed drive amplitude and a fixed frequency.

8. 8. The method of claim 1, wherein the splitting step is performed by a resistive power splitter, a reactive power splitter, or a multi-port coupler.

9. 9. The method of claim 1, wherein the splitting step is performed by a Wilkinson resistive power splitter, a wye power splitter, or a delta power splitter.

10. 10. The method of claim 1, further comprising performing error correction on the surface code architecture by cyclically performing at least one of X-parity and Z-parity.

11. detuning the first resonator from the second resonator; and shifting the drive frequency of the qubit control signal to a frequency at which a gate rate for the first qubit and the second tunable qubit is the same as a gate rate for the third qubit and the fourth tunable qubit. The method of claim 1 , further comprising:

12. First qubit; a second tunable qubit coupled to the first qubit via a first resonator; the third cubit; a fourth tunable qubit coupled to the third qubit through a second resonator; and a fixed drive line coupled to the first resonator and the second resonator, wherein the second tunable qubit is configured to be adjusted to compensate for variations in the amplitude of a qubit control signal of the fixed drive line. A quantum structure comprising:

13. The control line carries a signal to the resonator to drive the resonator-induced phase (RIP) gate; the first resonator is a RIP resonator; and The second resonator is a RIP resonator.

13. The quantum structure of claim 12.

14. 14. The quantum structure of claim 12, wherein the second tunable qubit and the fourth tunable qubit are flux-tunable ancilla qubits configured to modify a quantum-state-dependent frequency shift χ of their corresponding RIP resonators.

15. 15. The quantum structure of claim 14, wherein modifying χ of at least one of the first or third resonators is operable to mitigate disturbances in the pulse amplitude of the qubit control signal.

16. 16. A quantum structure according to any one of claims 12 to 15, wherein adjustment of the frequency of the fourth tunable qubit is operable to compensate for a second variation in the amplitude of the qubit control signal.

17. 17. A quantum structure according to any one of claims 12 to 16, wherein the qubit control signal is a radio frequency (RF) pulse having a fixed drive amplitude and a fixed frequency.

18. 18. A quantum structure according to any one of claims 12 to 17, wherein the splitting step is performed by a resistive power splitter, a reactive power splitter or a multi-port coupler.

19. 19. A quantum structure according to any one of claims 12 to 18, further comprising an RF splitter configured to split qubit control signals on the single fixed drive line.

20. First qubit; a second tunable qubit coupled to the first qubit via a first resonator; the third cubit; a fourth tunable qubit coupled to the third qubit through a second resonator; and a shared drive line coupled to the first resonator and the second resonator; where the first resonator is detuned from the second resonator; and the drive frequency of the qubit control signal is at a frequency at which the gate rate for the first qubit and the second tunable qubit is the same as the gate rate for the third qubit and the fourth tunable qubit. quantum structure.

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