Display device

Abstract

To provide a display device which reduces touch noise in an area in which a camera or a sensor is disposed.SOLUTION: A flexible display device includes: a substrate SUB which includes a display area including a first optical area and a normal area and a non-display area; a planarization layer PLN disposed on the substrate in the display area; a plurality of light emitting elements 120 disposed on the planarization layer and including an anode 121, a light-emission layer 122, and a cathode 123; a bank 116 disposed to cover an end of the anode 121 on the planarization layer; an encapsulation layer ENCAP disposed to cover the plurality of light emitting elements and the bank 116; a touch sensing layer TSL disposed on the encapsulation layer and including a plurality of touch electrodes 141; and a plurality of shielding patterns 145 disposed between the encapsulation layer ENCAP and the plurality of touch electrodes in the first optical area. The first optical area includes a transmission area TA in which the cathode 123 exposes the bank 116.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a display device, and more particularly to a display device capable of reducing touch noise in an area where a camera or a sensor is disposed. [Background technology]

[0002] 2. Description of the Related Art As we enter the information age, the field of display devices that visually display electrical information signals is rapidly developing, and research is ongoing to develop various display devices with improved performance, such as thinner, lighter, and less power consumption.

[0003] Representative display devices include liquid crystal displays (LCDs), field emission displays (FEDs), electro-wetting displays (EWDs), and organic light emitting displays (OLEDs).

[0004] Electroluminescent displays, such as organic light emitting displays, are self-emitting displays that do not require a separate light source, unlike liquid crystal displays, and can be manufactured in a lightweight and thin form. Electroluminescent displays are also advantageous in terms of power consumption due to their low voltage operation, and are also excellent in color realization, response speed, viewing angle, and contrast ratio (CR), and are expected to be used in a variety of fields.

[0005] In recent years, the multimedia functions of mobile terminals have been improved. For example, a camera or a sensor is basically built into the front of a display device. However, the camera or the sensor arranged on the front of the display device limits the screen design, making the screen design difficult. In order to reduce the space occupied by the camera or the sensor on the front of the display device, a design including a notch or a punch hole has been adopted for the display device, but the size of the screen is still limited by the camera or the sensor, making it difficult to realize a full-screen display.

[0006] In order to realize a full-screen display, a method has been proposed in which an area where low-resolution pixels are arranged is provided within the screen of a display device, and a camera and / or various sensors are arranged in the area where the low-resolution pixels are arranged. Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a display device capable of improving touch performance by reducing touch noise in an area where a camera or a sensor is arranged in the display device.

[0008] The object of the present invention is not limited to the above-mentioned objects, and other objects not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] A display device according to an embodiment of the present invention includes a substrate including a display region and a non-display region including a first optical region and a general region, a planarization layer disposed on the substrate in the display region, a plurality of light-emitting elements disposed on the planarization layer and including an anode, an emission layer, and a cathode, a bank disposed on the planarization layer to cover an end of the anode, an encapsulation portion disposed to cover the plurality of light-emitting elements and the bank, a touch sensing portion disposed on the encapsulation portion and including a plurality of touch electrodes, and a plurality of shielding patterns disposed between the encapsulation portion and the plurality of touch electrodes in the first optical region, and the first optical region includes a transmissive region through which the cathode exposes the bank.

[0010] Further details of the embodiments are included in the detailed description and the drawings. Effect of the Invention

[0011] In the display device of the present invention, a camera or a sensor is disposed at the lower end of a light emitting element or a touch electrode in a display area, so that the display or touch above it is not interrupted.

[0012] In the display device of the present invention, a transmissive region where no opaque components such as metal electrodes are disposed is located in an area overlapping an area where a camera or a sensor is disposed, thereby improving the light transmittance in the area where the camera or the sensor is disposed, and improving the visibility of the display device.

[0013] The display device of the present invention can reduce touch noise that may occur within the display device through the transparent region TA by arranging multiple shielding patterns so as to overlap multiple touch electrodes at the boundaries between multiple transparent regions and multiple light-emitting elements.

[0014] In the display device of the present invention, a highly fluid organic layer is disposed on the touch sensing unit to compensate for a step caused by the touch sensing unit, thereby improving visibility of the display device.

[0015] The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief description of the drawings]

[0016] [Figure 1a] 1 is a schematic plan view of a display device according to an embodiment of the present invention; [Figure 1b] 1 is a schematic plan view of a display device according to an embodiment of the present invention; [Figure 1c] 1 is a schematic plan view of a display device according to an embodiment of the present invention; [Figure 1d] 1 is a schematic plan view of a display device according to an embodiment of the present invention; [Diagram 2] 1 is a system configuration diagram of a display device according to an embodiment of the present invention. [Diagram 3] 4 is an equivalent circuit diagram of a sub-pixel in a display panel according to an embodiment of the present invention; [Figure 4] 2 is a diagram showing an arrangement of sub-pixels in a display area in a display panel according to an embodiment of the present invention. [Figure 5a] 4A to 4C are diagrams illustrating exemplary arrangements of signal lines in a first optical region and a general region in a display panel according to an embodiment of the present invention. [Figure 5b] 4A to 4C are diagrams illustrating exemplary arrangements of signal lines in a second optical region and a general region in a display panel according to an embodiment of the present invention. [Figure 6] FIG. 2 is a schematic plan view showing an enlarged general area of ​​the display device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII' of FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. [Figure 9] 2 is a schematic plan view showing an enlarged first optical region of the display device of FIG. 1. FIG. [Figure 10] 10 is a cross-sectional view taken along the line XX' of FIG. 9. [Figure 11a] FIG. 2 is a schematic plan view showing an X region in FIG. [Figure 11b] FIG. 11b is a schematic plan view showing region A of FIG. [Figure 11c]FIG. 11b is a schematic plan view showing region B of FIG. [Figure 11d] 11c is a cross-sectional view taken along line XI-XI'. FIG. [Figure 12] 1 shows simulation results of display touch noise (DTN) according to an embodiment and a comparative example of the present invention. [Figure 13] FIG. 4 is a plan view showing a first optical region of a flexible display device according to another embodiment of the present invention. [Figure 14] FIG. 14 is an enlarged view of a region Z in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The advantages and features of the present invention, as well as the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are provided solely for the purpose of making the disclosure of the present invention complete and fully conveying the scope of the invention to those skilled in the art to which the present invention pertains.

[0018] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited to the illustrated matters. The same reference symbols refer to the same components throughout the specification. In addition, when describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in the present invention, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0019] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0020] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., since "immediately" or "directly" is not used, one or more other parts may be located between the two parts.

[0021] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0022] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of the present invention.

[0023] Like reference numbers refer to like elements throughout the specification.

[0024] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the components shown.

[0025] The respective features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other, or may be implemented together in a related relationship.

[0026] In the following, the invention will be explained with reference to the drawings.

[0027] 1a to 1d are schematic plan views of a display device according to an embodiment of the present invention.

[0028] 1a to 1d, a display device 100 according to an embodiment of the present invention may include a display panel DP for displaying an image and one or more optical electronic devices 170, 170a, 170b. The optical electronic devices 170, 170a, 170b may include a light receiving device for receiving light, such as a camera or a sensor.

[0029] The display panel DP is a panel for displaying images to the user.

[0030] The display panel DP may include display elements for displaying images, driving elements for driving the display elements, and lines for transmitting various signals to the display elements and the driving elements. The display elements may be defined differently depending on the type of the display panel DP. For example, if the display panel DP is an organic light emitting display panel, the display elements may be organic light emitting elements including an anode, a light emitting layer, and a cathode. For example, if the display panel DP is a liquid crystal display panel, the display elements may be liquid crystal display elements.

[0031] In the following, it is assumed that the display panel DP is an organic light emitting display panel, but the display panel DP is not limited to being an organic light emitting display panel.

[0032] Meanwhile, the display panel DP may be configured to include a substrate, a number of insulating films on the substrate, a transistor layer, a light emitting element layer, etc. The display panel DP may include a number of sub-pixels and various signal lines for driving the sub-pixels to display an image. The signal lines may include a number of data lines, a number of gate lines, a number of power lines, etc. In this case, each of the sub-pixels may include a transistor located in the transistor layer and a light emitting element located in the light emitting element layer.

[0033] The display panel DP can include a display area DA and a non-display area NDA.

[0034] The display area DA is an area in which an image is displayed on the display panel DP.

[0035] In the display area DA, a number of sub-pixels constituting a number of pixels and a circuit for driving the number of sub-pixels may be arranged. The number of sub-pixels is the smallest unit constituting the display area DA, and a display element may be arranged in each of the number of sub-pixels, and the number of sub-pixels may constitute a pixel. For example, an organic light-emitting element including an anode, a light-emitting layer, and a cathode may be arranged in each of the number of sub-pixels, but is not limited thereto. In addition, the circuit for driving the number of sub-pixels may include a driving element and a line, etc. For example, the circuit may be composed of a thin film transistor, a storage capacitor, a gate line, a data line, etc., but is not limited thereto.

[0036] The non-display area NDA is an area where no image is displayed.

[0037] The non-display area NDA may be bent so that it is not visible at the front or may be hidden by a case (not shown) and is also called the bezel area.

[0038] 1a to 1d, the non-display area NDA is illustrated as surrounding the rectangular display area DA, but the shapes and arrangements of the display area DA and the non-display area NDA are not limited to the examples illustrated in Fig. 1a to 1d. That is, the display area DA and the non-display area NDA may have a shape suitable for the design of an electronic device equipped with the flexible display device 100. For example, the exemplary shape of the display area DA may be a pentagon, a hexagon, a circle, an ellipse, etc.

[0039] In the non-display area NDA, various wirings and circuits for driving the organic light emitting elements in the display area DA may be arranged, for example, link lines for transmitting signals to a number of sub-pixels and circuits in the display area DA, GIP (Gate-In-Panel) lines, ground lines GND, GRD, or driving ICs such as gate driver ICs and data driver ICs may be arranged, but are not limited thereto.

[0040] For example, the non-display area NDA may include a ground line GND that is disposed to surround the display area DA and applies a common voltage to the sub-pixels. For example, the ground line GND may be formed as one or more lines, and when two or more ground lines GND are formed, the ground line located closer to the display area DA may be referred to as an internal ground line GRD.

[0041] Although not shown, the display device 100 may include a touch sensing unit including a plurality of touch electrodes. Touch routing lines TL for transmitting touch signals may be arranged on the plurality of touch electrodes.

[0042] The display device 100 may further include various additional elements for generating various signals or driving pixels in the display area DA. The additional elements for driving the pixels may include an inverter circuit, a multiplexer, an electrostatic discharge (ESD) circuit, etc. The display device 100 may also include additional elements associated with functions other than driving the pixels. For example, the display device 100 may further include additional elements providing a touch sensing function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure sensing function, a tactile feedback function, etc. The aforementioned additional elements may be located in the non-display area NDA and / or an external circuit connected to the connection interface.

[0043] For example, the non-display area NDA of the display device 100 may include a pad area PA. In the pad area PA, various signal lines and pads connected to a printed circuit board are arranged. For example, the non-display area NDA may further include a bending area between the display area DA and the pad area PA. The bending area may be bent so that the pad area PA is located on the rear surface of the display panel DP, but is not limited thereto.

[0044] The pad area PA may include an integrated circuit bonding pad area COP disposed in the non-display area NDA and bonded to a driver integrated circuit DIC, and a film bonding pad area FOP disposed in the non-display area NDA and bonded to a ductile printed circuit. In this case, the integrated circuit bonding pad area COP may be located closer to the display area DA than the film bonding pad area FOP.

[0045] Referring to FIGS. 1a to 1d, a display area DA can include, but is not limited to, a first optical area DA1 and a general area NA.

[0046] In Figures 1a to 1d, one or more optical electronic devices 170, 170a, 170b are electronic components located below (opposite the viewing surface of) the display panel DP.

[0047] Light may be incident on the front (viewing) surface of the display panel DP and transmitted through the display panel DP to one or more optical electronic devices 170, 170a, 170b located below the display panel DP (opposite the viewing surface).

[0048] One or more of the optical / electronic devices 170, 170a, 170b may be devices that receive light transmitted through the display panel DP and perform a function determined by the received light.

[0049] For example, the optical electronic devices 170, 170a, 170b may include one or more of a camera or a proximity sensor.

[0050] As described above, the optical electronic devices 170, 170a, 170b, which are devices that need to receive light, may be located under the display panel DP. That is, the optical electronic devices 170, 170a, 170b may be located on the opposite side to the viewing surface of the display panel DP. The optical electronic devices 170, 170a, 170b are not exposed to the front surface of the flexible display device 100. Therefore, when a user looks at the front surface of the flexible display device 100, the optical electronic devices 170, 170a, 170b are not visible.

[0051] As an example, the camera located at the bottom of the display panel DP is a front camera that captures the front, and can also be seen through the camera lens.

[0052] The optical-electronic devices 170, 170a, 170b may be arranged to overlap with a display area DA of the display panel DP, i.e., the optical-electronic devices 170, 170a, 170b may be located within the display area DA.

[0053] Referring to FIGS. 1a to 1d, a display area DA may include a general area NA and one or more optical areas DA1, DA2.

[0054] One or more of the optical areas DA1, DA2 may be areas that overlap with one or more of the optical-electronic devices 170, 170a, 170b.

[0055] 1a, the display area DA may include a general area NA and a first optical area DA1, where at least a part of the first optical area DA1 may overlap with the first optical-electronic device 170.

[0056] Although FIG. 1a shows a structure in which the first optical area DA1 is circular, the shape of the first optical area DA1 according to the embodiment of the present invention is not limited thereto.

[0057] For example, as shown in FIG. 1b, the shape of the first optical area DA1 may be an octagon, or may be any other polygonal shape.

[0058] According to the example of Fig. 1c, the display area DA can include a general area NA, a first optical area DA1 and a second optical area DA2. In the example of Fig. 1c, the general area NA may be present between the first optical area DA1 and the second optical area DA2. Here, at least a portion of the first optical area DA1 may overlap with the first optical-electronic device 170a, and at least a portion of the second optical area DA2 may overlap with the second optical-electronic device 170b.

[0059] According to the example of Fig. 1d, the display area DA may include a general area NA, a first optical area DA1 and a second optical area DA2. In the example of Fig. 1d, there is no general area NA between the first optical area DA1 and the second optical area DA2. That is, the first optical area DA1 and the second optical area DA2 may be in contact with each other. Here, at least a portion of the first optical area DA1 may overlap with the first optical-electronic device 170a, and at least a portion of the second optical area DA2 may overlap with the second optical-electronic device 170b.

[0060] The one or more optical regions DA1, DA2 should have both an image display structure and a light transmission structure formed therein. That is, since the one or more optical regions DA1, DA2 are a part of the display region DA, sub-pixels for image display should be arranged in the one or more optical regions DA1, DA2. The one or more optical regions DA1, DA2 should have a light transmission structure formed therein to transmit light to one or more optical electronic devices 170, 170a, 170b.

[0061] One or more optical electronic devices 170, 170a, 170b, which are devices that need to receive light, are located behind (below, opposite the viewing surface) the display panel DP and receive light that has passed through the display panel DP.

[0062] The one or more optical-electronic devices 170, 170a, 170b are not exposed on the front (viewing) surface of the display panel DP, and therefore, when a user looks at the front surface of the flexible display device 100, the optical-electronic devices 170, 170a, 170b are not visible to the user.

[0063] For example, the first optical-electronic device 170, 170a may be a camera, and the second optical-electronic device 170b may be a detection sensor such as a proximity sensor, an illuminance sensor, etc. For example, the detection sensor may be an infrared sensor that detects infrared rays.

[0064] Conversely, the first optical / electronic device 170, 170a may be a sensing sensor and the second optical / electronic device 170b may be a camera.

[0065] In the following description, for convenience of explanation, the first optical electronic device 170, 170a is a camera, and the second optical electronic device 170b is a detection sensor, for example, where the camera may be a camera lens or an image sensor.

[0066] When the first optical electronic device 170, 170a is a camera, the camera may be a front camera located behind (below) the display panel DP, capturing an image in the front direction of the display panel DP. Thus, a user can capture an image through a camera that is not visible on the viewing surface while looking at the viewing surface of the display panel DP.

[0067] The general area NA and one or more optical areas DA1, DA2 included in the display area DA are areas in which images can be displayed, but the general area NA is an area in which a light-transmitting structure does not need to be formed, and the one or more optical areas DA1, DA2 are areas in which a light-transmitting structure must be formed.

[0068] Therefore, one or more of the optical regions DA1 and DA2 must have a transmittance above a certain level, and the general region NA may have no light transmittance or a low transmittance below a certain level.

[0069] For example, one or more of the optical areas DA1, DA2 and the general area NA may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, line arrangement structure, or the like.

[0070] For example, the number of sub-pixels per unit area in one or more optical regions DA1 and DA2 may be smaller than the number of sub-pixels per unit area in the general region NA. That is, the resolution of one or more optical regions DA1 and DA2 may be lower than the resolution of the general region NA. In this case, the number of sub-pixels per unit area is a unit for measuring resolution, and can also be called PPI (Pixels Per Inch), which means the number of pixels within 1 inch.

[0071] For example, the number of subpixels per unit area in the first optical region DA1 may be smaller than the number of subpixels per unit area in the general region NA, and the number of subpixels per unit area in the second optical region DA2 may be equal to or greater than the number of subpixels per unit area in the first optical region DA1.

[0072] For example, the resolution of the first optical area DA1 may be less than 400 ppi, for example, 200 ppi to 324 ppi, and the resolution of the general area NA may be 400 ppi or more.

[0073] The first optical area DA1 may have various patterns, such as a circle, an ellipse, a square, a hexagon, an octagon, etc. The second optical area DA2 may have various patterns, such as a circle, an ellipse, a square, a hexagon, an octagon, etc. The first optical area DA1 and the second optical area DA2 may have the same pattern or different patterns.

[0074] Referring to FIG. 1c, when the first optical area DA1 and the second optical area DA2 are adjacent, the entire optical area including the first optical area DA1 and the second optical area DA2 may also have various patterns, such as a circle, an ellipse, a square, a hexagon, or an octagon.

[0075] In the following, for convenience of explanation, an example will be given in which the first optical area DA1 and the second optical area DA2 are each circular.

[0076] In the flexible display device 100 according to an embodiment of the present invention, if the first optical electronic device 170, 170a, which is not exposed to the outside and is hidden under the display panel DP, is a camera, the flexible display device 100 according to an embodiment of the present invention can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0077] Accordingly, in the case of the flexible display device 100 according to an embodiment of the present invention, a notch or a camera hole for exposing a camera does not need to be formed in the display panel DP, so that the area of ​​the display area DA does not decrease.

[0078] As a result, since a notch or camera hole for exposing a camera does not need to be formed in the display panel DP, the size of the bezel area can be reduced, design restrictions can be eliminated, and design freedom can be increased.

[0079] In the flexible display device 100 according to an embodiment of the present invention, although one or more optical electronic devices 170, 170a, 170b are located hidden behind the display panel DP, the one or more optical electronic devices 170, 170a, 170b must be able to receive light normally and perform their designated functions normally.

[0080] In addition, in the flexible display device 100 according to an embodiment of the present invention, although one or more optical electronic devices 170, 170a, 170b are positioned behind the display panel DP and overlap with the display area DA, normal image display should be possible in one or more optical areas DA1, DA2 overlapping with the one or more optical electronic devices 170, 170a, 170b in the display area DA.

[0081] Therefore, the display device 100 according to an embodiment of the present invention may have a structure capable of improving the transmittance of the first optical area DA1 and the second optical area DA2 overlapped with the optoelectronic devices 170, 170a, and 170b.

[0082] FIG. 2 is a system configuration diagram of a display device according to an embodiment of the present invention.

[0083] Referring to FIG. 2, the display device 100 may include a display panel DP and a display driver circuit as components for displaying an image.

[0084] The display driving circuit is a circuit for driving the display panel DP, and may include a data driving circuit DDC, a gate driving circuit GDC, a display controller DCTR, and the like.

[0085] The display panel DP may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The non-display area NDA may be an outer peripheral area of ​​the display area DA, and may also be called a bezel area. The entire or a part of the non-display area NDA may be an area that is visible from the front surface of the display device 100, or an area that is bent so that it is not visible from the front surface of the display device 100.

[0086] The display panel DP may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB, and may further include various types of signal lines for driving the sub-pixels SP.

[0087] The display device 100 according to the embodiment of the present invention may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel DP emits light by itself. When the display device 100 according to the embodiment of the present invention is a self-emitting display device, each of the sub-pixels SP may include a light-emitting element.

[0088] For example, the display device 100 according to the embodiment of the present invention may be an organic light emitting display device in which the light emitting element is an organic light emitting diode (OLED). As another example, the display device 100 according to the embodiment of the present invention may be an inorganic light emitting display device in which the light emitting element is an inorganic-based light emitting diode. As still another example, the display device 100 according to the embodiment of the present invention may be a quantum dot display device in which the light emitting element is a quantum dot, which is a semiconductor crystal that emits light by itself.

[0089] The structure of each of the subpixels SP may vary depending on the type of display device 100. For example, when the display device 100 is a self-emitting display device in which the subpixels SP emit light by themselves, each subpixel SP may include a light-emitting element that emits light by itself, one or more transistors, and one or more capacitors.

[0090] For example, various types of signal lines may include a plurality of data lines DL that transmit data signals (also called data voltages or video signals) and a plurality of gate lines GL that transmit gate signals (also called scan signals).

[0091] The data lines DL and the gate lines GL may cross each other. Each of the data lines DL may be arranged to extend in a first direction. Each of the gate lines GL may be arranged to extend in a second direction.

[0092] Here, the first direction may be a column direction and the second direction may be a row direction, or the first direction may be a row direction and the second direction may be a column direction.

[0093] The data driving circuit DDC is a circuit for driving a plurality of data lines DL and can output data signals to the plurality of data lines DL. The gate driving circuit GDC is a circuit for driving a plurality of gate lines GL and can output gate signals to the plurality of gate lines GL.

[0094] The display controller DCTR is a device for controlling the data driving circuit DDC and the gate driving circuit GDC, and can control the driving timing for a plurality of data lines DL and the driving timing for a plurality of gate lines GL.

[0095] The display controller DCTR can supply a data drive control signal DCS to the data drive circuit DDC for controlling the data drive circuit DDC, and can supply a gate drive control signal GCS to the gate drive circuit GDC for controlling the gate drive circuit GDC.

[0096] The display controller DCTR can receive input image data from the host system HSYS and supply image data Data to the data driving circuit DDC based on the input image data.

[0097] The data driving circuit DDC can supply data signals to a plurality of data lines DL under the drive timing control of the display controller DCTR.

[0098] The data driving circuit DDC receives digital image data Data from the display controller DCTR, converts the received image data Data into analog data signals, and outputs the analog data signals to a plurality of data lines DL.

[0099] The gate driving circuit GDC can supply gate signals to a plurality of gate lines GL under timing control of the display controller DCTR. The gate driving circuit GDC can generate gate signals by receiving a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage together with various gate driving control signals GCS, and can supply the generated gate signals to a plurality of gate lines GL.

[0100] The gate driving circuit GDC supplies gate signals to the gate lines GL in response to a gate driving control signal GCS supplied from the display controller DCTR. The gate driving circuit GDC may be disposed on one or both sides of the display panel 100 in a GIP (Gate In Panel) manner.

[0101] The gate driving circuit GDC sequentially outputs gate signals to a plurality of gate lines GL under the control of a display controller DCTR. The gate driving circuit GDC can sequentially supply the signals to the gate lines GL by shifting the gate signals using a shift register.

[0102] The gate signal may include a scan signal SC and a light emission control signal EM in the organic light emitting display device. The scan signal SC may include a scan signal pulse that swings between a first gate voltage and a second gate voltage. The light emission control signal EM may include a light emission control signal pulse that swings between a third gate voltage and a fourth gate voltage.

[0103] The scan pulse is synchronized with the data voltage Vdata to select the sub-pixels SP of the line to which data is written. The light emission control signal EM defines the light emission time of each sub-pixel SP.

[0104] The gate driving circuit GDC may include an emission control signal driving part EDC that outputs an emission control signal EM and at least one scan driving part SDC that outputs a scan signal SC.

[0105] The light emission control signal driver EDC outputs a light emission control signal EM in response to a start pulse and a shift clock from the display controller DCTR, and sequentially shifts the light emission control signal pulses according to the shift clock.

[0106] At least one scan driver SDC outputs a scan signal SC in response to a start pulse and a shift clock from a display controller DCTR, and shifts the scan signal pulse in accordance with the shift clock timing.

[0107] In the gate driving circuit GDC arranged in the GIP manner, the shift registers may be configured symmetrically on both sides of the display area DA. Also, the gate driving circuit GDC may be configured such that the shift register on one side of the display area DA includes at least one scan driver SDC and an emission control signal driver 310, and the shift register on the other side of the display area DA includes at least one scan driver SDC. However, the present invention is not limited thereto, and the emission control signal driver EDC and the at least one scan driver SDC may be arranged differently depending on the embodiment.

[0108] The data driving circuit DDC may be connected to the display panel DP by a Tape Automated Bonding (TAB) method, or may be connected to a bonding pad of the display panel DP by a Chip On Glass (COG) or Chip On Panel (COP) method, or may be implemented as a Chip On Film (COF) method and connected to the display panel DP.

[0109] The gate driving circuit GDC may be connected to the display panel DP by a tape automated bonding (TAB) method, or may be connected to a bonding pad of the display panel DP by a chip-on-glass (COG) or chip-on-panel (COP) method, or may be connected to the display panel DP by a chip-on-film (COF) method. Alternatively, the gate driving circuit GDC may be formed in a non-display area NDA of the display panel DP as a gate-in-panel (GIP) type. The gate driving circuit GDC may be disposed on a substrate or connected to a substrate. That is, the gate driving circuit GDC may be disposed in the non-display area NDA of the substrate in the case of a GIP type. The gate driving circuit GDC may be connected to a substrate in the case of a chip-on-glass (COG) type, a chip-on-film (COF) type, or the like.

[0110] Meanwhile, at least one of the data driving circuit DDC and the gate driving circuit GDC may be disposed in the display area DA of the display panel DP. For example, at least one of the data driving circuit DDC and the gate driving circuit GDC may be disposed so as not to overlap with the sub-pixel SP, or may be disposed so as to overlap partially or entirely with the sub-pixel SP.

[0111] The data driving circuit DDC may be connected to one side (e.g., upper or lower side) of the display panel DP. Depending on the driving method, panel design method, etc., the data driving circuit DDC may be connected to both sides (e.g., upper and lower sides) of the display panel DP, or may be connected to two or more of the four sides of the display panel DP.

[0112] The gate driving circuit GDC may be connected to one side (e.g., the left or right side) of the display panel DP. Depending on the driving method, panel design method, etc., the gate driving circuit GDC may be connected to both sides (e.g., the left and right sides) of the display panel DP, or may be connected to two or more of the four sides of the display panel DP.

[0113] The display controller DCTR may be implemented as a component separate from the data driving circuit DDC, or may be integrated with the data driving circuit DDC and implemented as an integrated circuit.

[0114] The display controller DCTR may be a timing controller used in a conventional display technology, or may be a control device including a timing controller and capable of performing other control functions, or may be a control device different from the timing controller, or may be a circuit within the control device. The display controller DCTR may be realized as various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0115] The display controller DCTR may be mounted on a printed circuit board, a ductile printed circuit, or the like, and may be electrically connected to the data driving circuit DDC and the gate driving circuit GDC through the printed circuit board, the ductile printed circuit, or the like.

[0116] The display controller DCTR can transmit and receive signals to and from the data driving circuit DDC through one or more predetermined interfaces, where the interfaces can include, for example, a Low Voltage Differential Signaling (LVDS) interface, an Embedded Clock Point-to-Point Interface (EPI), a Serial Peripheral Interface (SPI), etc.

[0117] The display device 100 according to an embodiment of the present invention may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen, or to detect the touch position, in order to provide not only an image display function but also a touch sensing function.

[0118] The touch sensing circuit may further include a touch driving circuit that drives and senses the touch sensor to generate and output touch sensing data, and a touch controller that can sense the occurrence of a touch or detect a touch position using the touch sensing data.

[0119] The touch sensor may include a plurality of touch electrodes, and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to a touch driving circuit.

[0120] The touch sensor may be present outside the display panel DP in the form of a touch panel, or may be present inside the display panel DP. When the touch sensor is present outside the display panel DP in the form of a touch panel, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel DP may be fabricated separately and combined during an assembly process. The external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate, etc.

[0121] When the touch sensor is present inside the display panel DP, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during the manufacturing process of the display panel DP.

[0122] The touch driving circuit TDC may supply a touch driving signal to at least one of the plurality of touch electrodes and sense the at least one of the plurality of touch electrodes to generate touch sensing data.

[0123] The touch sensing circuit may perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0124] When the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (eg, a finger, a pen, etc.).

[0125] According to the self-capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit TDC can drive all or a part of the plurality of touch electrodes and sense all or a part of the plurality of touch electrodes.

[0126] When the touch sensing circuit performs touch sensing using a mutual-capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between the touch electrodes.

[0127] According to the mutual-capacitance sensing method, the plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes, and the touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0128] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented in separate devices or in a single device, and the touch driving circuit and the data driving circuit DDC may be implemented in separate devices or in a single device.

[0129] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or the touch sensing circuit.

[0130] The display device 100 according to an embodiment of the present invention may be a mobile terminal such as a smartphone or a tablet, or a monitor or television (TV) of various sizes, but is not limited thereto and may be displays of various types and sizes capable of displaying information or images.

[0131] As mentioned above, in the display panel DP, the display area DA can include a general area NA and one or more optical areas DA1, DA2.

[0132] The general area NA and the one or more optical areas DA1 and DA2 are areas where an image can be displayed. However, the general area NA is an area where a light-transmitting structure does not need to be formed, whereas the one or more optical areas DA1 and DA2 are areas where a light-transmitting structure must be formed.

[0133] As mentioned above, in the display panel DP, the display area DA may include one or more optical areas DA1, DA2 as well as a general area NA, but for ease of explanation, it is assumed that the display area DA includes both the first optical area DA1 and the second optical area DA2 (Figures 1b and 1c).

[0134] FIG. 3 is an equivalent circuit diagram of a sub-pixel in a display panel according to an embodiment of the present invention.

[0135] 3 is merely an example of a pixel circuit for the purpose of explanation, and is not limited to a specific structure as long as the light emission signal EM(n) is applied to control the emission of the light emitting element ED, 120. For example, the pixel circuit may include an additional scan signal and a switching thin film transistor connected thereto, and a switching thin film transistor to which an additional initialization voltage is applied, and the connection relationship of the switching elements and the connection positions of the capacitors may be variously arranged. In the following, for the convenience of explanation, a display device having the pixel circuit structure of FIG. 3 will be described.

[0136] Referring to FIG. 3, each of the sub-pixels SP may include a pixel circuit having a driving transistor Td, and a light emitting element ED, 120 coupled to the pixel circuit.

[0137] Each of the sub-pixels SP arranged in the general area NA, the first optical area DA1 and the second optical area DA2 included in the display area DA of the display panel DP may include a light-emitting element ED, 120, a driving transistor Td for driving the light-emitting element ED, 120, a plurality of scan transistors T1 to T7 for operating the driving transistor Td, and a capacitor Cst for maintaining a constant voltage during one frame.

[0138] The pixel circuit can drive the light emitting element ED, 120 by controlling a driving current flowing through the light emitting element ED, 120. The pixel circuit can include a driving transistor Td, first to seventh transistors T1 to T7, and a capacitor Cst. Each of the transistors DT, T1 to T7 can include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode can be a source electrode, and the other of the first electrode and the second electrode can be a drain electrode.

[0139] Each of the transistors DT and T1 to T7 may be a P type thin film transistor or an N type thin film transistor. In the embodiment of FIG. 3, the first transistor T1 and the seventh transistor T7 are N type thin film transistors, and the remaining transistors DT and T2 to T6 are P type thin film transistors. However, this is not limited thereto, and depending on the embodiment, all or some of the transistors DT and T1 to T7 may be P type thin film transistors or N type thin film transistors. Furthermore, the N type thin film transistors may be oxide thin film transistors, and the P type thin film transistors may be polycrystalline silicon thin film transistors.

[0140] In the following description, the first transistor T1 and the seventh transistor T7 are N-type thin film transistors, and the remaining transistors DT, T2 to T6 are P-type thin film transistors. Therefore, the first transistor T1 and the seventh transistor T7 are turned on when a high voltage is applied, and the remaining transistors DT, T2 to T6 are turned on when a low voltage is applied.

[0141] According to one example, the first transistor T1 constituting the pixel circuit can function as a compensation transistor, the second transistor T2 as a data supply transistor, the third and fourth transistors T3 and T4 as light emission control transistors, the fifth transistor T5 as a bias transistor, and the sixth and seventh transistors T6 and T7 as initialization transistors.

[0142] The light emitting element ED 120 may include an anode electrode (or an anode electrode) and a cathode electrode. The anode electrode of the light emitting element ED 120 may be coupled to the fifth node N5, and the cathode electrode may be coupled to a low potential driving voltage EVSS.

[0143] The driving transistor Td may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor Td may provide a driving current Id to the light emitting element ED, 120 based on a voltage of the first node N1 (or a data voltage stored in a capacitor Cst, which will be described later).

[0144] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode receiving a first scan signal SC1(n). The first transistor T1 is turned on in response to the first scan signal SC1(n), and the data voltage Vdata may be diode-coupled between the first node N1 and the third node N3 to sample the threshold voltage Vth of the driving transistor Td. Such a first transistor T1 may be a compensation transistor.

[0145] The capacitor Cst may be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst may store or maintain the high potential driving voltage EVDD provided. In addition, the capacitor Cst may further include one or more capacitors.

[0146] The second transistor T2 may include a first electrode connected to the data line DL (or receiving a data voltage Vdata), a second electrode connected to a second node N2, and a gate electrode receiving a second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) to transfer the data voltage Vdata to the second node N2. Such a second transistor T2 may be a data supply transistor.

[0147] The third transistor T3 and the fourth transistor T4 (or the first and second light emitting control transistors) are connected between the high potential driving voltage EVDD and the light emitting element ED, 120, and can form a current transfer path through which the driving current Id generated by the driving transistor Td transfers.

[0148] The third transistor T3 may include a first electrode connected to the fourth node N4 to receive a high potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving an emission control signal EM(n).

[0149] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to a fifth node N5 (or an anode electrode of the light emitting element ED, 120), and a gate electrode receiving a light emitting control signal EM(n).

[0150] The third and fourth transistors T3 and T4 are turned on in response to the light emission control signal EM(n), in which case the driving current Id is provided to the light emitting element ED, 120, and the light emitting element ED, 120 can emit light with a brightness corresponding to the driving current Id.

[0151] The fifth transistor T5 may include a first electrode receiving a bias voltage Vobs, a second electrode coupled to the second node N2, and a gate electrode receiving a third scan signal SC3(n), and may be a bias transistor.

[0152] The sixth transistor T6 may include a first electrode receiving a first initialization voltage Var, a second electrode coupled to a fifth node N5, and a gate electrode receiving a third scan signal SC3(n).

[0153] The sixth transistor T6 is turned on in response to the third scan signal SC3(n) before the light emitting element ED, 120 emits light (or after the light emitting element ED, 120 emits light) and can initialize the anode electrode (or pixel electrode) of the light emitting element ED, 120 using the first initialization voltage Var. The light emitting element ED, 120 may have a parasitic capacitor formed between the anode electrode and the cathode electrode. Then, while the light emitting element ED, 120 emits light, the parasitic capacitor is charged and the anode electrode of the light emitting element ED, 120 may have a specific voltage. Therefore, the amount of charge stored in the light emitting element ED, 120 can be initialized by applying the first initialization voltage Var to the anode electrode of the light emitting element ED, 120 through the sixth transistor T6.

[0154] In this specification, the gate electrodes of the fifth and sixth transistors T5 and T6 are configured to commonly receive the third scan signal SC3(n). However, this is not necessarily limited thereto, and the gate electrodes of the fifth and sixth transistors T5 and T6 may be configured to receive separate scan signals and be controlled independently.

[0155] The seventh transistor T7 may include a first electrode receiving the second initialization voltage Vini, a second electrode coupled to the first node N1, and a gate electrode receiving the fourth scan signal SC4(n).

[0156] The seventh transistor T7 is turned on in response to the fourth scan signal SC4(n) and can initialize the gate electrode of the driving transistor Td using the second initialization voltage Vini. Unnecessary charges may remain on the gate electrode of the driving transistor Td due to the high potential driving voltage EVDD stored in the capacitor Cst. Therefore, the amount of remaining charges can be initialized by applying the second initialization voltage Vini to the gate electrode of the driving transistor Td through the seventh transistor T7.

[0157] Meanwhile, as a method for increasing the transmittance of at least one of the first optical region DA1 and the second optical region DA2, the pixel density difference design method may be applied as described above. According to the pixel density difference design method, the display panel DP may be designed such that the number of sub-pixels per unit area of ​​at least one of the first optical region DA1 and the second optical region DA2 is less than the number of sub-pixels per unit area of ​​the general region NA.

[0158] However, in some cases, a pixel size difference design method may be applied as another method for increasing the transmittance of at least one of the first optical region DA1 and the second optical region DA2. According to the pixel size difference design method, the display panel DP may be designed such that the number of sub-pixels per unit area of ​​at least one of the first optical region DA1 and the second optical region DA2 is the same as or similar to the number of sub-pixels per unit area of ​​the general region NA, and the size of each sub-pixel SP (i.e., the size of the light-emitting region) arranged in at least one of the first optical region DA1 and the second optical region DA2 is smaller than the size of each sub-pixel SP (i.e., the size of the light-emitting region) arranged in the general region NA.

[0159] In the following, for ease of explanation, it will be assumed that the pixel density difference design method is applied out of the two methods (pixel density difference design method, pixel size difference design method) for increasing the transmittance of at least one of the first optical area DA1 and the second optical area DA2.

[0160] FIG. 4 is a diagram showing an arrangement of sub-pixels in a display area in a display panel according to an embodiment of the present invention.

[0161] That is, FIG. 4 shows the arrangement of sub-pixels SP in three areas NA, DA1, and DA2 included in the display area of ​​the display panel according to the embodiment of the present invention.

[0162] Referring to FIG. 4, a plurality of sub-pixels SP may be arranged in each of a general area NA, a first optical area DA1, and a second optical area DA2 included in a display area.

[0163] For example, the sub-pixels SP may include a red sub-pixel Red SP that emits red light, a green sub-pixel Green SP that emits green light, and a blue sub-pixel Blue SP that emits blue light.

[0164] Thus, each of the general area NA, the first optical area DA1, and the second optical area DA2 may include a light emitting area EA of the red sub-pixel Red SP, a light emitting area EA of the green sub-pixel Green SP, and a light emitting area EA of the blue sub-pixel Blue SP.

[0165] Referring to FIG. 4, the general area NA does not include a light-transmitting structure and may include the light-emitting area EA.

[0166] However, the first optical area DA1 and the second optical area DA2 must not only include the light emitting area EA but also include a light transmitting structure.

[0167] Thus, the first optical region DA1 may include a light-emitting region EA and a first transmissive region TA1, and the second optical region DA2 may include a light-emitting region EA and a second transmissive region TA2.

[0168] The luminescent area EA and the transmissive areas TA1 and TA2 can be distinguished based on whether they are capable of transmitting light or not, that is, the luminescent area EA can be an area that does not transmit light, and the transmissive areas TA1 and TA2 can be areas that can transmit light.

[0169] The light emitting area EA and the transmissive areas TA1 and TA2 can be distinguished by the presence or absence of a specific metal layer. For example, a cathode electrode may be formed in the light emitting area EA, but not in the transmissive areas TA1 and TA2. A light shielding layer may be formed in the light emitting area EA, but not in the transmissive areas TA1 and TA2.

[0170] In this case, since the first optical region DA1 includes the first transmission region TA1 and the second optical region DA2 includes the second transmission region TA2, both the first optical region DA1 and the second optical region DA2 are regions through which light can pass.

[0171] In this case, the transmittance (degree of transmission) of the first optical region DA1 may be the same as the transmittance (degree of transmission) of the second optical region DA2.

[0172] In this case, the first transmission regions TA1 in the first optical region DA1 and the second transmission regions TA2 in the second optical region DA2 may have the same pattern or size, or the first transmission regions TA1 in the first optical region DA1 and the second transmission regions TA2 in the second optical region DA2 may have different patterns or sizes, but the ratio of the first transmission regions TA1 in the first optical region DA1 and the ratio of the second transmission regions TA2 in the second optical region DA2 may be the same.

[0173] Alternatively, the transmittance (degree of transmission) of the first optical area DA1 and the transmittance (degree of transmission) of the second optical area DA2 may be different from each other.

[0174] In this case, the first transmission regions TA1 in the first optical region DA1 and the second transmission regions TA2 in the second optical region DA2 may have different patterns or sizes. Or, even if the first transmission regions TA1 in the first optical region DA1 and the second transmission regions TA2 in the second optical region DA2 have the same patterns or sizes, the ratio of the first transmission regions TA1 in the first optical region DA1 and the ratio of the second transmission regions TA2 in the second optical region DA2 may be different from each other.

[0175] For example, if the first optical electronic device overlapped with the first optical area DA1 is a camera and the second optical electronic device overlapped with the second optical area DA2 is a sensor, the camera may require a larger amount of light than the sensor.

[0176] Therefore, the transmittance (degree of transmission) of the first optical area DA1 can be higher than the transmittance (degree of transmission) of the second optical area DA2.

[0177] In this case, the first transmission region TA1 of the first optical region DA1 may be larger than the second transmission region TA2 of the second optical region DA2, or even if the first transmission region TA1 of the first optical region DA1 and the second transmission region TA2 of the second optical region DA2 are the same size, the ratio of the first transmission region TA1 in the first optical region DA1 may be larger than the ratio of the second transmission region TA2 in the second optical region DA2.

[0178] For convenience of explanation, the following description will be given taking as an example a case where the transmittance (degree of transmission) of the first optical area DA1 is greater than the transmittance (degree of transmission) of the second optical area DA2.

[0179] In addition, as shown in FIG. 4, in the embodiment of the present invention, the transmissive areas TA1 and TA2 can be called transparent areas, and the transmittance can be called transparency.

[0180] Also, as shown in FIG. 4, in the embodiment of the present invention, it is assumed that the first optical area DA1 and the second optical area DA2 are located at the upper end of the display area of ​​the display panel and are arranged side by side.

[0181] Referring to Figure 4, the horizontal display area in which the first optical area DA1 and the second optical area DA2 are arranged is called the first horizontal display area HA1, and the horizontal display area in which the first optical area DA1 and the second optical area DA2 are not arranged is called the second horizontal display area HA2.

[0182] 4, the first horizontal display area HA1 may include a general area NA, a first optical area DA1, and a second optical area DA2, whereas the second horizontal display area HA2 may include only the general area NA.

[0183] FIG. 5a is a diagram illustrating an example of the arrangement of signal lines in a first optical region and a general region in a display panel according to an embodiment of the present invention.

[0184] FIG. 5b is a diagram illustrating an example of the arrangement of signal lines in the second optical region and the general region in a display panel according to an embodiment of the present invention.

[0185] That is, Figure 5a shows the arrangement of signal lines in the first optical area DA1 and the general area in a display panel according to an embodiment of the present invention, and Figure 5b shows the arrangement of signal lines in the second optical area DA2 and the general area in a display panel according to an embodiment of the present invention.

[0186] The first horizontal display area HA1 shown in FIGS. 5a and 5b is a part of the first horizontal display area HA1 in the display panel, and the second horizontal display area HA2 is a part of the second horizontal display area HA2 in the display panel.

[0187] The first optical area DA1 shown in FIG. 5a is a part of the first optical area DA1 in the display panel, and the second optical area DA2 shown in FIG. 5b is a part of the second optical area DA2 in the display panel.

[0188] 5a and 5b, the first horizontal display area HA1 may include a general area, a first optical area DA1 and a second optical area DA2, and the second horizontal display area HA2 may include a general area.

[0189] Various types of horizontal lines HL1, HL2 and various types of vertical lines VLn, VL1, VL2 may be arranged on the display panel.

[0190] In the embodiment of the present invention, the horizontal direction and the vertical direction refer to two intersecting directions, and the horizontal direction and the vertical direction may differ depending on the viewing direction. For example, in the embodiment of the present invention, the horizontal direction may refer to the direction in which one gate line extends and is arranged, and the vertical direction may refer to the direction in which one data line extends and is arranged. Thus, the horizontal and vertical directions are taken as examples.

[0191] Referring to Figures 5a and 5b, the horizontal lines arranged on the display panel may include a first horizontal line HL1 arranged in the first horizontal display area HA1 and a second horizontal line HL2 arranged in the second horizontal display area HA2.

[0192] The horizontal lines arranged on the display panel may be gate lines, i.e., the first horizontal line HL1 and the second horizontal line HL2 may be gate lines, and may include various types of gate lines according to the structure of the sub-pixels.

[0193] Referring to Figures 5a and 5b, the vertical lines arranged on the display panel may include a general vertical line VLn arranged only in the general region, a first vertical line VL1 passing through the first optical region DA1 and the general region, and a second vertical line VL2 passing through the second optical region DA2 and the general region.

[0194] The vertical lines arranged in the display panel may include data lines, driving voltage lines, etc., and may further include reference voltage lines, initialization voltage lines, etc. That is, the general vertical line VLn, the first vertical line VL1, and the second vertical line VL2 may include data lines, driving voltage lines, etc., and may further include reference voltage lines, initialization voltage lines, etc.

[0195] In the embodiment of the present invention, the term "horizontal" in the second horizontal line HL2 only means that a signal is transmitted from left (or right) to right (or left), and does not mean that the second horizontal line HL2 extends in a straight line only in the exact horizontal direction. That is, in Figures 5a and 5b, the second horizontal line HL2 is shown in a straight line, but unlike this, the second horizontal line HL2 may include a bent or curved portion. Similarly, the first horizontal line HL1 may also include a bent or curved portion.

[0196] In the embodiment of the present invention, the term "vertical" in the general vertical line VLn only means that a signal is transmitted from the top (or bottom) to the bottom (or top), and does not mean that the general vertical line VLn extends in a straight line only in the exact vertical direction. That is, in Figures 5a and 5b, the general vertical line VLn is shown in a straight line, but unlike this, the general vertical line VLn may include a bent or curved portion. Similarly, the first vertical line VL1 and the second vertical line VL2 may also include a bent or curved portion.

[0197] 5a, the first optical region DA1 included in the first horizontal region HA1 may include a light-emitting region and a first transmissive region. In the first optical region DA1, an outer region of the first transmissive region may include a light-emitting region.

[0198] Referring to FIG. 5a, in order to improve the transmittance of the first optical area DA1, the first horizontal line HL1 passing through the first optical area DA1 can pass by avoiding the first transmission area within the first optical area DA1.

[0199] Therefore, each of the first horizontal lines HL1 passing through the first optical regions DA1 may include a curved section or a bending section that detours around the outside of the outer frame of each of the first transmission regions.

[0200] As a result, the first horizontal line HL1 arranged in the first horizontal region HA1 and the second horizontal line HL2 arranged in the second horizontal region HA2 may have different patterns, lengths, etc. In other words, the first horizontal line HL1 passing through the first optical region DA1 and the second horizontal line HL2 not passing through the first optical region DA1 may have different patterns, lengths, etc.

[0201] In addition, in order to improve the transmittance of the first optical area DA1, the first vertical line VL1 passing through the first optical area DA1 can pass while avoiding the first transmission area within the first optical area DA1.

[0202] Therefore, each of the first vertical lines VL1 passing through the first optical area DA1 may include a curved section or a bending section that detours around the outside of the outer frame of each first transmission area.

[0203] Accordingly, the first vertical line VL1 passing through the first optical region DA1 and the general vertical line VLn arranged in the general region without passing through the first optical region DA1 may have different patterns or lengths.

[0204] Referring to FIG. 5a, the first transmission areas included in the first optical area DA1 in the first horizontal region HA1 may be arranged in a diagonal direction.

[0205] 5a, in the first optical region DA1 in the first horizontal region HA1, a light emitting region may be disposed between two first transmissive regions adjacent to each other in the left and right direction. In the first optical region DA1 in the first horizontal region HA1, a light emitting region may be disposed between two first transmissive regions adjacent to each other in the up and down direction.

[0206] Referring to FIG. 5a, the first horizontal line HL1 arranged in the first horizontal region HA1, i.e., the first horizontal line HL1 passing through the first optical region DA1, may include at least one curved or bending section that detours outside the outer frame of the first transmission region.

[0207] 5b, the second optical region DA2 included in the first horizontal region HA1 may include a light emitting region and a second transmissive region TA2. Within the second optical region DA2, an outer region of the second transmissive region TA2 may include a light emitting region.

[0208] The positions and arrangement of the light emitting region and the second transmission region TA2 in the second optical region DA2 may be the same as the positions and arrangement of the light emitting region and the second transmission region in the first optical region DA1 in FIG. 5a.

[0209] Alternatively, as shown in FIG. 5b, the position and arrangement of the light-emitting region and the second transmission region TA2 in the second optical region DA2 may be different from the position and arrangement of the light-emitting region and the second transmission region in the first optical region DA1 in FIG. 5a.

[0210] For example, referring to Fig. 5b, in the second optical region DA2, the second transmission regions TA2 may be arranged in the horizontal direction (left-right direction). A light-emitting region may not be arranged between two second transmission regions TA2 adjacent in the horizontal direction (left-right direction). Also, a light-emitting region in the second optical region DA2 may be arranged between the second transmission regions TA2 adjacent in the vertical direction (up-down direction). That is, a light-emitting region may be arranged between two rows of the second transmission regions TA2.

[0211] When the first horizontal line HL1 passes through the second optical area DA2 in the first horizontal area HA1 and the general area therearound, it may follow the same form as in FIG. 5a.

[0212] Alternatively, as shown in FIG. 5b, the first horizontal line HL1 may have a different shape from that of FIG. 5a when passing through the second optical area DA2 in the first horizontal area HA1 and the surrounding general area.

[0213] That is, the positions and arrangement of the light emitting region and the second transmission region TA2 in the second optical region DA2 in FIG. 5b are different from the positions and arrangement of the light emitting region and the second transmission region in the first optical region DA1 in FIG. 5a.

[0214] Referring to FIG. 5b, when the first horizontal line HL1 passes through the second optical area DA2 in the first horizontal region HA1 and the surrounding general area, it can pass in a straight line between the adjacent second transmission areas TA2 above and below without any curved or bent sections.

[0215] In other words, one first horizontal line HL1 may have a curved section or a bending section in the first optical area DA1 but may not have a curved section or a bending section in the second optical area DA2.

[0216] To improve the transmittance of the second optical area DA2, the second vertical line VL2 passing through the second optical area DA2 can pass by avoiding the second transmission area TA2 within the second optical area DA2.

[0217] Therefore, each of the second vertical lines VL2 passing through the second optical area DA2 may include a curved section or a bending section that detours around the outside of the outer frame of each of the second transmission areas TA2.

[0218] Accordingly, the second vertical line VL2 passing through the second optical region DA2 and the general vertical line VLn arranged in the general region without passing through the second optical region DA2 may have different patterns or lengths.

[0219] As shown in FIG. 5a, the first horizontal line HL1 passing through the first optical area DA1 may have a curved or bent section that detours around the outside of the outline of the first transmission area.

[0220] Therefore, the length of the first horizontal line HL1 passing through the first optical area DA1 and the second optical area DA2 may be slightly longer than the length of the second horizontal line HL2 that is arranged only in the general area without passing through the first optical area DA1 and the second optical area DA2.

[0221] As a result, the resistance of the first horizontal line HL1 (hereinafter also referred to as the first resistance) passing through the first optical area DA1 and the second optical area DA2 may be slightly larger than the resistance of the second horizontal line HL2 (hereinafter also referred to as the second resistance) which does not pass through the first optical area DA1 and the second optical area DA2 and is arranged only in the general area.

[0222] Referring to Figures 5a and 5b, due to the light transmission structure, the first optical region DA1, which is at least partially overlapped with the first optical electronic device, includes a plurality of first transmission regions, and the second optical region DA2, which is at least partially overlapped with the second optical electronic device, includes a plurality of second transmission regions TA2, so that the first optical region DA1 and the second optical region DA2 may have a smaller number of sub-pixels per unit area than a general region.

[0223] The number of sub-pixels to which the first horizontal line HL1 passing through the first optical region DA1 and the second optical region DA2 is connected and the number of sub-pixels to which the second horizontal line HL2, which does not pass through the first optical region DA1 and the second optical region DA2 but is arranged only in the general region, are connected may be different from each other.

[0224] The number (first number) of sub-pixels to which a first horizontal line HL1 passing through the first optical region DA1 and the second optical region DA2 is connected may be less than the number (second number) of sub-pixels to which a second horizontal line HL2 is connected that is arranged only in the general region without passing through the first optical region DA1 and the second optical region DA2.

[0225] The difference between the first and second numbers may vary depending on the difference between the resolution of the first and second optical regions DA1 and DA2 and the resolution of the general region. For example, the greater the difference between the resolution of the first and second optical regions DA1 and DA2 and the resolution of the general region, the greater the difference between the first and second numbers may be.

[0226] As described above, since the number (first number) of sub-pixels to which the first horizontal line HL1 passing through the first optical region DA1 and the second optical region DA2 is connected is smaller than the number (second number) of sub-pixels to which the second horizontal line HL2 is connected, which does not pass through the first optical region DA1 and the second optical region DA2 and is arranged only in the general region, the area in which the first horizontal line HL1 overlaps with other surrounding electrodes and lines may be smaller than the area in which the second horizontal line HL2 overlaps with other surrounding electrodes and lines.

[0227] Therefore, the parasitic capacitance (hereinafter referred to as the first capacitance) formed by the first horizontal line HL1 with other surrounding electrodes or lines may be larger or smaller than the parasitic capacitance (hereinafter referred to as the second capacitance) formed by the second horizontal line HL2 with other surrounding electrodes or lines.

[0228] When considering the magnitude relationship between the first resistance and the second resistance (first resistance ≧ second resistance) and the magnitude relationship between the first capacitance and the second capacitance (first capacitance << second capacitance), the RC (Resistance-Capacitance) value (hereinafter also referred to as the first RC value) of the first horizontal line HL1 passing through the first optical area DA1 and the second optical area DA2 may be much smaller than the RC value (hereinafter also referred to as the second RC value) of the second horizontal line HL2 arranged only in the general area without passing through the first optical area DA1 and the second optical area DA2 (first RC value << second RC value).

[0229] The difference between the first RC value of the first horizontal line HL1 and the second RC value of the second horizontal line HL2 (hereinafter referred to as RC Load deviation) may change the signal transmission characteristics through the first horizontal line HL1 and the signal transmission characteristics through the second horizontal line HL2.

[0230] In the following, reference is made jointly to FIGS. 2 to 4 for a more detailed explanation of the general area NA of the display device 100. FIG.

[0231] Figure 6 is a schematic plan view of an enlarged general area NA of the display device of Figures 1a to 1d, Figure 7 is a schematic cross-sectional view along line VII-VII' of Figure 6, and Figure 8 is a schematic cross-sectional view along line VIII-VIII' of Figure 1a.

[0232] For convenience of explanation, only a plurality of sub-pixels SP and a plurality of touch electrodes are shown in FIG.

[0233] The general area NA may include a plurality of sub-pixels SP. The sub-pixels SP are the minimum units constituting a screen, and may include a plurality of light-emitting elements ED, 120 corresponding to the sub-pixels SP, respectively. That is, the sub-pixels SP may be arranged to correspond to a plurality of light-emitting elements ED, 120, respectively, and thus the sub-pixels SP may also be expressed as a plurality of light-emitting elements ED, 120. Each of the sub-pixels SP may emit light having a different wavelength. For example, the sub-pixels SP may include a red sub-pixel SPR, a green sub-pixel SPG, and a blue sub-pixel SPB. However, without being limited thereto, the sub-pixels SP may further include a white sub-pixel.

[0234] The touch electrodes 140 may be arranged between the sub-pixels SP in the general region NA, each having a mesh pattern that intersects with each other, so that a user's touch input can be sensed on the upper surfaces of the sub-pixels SP arranged in the general region.

[0235] In the following, reference will be made to both FIG. 7 and FIG. 8 for a more detailed description of the cross-sectional structure of the general area NA of the display device 100. FIG.

[0236] In the general region NA, a transistor layer TRL may be disposed on the substrate SUB, and a planarization layer PLN may be disposed on the transistor layer TRL. Also, a light emitting element layer EDL may be disposed on the planarization layer PLN, an encapsulation layer ENCAP may be disposed on the light emitting element layer EDL, a touch sensing layer TSL may be disposed on the encapsulation layer ENCAP, and a protective layer PAC may be disposed on the touch sensing layer TSL. Also, an organic layer PCL may be disposed on the protective layer PAC, and a polarizing layer POL may be disposed on the organic layer PCL.

[0237] The substrate SUB is configured to support various components included in the display device 100, and may be made of an insulating material. The substrate SUB may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. By configuring the substrate SUB with the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c in this manner, it is possible to prevent moisture penetration. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates.

[0238] In the general region NA, the transistor layer TRL may be arranged with various patterns 131, 132, 133, 134, 231, 232, 233, 234 for forming transistors such as a driving transistor Td and at least one switching transistor Ts, and at least one capacitor, various insulating films 111a, 111b, 112, 113a, 113b, 114, and various metal patterns TM, GM, 135.

[0239] The stacked structure of the transistor layer TRL will be described in further detail below.

[0240] A multi-buffer layer 111a may be disposed on the second substrate 110b, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0241] A metal layer 135 may be disposed on the multi-buffer layer 111a.

[0242] Here, the metal layer 135 can function as a light shield and can also be referred to as a light blocking layer.

[0243] An active buffer layer 111b may be disposed on the metal layer 135.

[0244] A first active layer 134 of the driving transistor Td may be disposed on the active buffer layer 111b. For example, the first active layer 134 may be formed of polycrystalline silicon (p-Si), amorphous silicon (a-Si), or an oxide semiconductor, but is not limited thereto. Meanwhile, the driving transistor Td is formed on the active buffer layer 111b and includes the first active layer 134, a first gate insulating film 112 covering the first active layer 134, a first gate electrode 131 disposed on the first gate insulating film 112, a first interlayer insulating film 113a covering the first gate electrode 131, a second gate insulating film 113b disposed on the first interlayer insulating film 113a, a third interlayer insulating film 113c disposed on the second gate insulating film 113b, and a first source electrode 132 and a first drain electrode 133 disposed on the third interlayer insulating film 113c.

[0245] A first gate insulating film 112 may be disposed on the first active layer 134. The first gate insulating film 112 may be made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

[0246] In addition, a first gate electrode 131 of the driving transistor Td may be disposed on the first gate insulating film 112. The first gate electrode 131 is disposed on the first gate insulating film 112 to overlap with the first active layer 134. The first gate electrode 131 may be formed of various conductive materials, for example, magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, but is not limited thereto.

[0247] A gate material layer GM may be disposed on the first gate insulating film 112 at a position different from the position where the driving transistor Td is formed.

[0248] A first interlayer insulating film 113a may be disposed on the first gate electrode 131 and the gate material layer GM. A metal pattern TM may be disposed on the first interlayer insulating film 113a. A second interlayer insulating film 113b may be disposed to cover the metal pattern TM disposed on the first interlayer insulating film 113a.

[0249] The second interlayer insulating film 113b separates the second active layer 234 from the first active layer 134 and provides a base on which the second active layer 234 can be formed.

[0250] A second active layer 234 of the switching transistor Ts may be disposed on the second interlayer insulating film 113b. For example, the second active layer 234 may be formed of polycrystalline silicon, amorphous silicon, or an oxide semiconductor, but is not limited thereto.

[0251] A second gate insulating film 113c may be disposed on the second active layer 234. In addition, a second gate electrode 231 of the switching transistor Ts may be disposed on the second gate insulating film 113c. The second gate electrode 231 is disposed so as to overlap the second active layer 234 on the second gate insulating film 113c.

[0252] The second gate insulating film 113c covers the second active layer 234 of the switching transistor Ts. The second gate insulating film 113c is embodied as an inorganic film since it is formed on the second active layer 234. For example, the second gate insulating film 113c may be silicon oxide (SiO2), silicon nitride (SiNx), or a composite layer thereof.

[0253] The second gate electrode 231 is made of a metal material, and may be, for example, a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0254] On the other hand, the switching transistor Ts is formed on the second interlayer insulating film 113b, and includes a second active layer 234, a second gate insulating film 113c covering the second active layer 234, a second gate electrode 231 arranged on the second gate insulating film 113c, a third interlayer insulating film 113c covering the second gate electrode 231, and a second source electrode 232 and a second drain electrode 233 arranged on the third interlayer insulating film 113c.

[0255] The switching transistor Ts further includes a gate material layer GM located under the first interlayer insulating film 113a and overlapping the second active layer 234. The gate material layer GM can block light incident on the second active layer 234 to ensure reliability of the switching transistor Ts. The gate material layer GM may be formed of the same material as the first gate electrode 131 and formed on an upper surface of the first gate insulating film 112. The gate material layer GM may be electrically connected to the second gate electrode 234 to form a dual gate. A first source electrode 132 and a first drain electrode 133 of the driving transistor Td and a second source electrode 232 and a second drain electrode 233 of the switching transistor Ts may be disposed on the third interlayer insulating film 113d.

[0256] The second source electrode 232 and the second drain electrode 233 are simultaneously formed with the first source electrode 132 and the first drain electrode 133 using the same material on the third interlayer insulating film 113d, thereby reducing the number of mask processes.

[0257] The first source electrode 132 and the first drain electrode 133 may be connected to one side and the other side of the first active layer 134, respectively, through contact holes provided in the third interlayer insulating film 113d, the second gate insulating film 113c, the second interlayer insulating film 113b, the first interlayer insulating film 113a and the first gate insulating film 112.

[0258] The second source electrode 232 and the second drain electrode 233 may be connected to one side and the other side of the second active layer 234 through contact holes formed in the third interlayer insulating layer 113d and the second gate insulating layer 113c, respectively.

[0259] The first source electrode 132 and the first drain electrode 133 and the second source electrode 232 and the second drain electrode 233 may be a single layer or multiple layers made of various conductive materials, such as, but not limited to, magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof.

[0260] A portion of the first active layer 134 overlapping with the first gate electrode 131 is a channel region. One of the first source electrode 132 and the first drain electrode 133 is connected to one side of the channel region in the first active layer 134, and the remaining one is connected to the other side of the channel region in the first active layer 134. The second active layer 234 may be configured in the same shape as the first active layer 134, and when the second active layer 234 is embodied with an oxide semiconductor material, it includes an intrinsic second channel region that is not doped with impurities, and second source and drain regions that are doped with impurities to be conductive.

[0261] A passivation layer 114 may be disposed on the first source electrode 132, the first drain electrode 133, and the second source electrode 232, and the second drain electrode 233. The passivation layer 114 is for protecting the driving transistor Td, and may be made of an inorganic film, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a composite layer thereof.

[0262] Meanwhile, the capacitor Cst may be implemented by arranging the gate material layer GM and the metal pattern TM to overlap on the first gate insulating film 112. The metal pattern TM may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0263] The capacitor Cst stores the data voltage applied through the data line DL for a certain period of time and then provides the data voltage to the light emitting element ED, 120. The capacitor Cst includes two electrodes corresponding to each other and a dielectric disposed therebetween. A first interlayer insulating film 113a is disposed between the gate material layer GM and the metal pattern TM.

[0264] In the capacitor Cst, the gate material layer GM or the metal pattern TM may be electrically connected to the switching transistor Ts, the second source electrode 232, or the second drain electrode 233. However, the present invention is not limited thereto, and the connection relationship of the capacitor Cst may be changed according to the pixel driving circuit.

[0265] Also, a metal layer 135 may be disposed on the multi-buffer layer 111a so as to overlap the gate material layer GM and the metal pattern TM to form a double capacitor Cst.

[0266] In the embodiments of the present specification, at least one switching transistor Ts uses an oxide semiconductor as an active layer. A transistor using an oxide semiconductor as an active layer has a good effect of blocking leakage current and is relatively inexpensive to manufacture compared to a transistor using polysilicon as an active layer. Therefore, in order to reduce power consumption and manufacturing costs, the pixel circuit according to the embodiments of the present specification includes a driving transistor or at least one switching transistor using an oxide semiconductor material.

[0267] All of the transistors constituting the pixel circuit, including the driving transistor, may be formed using an oxide semiconductor to form an active layer, or only some of the transistors may be formed using an oxide semiconductor.

[0268] However, since it is difficult to ensure the reliability of a transistor using an oxide semiconductor, and a transistor using polycrystalline silicon has high operating speed and excellent reliability, the examples in this specification include both a transistor using an oxide semiconductor and a transistor using polycrystalline silicon, but are not limited thereto, and a pixel circuit can be configured by using only transistors using an oxide semiconductor or only transistors using polycrystalline silicon depending on the design.

[0269] A planarization layer PLN may be located on top of the transistor layer TRL.

[0270] The planarization layer PLN may include a first planarization layer 115a and a second planarization layer 115b. The planarization layer PLN protects the driving transistor Td and planarizes the upper portion thereof.

[0271] A first planarization layer 115 a may be disposed on the passivation layer 114 .

[0272] A connecting electrode 125 may be disposed on the first planarization layer 115a.

[0273] The connecting electrode 125 may be connected to one of the first source electrode 132 and the first drain electrode 133 through a contact hole formed in the first planarization layer 115a.

[0274] A second planarization layer 115b may be disposed on the connecting electrode 125.

[0275] The light emitting element layer EDL may be located on the second planarization layer 115b.

[0276] The laminated structure of the light emitting element layer EDL will be considered in detail below.

[0277] The anode 121 may be disposed on the second planarization layer 115b. In this case, the anode 121 may be electrically connected to the connecting electrode 125 through a contact hole provided in the second planarization layer 115b. The anode 121 may be formed of a metallic material.

[0278] In the case where the display device 100 is a top emission type in which light emitted from the light emitting element ED, 120 is emitted to the top of the substrate SUB on which the light emitting element ED, 120 is disposed, the anode 121 may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be made of a transparent conductive oxide such as ITO or IZO, and the reflective layer may be made of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0279] The bank 116 may be disposed to cover the anode 121. A portion of the bank 116 corresponding to a light emitting region of the sub-pixel may be open. A portion of the anode 121 may be exposed in the open portion of the bank 116 (hereinafter, referred to as the open region). In this case, the bank 116 may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as a benzocyclobutene-based resin, an acrylic resin, or an imide-based resin, but is not limited thereto.

[0280] Although not shown, a spacer may further be located on the bank 116. The spacer may be made of the same material as the bank 116.

[0281] Light-emitting layer 122 may be disposed in and around the open areas of bank 116. This allows light-emitting layer 122 to be disposed on anode 121 exposed through the open areas of bank 116.

[0282] A cathode 123 may be disposed on the light-emitting layer 122 .

[0283] The anode 121, the light emitting layer 122 and the cathode 123 may form a light emitting element ED, 120. The light emitting layer 122 may include a number of organic films.

[0284] An encapsulation layer ENCAP may be located on top of the light emitting element layer EDL.

[0285] The encapsulation layer ENCAP may have a single-layer structure or a multi-layer structure. For example, the encapsulation layer ENCAP may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0286] In this case, the first and third sealing layers 117a and 117c may be made of an inorganic film, and the second sealing layer 117b may be made of an organic film. Among the first, second and third sealing layers 117a, 117b and 117c, the second sealing layer 117b is the thickest and may serve as a planarization layer.

[0287] The first encapsulation layer 117a may be disposed on the cathode 123 and may be disposed closest to the light emitting element ED, 120. The first encapsulation layer 117a may be formed of an inorganic insulating material that can be deposited at low temperatures. For example, the first encapsulation layer 117a may be composed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. Since the first encapsulation layer 117a is deposited in a low temperature atmosphere, it is possible to prevent the light emitting layer 122, which includes organic matter that is vulnerable to high temperature atmospheres, from being damaged during the deposition process.

[0288] The second encapsulation layer 117b may be formed to have a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be formed to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b may play a role of buffering to relieve stress between layers due to warping of the flexible display device and to enhance planarization performance.

[0289] For example, the second sealing layer 117b may be made of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon oxycarbon (SiOC), etc. For example, the second sealing layer 117b may be formed through an inkjet method, but is not limited thereto.

[0290] Although not shown, a color filter may be disposed on the encapsulation layer ENCAP.

[0291] Referring to FIG. 8, a first dam DAM1 may be disposed in the non-display area NDA to block the flow of the second encapsulation layer 117b constituting the encapsulation layer ENCAP. One or more first dams DAM1 may be disposed at or near the end of the inclined surface of the encapsulation layer ENCAP to prevent the encapsulation layer ENCAP from collapsing. One or more first dams DAM1 may be disposed at or near the boundary between the display area DA and the non-display area NDA. The first dam DAM1 may be formed of at least one layer made of an organic material. For example, the first dam DAM1 may include, but is not limited to, a lower layer made of the same material as the second planarization layer 115b and an upper layer made of the same material as the bank 116. In addition, the height of the first dam DAM1 may be further adjusted by adding a layer made of the same material as the spacer on the upper layer, but is not limited to this.

[0292] The second sealing layer 117b containing an organic substance may be located only on the inner surface of the innermost dam of the first dam DAM1. That is, the second sealing layer 117b may not be present on the upper part of all dams. In contrast, the second sealing layer 117b containing an organic substance may be located on at least the upper part of the innermost dam of the first dam DAM1. That is, the second sealing layer 117b may be located so as to extend to the upper part of the innermost dam of the first dam DAM1. Alternatively, the second sealing layer 117b may be located so as to extend through the upper part of at least the innermost dam of the first dam DAM1 to the upper part of the dam located on the outer side of the first dam DAM1.

[0293] The third encapsulation layer 117c may be formed on the substrate SUB on which the second encapsulation layer 117b is formed, to cover the top and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a. At this time, the third encapsulation layer 117c may minimize or block external moisture or oxygen from penetrating into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0294] A touch sensing layer TSL may be disposed on top of the encapsulation layer ENCAP mentioned above.

[0295] A touch buffer film 118a may be disposed on top of the encapsulation layer ENCAP, and a touch electrode 140 may be disposed on the touch buffer film 118a.

[0296] The touch electrode 140 may include a touch sensor electrode 141 and a bridge electrode 142 located in different layers. Between the touch sensor electrode 141 and the bridge electrode 142, a touch interlayer insulating film 118b may be disposed.

[0297] For example, the touch sensor electrode 141 may include a first touch sensor electrode, a second touch sensor electrode, and a third touch sensor electrode arranged adjacent to each other. For example, the first touch sensor electrode and the second touch sensor electrode may be arranged in a first direction, while the third touch sensor electrode may be arranged in a second direction intersecting the first touch sensor electrode and the second touch sensor electrode. The first touch sensor electrode and the second touch sensor electrode are electrically connected to each other, but when a third touch sensor electrode arranged in a second direction intersecting the first direction is present between the first touch sensor electrode and the second touch sensor electrode arranged in the first direction, the first touch sensor electrode and the second touch sensor electrode may be electrically connected through a bridge electrode 142 in another layer. The bridge electrode 142 may be insulated from the third touch sensor electrode by the touch interlayer insulating film 118b.

[0298] In other words, in order to prevent the multiple touch electrodes arranged in the first and second directions from being short-circuited to each other in the areas where they intersect with each other, the multiple touch electrodes extending in the first direction may be electrically connected to each other through the bridge electrode 142.

[0299] When the touch sensing layer TSL is formed, a chemical solution (such as a developer or an etchant) used in the process or moisture from the outside may be generated. By disposing the touch buffer film 118a and disposing the touch sensing layer TSL thereon, it is possible to prevent the chemical solution, moisture, etc., used during the manufacture of the touch sensing layer TSL from penetrating into the light emitting layer 122 containing an organic substance. As a result, the touch buffer film 118a can prevent damage to the light emitting layer 122, which is vulnerable to the chemical solution or moisture.

[0300] The touch buffer film 118a may be formed of an organic insulating material having a low dielectric constant of 1 to 3 and may be formed at a certain temperature (e.g., a low temperature of 100° C. or less) to prevent damage to the light emitting layer 122 including an organic material vulnerable to high temperatures. For example, the touch buffer film 118a may be formed of an acrylic, epoxy, or siloxane-based material. The encapsulation layer ENCAP may be damaged and the touch sensor electrode 141 located on the touch buffer film 118a may be cracked due to warping of the flexible display device. Even if the flexible display device is warped, the touch buffer film 118a made of an organic insulating material and having a planarization performance can prevent damage to the encapsulation layer ENCAP and cracking of the touch sensor electrode 141 and bridge electrode 142 constituting the plurality of touch electrodes 140.

[0301] A protective layer PAC, 119 may be disposed to cover the multiple touch electrodes 140. The protective layer 119 may be composed of an organic insulating film.

[0302] An organic layer PCL, 150 is disposed so as to cover the protective layer 119 .

[0303] If only the protective layer 119 made of an organic insulating film is disposed on the top layer of the display device 100, the protective layer 119 alone cannot completely compensate for the step caused by the touch sensing layer TSL disposed below the protective layer 119, and a problem may occur in which a user may see spots caused by multiple touch electrodes 140.

[0304] By adding an organic layer 150 made of an organic insulating film on the upper part of the protective layer 119, a step is prevented from occurring at the topmost layer of the display device 100, and the visibility of the display device 100 can be improved.

[0305] The organic layer 150 may be formed of the same material as the second encapsulation layer 117b of the encapsulation layer ENCAP, and may be made of an organic insulating material such as, for example, acrylic resin, epoxy resin, polyimide, polyethylene, silicon oxycarbonate (SiOC), etc. The organic layer 150 may be formed by an inkjet method, but is not limited thereto.

[0306] 8, a second dam DAM2 may be further included on the outer periphery of the first dam DAM1 disposed in the non-display area NDA. For example, the second dam DAM2 may be formed in the same layer and of the same material as the protective layer 119. The height of the second dam DAM2 may be higher than the height of the first dam DAM1, and the organic layer 150 may be prevented from flowing to a pad disposed in the non-display area NDA.

[0307] On the organic layer 150, a polarizing layer POL, 160 is disposed.

[0308] The polarizing layer 160 suppresses reflection of external light on the display area DA of the substrate SUB. When the display device 100 is used outdoors, external natural light enters and may be reflected by a reflective layer included in the anode 121 of the light emitting element, or by an electrode made of metal disposed under the light emitting element ED, 120. Images displayed on the display device 100 may be obscured due to the reflected light. The polarizing layer 160 polarizes the light entering from the outside in a specific direction and prevents the reflected light from being emitted outside the display device 100.

[0309] Although not shown, a cover glass may be attached by an adhesive layer on the polarizing layer 160. The adhesive layer may serve to bond each component of the display device 100 to each other, and may be formed using an optically transparent adhesive for displays, such as, but not limited to, a pressure sensitive adhesive, an optical clear adhesive (OCR), an optical clear resin (OCR), etc.

[0310] The cover glass protects the components of the display device 100 from external impacts and can prevent damage such as scratches.

[0311] In the following, reference is made to both FIG. 9 and FIG. 10 for a more detailed description of the first optical area DA1 of the display device 100. FIG.

[0312] Fig. 9 is a schematic plan view showing an enlarged first optical area DA1 of the display device of Fig. 1a, and Fig. 10 is a schematic cross-sectional view taken along line XX' of Fig. 5.

[0313] In FIG. 9, for convenience of explanation, only a plurality of transmissive regions, a plurality of sub-pixels and a plurality of touch electrodes are shown.

[0314] 9 and 10, the first optical area DA1 may include a plurality of transmissive areas TA and a plurality of sub-pixels SP surrounding the transmissive areas.

[0315] The transmissive region TA of the first optical region DA1 and the sub-pixels SP surrounding the transmissive region TA can basically include a substrate SUB, a transistor layer TRL, a planarization layer PLN, a light-emitting element layer EDL, an encapsulation layer ENCAP, a touch sensor layer TSL, a protective layer PAC, an organic layer PCL, and a polarizing layer POL. The substrate SUB, the transistor layer TRL, the planarization layer PLN, the light-emitting element layer EDL, the encapsulation layer ENCAP, the touch sensor layer TSL, the protective layer PAC, the organic layer PCL, and the polarizing layer POL included in the first optical region DA1 are substantially the same as the components having the same reference numerals arranged in the general region NA of the display panel DP, and therefore will not be described again.

[0316] First, the transmission area TA arranged in the first optical area DA1 will be described.

[0317] The transmissive areas TA of the first optical region DA1 refer to areas where the cathode 123 exposes the banks 116. For example, the transmissive areas TA are areas where an opaque structure such as the cathode 123 is removed to allow external light to be transmitted to the optical-electronic device 170.

[0318] Specifically, the substrate SUB and various insulating films 111a, 111b, 112, 113a, 113b, 114, 115a, 115b, 117a, 117b, 117c, and PAC arranged in one sub-pixel SPG1 of the first optical region DA1 may be identically arranged in the transmission region TA of the first optical region DA1.

[0319] However, in the area of ​​one subpixel SPG1 of the first optical region DA1, a material layer having electrical properties or opaque properties (e.g., a metal material layer, a semiconductor layer, etc.) other than an insulating material may not be disposed in the transmissive region TA of the first optical region DA1.

[0320] For example, not only the cathode 123 included in the light emitting element ED, 120, but also the metal layers 135, 131, GM, TM, 132, 133, 125 and the semiconductor layer 134 associated with the transistors are not disposed in the transparent region TA. Also, the anode 121 included in the light emitting element ED, 120 may not be disposed in the transparent region TA. The light emitting layer 122 may or may not be disposed in the transparent region TA. Also, the plurality of touch electrodes are not disposed in the transparent region TA. However, the present invention is not limited thereto.

[0321] That is, since the transmissive area TA of the first optical region overlaps with the optical electronic device 170, in order to ensure normal operation of the optical electronic device 170, the transmittance of the transmissive area TA can be increased by not disposing opaque components such as metal electrodes in the transmissive area TA.

[0322] Next, a region in which one sub-pixel SPG1 adjacent to one transmission region TA among the plurality of sub-pixels SP that are disposed in the first optical region DA1 and surround the plurality of transmission regions TA will be described.

[0323] The area in which one sub-pixel SPG1 adjacent to one transmissive area TA in the first optical area DA1 is arranged has substantially the same structure as the general area NA of the display panel DP, except for the touch sensing layer TSL including a plurality of touch electrodes, so duplicated explanations will be omitted.

[0324] Each of the sub-pixels SP surrounding the transmission regions TA may include a light-emitting element ED, 120 and a driving circuit. That is, the sub-pixels SP may be arranged to correspond to the light-emitting elements ED, 120, respectively, and thus the sub-pixels SP may also be expressed as the light-emitting elements ED, 120.

[0325] Conventionally, when a plurality of transmissive regions and a plurality of sub-pixels are arranged in the first optical region, a plurality of touch electrodes are arranged in a crossing shape between the plurality of sub-pixels, and the crossing touch electrodes arranged between the plurality of sub-pixels only avoid the plurality of transmissive regions. That is, conventionally, the plurality of transmissive regions and the crossing touch electrodes are very close to each other. However, in this case, there is a problem that the plurality of touch electrodes are present between the plurality of sub-pixels in the first optical region, and the touch lines hide the plurality of sub-pixels, thereby deteriorating the visual characteristics. In addition, there is a problem that the plurality of transmissive regions are vulnerable to touch noise because the interval between the plurality of transmissive regions and the plurality of touch electrodes is narrow.

[0326] Therefore, in the display device 100 according to the embodiment of the present invention, the sub-pixels SP arranged in the first optical region DA1 are grouped into a plurality of sub-pixel groups PG surrounding a plurality of transmissive regions TA, and the touch electrodes 140 in the first optical region DA1 are arranged to form a closed curve surrounding one of the transmissive regions TA and one of the sub-pixel groups PG. In other words, one transmissive region TA and one sub-pixel group PG may be configured as one group G.

[0327] For example, the subpixel groups PG surrounding the transmissive regions TA may each include a red subpixel SPR, a first green subpixel SPG1, a blue subpixel SPB, and a second green subpixel SPG2.

[0328] The multiple touch electrodes 140 arranged in the first optical area DA1 may be in the form of a closed curve having an “x”-shaped or “+”-shaped mesh pattern surrounding one of the multiple transmissive areas TA and one of the multiple sub-pixel groups PG, i.e., one group G.

[0329] In the first optical region DA1, a touch electrode 140 is not arranged between one of the plurality of transmissive regions TA and one of the plurality of subpixel groups PG, i.e., between the transmissive region TA and the plurality of subpixels SP within one group G, so that the phenomenon of hiding the subpixel SP in the transmissive region TA can be improved, thereby improving the visibility of the display device 100.

[0330] In FIG. 9, the transmissive area TA is shown to be circular; however, the shape of the transmissive area TA may be any shape that minimizes contact with the multiple touch electrodes 140, and may be, for example, a circle, a triangle, an ellipse, a rectangle, a polygon, or the like.

[0331] In addition, the touch electrode 140 is arranged to surround one group G, and is spaced apart from the multiple transmissive areas TA by a certain distance or more, thereby reducing the problem of touch noise that may occur when multiple transmissive areas TA and multiple touch electrodes 140 are adjacent to each other.

[0332] However, referring to FIG. 9, even if the touch electrodes 140 are arranged to surround one group G, there may be an area Y in which a plurality of transmissive areas TA and a plurality of touch electrodes 140 are adjacent to each other within the first optical area DA1.

[0333] Touch noise may occur in an area Y where the plurality of transmissive areas TA of the first optical area DA1 are adjacent to the plurality of touch electrodes 140. If the plurality of transmissive areas TA are reduced to solve this problem, the transmittance of the first optical area DA1 may be reduced, limiting the operation of the optical electronic device 170, such as a camera or a sensor.

[0334] Therefore, in the display device 100 according to one embodiment of the present invention, the multiple transmissive regions TA ensure the transmittance for the optical electronic device 170 to operate normally, while the multiple shielding patterns 145 are disposed between the encapsulation portion ENCAP and the multiple touch electrodes 140.

[0335] The shielding patterns 145 are grounded to effectively shield touch noise that may occur when the transmissive areas TA are adjacent to the touch electrodes 140. In particular, the shielding patterns 145 are connected to a ground line GND to which a ground voltage is applied, and can receive a ground voltage. Thus, the shielding patterns 145 can serve as a ground for blocking touch noise during touch driving. This will be described in detail below with reference to FIGS. 11a to 11d.

[0336] The shielding patterns 145 may be arranged to overlap the touch electrodes 140, particularly in a boundary region of the transmissive area TA and one of the sub-pixels SP adjacent to the transmissive area TA.

[0337] Therefore, touch noise signals that may occur when the transmissive area TA and the touch electrodes 140 are adjacent to each other are shielded by the shielding patterns 145, so that the generation of touch noise in the display device 100 can be prevented.

[0338] The multiple shielding patterns 145 may be disposed in the same layer and of the same material as the bridge electrodes 142 disposed in the general area NA.

[0339] Accordingly, when forming the plurality of shielding patterns 145, the plurality of shielding patterns 145 can be formed using the same mask as that for the bridge electrode 142 without the application of an additional mask, thereby reducing process steps and costs.

[0340] A width of the plurality of shielding patterns 145 may be equal to or greater than a width of the plurality of touch electrodes 140. When a width of the plurality of shielding patterns 145 is greater than a width of the plurality of touch electrodes 140, a touch noise shielding effect by the plurality of shielding patterns 145 may be further improved.

[0341] In the following, reference is made to both FIGS. 11a to 11d for a more detailed explanation of the grounding of the shielding patterns 145. FIG.

[0342] Figure 11a is a schematic plan view showing region X of Figure 1a, Figure 11b is a schematic plan view showing region A of Figure 11a, Figure 11c is a schematic plan view showing region B of Figure 11a, and Figure 11d is a cross-sectional view taken along line XI-XI' of Figure 11c.

[0343] 11a and 11b, a ground line GND disposed in the non-display area NDA may be connected to the general area NA and the optical electronic device 170 overlapping the first optical area DA1 through a connection line CL.

[0344] Specifically, the ground line GND may extend from the non-display area NDA and be electrically connected to the connection line CL.

[0345] In this case, the ground line GND may be disposed in the same layer as the plurality of touch electrodes 141 and may be made of the same material, and the connection line CL may be disposed in the same layer as the ground line GND and may be made of the same material.

[0346] In other words, the connection line CL may be electrically connected to the ground line GND arranged in the non-display area NDA and may be branched off from the ground line GND.

[0347] Hereinafter, the connection of the ground line GND in the connection region B of the first optical region DA1 and the general region NA will be described with reference to FIG. 11c and FIG. 11d.

[0348] In the general area NA, the ground line GND is formed in the same layer as the plurality of touch electrodes 140, and a connection line CL branched from the ground line GND is connected to the optical electronic device 170 overlapping the first optical area DA1.

[0349] Through a contact hole CH arranged at the boundary between the first optical area DA1 and the general area NA, i.e., the connection area (area B), a connection line CL branched off from the ground line GND may contact a plurality of shielding patterns 145 arranged in the first optical area DA1.

[0350] As a result, the ground line GND arranged in the non-display area NDA is electrically connected to the plurality of shielding patterns 145 arranged in the first optical area DA1 and can receive a ground voltage. Therefore, the plurality of shielding patterns 145 act as a ground for blocking touch noise during touch driving, and can effectively block touch noise.

[0351] The above-mentioned effects of the present invention will be described in more detail below through examples and comparative examples. However, the following examples are merely for illustration of the present invention, and the scope of the present invention is not limited by the following examples.

[0352] FIG. 12 shows simulation results of display touch noise (DTN) according to the embodiment and the comparative example of the present invention.

[0353] In order to examine the effects of the present invention, a display device having a structure in which a plurality of shielding patterns are arranged to overlap a plurality of touch electrodes adjacent to a plurality of transmissive regions in a first optical region, as shown in FIG. 10, was manufactured as an embodiment of the present invention, and a display device having a structure in which only a plurality of touch electrodes adjacent to a plurality of transmissive regions in a first optical region was manufactured as a comparative example of the present invention.

[0354] As shown in FIG. 12, in the case of the display device of the embodiment including a plurality of shielding patterns arranged to overlap a plurality of touch electrodes adjacent to a plurality of transmissive regions, it was confirmed that the touch noise level during touch driving was significantly lower than that of the display device of the comparative example in which only a plurality of touch electrodes adjacent to a plurality of transmissive regions were arranged.

[0355] Through the above experiments, it was confirmed that the display device of the present invention can prevent touch noise from occurring during touch driving by including a plurality of shielding patterns that overlap a plurality of transmissive regions of the first optical region and a plurality of adjacent touch electrodes.

[0356] FIG. 13 is a plan view showing a first optical region of a flexible display device according to another embodiment of the present invention.

[0357] FIG. 14 is an enlarged view of region Z in FIG.

[0358] First, referring to FIG. 13, the first optical area DA1 may include a central area 910 and a bezel area 920 located on the outer periphery of the central area 910.

[0359] The first optical region DA1 may include a plurality of horizontal lines HL, which may connect the transistors located in the bezel region 920 and the light emitting elements located in the central region 910.

[0360] The flexible display device 100 according to the embodiment may include a routing structure 940. By including the routing structure 940, the central region 910 may be expanded by the predetermined region a because the pixels located in the predetermined region a may be connected to transistors located in the bezel region 920 by the routing structure 940.

[0361] Specifically considering the structure of the first optical area DA1 including the routing structure 940, it is as follows.

[0362] 14, the first optical region may include a plurality of light-emitting elements ED located in a central region 910 and a bezel region 920. The first optical region may include a plurality of light-emitting elements ED, so that the first optical region may display a screen.

[0363] The first optical region can include a number of transistors 1050 located in the bezel region 920. The central region 910 can be free of transistors 1050. By not having transistors located in the central region 910, the central region 910 can have a higher transmittance.

[0364] The first optical region includes a plurality of rows, and may include a first row R1 and a second row R2. The plurality of rows included in the first optical region may be any region that traverses the first optical region in a horizontal direction and may be defined by a pattern of transistors 1050.

[0365] The flexible display device may include light emitting elements ED located in a central region 910 and arranged in a first row R1, and transistors 1050 located in a bezel region 920 and arranged in a second row R2.

[0366] The flexible display device may include a routing structure 940 that electrically couples the light emitting elements ED in the first row R1 to the transistors 1050 in the second row R2.

[0367] The routing structure 940 can connect the transistors 1050 and the light-emitting elements ED located in different rows, so that the transistors 1050 located in a row in which a greater number of transistors 1050 than the light-emitting elements ED are arranged can be connected to the light-emitting elements ED located in a row in which a greater number of light-emitting elements ED than the transistors 1050 are arranged.

[0368] The number of light emitting elements ED included in the first row R1 of the central region 910 may be greater than the number of light emitting elements ED included in the second row R2 of the central region 910. Therefore, a greater number of transistors 1050 are required to drive the light emitting elements ED included in the first row R1, and a smaller number of transistors 1050 are required to drive the light emitting elements ED included in the second row R2. Therefore, among the transistors 1050 located in the second row R2 of the bezel region 920, the surplus transistors 1050 that are not electrically connected to the light emitting elements ED located in the second row R2 may be electrically connected to the light emitting elements ED located in the first row R1 by the routing structure 940.

[0369] The central region 910 may have a substantially uniform number of pixels per unit area throughout the central region 910. A substantially uniform number of pixels per unit area may mean, for example, that a pixel pattern is substantially uniform throughout the central region 910. Thus, a greater number of light-emitting elements ED may be located in the first row R1, which has a larger area overlapping with the central region 910 than the second row R2.

[0370] For example, the number of transistors 1050 included in the first row R1 of the bezel region 920 may be substantially the same as the number of transistors 1050 included in the second row R2 of the bezel region 920. In the above example, if the central region 910 includes more light emitting elements ED in the first row R1 and the central region 910 includes fewer light emitting elements ED in the second row R2, some of the transistors 1050 included in the second row R2 may not be electrically connected to the light emitting elements ED located in the second row R2, but may be electrically connected to the light emitting elements ED located in the first row R1.

[0371] And, the bezel region 920 may have a substantially identical number of transistors 1050 per unit area throughout the bezel region 920. A substantially identical pattern of transistors per unit area may mean that one transistor pattern is substantially uniform throughout the bezel region 920.

[0372] The area of ​​the area where the bezel region 920 overlaps with the first row R1 may be substantially the same as the area of ​​the area where the bezel region 920 overlaps with the second row R2. In such an example, the number of transistors 1050 located in the first row R1 of the bezel region 920 may be substantially the same as the number of transistors 1050 located in the second row R2 of the bezel region.

[0373] In such a case, the number of transistors 1050 located in a row of the bezel region 920 can remain constant, and the routing structure 940 can electrically connect excess transistors in a particular row to excess light-emitting elements in other rows, so that the flexible display device according to the embodiment can have a larger central area 910 than the flexible display device of the comparative example.

[0374] Display devices according to various embodiments of the present invention can be described as follows.

[0375] A display device according to an embodiment of the present invention includes a substrate including a display region and a non-display region including a first optical region and a general region, a planarization layer disposed on the substrate in the display region, a plurality of light-emitting elements disposed on the planarization layer and including an anode, an emitting layer, and a cathode, a bank disposed on the planarization layer to cover an end of the anode, an encapsulation portion disposed to cover the plurality of light-emitting elements and the bank, a touch sensing portion disposed on the encapsulation portion and including a plurality of touch electrodes, and a plurality of shielding patterns disposed between the encapsulation portion and the plurality of touch electrodes in the first optical region, and the first optical region includes a transmissive region through which the cathode exposes the bank.

[0376] According to another feature of the present invention, the display device may further include a camera or a sensor disposed below the substrate and overlapping with the first optical region.

[0377] According to another aspect of the present invention, the plurality of shielding patterns may be arranged to overlap the plurality of touch electrodes at boundary regions of the plurality of transparent regions and the plurality of light emitting elements.

[0378] According to another feature of the present invention, the touch sensing unit may include a touch buffer film, a touch interlayer insulating layer disposed on the touch buffer film, a plurality of touch electrodes disposed on the touch interlayer insulating layer and arranged in a first direction and a second direction intersecting the first direction, and a bridge electrode connecting the plurality of touch electrodes arranged in the first direction, and the bridge electrode may be disposed in the same layer as the plurality of shielding patterns.

[0379] According to another feature of the present invention, a width of the plurality of shielding patterns may be greater than a width of the plurality of touch electrodes.

[0380] According to another feature of the invention, the shielding patterns may be grounded.

[0381] According to another aspect of the present invention, the semiconductor device may further include a ground line connected to the plurality of shielding patterns.

[0382] According to another feature of the present invention, the ground line may be disposed in the same layer as the plurality of touch electrodes and may be made of the same material.

[0383] According to another aspect of the present invention, the semiconductor device may further include a ground line and a connection line including a plurality of shielding patterns.

[0384] According to another feature of the invention, the plurality of transmissive regions may be circular, triangular, elliptical, rectangular or polygonal in shape.

[0385] Although the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of ​​the present invention. Therefore, the embodiments disclosed in the present invention are for illustration purposes, not for limiting the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative and not restrictive in all respects. The scope of protection of the present invention should be interpreted according to the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

Claims

1. a substrate including a display area and a non-display area, the display area including a first optical area and a general area; a planarization layer disposed on the substrate in the display area; a plurality of light-emitting devices disposed on the planarization layer, the light-emitting devices including an anode, a light-emitting layer, and a cathode; a bank disposed on the planarization layer so as to cover an end of the anode; an encapsulation portion disposed to cover the plurality of light-emitting elements and the bank; a touch sensing portion disposed on the encapsulant portion; and a plurality of shielding patterns disposed between the sealing portion and a plurality of touch electrodes in the first optical region; the first optical region includes a plurality of transmissive regions through which the cathode exposes the banks; the touch sensing unit includes a touch buffer film, a touch interlayer insulating layer disposed on the touch buffer film, the touch electrodes disposed on the touch interlayer insulating layer and arranged in a first direction and a second direction intersecting the first direction, and a bridge electrode connecting the touch electrodes arranged in the first direction, The bridge electrode is disposed in the same layer as the plurality of shielding patterns.

2. The display device of claim 1 , further comprising an optical / electronic device disposed under the substrate and overlapping the first optical region.

3. The display device according to claim 1 , wherein the plurality of shielding patterns are arranged so as to overlap the plurality of touch electrodes in boundary regions between the plurality of transmissive regions and the plurality of light-emitting elements.

4. The display device of claim 1 , wherein a width of the shielding patterns is greater than a width of the touch electrodes.

5. The display device according to claim 1 , wherein the plurality of shielding patterns are grounded.

6. The display device of claim 5 , further comprising a ground line connected to the plurality of shielding patterns.

7. The display device of claim 6 , wherein the ground line is disposed in the same layer as the plurality of touch electrodes and is made of the same material as the plurality of touch electrodes.

8. The display device of claim 6 , further comprising a connection line connecting the ground line and the plurality of shielding patterns.

9. The display device according to claim 1 , wherein the plurality of transmissive regions are circular, triangular, elliptical, rectangular or polygonal in shape.

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