Semiconductor Device

Abstract

To provide a flip-flop capable of solving problems that, conventionally, although the shift in the threshold voltage of a transistor is suppressed by applying an AC pulse to the gate of the transistor prone to degradation, however, when amorphous silicon is used as the semiconductor layer of the transistor, naturally, the transistors that make up the circuit for generating AC pulse also cause a shift in threshold voltage.SOLUTION: By inputting a signal to the gate electrode of a transistor that is prone to deterioration via a transistor that is turned on, the shift in threshold voltage of the transistor that is prone to deterioration and the shift in threshold voltage of transistors that are turned on are suppressed. That is, the flip-flop has a constitution that via the transistor with the gate electrode to which a high voltage (VDD) is applied (or via an element with a resistive component), an AC pulse is applied to the gate electrode of the transistor that is prone to deterioration.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device having a circuit configured using transistors, and in particular to a display device such as a liquid crystal display. Display devices that use electro-optical elements or light-emitting elements as display media and methods for driving such devices do. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, non-crystalline semiconductor (hereinafter referred to as amorphous silicon) is used on an insulating substrate. A pixel circuit and a driver circuit including a shift register and the like are formed using transistors configured as above. The technology for forming the internal circuitry (also called the internal circuitry) has contributed greatly to lowering power consumption and costs. The internal circuit formed on the insulator is It is connected to a controller IC etc. (hereinafter referred to as an external circuit) via an do.

[0003] Among the internal circuits shown above, transistors made of amorphous semiconductors (hereinafter referred to as amorphous semiconductors) A shift register using amorphous silicon transistors (also known as amorphous silicon transistors) has been devised. The configuration of the flip-flops in a conventional shift register is shown in FIG. 124(A) (Patent Document Reference 1). The flip-flop in Figure 124(A) consists of transistors 11, 12, transistor 13, transistor 14, transistor 15 and transistor 17; Connected to signal line 21, signal line 22, wiring 23, signal line 24, power line 25, and power line 26 The signal lines 21, 22, 24, the power supply lines 25, and the power supply lines 26 are each provided with a switch. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input. The operation period of the flip-flop in FIG. 124(A) is the timing chart in FIG. 124(B). As shown in the figure, the period is divided into a set period, a selection period, a reset period, and a non-selection period. Most of the period will be non-selection periods.

[0004] Here, during the non-selection period, the transistors 12 and 16 are on. Therefore, amorphous silicon is used for the semiconductor layers of the transistors 12 and 16. Therefore, the threshold voltage (Vth) fluctuates due to degradation, etc. In other words, the threshold voltage of the conventional shift register is increased by transistor 12 and transistor The threshold voltage of the transistor 16 rises and the transistor 16 cannot be turned on. VSS cannot be supplied, causing malfunctions.

[0005] To solve this problem, Non-Patent Documents 1, 2 and 3 describe the A shift register capable of suppressing the shift in the threshold voltage of the transistor 12 has been devised. In Patent Document 1, Non-Patent Document 2 and Non-Patent Document 3, a new transistor (first transistor A transistor 12 (hereinafter referred to as a second transistor) is arranged in parallel with the transistor 13 (hereinafter referred to as a second transistor), and Between the gate electrode of the first transistor and the gate electrode of the second transistor, By inputting the inverted signals, the first transistor and the second transistor are This suppresses the shift in the threshold voltage.

[0006] Furthermore, in Non-Patent Document 4, the threshold voltage of not only the transistor 12 but also the transistor 16 is A shift register that can also suppress voltage shifts has been devised. Transistor (referred to as the first transistor) is connected to transistor 12 (referred to as the second transistor). In addition, another new transistor (called the third transistor) is placed in parallel. The transistor 16 (hereinafter referred to as the fourth transistor) is arranged in parallel. In the above, the gate electrode of the first transistor and the gate electrode of the second transistor are connected to each other. The gate electrode of the third transistor and the gate electrode of the fourth transistor are inverted. By inputting an inverted signal to the gate electrode, the first transistor and the second transistor and suppressing the shift of the threshold voltages of the first transistor, the third transistor, and the fourth transistor. are.

[0007] Furthermore, Non-Patent Document 5 describes that applying an AC pulse to the gate electrode of the transistor 12 This suppresses the shift in the threshold voltage of the transistor 12.

[0008] The display devices of Non-Patent Documents 6 and 7 use amorphous silicon transistors. A shift register consisting of these is used as the scanning line driver circuit, and the R, G, and B sub-pixels are By inputting the video signal from a single signal line, the number of signal lines is reduced to one-third. Thus, the display devices of Non-Patent Documents 6 and 7 are composed of a display panel, a driver IC, and The number of connections is being reduced. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-157508 [Non-patent literature]

[0010] [Non-Patent Document 1] Soo Young Yoon, et al., “Highly Stable Integrated Gate Driver Circuit using a-Si TFT with Dual Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2005 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVI, p.348-351 [Non-patent document 2] Binn Kim, et al., “a-Si Gate Driver Integration with Time Shared Data Driving”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, p.1073-1076 [Non-patent document 3] Mindoo Chun, et al., ``Integrated Gate Driver Using Highly Stable a-Si TFT's'', Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, p.1077-1080 [Non-patent document 4] Chun-Ching, et al., “Integrated Gate Driver Circuit Using a-Si TFT”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, p.1023-1026 [Non-patent document 5] Yong Ho Jang, et al., “A-Si TFT lntegrated Gate Driver with AC-Driven Single Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p.208-211 [Non-patent document 6] Jin Young Choi, et al., “A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixcel Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p.274-276 [Non-Patent Document 7] Yong Soon Lee, et al., “Advanced TFT-LCD Data Line Reduction Method”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p.1083-1086 Summary of the Invention [Problem to be solved by the invention]

[0011] According to conventional technology, applying an AC pulse to the gate of a transistor that is prone to deterioration However, the shift in the threshold voltage of the transistor is suppressed. When amorphous silicon is used as the semiconductor layer of the capacitor, the circuit that generates the AC pulse is naturally The transistors that make up the path also have a problem in that they experience a shift in threshold voltage. In addition, the number of signal lines has been reduced to one-third, reducing the number of contact points between the display panel and the driver IC. It has been proposed (Non-Patent Documents 6 and 7), but in practice, There is a demand for further reduction in the number of contact points.

[0012] That is, the problem that cannot be solved by the conventional technology is to suppress the fluctuation of the threshold voltage of the transistor. The number of contacts on the driver IC mounted on the display panel is The technology to reduce power consumption of display devices remains a challenge. However, there remains a problem of increasing the size and resolution of display devices.

[0013] The invention disclosed in this specification is industrially useful by solving one or more of these problems. The aim is to provide useful technology. [Means for solving the problem]

[0014] The display device according to the present invention has a gate electrode of a transistor that is prone to deterioration. By inputting a signal through a transistor, the threshold voltage of a transistor that is prone to deterioration can be shifted. The shift in threshold voltage of the turned-on transistor is suppressed. The present invention provides a method for controlling a power supply voltage through a transistor to which a high potential (VDD) is applied (if (or through an element with a resistive component) to apply an AC pulse to the gate voltage of a transistor that is prone to deterioration. It includes a configuration to add to the pole.

[0015] The switches shown herein may take a variety of forms, including electrical There are electrical switches and mechanical switches. In other words, anything that can control the flow of current. For example, a transistor (e.g., Bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes) diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator or Metal) diode, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, thyristors, etc. Alternatively, a logic circuit combining these can be used as a switch. Yes, it is possible.

[0016] When a transistor is used as a switch, the transistor acts as a simple switch. However, the polarity (conductivity type) of the transistor is not particularly limited. To suppress this, it is desirable to use a transistor with a polarity that reduces the off-state current. As a transistor with low current, a transistor with LDD region or a multi-gate structure There are transistors with a structure such as a switch. When the power supply voltage is close to the low-potential power supply (VSS, GND, 0V, etc.), In this case, it is desirable to use an N-channel transistor. When operating near the high-potential power supply (such as VDD), a P-channel transistor is used. This is because the source terminal of an N-channel transistor is connected to the low-potential side When operating close to the power supply, the source terminal of a P-channel transistor is connected to the high-potential power supply. When the switch operates in a state close to In addition, the output voltage is low because the source follower operation is rarely performed. This is because the magnitude of the voltage is unlikely to become small.

[0017] CMOS type switching is performed using both N-channel and P-channel transistors. A CMOS switch can be used as a switch. If either the N-channel transistor or the N-channel transistor is conductive, For example, the input signal to the switch is It can output the voltage appropriately whether the voltage is high or low. The voltage amplitude of the signal used to turn the switch on and off can be reduced, reducing power consumption. It is also possible to reduce the power consumption.

[0018] When a transistor is used as a switch, the switch is connected to the input terminal (source terminal or drain terminal). The output terminal (the other of the source or drain terminal) and the On the other hand, when a diode is used as a switch, In this case, the switch may not have a terminal for controlling conduction. Using a diode as a switch rather than a capacitor reduces the amount of wiring required to control the terminal. It is possible to do this.

[0019] In this specification, when it is explicitly stated that "A and B are connected," it means that A and B are When A and B are electrically connected, when A and B are functionally connected, and when A and B are Here, A and B are objects (e.g., equipment) (device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.). In the configuration disclosed in the specification, a predetermined connection relationship, for example, a connection shown in a drawing or text, The present invention is not limited to the above relationships, and includes connections other than those shown in the drawings or text.

[0020] For example, if A and B are electrically connected, the electrical connection between A and B can be The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more ions (such as ions) may be placed between A and B. Alternatively, A and B may be In the case of functional connection, a circuit that allows the functional connection between A and B (e.g. , logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, voltage sources, current sources, Switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc.), operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, signal generation circuits, memory circuits, control One or more control circuits may be arranged between A and B. Alternatively, A and B may be arranged In the case of direct connection, A and B are connected without any other elements or circuits between them. and may be directly connected.

[0021] When explicitly stating "A and B are directly connected," it means that A and B are directly connected. (i.e., there is no other element or circuit between A and B) When A and B are electrically connected (i.e., there is no other element or (when connected across another circuit)

[0022] When explicitly stating that "A and B are electrically connected," it means that A and B are electrically When A and B are connected (i.e., when another element or circuit is sandwiched between A and B), A and B are functionally connected (i.e., there is another circuit between A and B) When A and B are functionally connected across the (When A and B are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it simply means that it is connected. The same applies as if the document were expressly stated to be "incomplete" and "unreadable."

[0023] Display elements, display devices that are devices having display elements, light-emitting elements, and devices that are devices having light-emitting elements. The light emitting device can have various forms and various elements. The elements, display devices, light-emitting elements, or light-emitting devices include EL elements (organic EL elements, inorganic EL elements) elements or EL elements including organic and inorganic materials), electron emission elements, liquid crystal elements, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP) , Digital Micromirror Device (DMD), Piezoelectric Ceramic Display, Carbon Nanotubes, etc., have electromagnetic effects that can affect contrast, brightness, reflectivity, transmittance, etc. The display medium that changes the light intensity can be used. LED displays, and field emission displays as display devices using electron emission elements. FED and SED flat panel displays (SED: Surface-cond LCDs using liquid crystal elements such as LCDs (Electron-emitter Displays) As a display device, a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display) (I), reflective LCD display, direct-view LCD display, projection LCD display), An example of a display device using ink or electrophoretic elements is electronic paper.

[0024] The transistors described herein may take various forms. Therefore, there is no limitation on the type of transistor to be used. For example, amorphous silicon, polycrystalline silicon, crystalline silicon, microcrystalline (also called microcrystalline or semi-amorphous) silicon, etc. It is possible to use thin film transistors (TFTs) with non-single crystal semiconductor films, which are typified by There are various advantages to using TFTs. For example, they are It can be manufactured at a very low temperature, which reduces manufacturing costs and makes it possible to reduce the size of the manufacturing equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on a large substrate. Since a large number of display devices can be manufactured, they can be manufactured at low cost. Therefore, a substrate with low heat resistance can be used. Then, transistors on a transparent substrate can be used to control the light transmission through the display element. Alternatively, since the film thickness of the transistor is thin, the A part of the film can transmit light, which improves the aperture ratio. do.

[0025] When producing polycrystalline silicon, a catalyst (such as nickel) is used to improve the crystallinity. This makes it possible to further improve the characteristics of transistors and manufacture transistors with excellent electrical properties. Gate driver circuits (scanning line driver circuits), source driver circuits (signal line driver circuits), signal Processing circuits (signal generation circuits, gamma correction circuits, DA conversion circuits, etc.) are integrally formed on the board. It is possible.

[0026] When manufacturing microcrystalline silicon, the crystallinity is improved by using a catalyst (such as nickel). This makes it possible to further improve the characteristics of transistors and manufacture transistors with excellent electrical properties. The crystallinity can be improved by simply applying heat treatment without using a laser. , gate driver circuits (scanning line driving circuits) and part of the source driver circuits (analog switches It is possible to form a single layer of a semiconductor material on a substrate. If there is no silicon, the unevenness of the crystallinity of the silicon can be suppressed. It can be shown.

[0027] However, polycrystalline silicon and microcrystalline silicon are produced without using a catalyst (such as nickel). It is possible.

[0028] Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. In this case, MOS transistors, junction transistors, bipolar transistors, etc. These can be used as transistors described in the specification. The transistors are small in size, shape, and have a high current supply capacity. These transistors can be used to create circuits with low power consumption. Alternatively, high integration can be achieved.

[0029] Or ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, SnO, etc. Transistors having any compound semiconductor or oxide semiconductor, and further, A thin film transistor made of a semiconductor or an oxide semiconductor can be used. This allows the manufacturing temperature to be lowered, making it possible to manufacture transistors at room temperature, for example. As a result, direct transfer to a substrate with low heat resistance, such as a plastic substrate or a film substrate, These compound semiconductors or oxide semiconductors can be used to form a transistor. It can be used not only for the channel portion of a transistor but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistor elements, pixel electrodes, transparent electrodes, etc. Furthermore, they can be formed simultaneously with the transistors or can be used as a film. This makes it possible to reduce costs.

[0030] Alternatively, a transistor formed by inkjet or printing can be used. These features allow manufacturing at room temperature, in a low vacuum, or on a large substrate. In addition, since it is possible to manufacture without using a mask (reticle), The layout of the transistors can be easily changed. This reduces material costs and the number of processes. This method is more cost-effective than the method of forming a film over the entire surface and then etching it. and can be done at low cost.

[0031] Alternatively, a transistor having an organic semiconductor or a carbon nanotube may be used. These features make it possible to form transistors on a flexible substrate. This makes it resistant to impacts.

[0032] In addition, various other transistors can be used.

[0033] The type of substrate on which the transistor is formed can be various, and a specific The substrate on which the transistor is formed is, for example, a single crystal substrate. Plate, SOI substrate, glass substrate, quartz substrate, plastic substrate, paper substrate, cellophane substrate, Stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane) Tan, polyester) or recycled fiber (acetate, cupro, rayon, recycled polyester) (including stainless steel), leather substrate, rubber substrate, stainless steel substrate, stainless steel Alternatively, a substrate with a foil or the like can be used. The skin surface, dermis, or subcutaneous tissue may be used as a substrate. Then, the transistor is transferred to another substrate. The substrate on which the transistor is transferred may be a single crystal substrate, an SOI substrate, a glass substrate, or the like. Substrate, quartz substrate, plastic substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, Fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.) , leather substrate, rubber substrate, stainless steel substrate, stainless steel foil Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used. By using these substrates, transistors with good characteristics can be produced. Formation of transistors with low power consumption, fabrication of durable devices, and heat resistance It is possible to increase the weight or reduce the weight.

[0034] The transistor configuration can take various forms and is not limited to a specific configuration. For example, a multi-gate structure having two or more gate electrodes may be used. When this happens, the channel regions are connected in series, resulting in a structure in which multiple transistors are connected in series. The multi-gate structure reduces off-current and improves the breakdown voltage of the transistor, resulting in improved reliability. Alternatively, when operating in the saturation region, the drain-source Even if the voltage between the drain and source changes, the current between the drain and source does not change much, and the slope of the voltage-current characteristic The voltage-current characteristic has a flat slope. By using this, it is possible to realize ideal current source circuits and active loads with very high resistance values. As a result, it is possible to realize differential circuits and current mirror circuits with good characteristics. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be used. By using a structure in which a gate electrode is placed, the channel area increases, so the current value Alternatively, the depletion layer can be easily formed, which can reduce the S value. When gate electrodes are placed above and below the channel, multiple transistors are connected in parallel. The structure is as follows.

[0035] Alternatively, a structure in which a gate electrode is disposed on the channel region may be used. Alternatively, a gate electrode may be disposed under the gate electrode region. A tag structure may be used, or the channel region may be divided into a plurality of regions. may be connected in parallel, or the channel regions may be connected in series. The channel region (or a part thereof) may be overlapped with a source electrode or a drain electrode. A structure in which the source electrode and drain electrode overlap the channel region (or part of it). This prevents charge from accumulating in part of the channel region, causing instability in operation. Furthermore, an LDD region may be provided. By providing the LDD region, the off-current can be reduced. This reduces the voltage resistance of the transistor, improving reliability. When operating in the low-voltage range, the drain-source current remains constant even if the drain-source voltage changes. does not change much, and the slope of the voltage-current characteristic can be made flat.

[0036] In this specification, one pixel refers to the smallest unit of an image. In the case of a full-color display device consisting of the color elements A (green) and B (blue), one pixel is the color element R It is assumed that the dots are composed of dots of the color elements of G and B. The color elements are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. For example, you can add white to make it RGBW (W is white). If you add one or more colors, such as yellow, cyan, magenta, emerald green, or vermilion, Alternatively, for example, a color similar to at least one color in RGB may be added to the RGB. For example, R, G, B1, B2 may be used. B1 and B2 are both blue. Similarly, R1, R2, G, and B may be used. By using various color elements, it is possible to display more realistic images and reduce power consumption. It is possible to reduce the number of dots. Note that one pixel may have multiple dots of the same color element. In this case, the plurality of color elements may each have a different size of the area that contributes to the display. In addition, by controlling each of the multiple dots of the same color element, gradation can be displayed. This is called the area gradation method. Alternatively, multiple color elements of the same color may be displayed. By using dots and supplying slightly different signals to each dot, the viewing angle can be adjusted. That is, the pixel electrodes of the color elements of the same color may be widened. As a result, the voltage applied to the liquid crystal molecules varies depending on the pixel electrodes. Therefore, the viewing angle can be widened.

[0037] In this specification, one pixel refers to one element whose brightness can be controlled. For example, one pixel refers to one color element, and the brightness is determined by that one color element. Therefore, in this case, the color is made up of the color elements R (red), G (green), and B (blue). In the case of a display device, the smallest unit of an image is made up of three pixels: an R pixel, a G pixel, and a B pixel. The number of color elements is not limited to three, and more than three colors may be used. Colors other than RGB may be used. For example, adding white makes it possible to use RGBW (W is white). Also, for example, yellow, cyan, magenta, emerald green, vermilion, One or more colors may be added. For example, a color similar to at least one of the RGB colors may be added. The colors can be added to RGB, for example R, G, B1, B2. 2 and R1 are both blue, but have slightly different frequencies. By using such color elements, it is possible to display the image more realistically. As another example, it is possible to When controlling brightness using multiple areas, each area can be counted as one pixel. Therefore, for example, when area gradation is performed or when a pixel has sub-pixels, In this case, there are multiple areas that control brightness for each color element, and the gradation is expressed by the entire area. However, one area for controlling brightness may be one pixel. In this case, one color element is made up of multiple pixels. Even if there are multiple areas in one color element, they are grouped together and one color element is treated as one pixel. In this case, one color element is composed of one pixel. In addition, when controlling brightness using multiple regions for one color element, The size of the area that contributes to the display may differ depending on the color element. In the multiple brightness control areas, the signal supplied to each is slightly different. In other words, for one color element, multiple The potentials of the pixel electrodes of the respective regions may be different from each other. The voltage applied to each pixel electrode is different, which makes it possible to widen the viewing angle.

[0038] When explicitly stating one pixel (three colors), it means that one pixel is considered to consist of three pixels: R, G, and B. When explicitly describing one pixel (one color), it means multiple pixels per color element. When there are several regions, they are considered as one pixel.

[0039] In this specification, pixels may be arranged (distributed) in a matrix. The pixels are arranged in a matrix, which means that the pixels are arranged vertically or horizontally. This includes cases where elements are arranged in a straight line or in a jagged line. For example, when displaying full color using three color elements (e.g., RGB), the stripe arrangement This also includes cases where the dots of the three color elements are arranged in a delta pattern. This also includes the case where the color elements are arranged in a Bayer pattern. Note that the number of color elements is not limited to three, and may be more than three. For example, RGBW (W is white) or RGB plus yellow, cyan, magenta, etc. There are also some that add more than one color. Also, the size of the display area for each dot of the color element is different. This can reduce power consumption. It can extend the life of the

[0040] In this specification, the term "active matrix type" refers to a type in which pixels have active elements, or A passive matrix system that does not have active elements can be used.

[0041] In the active matrix system, the active element (active element, nonlinear element) is a transistor. Use not only transistors but also various active elements (active elements, nonlinear elements) For example, MIM (Metal Insulator Metal) and TFD (Th It is also possible to use in-film diodes. Since there are fewer of them, they can be manufactured at low cost, or the yield can be increased. Furthermore, since the size of the element is small, the aperture ratio can be improved. This makes it possible to achieve low power consumption and high brightness.

[0042] Active elements (active elements, non-linear elements) other than the active matrix type It is also possible to use a passive matrix type that does not use active elements (active elements Since it does not use any nonlinear elements, the manufacturing process is reduced and it can be manufactured at low cost. Alternatively, it is possible to increase the yield. Since it does not use any optical elements (electrodes, non-linear elements), it is possible to improve the aperture ratio, reduce power consumption, and Brightness can be increased.

[0043] A transistor is a device that has at least three terminals, including a gate, a drain, and a source. The element has a channel region between the drain region and the source region, and the drain region A current can flow through the source region, the channel region, and the source region. The drain varies depending on the transistor structure and operating conditions, so it is difficult to determine which is the source or drain. Therefore, in this specification, it is difficult to define whether the source is the drain. The regions that function as the source and drain are sometimes not called the source or drain. In this case, for example, they may be referred to as a first electrode and a second electrode, respectively.

[0044] A transistor is a device having at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector are also referred to as the first terminal and the second terminal. It may be written.

[0045] A gate is a gate electrode and a gate wiring (gate line, gate signal line, scanning line, scanning signal line, etc.) The gate electrode is the whole or part of the The semiconductor that forms the channel region and the conductive part that overlaps with the gate insulating film are A part of the gate electrode is a lightly doped dielectric film (LDD). ain) region or source region and drain region, and overlapping with the gate insulating film. The gate wiring is the connection between the gate electrodes of each transistor, or This refers to the wiring that connects the gate electrode to another wiring.

[0046] However, there are areas (regions, conductive layers) that function as both gate electrodes and gate wiring. Such parts (regions, conductive films, wiring, etc.) are also present. In other words, the gate electrode and the gate wiring However, there are also regions that cannot be clearly distinguished. For example, If a part of the line overlaps with the channel region, that part (region, conductive film, wiring ) functions as a gate wiring, but also functions as a gate electrode. Therefore, such a part (region, conductive film, wiring, etc.) may be called a gate electrode. , which may also be called gate wiring.

[0047] It is made of the same material as the gate electrode and forms the same island as the gate electrode. The part (region, conductive film, wiring, etc.) that is connected to the gate electrode may also be called the gate electrode. It is made of the same material as the gate wiring and forms the same island as the gate wiring. The part (region, conductive film, wiring, etc.) that is connected to the gate may also be called the gate wiring. In the strict sense, the conductive film, wiring, etc.) does not overlap with the channel region. However, the gate electrode or It is made of the same material as the gate wiring and is the same island as the gate electrode or gate wiring. There are parts (regions, conductive films, wiring, etc.) that form a network and are connected. The gate electrode or gate wiring may also be called a gate electrode or gate wiring.

[0048] For example, in a multi-gate transistor, one gate electrode and another gate electrode In many cases, the gate electrode is connected to the semiconductor substrate through a conductive film made of the same material as the gate electrode. The part (region, conductive film, wiring, etc.) for connecting the gate electrodes is It can be called gate wiring because it is a multi-gate transistor. Since the transistor can be considered as one transistor, it may also be called a gate electrode. That is, the gate electrode or the gate wiring is formed of the same material, and the gate electrode or the gate wiring is formed of the same material. The parts (areas, conductive films, wiring, etc.) that form the same island as the line and are connected For example, the gate electrode and the gate wiring may be called gate electrodes and gate wiring. The conductive film of the part connecting the gate electrode and the gate wiring is made of a different material. The formed conductive film may also be called a gate electrode or a gate wiring.

[0049] The gate terminal is the part of the gate electrode (region, conductive film, wiring, etc.) or the part of the gate electrode and the It refers to a part of an electrically connected part (area, conductive film, wiring, etc.). cormorant.

[0050] When we refer to gate wiring, gate lines, gate signal lines, scanning lines, scanning signal lines, etc., it is because the wiring has a In some cases, the gate of the transistor is not connected. In this case, the gate wiring, gate line, and gate The gate signal line, scanning line, and scanning signal line are wirings formed in the same layer as the transistor gate. Wiring made of the same material as the transistor gate or at the same time as the transistor gate It may refer to a deposited wiring. Examples include wiring for storage capacitors, power supply lines, and reference There are potential supply wirings, etc.

[0051] The source is a combination of a source region, a source electrode, and a source wiring (a source line, a source signal line, a data line, etc.). This refers to the whole or part of the signal lines (also called data signal lines, etc.). The base region is where P-type impurities (such as boron or gallium) or N-type impurities (such as phosphorus or arsenic) are introduced. Therefore, it refers to a semiconductor region that contains a small amount of P-type impurities or N-type impurities. The area where the drain current is generated, so-called LDD (Lightly Doped Drain) area, is the area where the drain current is generated. The source electrode is formed of a material different from the source region and is not included in the source region. The source electrode is a conductive layer that is electrically connected to the source electrode. The source electrode is sometimes called the source electrode, including the source region. or a wiring for connecting a source electrode to another wiring.

[0052] However, there is a part (area) that functions as both a source electrode and a source wiring. Such parts (areas, conductive films, wiring, etc.) are also present. It may be called a source electrode or a source wiring. There are also areas where it is difficult to clearly distinguish between lines and objects. When a part of the source wiring overlaps with the source region, the part (region, conductive film) , wiring, etc.) functions as a source wiring, but also as a source electrode. Therefore, such a part (region, conductive film, wiring, etc.) can be called a source electrode. That's fine, you can call it source wiring.

[0053] It is made of the same material as the source electrode and forms the same island as the source electrode. The part where the source electrode is connected (region, conductive film, wiring, etc.) The source electrode (region, conductive film, wiring, etc.) may also be called the source electrode. The burlapped part can also be called the source electrode. The area that is connected to the source wiring and forms the same island is also called the source wiring. Such parts (areas, conductive films, wiring, etc.) are, in the strict sense, However, there are cases where the source electrode has no function to connect to another source electrode. It is made of the same material as the source electrode or source wiring and is connected to the source electrode or source wiring. Therefore, there are parts (regions, conductive films, wiring, etc.) that are The source electrode or source wiring may also be called a source electrode or a source wiring.

[0054] For example, the conductive film in the portion connecting the source electrode and the source wiring is Alternatively, a conductive film formed of a material different from the source wiring may also be called a source electrode. This may also be called a source wiring.

[0055] The source terminal is a region of the source region, a source electrode, or a region electrically connected to the source electrode. It refers to a part of a part (area, conductive film, wiring, etc.) that is being used.

[0056] When referring to source wiring, source line, source signal line, data line, data signal line, etc., In some cases, the source (drain) of a transistor is not connected. The line, source line, source signal line, data line, and data signal line are connected to the source (drain) of the transistor. Wiring formed in the same layer as the source (drain) of the transistor, and made of the same material as the source (drain) of the transistor This refers to wiring formed by a thin film or wiring formed at the same time as the source (drain) of a transistor. Examples include wiring for storage capacitors, power supply lines, and wiring for supplying reference potential.

[0057] The drain is similar to the source.

[0058] A semiconductor device is a circuit that includes semiconductor elements (transistors, diodes, thyristors, etc.). Furthermore, the term "semiconductor" refers to any device that can function by utilizing the properties of semiconductors. It may also be called a conductor device.

[0059] Display elements include optical modulation elements, liquid crystal elements, light-emitting elements, EL elements (organic EL elements, inorganic EL elements) element or EL element including organic and inorganic materials), electron emission element, electrophoresis element, discharge element, These include optical reflecting elements, optical diffraction elements, and digital micromirror devices (DMDs). However, it is not limited to this.

[0060] The display device refers to a device having a display element. A display in which a plurality of pixels including the pixel and a peripheral driving circuit for driving the pixels are formed on the same substrate. The display device may be a display panel body. The peripheral drive circuits arranged on the board are connected by chip-on-glass (COG). The IC chip may include an IC chip attached to the board or an IC chip connected by a tab or the like. The display device is equipped with IC chips, resistors, capacitors, inductors, transistors, etc. The display device may include a flexible printed circuit (FPC) attached thereto. It is connected via flexible printed circuit boards (FPCs) and contains IC chips, resistors, capacitors, and inductors. It includes a printed wiring board (PWB) on which inductors, transistors, etc. are mounted. The display device may include an optical sheet such as a polarizing plate or a retardation plate. The display device may include a lighting device, a housing, an audio input / output device, an optical sensor, etc. Here, a lighting device such as a backlight unit includes a light guide plate, a prism sheet, a diffusion sheet, and a Sheets, reflective sheets, light sources (LEDs, cold cathode fluorescent lamps, etc.), cooling devices (water-cooled, air-cooled), etc. It may also include:

[0061] The lighting device includes a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, and a reflective sheet. A device that has a light source (LED, cold cathode fluorescent lamp, hot cathode fluorescent lamp, etc.), a cooling device, etc. cormorant.

[0062] Note that a light-emitting device refers to a device having a light-emitting element or the like.

[0063] A reflecting device is a device that has a light reflecting element, a light diffracting element, a light reflecting electrode, etc. .

[0064] A liquid crystal display device is a display device that has a liquid crystal element. There are two types of liquid crystal display devices: direct-view type, There are projection type, transmissive type, reflective type, semi-transmissive type, etc.

[0065] A driving device is a device that has semiconductor elements, electric circuits, and electronic circuits. A transistor (selection transistor, switch transistor) that controls the input of signals from the switch signal line to the pixel. (sometimes called switching transistors, etc.) that supply voltage or current to the pixel electrode. The transistors that supply voltage or current to the light-emitting element and the like are Furthermore, a circuit for supplying signals to the gate signal lines (gate driver, gate line driver) a circuit that supplies signals to the source signal lines (source drivers, A driving device such as a source line driver circuit is an example of a driving device.

[0066] Display devices, semiconductor devices, lighting devices, cooling devices, light-emitting devices, reflecting devices, driving devices, etc. For example, a display device may have a semiconductor device and a light-emitting device. In some cases, the semiconductor device includes a display device and a driver device.

[0067] In this specification, B is formed on A, or B is formed on A. When explicitly stating "A", it is not limited to B being formed directly on A. This also includes cases where there is no direct contact between A and B, i.e., there is another object between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, Conductive film, layer, etc.

[0068] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). When the layer is placed on top of the substrate, there are cases where layer B is formed directly on top of layer A, and cases where layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed adjacent to it, and layer B is formed directly on top of it. It should be noted that other layers (such as layer C and layer D) may be formed separately. It may be a single layer or multiple layers.

[0069] Furthermore, the same applies when it is explicitly stated that B is formed above A. This is not limited to B being directly on top of A, but also includes the presence of another object between A and B. For example, if layer B is formed above layer A, In this case, there are two cases: when layer B is formed directly on top of layer A, and when layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be single layers. Alternatively, it may be multi-layered.

[0070] When explicitly stating that B is formed directly on A, it is assumed that B is formed directly on A. This includes cases where B is formed by A and B, but does not include cases where another object is interposed between A and B. Let's say.

[0071] The same is true when B is below A, or when B is below A. [Effects of the Invention]

[0072] It is possible to suppress the deterioration of the characteristics of all the transistors in the shift register. Therefore, malfunctions of semiconductor devices using the shift register, such as liquid crystal display devices, can be suppressed. It can be controlled. [Brief explanation of the drawings]

[0073] [Figure 1] 1A to 1C illustrate a structure of a flip-flop described in Embodiment 1. [Figure 2] 2 is a timing chart illustrating the operation of the flip-flop shown in FIG. 1; [Figure 3]FIG. 2 is a diagram for explaining the operation of the flip-flop shown in FIG. [Figure 4] 1A to 1C illustrate a structure of a flip-flop described in Embodiment 1. [Figure 5] 1A to 1C illustrate a structure of a flip-flop described in Embodiment 1. [Figure 6] 4 is a timing chart illustrating the operation of the flip-flop shown in Embodiment 1. [Figure 7] 1A to 1C illustrate a structure of a flip-flop described in Embodiment 1. [Figure 8] 1A to 1C illustrate a structure of a display device described in Embodiment 1. [Figure 9] 9 is a timing chart illustrating a writing operation of the display device shown in FIG. 8. [Figure 10] FIG. 2 illustrates a structure of a shift register described in Embodiment 1. [Figure 11] 11 is a timing chart illustrating the operation of the shift register shown in FIG. 10. [Figure 12] 11 is a timing chart illustrating the operation of the shift register shown in FIG. 10. [Figure 13] FIG. 2 illustrates a structure of a shift register described in Embodiment 1. [Figure 14] FIG. 2 illustrates a structure of a shift register described in Embodiment 1. [Figure 15] FIG. 2 illustrates a structure of a shift register described in Embodiment 1. [Figure 16] 10A to 10C illustrate a structure of a display device described in Embodiment 2. [Figure 17] FIG. 2 illustrates a structure of a shift register described in Embodiment 1. [Figure 18] 1A to 1C illustrate a structure of a display device described in Embodiment 1. [Figure 19] 19 is a timing chart illustrating a writing operation of the display device shown in FIG. 18. [Figure 20] 1A to 1C illustrate a structure of a display device described in Embodiment 1. [Figure 21] 1A to 1C illustrate a structure of a flip-flop described in Embodiment 1. [Figure 22] 10A to 10C illustrate a structure of a flip-flop described in Embodiment 2. [Figure 23] 10A to 10C illustrate a structure of a flip-flop described in Embodiment 4. [Figure 24] 24 is a timing chart illustrating the operation of the flip-flop shown in FIG. 23. [Figure 25] Top view of the flip-flop shown in Figure 1. [Figure 26] FIG. 14 is a diagram for explaining the configuration of the buffer shown in FIG. 13. [Figure 27] 10A to 10C illustrate a structure of a flip-flop described in Embodiment 3. [Figure 28] 28 is a timing chart illustrating the operation of the flip-flop shown in FIG. 27. [Figure 29] 10A and 10B illustrate a structure of a shift register described in Embodiment 3. [Figure 30] 30 is a timing chart illustrating the operation of the shift register shown in FIG. 29. [Figure 31] 10 is a timing chart illustrating the operation of the flip-flop shown in Embodiment 2. [Figure 32] 10 is a timing chart illustrating the operation of the flip-flop shown in Embodiment 2. [Figure 33] 10A and 10B illustrate a structure of a shift register described in Embodiment 2. [Figure 34] 10A and 10B illustrate a structure of a shift register described in Embodiment 2. [Figure 35] 34 is a timing chart illustrating the operation of the shift register shown in FIG. 33. [Figure 36] 34 is a timing chart illustrating the operation of the shift register shown in FIG. 33. [Figure 37] 10 illustrates a configuration of a signal line driver circuit described in Embodiment 5. [Figure 38] 38 is a timing chart illustrating the operation of the signal line driver circuit shown in FIG. 37. [Figure 39] 10 illustrates a configuration of a signal line driver circuit described in Embodiment 5. [Figure 40]40 is a timing chart illustrating the operation of the signal line driver circuit shown in FIG. 39. [Figure 41] 10 illustrates a configuration of a signal line driver circuit described in Embodiment 5. [Figure 42] 10A and 10B illustrate a structure of a protection diode described in Embodiment 6. [Figure 43] 10A and 10B illustrate a structure of a protection diode described in Embodiment 6. [Figure 44] 10A and 10B illustrate a structure of a protection diode described in Embodiment 6. [Figure 45] 10A to 10C illustrate a structure of a display device described in Embodiment 7. [Figure 46] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device; [Figure 47] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device; [Figure 48] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device; [Figure 49] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device; [Figure 50] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device; [Figure 51] FIG. 1 is a cross-sectional view of a display element of a semiconductor device. [Figure 52] FIG. 1 is a cross-sectional view of a display element of a semiconductor device. [Figure 53] FIG. 1 is a cross-sectional view of a display element of a semiconductor device. [Figure 54] FIG. 10 is a top view of a display element of a semiconductor device. [Figure 55] FIG. 10 is a top view of a display element of a semiconductor device. [Figure 56] FIG. 10 is a top view of a display element of a semiconductor device. [Figure 57] FIG. 2 is a diagram illustrating a peripheral circuit configuration of a semiconductor device. [Figure 58] FIG. 2 is a diagram illustrating a peripheral circuit configuration of a semiconductor device. [Figure 59] 1A and 1B are diagrams illustrating a panel circuit configuration of a semiconductor device. [Figure 60] 1A and 1B are diagrams illustrating a panel circuit configuration of a semiconductor device. [Figure 61] FIG. [Figure 62] FIG. 2 is a diagram illustrating a peripheral circuit configuration of a semiconductor device. [Figure 63] FIG. [Figure 64] FIG. [Figure 65] FIG. [Figure 66] FIG. [Figure 67] FIG. [Figure 68] FIG. [Figure 69] FIG. [Figure 70] FIG. [Figure 71] FIG. [Figure 72] FIG. [Figure 73] FIG. [Figure 74] FIG. [Figure 75] FIG. [Figure 76] FIG. [Figure 77] FIG. [Figure 78] FIG. [Figure 79] FIG. [Figure 80] FIG. [Figure 81] FIG. [Figure 82] 2A and 2B are diagrams illustrating peripheral components of a semiconductor device. [Figure 83] FIG. 2 is a diagram illustrating a peripheral circuit configuration of a semiconductor device. [Figure 84] 2A and 2B are diagrams illustrating peripheral components of a semiconductor device. [Figure 85] 2A and 2B are diagrams illustrating peripheral components of a semiconductor device. [Figure 86] 2A and 2B are diagrams illustrating peripheral components of a semiconductor device. [Figure 87] 1A to 1C illustrate a semiconductor device. [Figure 88]1A to 1C illustrate a method for driving a semiconductor device. [Figure 89] 1A to 1C illustrate a method for driving a semiconductor device. [Figure 90] 1A to 1C illustrate a method for driving a semiconductor device. [Figure 91] 1A to 1C illustrate a method for driving a semiconductor device. [Figure 92] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device; [Figure 93] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device; [Figure 94] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device; [Figure 95] FIG. 1 is a cross-sectional view of a display element of a semiconductor device. [Figure 96] 1A and 1B are diagrams illustrating an apparatus for forming a display element of a semiconductor device. [Figure 97] 1A and 1B are diagrams illustrating an apparatus for forming a display element of a semiconductor device. [Figure 98] 1A to 1C illustrate a method for driving a semiconductor device. [Figure 99] 1A to 1C illustrate a method for driving a semiconductor device. [Figure 100] FIG. 2 is a diagram illustrating one pixel circuit of a semiconductor device. [Figure 101] FIG. 2 is a diagram illustrating one pixel circuit of a semiconductor device. [Figure 102] 1A to 1C are diagrams illustrating a process for manufacturing a semiconductor device. [Figure 103] 1A to 1C illustrate a display element of a semiconductor device. [Figure 104] 1A to 1C illustrate a display element of a semiconductor device. [Figure 105] 1A to 1C illustrate a structure of a semiconductor device. [Figure 106] 1A to 1C illustrate a structure of a semiconductor device. [Figure 107] 1A to 1C illustrate a structure of a semiconductor device. [Figure 108] 1A to 1C illustrate a structure of a semiconductor device. [Figure 109] 1A to 1C illustrate a structure of a semiconductor device. [Figure 110] 1A to 1C illustrate a structure of a semiconductor device. [Figure 111] 1A to 1C illustrate a structure of a semiconductor device. [Figure 112] 1A to 1C illustrate a structure of a semiconductor device. [Figure 113] 1A to 1C illustrate a structure of a semiconductor device. [Figure 114] 1A to 1C illustrate a structure of a semiconductor device. [Figure 115] 1A to 1C illustrate a structure of a semiconductor device. [Figure 116] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 117] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 118] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 119] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 120] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 121] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 122] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 123] FIG. 14 is a diagram for explaining the configuration of the buffer shown in FIG. 13. [Figure 124] 1A and 1B are diagrams illustrating the configuration and timing chart of a flip-flop according to the prior art; DETAILED DESCRIPTION OF THE INVENTION

[0074] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. It is to be understood that the invention may be practiced in various different ways without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes can be made in form and detail. It should not be construed as being limited to the description of this embodiment mode.

[0075] (Embodiment 1) In this embodiment mode, a flip-flop, a driver circuit including the flip-flop, and a driver circuit including the flip-flop will be described. The configuration of a display device having the driver circuit and a driving method thereof will be described.

[0076] The basic structure of a flip-flop of this embodiment will be described with reference to FIG. The flip-flop shown includes a first transistor 101, a second transistor 102, a third transistor 103, and a the first transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor The transistor 106 and the seventh transistor 107 are included. The first transistor 101, the second transistor 102, the third transistor 103, and the fourth transistor the first transistor 104, the fifth transistor 105, the sixth transistor 106 and the seventh transistor The transistor 107 is an N-channel transistor, and the gate-source voltage (V When the gate voltage (g) exceeds the threshold voltage (Vth), the transistor becomes conductive.

[0077] The connection relationship of the flip-flop in FIG. The electrode (either the source electrode or the drain electrode) is connected to the fifth wiring 125, and the first transistor The second electrode (the other of the source electrode and the drain electrode) of the transistor 101 is connected to the third wiring 12. 3. The first electrode of the second transistor 102 is connected to the fourth wiring 124. The second electrode of the second transistor 102 is connected to a third wiring 123. The first electrode of the third transistor 103 is connected to the sixth wiring 126. The second electrode is connected to the gate electrode of the second transistor 102, and the third transistor 1 The gate electrode of the fourth transistor 104 is connected to the seventh wiring 127. The second electrode of the fourth transistor 104 is connected to the ninth wiring 129, and the second electrode of the fourth transistor 104 is connected to the second wiring 129. The gate electrode of the fourth transistor 104 is connected to the gate electrode of the first transistor 102. The first gate electrode of the fifth transistor 105 is connected to the gate electrode of the fifth transistor 101. The second electrode of the fifth transistor 105 is connected to the eighth wiring 128, and the second electrode of the fifth transistor 105 is connected to the first wiring 128. The gate electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101. The first electrode of the sixth transistor 106 is connected to the tenth wiring 121. 30, and the second electrode of the sixth transistor 106 is connected to the first transistor 101. The gate electrode of the sixth transistor 106 is connected to the gate of the second transistor 1 The first electrode of the seventh transistor 107 is connected to the gate electrode of the eleventh wiring. 131, and the second electrode of the seventh transistor 107 is connected to the first transistor 101 The gate electrode of the seventh transistor 107 is connected to the second wiring 122. Connected.

[0078] The gate electrode of the first transistor 101 and the gate electrode of the fourth transistor 104 , a second electrode of the fifth transistor 105, a second electrode of the sixth transistor 106, and The connection point of the second electrode of the seventh transistor 107 is a node 141. the gate electrode of the first transistor 102, the second electrode of the third transistor 103, The connection point of the second electrode of the sixth transistor 104 and the gate electrode of the sixth transistor 106 is Let's call it node 142.

[0079] The fourth wiring 124, the ninth wiring 129, the tenth wiring 130 and the eleventh wiring 13 1 may be connected to each other or may be the same wiring. The eighth wiring 128 may be connected to each other or may be the same wiring.

[0080] The first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, and The sixth wiring 126 is connected to the first signal line, the second signal line, the third signal line, and the fourth signal line. , and the fifth signal line. The wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 are respectively The first power line, the second power line, the third power line, the fourth power line, the fifth power line, the sixth power line, It may also be called a source line.

[0081] The seventh wiring 127 and the eighth wiring 128 are supplied with a potential of V1. The first wiring 124, the ninth wiring 129, the tenth wiring 130 and the eleventh wiring 131 are Each is supplied with a potential of V2. Furthermore, V1>V2.

[0082] The first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126 A signal is input to each of the first wiring 121 and the second wiring 122. The signal input to the first wiring 121 is a start signal. The signal input to the second wiring 122 is a reset signal, and the signal input to the fifth wiring 125 is a reset signal. The signal input to the sixth wiring 126 is the first clock signal, and the signal input to the sixth wiring 127 is the second clock signal. Furthermore, the first wiring 121, the second wiring 122, the fifth wiring 125 and The potential of the H signal is V1 (hereinafter referred to as H level) and the potential of the H signal is V2 (hereinafter referred to as H level). The potential of the L signal is V2 (hereinafter also referred to as the L level).

[0083] The first wiring 121, the second wiring 122, and the second wiring 122 to the eleventh wiring 131 may be input with various signals, potentials, and currents.

[0084] A signal is output from the third wiring 123. is the output signal of the flip-flop of each stage, and the output signal of the flip-flop of the next stage Furthermore, the signal output from the third wiring 123 is also a start signal (hereinafter also referred to as a transfer signal). The potential of the H signal is V1 (hereinafter also referred to as the H level), and the potential of the L signal is V2. (hereinafter referred to as L level) digital signal.

[0085] Next, the operation of the flip-flop shown in FIG. 1 will be explained with reference to the timing chart and FIG. 3. Furthermore, the timing chart of FIG. The non-selection period is divided into a first non-selection period, a second non-selection period, and a set The non-selection period is divided into a set period and a reset period. The operation period excluding the selection period and the reset period includes a first non-selection period and a second non-selection period. Repeat in order.

[0086] In FIG. 2, the signals 221, 225, 226, the potential 241, the potential 242, The signal 222 and the signal 223 are signals input to the first wiring 121 and the fifth wiring 122, respectively. A signal input to the sixth wiring 125, a signal input to the sixth wiring 126, the potential of the node 141, The potential of the node 142, the signal input to the second wiring 122, the signal output from the third wiring 123, The figure shows the signal.

[0087] First, during the set period shown in FIGS. 2(A) and 3(A), since signal 221 is at the H level, the fifth transistor 105 is turned on, and since signal 222 is at the L level, the seventh transistor 107 is turned off. At this time, the potential of node 141 is such that the second electrode of the fifth transistor 105 becomes the source electrode, and it is a value obtained by subtracting the threshold voltage of the fifth transistor 105 from the potential of the eighth wiring 128, so it becomes V1 - Vth(105) (Vth(105): the threshold voltage of the fifth transistor 105). Therefore, the first transistor 101 and the fourth transistor 104 are turned on, and the fifth transistor 105 is turned off. At this time, the potential of node 142 (potential 242) is determined by the resistance ratio (L / W and applied voltage) between the third transistor 103 and the fourth transistor 104, and becomes V2 + β (β: an arbitrary positive number ). Furthermore, let β < Vth(102) (Vth(102): the threshold voltage of the second transistor 10 2) and β < Vth(106) (the threshold voltage of the sixth transistor 106). That is, the potential difference (V1 - V2) between the potential (V2) of the ninth wiring 129 and the potential (V1 ) of the sixth wiring 126 is divided by the third transistor 103 and the fourth transistor 104. Therefore, the second transistor 102 and the sixth transistor 106 are turned off. Thus, during the set period, since the third wiring 123 is connected to the fifth wiring 125 with an L signal input, the potential of the third wiring 123 becomes V2. Therefore, an L signal is output from the third wiring 123. Furthermore, node 141 remains in a floating state while maintaining the potential at V1 - Vth(105).

[0088] During the selection period shown in FIGS. 2(B) and 3(B), signal 221 becomes at the L level, and the fifth transistor​​​​​​​​​​​​​​ The seventh transistor 105 is turned off and the signal 222 remains at the L level. 7 remains off. At this time, the potential of the node 141 is maintained at V1-Vth(105). Therefore, the first transistor 101 and the fourth transistor 104 remain on. At this time, the potential of the node 142 is V 2. Therefore, the second transistor 102 and the sixth transistor 106 remain off. Here, since an H signal is input to the fifth wiring 125, the voltage of the third wiring 123 At this time, the potential of node 141 rises to V V1+Vth(101)+α(Vth(101):Vth(105)) 1, and α is an arbitrary positive number). The potential of the fifth wiring 123 is equal to that of the fifth wiring 125, and is therefore V1. The bootstrap operation is performed by connecting the gate electrode of the first transistor 101 to the second electrode of the first transistor 102. In this manner, during the selection period, the third wiring 123 Since the third wiring 123 is electrically connected to the fifth wiring 125 to which the H signal is input, the potential of the third wiring 123 Therefore, the H signal is output from the third wiring 123.

[0089] During the reset period shown in FIG. 2(C) and FIG. 3(C), the signal 221 remains at the L level. The fifth transistor 105 remains off, and the signal 222 goes high to turn on the seventh transistor. The transistor 107 turns on. At this time, the potential of the node 141 is equal to the potential of the 11th wiring ( V2) is supplied via the seventh transistor 107, so it becomes V2. The transistor 101 and the fourth transistor 104 are turned off. At this time, the node 142 The potential of the third transistor 103 is supplied to the sixth wiring 1 Since the potential (V1) of 26 is subtracted by the threshold voltage of the third transistor 103, V1-Vth(103) (Vth(103): threshold voltage of the third transistor 103) ) As a result, the second transistor 102 and the sixth transistor 106 are turned on. In this way, during the reset period, the third wiring 123 is connected to the fourth wiring 123 to which V2 is supplied. 124, the potential of the third wiring 123 becomes V2. 3 is output from wiring 123.

[0090] During the first non-selection period shown in FIG. 2(D) and FIG. 3(D), the signal 221 remains at the L level. Therefore, the fifth transistor 105 remains off, and the signal 222 becomes L level, and the seventh The transistor 107 is turned off. At this time, the potential of the node 142 is Since an L signal is input to the second transistor 102, the voltage becomes V2. The transistor 106 is turned off. At this time, the node 141 is in a floating state, and the potential is V 2. Therefore, the first transistor 101 and the fourth transistor 104 are turned off. In this way, during the first non-selection period, the third wiring 123 is in a floating state. Therefore, the potential of the third wiring 123 is maintained at V2.

[0091] During the second non-selection period shown in FIG. 2(E) and FIG. 3(E), the signal 221 remains at the L level. Therefore, the fifth transistor 105 remains off and the signal 222 remains at the L level. The seventh transistor 107 remains off. At this time, the potential of the node 142 is Since the H signal is input to the wiring 126 and the transistor 104 is turned off, V1-Vth (103). Therefore, the second transistor 102 and the sixth transistor 106 At this time, the potential of the node 141 is set such that the potential (V2) of the tenth wiring 130 is higher than the potential (V3) of the sixth wiring 130. The voltage remains V2 because it is supplied through the first transistor 106. The second non-transistor 101 and the fourth transistor 104 remain off. During the selection period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied. Therefore, the potential of the third wiring 123 remains at V2. It is output from 3.

[0092] From the above, the flip-flop in Figure 1 operates in bootstrap mode during the selection period. By using this operation, the potential of the node 141 is made higher than V1+Vth(101). The potential of the third wiring 123 can be set to V1. This bootstrap operation is performed by connecting the second electrode and gate electrode of the first transistor 101. This is done by using capacitive coupling of the parasitic capacitance between the This provides benefits such as a reduction in the number of children.

[0093] Furthermore, the flip-flop of FIG. 1 includes the second transistor 102 and the sixth transistor Since the second transistor 106 is turned on only during the second non-selection period, the second transistor 102 and Therefore, the shift in the threshold voltage of the transistor 106 in No. 6 can be suppressed.

[0094] In addition, in the flip-flop of FIG. 1, V1 is supplied to the gate electrode of the third transistor 103. By inputting a second clock signal to the first electrode, the third transistor 103 The shift in threshold voltage can also be suppressed.

[0095] Furthermore, the flip-flop of FIG. 04, the fifth transistor 105 and the seventh transistor 107 are in the first non-selection period and Since the first transistor 101 and the fourth transistor 102 are not turned on during the second non-selection period, The threshold voltages of the fifth transistor 104, the fifth transistor 105 and the seventh transistor 107 are The shift can be suppressed.

[0096] Furthermore, in the flip-flop of FIG. 1, the potential of the node 141 and the potential of the third wiring 123 are Even if the voltage fluctuates during the first non-selection period, the voltages of the nodes 141 and 142 will remain constant during the next second non-selection period. By supplying V2 to the third wiring 123, the potential of the node 141 and the potential of the third wiring 123 The potential can be reset to V2. Therefore, the flip-flop of Figure 1 The node 141 and the wiring 123 are in a floating state, and the potential of the node 141 and the third wiring 123 This can suppress malfunctions caused by fluctuations in the

[0097] Furthermore, the flip-flop in Figure 1 can suppress the threshold shift of the transistor, It is possible to suppress malfunctions caused by a shift in the threshold voltage of a transistor.

[0098] Furthermore, the flip-flop of FIG. 1 includes the first transistor 101 to the seventh transistor 107 are all composed of N-channel transistors. The flop can use amorphous silicon as the semiconductor layer of the transistor. This allows for the simplification of the manufacturing process, reducing manufacturing costs and improving yields. Furthermore, it is possible to fabricate a large display device. Even if polysilicon or polycrystalline silicon is used as the semiconductor layer of the photoresist, the manufacturing process can be simplified. It is possible.

[0099] The flip-flop in Figure 1 has a semiconductor layer that is prone to characteristic degradation (threshold voltage Even when amorphous silicon is used, where the voltage shift is clearly visible, the degradation of transistor characteristics is not Since the increase in the capacitance can be suppressed, a display device with a long lifetime can be manufactured.

[0100] Here, functions of the first to eighth transistors 101 to 108 will be described. The first transistor 101 supplies the potential of the fifth wiring 125 to the third wiring 123. The timing is selected to raise the potential of the node 141 by the bootstrap operation. The second transistor 10 has a function of blocking the first and second gates of the transistors 10 and 10, and functions as a bootstrap transistor. 2 is a function of selecting the timing for supplying the potential of the fourth wiring 124 to the third wiring 123. The third transistor 103 has a sixth a resistor element or a resistor component that has a function of dividing the potential of the wiring 124 and the potential of the ninth wiring 129; The fourth transistor 104 functions as a transistor having the ninth wiring 129. The switching transistor has a function of selecting the timing at which the potential of the The fifth transistor supplies the potential of the eighth wiring to the node 141. The sixth transistor has the function of selecting the timing to The transistor 106 selects the timing to supply the potential of the tenth wiring 130 to the node 141. The seventh transistor 10 has a function of selecting the first and second terminals and functions as a switching transistor. 7 has a function of selecting the timing at which the potential of the eleventh wiring 131 is supplied to the node 141. The first transistor 101 has a gate electrode 102 and functions as a switching transistor. The first to seventh transistors 107 are not limited to transistors as long as they have the functions described above. For example, the second transistor 102 that functions as a switching transistor , the fourth transistor 104, the sixth transistor 106, and the seventh transistor 107 If it is an element with a switching function, it can be a diode, a CMOS analog switch, or Various logic circuits may be applied. The transistor 105 in No. 5 increases the potential of the node 141 to select the timing to turn it off. It is sufficient if it has the function of Any of the above may be applied.

[0101] The third transistor 103 and the fourth transistor 104 constitute an AC pulse generating circuit. The AC pulse generating circuit receives an input from the first electrode of the third transistor 103. The AC pulse generating circuit outputs a signal to the node 142. When the gate electrode of the third transistor 104 is at H level, It outputs an L signal to node 142 regardless of the signal input from

[0102] In the flip-flop of this embodiment, the first transistor 101 to the seventh transistor Among the W / L values ​​of the first transistor 101 and the second transistor 107, When the value is maximized, the fall time and rise time of the signal 223 are shortened. As a result, the flip-flop of this embodiment can provide a large Even when a load is connected, it is possible to output a signal with little distortion or delay.

[0103] Furthermore, in the flip-flop of this embodiment, the W / L of the first transistor 101 The value of W / L is preferably 2 to 5 times larger than the value of W / L of the fifth transistor 105. More preferably, it is three to four times as many. Even if a large load is connected to the wiring 123, a signal with little distortion or delay can be output. can.

[0104] Furthermore, in the flip-flop of this embodiment, the W / L of the fourth transistor 104 If the value of W / L is made larger than the value of W / L of the third transistor 103, The potential of the node 142 can be reduced. The flip-flop can reliably turn off the sixth transistor 106 during the set period, thereby suppressing malfunction. It can be controlled.

[0105] Furthermore, in the flip-flop of this embodiment, the value of L of the third transistor 103 is preferably greater than the value of L of the fourth transistor 104, and more preferably 2 This makes the flip-flop of this embodiment a third transistor. Since the value of W / L of the fourth transistor 103 is small, the value of W of the fourth transistor 104 is small. This allows the layout area to be reduced.

[0106] If the operation is the same as that shown in FIG. 1, the arrangement and number of transistors may be the same as those shown in FIG. As can be seen from FIG. 3, which illustrates the operation of the flip-flop of FIG. In this embodiment, a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period are included. It is sufficient that conduction is maintained during the periods shown by the solid lines in FIGS. Therefore, if the transistors and other components are arranged and operated in a way that satisfies this requirement, resistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches, various logic A new circuit or the like may be arranged.

[0107] For example, in the flip-flop shown in FIG. 4A, the gate electrode of the first transistor 101 By disposing the capacitor element 401 between the first electrode and the second electrode, bootstrap Furthermore, the flip-flop shown in FIG. Since the parasitic capacitance between the gate electrode and the second electrode of the transistor 101 can be reduced, Each transistor can be switched at high speed. Alternatively, as shown in Figure 4(B), A transistor 402 may be used as the element 401. The transistor 402 has a gate voltage The first electrode is connected to the node 141, and the first electrode and the second electrode are connected to the third wiring 123. By doing so, it can function as a capacitive element with a large capacitance component. The resistor 402 does not function as a capacitor even if either the first electrode or the second electrode is floating. In addition, the same reference numerals are used to describe the components common to the configuration in FIG. Omitted.

[0108] The capacitor 401 uses a gate insulating film as an insulating layer and a gate electrode layer as a conductive layer. Alternatively, a gate insulating film may be used as the insulating layer and a gate electrode may be used as the conductive layer. A polar layer and a semiconductor layer to which impurities are added may be used, and an interlayer film (insulating film) may be used as an insulating layer. However, the capacitor element 401 may be formed by using a wiring layer and a transparent electrode layer as a conductive layer. When a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is The wiring layer is connected to the gate electrode of the first transistor 101, and the wiring layer is connected to the second electrode of the first transistor 101. More preferably, when a gate electrode layer and a wiring layer are used as the conductive film, The gate electrode layer is directly connected to the gate electrode of the first transistor 101, and the wiring layer is connected to the gate electrode of the first transistor 102. It is preferable to directly connect the second electrode of the capacitor 101 to the second electrode of the capacitor 101. This is because the increase in layout area of ​​the flip-flops is small.

[0109] As another example, the flip-flop illustrated in FIG. 4C has a first transistor 101. By connecting the electrode of the first transistor 101 to the first wiring 121 (connecting the first transistor 101 as a diode), By connecting the eighth wiring 128, the eighth wiring 128 becomes unnecessary, and one wiring and power supply (V1) are reduced. In addition, the same reference numerals are used for the components common to the configuration in FIG. 1, and the description thereof will be omitted. do.

[0110] As another example, the flip-flop shown in FIG. 4D has a transistor By using the resistor element 403 instead, the number of wirings and power sources can be reduced by one. The flip-flop of FIG. 4D sets the potential of the node 142 to the sixth potential during the second non-selection period. Since the potential (V1) of the wiring 126 can be made equal to the potential (V1) of the wiring 126, the driving capability can be improved. Note that the same components as those in FIG. 1 are designated by the same reference numerals and their explanations are omitted.

[0111] As another example, the flip-flop shown in FIG. 7A has a gate of the second transistor 102. The second transistor 10 is connected to a wiring 711 to which a signal is input. A reverse bias can be applied to the gate electrode of the second transistor 102. Therefore, the threshold voltage shift of the second transistor 102 can be further suppressed. In addition, the same reference numerals are used to describe the components common to the configuration of FIG. Omitted.

[0112] As another example, the flip-flop shown in FIG. 7B has a gate of the second transistor 102. The set electrode is connected to the sixth wiring 126, so that the second transistor remains in the set state even during the set period. Since the third wiring 102 can be turned on, the driving capability can be improved. 23 can be achieved. The parts common to the configuration of FIG. 1 are designated by the same symbols. The explanation will be omitted by using the numbers.

[0113] As another example, a flip-flop shown in FIG. 7C has a second transistor instead of the third transistor 103. In addition, a diode-connected transistor 701 and a diode-connected transistor 702 are used. By using the first electrode of the transistor 701, the number of wirings and power supplies can be reduced by one. The second electrode of the transistor 702 and the gate electrode of the transistor 701 are connected to a sixth wiring 1 26, the second electrode of transistor 701, the second electrode of transistor 702, and The gate electrode of the transistor 702 is connected to the node 141. Two diodes in opposite directions are connected in parallel between the node 26 and the node 141. The same reference numerals are used for the components common to those in the previous example, and the description thereof will be omitted.

[0114] As another example, as shown in FIG. 21A, the sixth transistor 106 is not necessarily required. This is because the sixth transistor 106 does not have a voltage at the node 141 during the non-selection period. This is because it is not necessarily required if the level can be maintained at L level. The flip-flop in 21(A) can reduce the number of transistors, so the layout This has the advantage of reducing the area of ​​the circuit board. Common reference numerals will be used and their explanations will be omitted.

[0115] As another example, as shown in FIG. 21B, instead of the fourth transistor 104, an eighth The first electrode of the eighth transistor 2108 may be connected to the 12, and the second electrode of the eighth transistor 2108 is connected to the wiring 2132 of the node 14. 2, and the gate electrode of the eighth transistor 2108 is connected to the first wiring 121. Furthermore, V2 is supplied to the twelfth wiring 2132. ) flip-flop is turned on / off by the start signal. Since the fall time of the potential of the node 142 is controlled, the fall time of the potential of the node 142 is shortened during the set period. The second transistor 102 and the sixth transistor 106 are turned off. Furthermore, the flip-flop in FIG. 21(B) has a sixth transistor. Since the transistor 106 is turned off earlier, the voltage of the node 141 is Thus, the flip-flop shown in FIG. This flip-flop can improve the driving ability of the flip-flop. Where applicable, common reference numerals will be used and the description thereof will be omitted.

[0116] The eighth wiring 128 is connected to the fourth wiring 124, the ninth wiring 129, and the tenth wiring 130. Alternatively, it may be connected to the eleventh wiring 131 .

[0117] As another example, an eighth transistor 2108 may be added as shown in FIG. 21(C). The eighth transistor 2108 turns on the voltage of the node 142 when the start signal is at H level. Since it is sufficient to set the output to the L level, the transistor size can be reduced. The flip-flop (C) turns on the eighth transistor 2108 in response to the start signal. Since the off state is controlled, the flip-flop is the same as the flip-flop in Figure 22(B). The driving capability of the device can be improved. For the latter, common reference numerals will be used and their explanations will be omitted.

[0118] It should be noted that the connection relationship of each wire is not limited to that shown in FIG. 1, as long as the same operation as in FIG. 1 is performed. As can be seen from FIG. 3, which explains the operation of the flip-flop of FIG. 1, in this embodiment, The set period, selection period, reset period, first non-selection period and second non-selection period are respectively It is sufficient if the electrical continuity is established as shown by the solid lines in Figures 3(A) to 3(E). It is sufficient that the wiring is arranged or connected so as to satisfy the above requirements.

[0119] For example, as shown in FIG. 5A, the first electrode of the second transistor 102, the a first electrode of the sixth transistor 104, a first electrode of the seventh transistor 106, The first electrode of the resistor 107 may be connected to the sixth wiring 506. The first electrode of the transistor 103 and the first electrode of the fifth transistor 105 are connected to the seventh 5A may be connected to the line 507. Thus, the flip-flop of FIG. Compared to flip-flops, the number of wires can be reduced from 11 to 7. The flip-flop in 5(A) reduces the number of wires, which improves the yield of the shift register. Furthermore, the flip-flop shown in FIG. 5(A) has a wiring arrangement The area can be reduced, and the layout area of ​​the shift register can be reduced. The flip-flop in Fig. 5(A) can reduce the voltage drop because the width of each wiring can be increased. This improves the driving capability of the shift register. Wherever possible, common reference numerals will be used and their explanations will be omitted.

[0120] The sixth wiring 506 shown in FIG. 5A corresponds to the fourth wiring 124 and the ninth wiring 125 shown in FIG. These correspond to the line 129, the tenth wiring 130, and the eleventh wiring 131. Furthermore, in FIG. The seventh wiring 127 shown in FIG. 1 corresponds to the seventh wiring 127 and the eighth wiring 128 shown in FIG. Furthermore, the first wiring 501, the second wiring 502, and the third wiring 50 The third, fourth wiring 504 and fifth wiring 505 are respectively the first wiring 121 shown in FIG. , the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126. do.

[0121] The sixth wiring 506 and the seventh wiring 507 are respectively referred to as a first power supply line and a second power supply line. Furthermore, the first wiring 501, the second wiring 502, the third wiring 503, the The fourth wiring 504 and the fifth wiring 505 are respectively connected to the first signal line, the second signal line, and the third signal line. These may also be called the signal line, the fourth signal line, and the fifth signal line.

[0122] As another example, as shown in FIG. 5B, the first electrode of the fourth transistor 104 may be connected to the eighth The flip-flop in FIG. 5B may be connected to the wiring 508 in the set period. The instantaneous current generated in the fourth transistor 104 is passed through the eighth wiring 508, It is possible to suppress malfunction due to a voltage drop in the wiring 506. Note that, in FIGS. The same reference numerals are used for the components common to those in the previous example, and the description thereof will be omitted.

[0123] As another example, as shown in FIG. 5C, the first electrode of the second transistor 102 may be connected to the ninth The flip-flop in FIG. 5B may be connected to the wiring 509 in the reset period. The instantaneous current generated in the second transistor 102 is passed through the ninth wiring 509, It is possible to suppress malfunctions due to voltage drops in the wiring 506. ) will be designated by the same reference numerals and the description thereof will be omitted.

[0124] As another example, as shown in FIG. 5D, the gate electrode of the third transistor 103 is The flip-flop in FIG. 5D may be connected to the tenth wiring 510. If a potential lower than V1 is supplied to 10, the second transistor The potential of the gate electrode of the sixth transistor 102 and the potential of the gate electrode of the sixth transistor 106 are lowered. Therefore, deterioration of the characteristics of the second transistor 102 and the sixth transistor 106 can be suppressed. In addition, the same reference numerals are used to designate the parts common to the configurations in FIG. 1 and FIG. 5(A). The explanation will be omitted.

[0125] If the same operation as in FIG. 1 is performed, the power supply potential, signal amplitude, and signal timing are The timing chart is not limited to that of Figure 2. As can be seen from 3, in this embodiment, there are a set period, a selection period, a reset period, and a first The non-selection period and the second non-selection period are respectively indicated by the solid lines in FIGS. 3(A) to 3(E). Therefore, the power supply potential, signal amplitude and signal type are set to satisfy this. You may change the timing.

[0126] For example, as shown in the timing chart of FIG. 6, the first wiring 121 and the fifth wiring 125 2. Alternatively, the period for inputting the H signal to the sixth wiring 126 may be shortened. Compared with the timing chart, the timing when the signal switches from L level to H level is within the period Ta The timing at which the signal switches from H level to L level is delayed by period Ta2. In other words, in FIG. 6, the period during which the signal is at the H level (period Tb ) is shortened by period Ta1 + period Ta2. The flip-flops that use this technology have a smaller instantaneous current in each wiring, which reduces power consumption and prevents malfunctions. This can suppress the operation and improve the driving capacity. In the reset period, the flip-flop to which the above-mentioned method is applied outputs a signal from the third wiring 123. This shortens the fall time of the signal that is output when the potential of the node 141 becomes L level. The timing for this is delayed by a period Ta1 + a period Ta2, so the L signal input to the fifth wiring 125 is supplied to the third wiring 123 through the first transistor 101 with a large current capacity (large channel width). This is why. The parts common to the timing chart of FIG. 2 are denoted by common reference numerals and their description is omitted.

[0127] Note that the relationship among the periods Ta1, Ta2, and Tb is desirably ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 < 10 [%]. More desirably, ((T (Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 < 5 [%] is desirable. Furthermore, it is desirable that the period Ta1 ≒ the period Ta2.

[0128] As another example, when Va (V2 < Va < V1) is supplied to the seventh wiring 127, the potential at the node 142 becomes Va - Vth(103) during the reset period and the second non - selection period, so that the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed.

[0129] As another example, when Vb (V1 + Vth(103) < Vb) is supplied to the seventh wiring 127, the potential at the node 142 becomes V1 during the reset period and the second non - selection period, so that the second transistor 102 and the sixth transistor 106 can be easily turned on.

[0130] As another example, by setting the potential of the L signal input to the sixth wiring 126 to Vc (Vc < V2) and the potential of the H signal to Vd (V1 > Vd > V2), the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed. Because, when setting During the first non-selection period and the first non-selection period, the potential of the node 142 becomes Vc, and the second transistor This is because a reverse bias is applied to the first transistor 102 and the sixth transistor 106. During the reset period and the second non-selection period, the potential of the node 142 becomes Vd, and This is because the Vgs of the first transistor 102 and the sixth transistor 106 become smaller.

[0131] An example of a top view of the flip-flop shown in FIG. 5(A) is shown in FIG. 25. The conductive layer 2501 , the gate electrode of the second transistor 102, the gate electrode of the sixth transistor 106, The conductive layer 2502 includes a portion that functions as a conductive layer 2503 and is connected to the conductive layer 2502 via a wiring 2547. 02 is the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, The conductive layer 2503 includes a portion that functions as a first electrode of the second transistor 102. a first electrode of the sixth transistor 106; a first electrode of the fourth transistor 104; The conductive layer 2504 includes a portion that functions as a second wiring and is connected to the sixth wiring 506. The third electrode 2548 includes a portion that functions as the second electrode of the transistor 102. The conductive layer 2505 is connected to the wiring 503. The seventh transistor 107 includes a portion serving as a second electrode thereof and is connected to the first electrode of the seventh transistor 107 through a wiring 2549. The conductive layer 2506 is connected to the first conductive layer 2510 of the seventh transistor 107. The conductive layer 2507 includes a portion that functions as an electrode and is connected to the sixth wiring 506. 2541 through a wiring 2541. The conductive layer 2508 is connected to the fourth wiring 504. It includes a portion that functions as an electrode and is connected to the third wiring 503 via a wiring 2548 . The conductive layer 2510 is a gate electrode of the first transistor 101, a gate electrode of the fourth transistor 104, and a gate electrode of the fourth transistor 104. The conductive layer 2511 includes a portion that functions as a gate electrode of the seventh transistor 107. The gate electrode 2546 is connected to the second wiring 502. The conductive layer 2512 is a portion that functions as a gate electrode of the third transistor 103. and is connected to the seventh wiring 507 via a wiring 2544. The conductive layer 2513 is The first electrode of the transistor 103 is connected to the first electrode of the transistor 103 through a wiring 2543. The conductive layer 2514 is connected to the gate electrode 505 of the fifth transistor 105. It includes a portion that functions as an electrode and is connected to the first wiring 501 via a wiring 2545. The electrode layer 2515 includes a portion that functions as the second electrode of the sixth transistor 106. It is connected to the conductive layer 2510 via a line 2547 .

[0132] Note that the first transistor 101 has a gate electrode, a first electrode, and a second electrode. The portions are formed by overlapping the conductive layer including each of them with the semiconductor layer 2581. The portions functioning as the gate electrode, the first electrode, and the second electrode of the second transistor 102 are The portions are formed by overlapping the conductive layer including each of them with the semiconductor layer 2582. The portions functioning as the gate electrode, the first electrode, and the second electrode of the third transistor 103 are , and the conductive layer including the semiconductor layer 2583 overlap each other. The portions functioning as the gate electrode, the first electrode, and the second electrode of the transistor 104 are The fifth transistor is formed by overlapping the conductive layer including the first and second transistors and the semiconductor layer 2584. The portions of the transistor 105 that function as the gate electrode, the first electrode, and the second electrode are This is a portion where the conductive layer including the transistor and the semiconductor layer 2585 overlap. The portions of the gate electrode, the first electrode, and the second electrode of the gate electrode 106 are respectively The seventh transistor is formed by overlapping a conductive layer containing the semiconductor layer 2586. The portions functioning as the gate electrode, the first electrode, and the second electrode of 107 include This is the portion where the conductive layer and the semiconductor layer 2587 overlap each other.

[0133] The configuration and driving method of the shift register having the flip-flop of this embodiment mode described above We will explain about this.

[0134] The configuration of the shift register of this embodiment will be described with reference to FIG. The register consists of n flip-flops (flip-flop 1001_1 to flip-flop 1001_2). It has a function (top 1001_n).

[0135] The connection relationship of the shift register in Fig. 10 will be explained. The shift register in Fig. 10 has i-stage Flip-flop 1001_i (Flip-flop 1001_1~1001_n) Any one of them is a second wiring 1012, a third wiring 1013, a fourth wiring 1014, The fifth wiring 1015, the sixth wiring 1016, the eighth wiring 1018_i-1, the eighth wiring 10 18_i and the eighth wiring 1018_i+1. The chip 1001_1 includes a first wiring 1011, a second wiring 1012, a third wiring 1013, A fourth wiring 1014, a fifth wiring 1015, a sixth wiring 1016, an eighth wiring 1018 1 and the eighth wiring 1018_2. Furthermore, the nth stage flip-flop 100 1_n is a second wiring 1012, a third wiring 1013, a fourth wiring 1014, a fifth wiring 1015, a sixth wiring 1016, a seventh wiring 1017, an eighth wiring 1018_n-1, and It is connected to the eighth wiring 1018_n.

[0136] The first wiring 1011 is connected to the first wiring 121 of the flip-flop 1001_1 shown in FIG. The second wiring 1012 is connected to the fifth wiring shown in FIG. In the even-numbered flip-flops, the sixth wiring 126 shown in FIG. The third wiring 1013 is connected to the sixth wiring shown in FIG. In the even-numbered flip-flops, the fifth wiring 125 shown in FIG. The fourth wiring 1014 is connected to the seventh wiring 1012 shown in FIG. 27. The fifth wiring 1015 is connected to the eighth flip-flop shown in FIG. The sixth wiring 1016 is connected to the wiring 128. Connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130 and the eleventh wiring 131 The eighth wiring 1018_i is connected to the flip-flop 1001_i-1 shown in FIG. The second wiring 122, the third wiring 123 and the flip-flop 1001_i shown in FIG. The flip-flop 1001_i+1 is connected to the first wiring 121 shown in FIG. The eighth wiring 1018_1 is connected to the third wiring 12 shown in FIG. 1 of the flip-flop 1001_1. 3 and the first wiring 121 of the flip-flop 1001_2 shown in FIG. The eighth wiring 1018_n is connected to the second flip-flop 1001_n-1 shown in FIG. The wiring 122 and the third wiring 123 of the flip-flop 1001_n shown in FIG. do.

[0137] The fourth wiring 1014 and the fifth wiring 1015 are supplied with a potential of V1. The sixth wiring 1016 is supplied with a potential of V2.

[0138] The first wiring 1011, the second wiring 1012, the third wiring 1013 and the seventh wiring 1014 are A signal is input to each of the first wirings 1017. The signal input to the second wiring 1012 is the first clock signal, and the signal input to the third wiring 1013 is the second clock signal. The signal input to the wiring 1013 is the second clock signal, and the signal input to the seventh wiring 1017 is the second clock signal. The signal to be sent is a reset signal. The signals input to the third wiring 1013 and the seventh wiring 1017 are at a potential of an H signal. is a digital signal with the potential of V1 and the potential of the L signal is V2.

[0139] Note that various signals, power supply potentials, or currents are applied to the first wiring 1011 to the seventh wiring 1017. may be input.

[0140] Signals are output from the eighth wirings 1018_1 to 1018_n. For example, the signal output from the eighth wiring 1018_i is the output of the flip-flop 1001_i. Furthermore, the signal output from the eighth wiring 1018_i is a flip-flop. The start signal of flip-flop 1001_i+1 and the reset signal of flip-flop 1001_i-1 It is also the number.

[0141] Note that the signals input to or voltages supplied to the first wiring 1011 to the seventh wiring 1017 are If the wirings are the same, the first wiring 1011 to the seventh wiring 1017 may be connected to each other. Alternatively, the same wiring may be used.

[0142] Next, the operation of the shift register shown in FIG. 10 will be described with reference to the timing chart and The following description will be made with reference to the timing chart of Fig. 12. The scanning period is divided into a scanning period and a blanking period. The output of the selection signal from the eighth wiring 1018_n is started until the output of the selection signal from the eighth wiring 1018_n is completed. The blanking period is a period in which the output of the selection signal from the eighth wiring 1018_n is completed. This is the period until the output of the selection signal from the eighth wiring 1018_1 starts.

[0143] In FIG. 11, a signal 1111 is input to the first wiring 1011, and a signal 1112 is input to the second wiring 1012. 12, a signal 1112 input to the third wiring 1013, a signal 1113 input to the seventh wiring 1014, A signal 1117 input to the wiring 1017, a signal 8 output to the eighth wiring 1018_1 1018_2 and a signal 1118_n output to the eighth wiring 1018_n. Furthermore, in FIG. 12, a signal 1211 input to the first wiring 1011, A signal 1218_1 is output to the wiring 1018_1, and a signal 1218_2 is output to the eighth wiring 1018_i. signal 1218_i, a signal 1218_i+1 output to the eighth wiring 1018_i+1, and A signal 1218_n output to an eighth wiring 1018_n is shown.

[0144] As shown in FIG. 12, for example, when the flip-flop 1001_i is in the selection period ( At this time, the flip-flop 1001_i outputs a high-level signal. i+1 is the set period. After that, flip-flop 1001_i is in the reset period. As a result, an L signal is output from the eighth wiring 1018_i. 001_i+1 is the selected period. After that, the flip-flop 1001_i is the first non-selected In the selection period, the eighth wiring 1018_i is in a floating state and the potential is maintained at the L level. At this time, the flip-flop 1001_i+1 is in the reset period. The flip-flop 1001_i is in the second non-selection period and outputs the L signal from the eighth wiring 1018_i. At this time, the flip-flop 1001_i+1 is in the first non-selection period. In this way, the flip-flop 1001_i remains in the first non-selection period until the next set period. The first and second non-selection periods are repeated.

[0145] From the above, the shift register of FIG. 10 sequentially transmits the selection signal from the eighth wiring 1018_1. 10. That is, the shift register 1018_n can output up to the eighth wiring 1018_n. can scan the eighth wirings 1018_1 to 1018_n. Therefore, the shift register of FIG. 10 can fully function as a shift register. .

[0146] Furthermore, the reset signal input to the flip-flop 1001_n in the final stage is The input is made via line 1017. By doing so, the shift register of FIG. The standard reduces the layout area by eliminating the need for dummy flip-flops. However, a dummy flip-flop may be placed.

[0147] Furthermore, the shift register of FIG. 10 is configured such that the timing of the signal input to the first wiring 1011 is Therefore, the blanking period can be freely determined.

[0148] Furthermore, the shift register of FIG. 10 applies the flip-flop shown in this embodiment. This makes it possible to suppress the threshold shift of the transistor. Furthermore, the shift register shown in FIG. It is possible to improve the dynamic capability. Furthermore, it is possible to suppress malfunctions. The shift register of FIG. 10 can simplify the manufacturing process.

[0149] It should be noted that the configuration is not limited to that of FIG. 10 as long as it performs the same operation as that of FIG.

[0150] For example, as shown in Figure 13, the output signals of each flip-flop are buffered and The shift register in FIG. 13 includes flip-flops 1001_1 to 1001_2. The flop 1001_n is connected to the buffer 1301_1 through the buffer 1301_n. 1018_1 to 1018_n, and thus a wide driving capability is provided. This is because the eighth wiring 1018_1 to the eighth wiring 1018_n are When a large load is connected to the eighth wiring 1018_1 to the eighth wiring 1018_n, The signals output from the eighth wiring 1018_1 to The delay and distortion of the signal output from each of the eighth wirings 1018_n are calculated by the shift register. This is because it does not affect the operation of the device. Note that the same reference numerals are used for the parts common to the configuration in FIG. Therefore, the explanation will be omitted.

[0151] Each of the buffers 1301_1 to 1301_n is a NAND, NOR, etc. Logic circuits, operational amplifiers, and circuits that combine these can be used. In other words, an inverter or an analog buffer can be used. Each of the buffers 301_1 to 1301_n has an N-channel flip-flop. If the transistor is an N-channel transistor, it is preferable that the transistor is an N-channel transistor. Furthermore, each of the buffers 1301_1 to 1301_n is a buffer for bootstrap operation. It is desirable to have a configuration that allows for this operation. The drive voltage (potential difference between the negative and positive power supplies) of each 1301_n flip-flop is It is preferable that the drive voltage of each of the flip-flops 001_1 to 1001_n is larger than that of the other. It's nice.

[0152] Here, the buffers 1301_1 to 1301_2 included in the shift register shown in FIG. An example of the _n will be described with reference to Figs. 123(A) and 123(B). The buffer 8000 shown in A) has an inverter 8001 between a wiring 8011 and a wiring 8012. a, inverter 8001b, and inverter 8001c are connected, and wiring 8011 An inverted signal of the input signal is output from the wiring 8012. However, the wiring 8011 and the wiring There is no limit to the number of inverters connected between the wiring 8011 and the wiring 8012. When an even number of inverters are connected between the wiring 8011 and the inverter 12, the same signal as that input to the wiring 8011 is output. A signal of the same polarity is output from the wiring 8012. Furthermore, the buffer 810 in FIG. As shown in FIG. 0, an inverter 8002a, an inverter 8002b, and an inverter 8002c are connected in series. Inverter 8002c, inverter 8003a, inverter 8003b arranged in series and inverter 8003c may be connected in parallel. 00 can average out the variations in transistor characteristics, so it is output from wiring 8012. Furthermore, the inverter 8002a and the inverter 8002b can reduce the delay and distortion of the signal. The outputs of inverter 8002a and inverter 8002b are mutually may be connected to either

[0153] In FIG. 123A, the W<in> of the transistors included in the inverter 8001a is The W of the transistors in inverter 8001b is less than the W of the transistors in inverter 8001c. It is preferable to set the W of the inverter 8001a to a small value. The driving capability of the flip-flop (specifically, the W / L value of the transistor 101 in FIG. 1) is reduced. Therefore, the layout area of ​​the shift register of this embodiment can be reduced. In FIG. 123B, the W<inverter The W of the transistors in the inverter 8002b is less than the W of the transistors in the inverter 8002c. Similarly, in FIG. 123(B), the inverter 8003a is The W of the transistors in the inverter 8003b is less than the W of the transistors in the inverter 8003b. It is preferable that the transistor W of the inverter 8003c is used. W of the transistor in inverter 8003a = W of the transistor in inverter 8003a W of the transistor in inverter 8002b = W of the transistor in inverter 8003b W of the transistor in inverter 8002c = W of the transistor in inverter 8003c It is preferable to set the W of the transistor.

[0154] The inverters shown in FIGS. 123(A) and 123(B) are configured to convert the input signal There is no particular limitation as long as it can be output in reverse. For example, as shown in Figure 123(C), Then, an inverter is formed by a first transistor 8201 and a second transistor 8202. Furthermore, a signal is input to the first wiring, and a signal is output from the second wiring 8212. A signal is output, V1 is supplied to the third wiring 8213, and V2 is supplied to the fourth wiring 8214. When an H signal is input to the first wiring 8211, the inverter in FIG. , V1-V2 is divided by the first transistor 8201 and the second transistor 8202. The order (W / L of the first transistor 8201<W / L of the second transistor 8202) is The output is from the second wiring 8212. Furthermore, the inverter in FIG. When an L signal is input to 8211, V1-Vth(8201) (Vth(8201): 1st The threshold voltage of the transistor 8201 is output from the second wiring 8212. The first transistor 8201 may be a PN junction diode as long as it has a resistance component. Alternatively, it may simply be a resistance element.

[0155] Furthermore, as shown in FIG. 123(D), the first transistor 8301 and the second transistor The inverter 8302, the third transistor 8303, and the fourth transistor 8304 Furthermore, a signal is input to the first wiring 8311, and a signal is input to the second wiring 8321. A signal is output from 8312, and V1 is output to the third wiring 8313 and the fifth wiring 8315. V is supplied to the fourth wiring 8314 and the sixth wiring 8316, and V2 is supplied to the fourth wiring 8314 and the sixth wiring 8316. When an H signal is input to the first wiring 8311, the inverter of (D) outputs V2 to the second wiring 8 At this time, the node 8341 is set to the L level potential, so the first transistor The transistor 8301 is turned off. Furthermore, the inverter of FIG. 123(D) has a first wiring 83 When an L signal is input to node 11, V1 is output from the second wiring 8312. The potential of 8341 is V1-Vth(8303) (Vth(8303): third transistor When the voltage reaches the threshold voltage of 8303, the node 8341 becomes floating, and the node 8341 The potential of V1+Vth(8301)(Vth(8301) : the threshold voltage of the first transistor 8301) becomes higher, The first transistor 8301 is turned on. Furthermore, the first transistor 8301 is a bootstrap transistor. Since it functions as a transistor, even if a capacitance element is disposed between the second electrode and the gate electrode, good.

[0156] Furthermore, as shown in FIG. 26A, a first transistor 8401 and a second transistor 8402, a third transistor 8403, and a fourth transistor 8404 The inverter in FIG. 26(A) is a two-input inverter, Furthermore, a signal is input to the first wiring 8411, and An inverted signal is input to the second wiring 8412, and a signal is output from the third wiring 8413. The fourth wiring 8414 and the sixth wiring 8416 are supplied with V1, and the fifth wiring 8415 and The inverter in FIG. 26A is connected to the first wiring 8411 and the seventh wiring 8417. When an L signal is input to 8411 and an H signal is input to the second wiring 8412, V2 is connected to the third wiring 841 At this time, the potential of the node 8441 becomes V2, so the first transistor 26A. Furthermore, the inverter in FIG. 26A has a first wiring 8411 connected to H When an L signal is input to the second wiring 8412, V1 is output from the third wiring 8413. At this time, the potential of the node 8441 is V1-Vth(8403) (Vth(8403) When the voltage Vth of the third transistor 8403 is equal to or lower than the threshold voltage Vth of the third transistor 8403, the node 8441 is in a floating state. The potential of the node 8441 becomes V1+Vth(8401) by the bootstrap operation. (Vth(8401): threshold voltage of the first transistor 8401) Then, the first transistor 8401 is turned on. To function as a basestrap transistor, a capacitance is created between the second electrode and the gate electrode. Furthermore, a capacitance element may be disposed between the first wiring 8411 and the second wiring 8412. One end is connected to the third wiring 123 shown in FIG. 1, and the other end is connected to the node 142 shown in FIG. It is best to continue.

[0157] Furthermore, as shown in FIG. 26(B), the first transistor 8501 and the second transistor An inverter may be configured by the transistor 8502 and the third transistor 8503. The inverter 6(B) is a two-input inverter and is capable of bootstrap operation. Furthermore, a signal is input to the first wiring 8511, and an inverted signal is input to the second wiring 8512. A signal is input to the third wiring 8513, a signal is output from the fourth wiring 8514, and a signal is output from the sixth wiring 8515. The first wiring 8516 is supplied with V2, and the fifth wiring 8515 is supplied with V2. The inverter in (B) inputs an L signal to the first wiring 8511 and an H signal to the second wiring 8512. When V2 is input, V2 is output from the third wiring 8513. At this time, the potential of the node 8541 is Since the voltage V2 is reached, the first transistor 8501 is turned off. When an H signal is input to the first wiring 8511 and an L signal is input to the second wiring 8512, 1 is output from the third wiring 8513. At this time, the potential of the node 8541 is V1-Vth (8503) (Vth(8503): threshold voltage of the third transistor 8503) Then, the node 8541 is in a floating state, and the potential of the node 8541 is V1+Vth(8501) (Vth(8501): first transistor 8501 Since the voltage at the first transistor 8501 becomes higher than the threshold voltage of the first transistor 8501, the first transistor 8501 is turned on. Since the first transistor 8501 functions as a bootstrap transistor, A capacitance element may be disposed between the second electrode and the gate electrode. The third wiring 123 shown in FIG. 1 is connected to one of the first wiring 11 and the second wiring 8512, and the other The node 142 shown in FIG. 1 may be connected to the other side.

[0158] Furthermore, as shown in FIG. 26(C), the first transistor 8601 and the second transistor 8602, a third transistor 8603, and a fourth transistor 8604 The inverter in FIG. 26(C) is a two-input inverter, Furthermore, a signal is input to the first wiring 8611, and An inverted signal is input to the second wiring 8612, and a signal is output from the third wiring 8613. V1 is supplied to the fourth wiring 8614, and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. 26A is supplied with an L signal to the first wiring 8611 and V2 to the second wiring 8622. When an H signal is input to the first wiring 8612, V2 is output from the third wiring 8613. Then, the potential of the node 8641 becomes V2, and the first transistor 8601 is turned off. Furthermore, the inverter of FIG. 26(C) has a first wiring 8611 that is connected to a H signal and a second wiring 861 When an L signal is input to node 8, V1 is output from the third wiring 8613. The potential of the third transistor 8603 is V1-Vth(8603) (Vth(8603): When the voltage reaches the threshold voltage of node 603, node 8641 becomes floating, and the voltage of node 8641 The voltage is V1+Vth(8601)(Vth(8601): Since the threshold voltage of the first transistor 8601 is higher than that of the first transistor 8602, 8601 is turned on. Furthermore, the first transistor 8601 is a bootstrap transistor. To function as a transistor, a capacitance element may be disposed between the second electrode and the gate electrode. Furthermore, one of the first wiring 8611 and the second wiring 8612 is connected to the first wiring 8611 shown in FIG. 1. The other end of the wiring 123 is connected to the node 142 shown in FIG.

[0159] As another example, the reset signal input to the flip-flop 1001_n is Other input or output signals of the flip-flop 100 can be used. By generating the reset signal input to 1_n inside the shift register, one array For example, if the flip-flop 1001_n is an even-numbered stage, In this case, as shown in FIG. 14, it may be connected to the eighth wiring 1018_1. When the flip-flop 1001_n is an even-numbered stage, as shown in FIG. Alternatively, as shown in FIG. 17, a dummy The flip-flop 1001_d is used to set the reset input to the flip-flop 1001_n. The dummy flip-flop 1001_d may generate a flip-flop The same as 1001_n-1 can be used, except that the dummy flip-flop The second wiring 122 shown in FIG. 1 of group 1001_d is connected to the sixth wiring 1016 shown in FIG. Note that the same reference numerals are used for the components common to those in FIG. 10, and the description thereof will be omitted.

[0160] Next, the structure and driving method of the display device having the shift register of the present embodiment will be described. However, the display device of this embodiment is at least All you need is a p-flop.

[0161] The structure of the display device of this embodiment will be described with reference to FIG. 18. 1801, a scanning line driver circuit 1802, and a pixel portion 1804. 1804, a plurality of signal lines S extending from the signal line driving circuit 1801 in the column direction are arranged. 1 to Sm, and a plurality of scanning lines G1 to Gm arranged extending in the row direction from the scanning line driving circuit 1802. Gn and the signal lines S1 to Sm and the scanning lines G1 to Gn. The pixel 1803 has a plurality of pixels 1803. Each pixel 1803 is connected to a signal line Sj (signal lines S1 to S m), and the scanning line Gi (one of the scanning lines G1 to Gn) Furthermore, the scanning line driver circuit 1802 may also be called a driver circuit.

[0162] The shift register of this embodiment mode can be applied to the scanning line driver circuit 1802. Of course, the shift register of this embodiment mode can also be used in the signal line driver circuit 1801. Good too.

[0163] The scanning lines G1 to Gn are shown in FIGS. 10, 12, 13, 14, 15 and 17. The eighth wirings 1808_1 to 1808_n are also connected to the eighth wirings 1808_1 to 1808_n.

[0164] The signal lines and the scanning lines may be simply called wirings. and the scan line driver circuit 1802 may each be called a driver circuit.

[0165] The pixel 1803 includes at least one switching element, one capacitor element, and a pixel electrode. However, the pixel 1803 has a plurality of switching elements or a plurality of capacitance elements. Furthermore, the capacitance element is not necessarily required. The pixel 1803 may further include a transistor that operates in the saturation region. The display element may have a display element such as a liquid crystal element or an EL element. A transistor and a PN junction diode can be used as the element. When using a transistor as a switching element, the transistor must operate in the linear region. Furthermore, it is desirable that the scanning line driver circuit 1802 is composed of only N-channel transistors. In this case, it is desirable to use an N-channel transistor as the switching element. Furthermore, when the scanning line driver circuit 1802 is composed of only P-channel transistors, In this case, it is desirable to use a P-channel transistor as the switching element.

[0166] The scanning line driver circuit 1802 and the pixel portion 1804 are formed on an insulating substrate 1805. The signal line driver circuit 1801 is not formed on the insulating substrate 1805. , formed on a single crystal substrate, an SOI substrate, or an insulating substrate other than the insulating substrate 1805. The signal line driver circuit 1801 transmits the signal via a printed circuit board such as an FPC. However, the signal line driver circuit 1801 is formed on an insulating substrate 1805. Alternatively, a circuit that constitutes part of the function of the signal line driver circuit 1801 may be formed on an insulating substrate. 1805.

[0167] Wiring, electrodes, conductive layers, conductive films, terminals, etc. are made of aluminum (Al), tantalum (T a), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd) , Chromium (Cr), Nickel (Ni), Platinum (Pt), Gold (Au), Silver (Ag), Copper (C u), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn) , niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium selected from the group consisting of gallium (Ga), indium (In), tin (Sn), and oxygen (O). or one or more elements selected from the above group Compounds and alloy materials (e.g., indium tin oxide (ITO), indium zinc oxide) (IZO), indium tin oxide with silicon oxide (ITSO), zinc oxide (ZnO), Aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), molybdenum niobium ( It is desirable that it is made of Mo-Nb, etc. Alternatively, it is used for wiring, electrodes, conductive layers, conductive films It is desirable that terminals and the like are formed using a material that combines these compounds. Alternatively, a compound of one or more elements selected from the above group with silicon (silica) silicide) (e.g., aluminum silicon, molybdenum silicon, nickel silicide, etc.), Compounds of nitrogen with one or more elements selected from the group (e.g., titanium nitride, titanium nitride) It is preferable that the insulating layer is formed of a material such as tantalum, molybdenum nitride, or the like.

[0168] Silicon (Si) can contain n-type impurities (such as phosphorus) or p-type impurities (such as boron). The silicon may contain impurities, which can improve the electrical conductivity. Therefore, it can behave like a normal conductor. This makes it easier to use.

[0169] Silicon can be classified into single crystal, polycrystalline (polysilicon), and microcrystalline (microcrystalline silicon). Silicon with various crystallinity can be used, such as amorphous silicon ( Amorphous silicon) can also be used. Single crystal silicon or polycrystalline silicon By using a conductive film, the resistance of wiring, electrodes, conductive layers, conductive films, terminals, etc. can be reduced. By using amorphous silicon or microcrystalline silicon, wiring can be achieved through simple processes. etc. can be formed.

[0170] Aluminum or silver has high conductivity, and therefore can reduce signal delay. Furthermore, it is easy to etch, making it easy to pattern and enabling fine processing. .

[0171] Copper has high conductivity, so it can reduce signal delay. When using copper, To improve adhesion, it is desirable to use a laminated structure.

[0172] Molybdenum or titanium can be used in oxide semiconductors (ITO, IZO, etc.) or silicon It has the advantages of not causing defects even when in contact with metals, being easy to etch, and having high heat resistance. Therefore, it is desirable.

[0173] Tungsten is desirable because it has advantages such as high heat resistance.

[0174] Neodymium is desirable because it has the advantage of being highly heat resistant. When alloyed with aluminum, the heat resistance improves and the aluminum does not form hillocks. It becomes difficult.

[0175] Silicon has high heat resistance and can be formed simultaneously with the semiconductor layer of the transistor. This is desirable because of the advantages it offers.

[0176] In addition, ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S nO) has translucency, so it can be used in areas where light is transmitted. For example, it can be used as a pixel electrode or a common electrode.

[0177] The wiring, electrodes, conductive layers, conductive films, terminals, etc. may have a single-layer structure or a multi-layer structure. By forming it into a single layer structure, it is possible to easily manufacture wiring, electrodes, conductive layers, conductive films, terminals, etc. The manufacturing process can be simplified, the number of days required for the process can be reduced, and costs can be reduced. Alternatively, by using a multi-layer structure, it is possible to take advantage of the advantages of each material while minimizing their disadvantages. This reduces the number of pits and allows for the formation of high-performance wiring and electrodes. By including a resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. In addition, by using a laminated structure in which a low heat-resistant material is sandwiched between high heat-resistant materials, While taking advantage of the advantages of low heat resistance materials, we aim to increase the heat resistance of wiring, electrodes, etc. For example, a layer containing aluminum can be formed by a layer containing molybdenum, titanium, neodymium, etc. It is desirable to have a laminated structure in which the material is sandwiched between layers of the same material.

[0178] In addition, when wiring, electrodes, etc. come into direct contact with each other, they may have a negative effect on each other. In this case, one wiring or electrode penetrates into the other wiring or electrode, changing the properties. This can cause the material to fail to perform its intended purpose. Or, problems may occur during manufacturing, making it impossible to manufacture normally. In such cases, a laminated structure is used in which a reactive material is sandwiched between less reactive materials. For example, when connecting ITO to aluminum, It is desirable to sandwich a titanium, molybdenum, or neodymium alloy between the aluminum and the aluminum. Also, when connecting silicon and aluminum, between ITO and aluminum, It is preferable to use titanium, molybdenum, or neodymium alloys.

[0179] The wiring refers to an arrangement of conductors. It may be linear or may be elongated. Therefore, the electrodes may be included in the wiring.

[0180] The above-described wiring and electrodes are also applicable to other display devices, shift registers, and pixels. It is possible.

[0181] The signal line driver circuit 1801 supplies a voltage or a current as a video signal to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. In addition, the video signal may be inverted between positive and negative polarities every frame (frame inversion drive). ), the positive and negative polarities may be inverted for each row (gate line inversion drive), or the positive and negative polarities may be inverted for each column (gate line inversion drive). The negative polarity may be inverted (source line inversion drive), or the positive and negative polarities may be inverted for each row and column. Furthermore, the video signal may be transmitted to the signal lines S1 to Sm in dot order (dot line inversion drive). The signals may be inputted by line sequential driving or line sequential driving. 1801 transmits not only video signals but also constant voltages such as precharge voltages to signal lines S1 to Sm. A constant voltage such as a precharge voltage may be input for each gate selection period and for each frame. It is recommended to enter the information for each program.

[0182] The scanning line driver circuit 1802 inputs signals to the scanning lines G1 to Gn. The scanning line driving circuit 180 selects (hereinafter also referred to as scanning) the pixels in order from the first row. 2 selects a plurality of pixels 1803 connected to the selected scan line. The period during which a scan line is selected is called one gate selection period, and the period during which the scan line is not selected is called one gate selection period. Furthermore, the scanning line driver circuit 1802 scans the signals output to the scanning lines. Furthermore, the maximum value of the scanning signal is greater than the maximum value of the video signal or the maximum voltage of the signal line. The minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line. It is characterized by the following.

[0183] When the pixel 1803 is selected, the signal line driver circuit 1801 supplies a signal to the pixel 1803 via a signal line. A video signal is input to the pixel 1803 through the selected pixel. In this case, the pixel 1803 receives the video signal (potential corresponding to the video signal) input during the selection period. holds.

[0184] Although not shown, the signal line driver circuit 1801 and the scanning line driver circuit 1802 have a plurality of potential and a number of signals are supplied to the circuit.

[0185] Next, the operation of the display device shown in FIG. 18 will be described with reference to the timing chart of FIG. Furthermore, in FIG. 19, one frame corresponds to a period for displaying one screenful of image. However, there is no particular limit to the length of one frame period, but if the person viewing the image feels flickering, It is preferable to set the exposure time to at least 1 / 60 seconds or less so that flicker is not noticeable.

[0186] In the timing chart of FIG. 19, the first scanning line G1, the i-th scanning line Gi, The timings at which the +1st row scanning line Gi+1 and the nth row scanning line Gn are selected are shown. is doing.

[0187] In FIG. 19, for example, the i-th row of the scanning line Gi is selected, and a plurality of The pixel 1803 is selected. Then, the pixels 1803 connected to the scanning line Gi are A video signal is input to each pixel, and the potential corresponding to the video signal is maintained. The line Gi is deselected, the scanning line Gi+1 in the i+1th row is selected, and the line Gi+1 is connected to the scanning line Gi+1. Then, a plurality of pixels 1803 connected to the scanning line Gi+1 are selected. The pixels 1803 each receive a video signal and hold a potential corresponding to the video signal. As shown above, in one frame period, scanning lines G1 to Gn are selected in order, and each The pixels 1803 connected to the scan lines are also selected in turn. A plurality of pixels 1803 input a video signal and hold a potential corresponding to the video signal. do.

[0188] From the above, the display device of FIG. 18 can input video signals to all pixels independently. Therefore, the function as an active matrix display device can be fully obtained.

[0189] Furthermore, the display device of FIG. 18 uses the shift register of this embodiment as the scanning line driver circuit 1802. The use of a transistor can suppress the threshold shift of the transistor. The display device shown in FIG. 18 has improved driving capability. The display device of FIG. 18 can suppress malfunctions. It is possible to simplify the process.

[0190] Furthermore, the display device of FIG. 18 includes a signal line driver circuit 1801 that requires high-speed operation and a scanning line driver circuit 1802 that requires high-speed operation. Since the circuit 1802 and the pixel 1803 are formed on different substrates, the scanning line driver circuit 180 2 and the semiconductor layer of the transistor included in the pixel 1803. Therefore, amorphous silicon can be used to simplify the manufacturing process. This allows for a reduction in manufacturing costs. Furthermore, the display device of this embodiment can be made larger. Alternatively, polysilicon or polycrystalline silicon can be used as the semiconductor layer of the transistor. The manufacturing process can be simplified even if the above method is used.

[0191] It is to be noted that the signal line driver circuit 1801, the scanning line driver circuit 1802, and the pixel 1803 are formed on the same substrate. In the case of forming the scanning line driver circuit 1802 on a substrate, the semiconductor layer of the transistor and the pixel The semiconductor layer of the transistor in element 1803 is made of polysilicon or polycrystalline silicon. It would be good to do so.

[0192] As shown in Figure 18, it is possible to select pixels and write video signals to the pixels independently. In this case, the number and arrangement of the driving circuits are not limited to those shown in FIG.

[0193] For example, as shown in FIG. 20, the scanning lines G1 to Gn are connected to the first scanning line driving circuit 2002. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b may be used for scanning. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b are the same as the first scanning line driving circuit 1 shown in FIG. It has the same configuration as 802, and scans the scanning lines G1 to Gn at the same timing. , a first scanning line driving circuit 2002a and a second scanning line driving circuit 2002b, They may also be called a first drive circuit and a second drive circuit.

[0194] The display device of FIG. 20 includes a first scanning line driving circuit 2002a and a second scanning line driving circuit 200 Even if a defect occurs in one of the scanning line driving circuits 2002a and 2b, the scanning line driving circuit 2002a and the second scanning line driving circuit 2002b can be Since the other of 2002b can scan the scanning lines G1 to Gn, it has redundancy. Furthermore, the display device of FIG. 20 has a load (scanning line The wiring resistance and the parasitic capacitance of the scanning line) and the load of the second scanning line driving circuit 2002b are shown in FIG. Since the signal input to the scanning lines G1 to Gn (first scanning line Delay and distortion of the output signals of the driving circuit 2002a and the second scanning line driving circuit 2002b Furthermore, the display device of FIG. 20 can reduce the load and Since the load on the first scanning line driving circuit 2002b and the second scanning line driving circuit 2002b is reduced, the scanning lines G1 to Gn are Furthermore, the scanning lines G1 to Gn can be scanned at high speed. Therefore, it is possible to increase the size of the panel or the resolution of the panel. The advantage of the display device is that the first scanning line driver circuit 2002a and the second scanning line driver circuit When amorphous silicon is used for the semiconductor layer of the transistor of 2002b, It is to be noted that the same reference numerals are used to describe the components common to the configuration of FIG. is omitted.

[0195] As another example, FIG. 8 shows a display device that can write video signals to pixels at high speed. In the display device of FIG. 8, video signals are input to the pixels 1803 in odd-numbered rows from signal lines in odd-numbered columns. The video signal is input to the pixels 1803 on the even-numbered rows from the signal lines on the even-numbered columns. In the display device of FIG. 8, the odd-numbered scanning lines among the scanning lines G1 to Gn are the first scanning line drivers. The scanning lines G1 to Gn are scanned by the driving circuit 802a, and the even-numbered scanning lines are scanned as the first scanning lines. The first scanning line driver circuit 802b scans the first scanning line. The start signal input to the first scanning line driving circuit 802a is the same as the start signal input to the first scanning line driving circuit 802b. The input is delayed by 1 / 4 of the clock signal period.

[0196] In the display device of FIG. 8, a positive video signal is supplied to each signal line for each column during one frame period. By simply inputting a negative polarity video signal, dot inversion driving can be performed. The display device of FIG. 8 inverts the polarity of the video signal input to each signal line every frame period. This allows frame inversion driving.

[0197] The operation of the display device of FIG. 8 will be described with reference to the timing chart of FIG. In the timing chart, the first scanning line G1, the i-1th scanning line Gi-1, the i-th scanning line The scanning line Gi, the (i+1)th scanning line Gi+1, and the nth scanning line Gn are selected, respectively. Furthermore, in the timing chart of FIG. 9, one selection period is selected. The selection period is divided into selection period a and selection period b. The case where the display device performs dot inversion driving and frame inversion driving will be described.

[0198] In FIG. 9, for example, the selection period a of the i-th row scanning line Gi is The selection period Tb of the i-th scanning line Gi overlaps with the selection period b of the i+1-th scanning line Gi. The selection period a of line Gi+1 overlaps with the selection period a of line Gi+1. Therefore, in selection period a, the i-1th row · The same video signal as that input to pixel 1803 in the j+1th column is input to pixel 1804 in the i-th row and j-th column. Furthermore, during the selection period b, the pixel 1803 in the i-th row and j-th column receives A video signal similar to the one input to the pixel 1803 in the (i+1)th row and the (j+1)th column is input. In the selection period b, the video signal input to the pixel 1803 is the original video signal. In the selection period a, the video signal input to the pixel 1803 is Therefore, each pixel 1803 receives i The pixel 1803 in the -1th row and the j+1th column is precharged by the video signal input thereto. In addition, the original video signal (row i, column j) is input during selection period b.

[0199] From the above, the display device of FIG. 8 can write video signals to the pixels 1803 at high speed. Therefore, it is possible to easily realize a larger size or a higher resolution. In the device, video signals of the same polarity are input to each signal line during one frame period. The charge and discharge of each signal line is small, and low power consumption can be achieved. The load on the IC for supplying the video signal is significantly reduced, so the heat generated by the IC and the power consumption of the IC are reduced. Furthermore, the display device of FIG. 8 has a first scanning line driving circuit. The driving frequencies of the second scanning line driving circuit 802a and the second scanning line driving circuit 802b can be reduced to about half.

[0200] Note that the display device of this embodiment mode can be driven in various ways depending on the structure and driving method of the pixel 1803. For example, in one frame period, the scanning line driving circuit The line may be scanned multiple times.

[0201] 8, 18, and 20 may be implemented using different wirings depending on the configuration of the pixel 1803. For example, a power supply line, a capacitance line, and a new scanning line that are kept at a constant potential may be added. However, when a new scanning line is added, the shift register of this embodiment is Alternatively, a scanning line driver circuit using a dummy resistor may be newly added. A scanning line, a signal line, a power supply line, or a capacitance line may be arranged in the pixel portion.

[0202] In this embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to the content or part of the content described in another figure. Furthermore, in the diagrams mentioned above, for each part, By combining different parts, more figures can be constructed.

[0203] Similarly, the contents or part of the contents described in each drawing of this embodiment may be applied to the drawings of another embodiment. The present invention can also be applied to the contents or parts of the contents described in the above, or can be combined. Furthermore, in the drawings of this embodiment, each part may be combined with a part of another embodiment. By combining them, even more figures can be constructed.

[0204] It should be noted that this embodiment is an example of a case where the contents described in the other embodiments are embodied, and is slightly modified. Examples of cases where the product has been shaped, examples of cases where a part has been changed, examples of cases where the product has been improved, and examples of cases where the product has been described in detail It shows examples of the concept, examples of its application, and examples of related parts. Therefore, the contents described in the other embodiments can also be applied to this embodiment. It can be combined.

[0205] (Embodiment 2) In this embodiment, a flip-flop different from that in the first embodiment is used. The present invention will now be described with reference to the accompanying drawings, in which: a driving circuit for a display device having the driving circuit; a configuration of the display device having the driving circuit; and a driving method thereof. In addition, the same parts as those in the first embodiment are designated by the same reference numerals, and the same parts or A detailed description of parts having similar functions will be omitted.

[0206] The flip-flop of this embodiment has the same structure as that of the first embodiment. However, the timing of driving the flip-flop may differ from that of the first embodiment. Therefore, in this embodiment, the description of the configuration of the flip-flop will be omitted.

[0207] In addition, when the driving timing of this embodiment is applied to the flip-flop of FIG. The driving timing of this embodiment will be explained with reference to FIGS. 4(A), 4(B), 4(C), and 4(D). 4(D), Fig. 5(A), Fig. 5(B), Fig. 5(C), Fig. 5(D), Fig. 7(A), Fig. 7(B) The flip-flops of Fig. 7(C), Fig. 21(A), Fig. 21(B), or Fig. 21(C) and free Furthermore, the driving timing of this embodiment can be implemented in combination with It is also possible to freely combine this with the drive timing described in the first embodiment.

[0208] Next, the operation of the flip-flop of this embodiment will be explained with reference to the flip-flop of FIG. The following description will be given with reference to the timing chart of FIG. The non-selection period will be divided into a first non-selection period and a second non-selection period. The second non-selection period, the set period a, the set period b, and the reset period will be explained separately. Furthermore, the selection period will be explained by dividing it into selection period a and selection period b. During this time, set period a, set period b, selection period a, selection period b, and reset period are The excluding operation period alternates between a first non-selection period and a second non-selection period.

[0209] In FIG. 31, the signal 3121, the signal 3125, the signal 3126, the potential 3141, the potential The output 3142, the signal 3122, and the signal 3123 are input to the first wiring 121. A signal, a signal input to the fifth wiring 125, a signal input to the sixth wiring 126, a node The potential of the node 141, the potential of the node 142, the signal input to the second wiring 122, the potential of the third wiring 1 23.

[0210] In addition, the signal 3121, the signal 3125, the signal 3126, the potential 3141, the potential 3142, the signal 2. The signals 221, 225, and 226, and the potential 241, potential 242, signal 222 and signal 223, and have similar characteristics. do.

[0211] The flip-flop of this embodiment is basically the same as that described in the first embodiment. However, the flip-flop of this embodiment operates in the same manner as the first wiring. The timing when the H signal is input to 121 is delayed by 1 / 4 cycle of the clock signal. However, it differs from the flip-flop of the first embodiment.

[0212] Note that the flip-flop of this embodiment mode operates in the first non-selection period and the second non-selection period. In this regard, the first non-selection period and the second non-selection period of the flip-flop described in the first embodiment Furthermore, the flip-flop of this embodiment operates in the same manner as during the set period a. In this embodiment, the flip-flop operates in the same manner as in the second non-selection period. In the reset period, the reset period of the flip-flop explained in the first embodiment is Furthermore, the flip-flop of this embodiment performs the same operation as the selection period a and the selection period During the period b, the same operation as during the selection period of the flip-flop explained in the first embodiment is performed. However, in the flip-flop of this embodiment, the first wiring 121 is connected to the first wiring 121 during the selection period a. The flip-flop differs from the flip-flop of the first embodiment in that a high signal is input. Even if an H signal is input to the first wiring 121 during the period a, the fifth transistor 105 is turned on. Therefore, the operation of this embodiment is hardly affected. a, a set period b, a selection period a, a selection period b, a reset period, a first non-selection period, and a second A detailed description of the flip-flop of this embodiment during the non-selection period will be omitted.

[0213] Note that the flip-flop of this embodiment is the same as the flip-flop shown in Embodiment 1. In the same way, the layout area can be reduced. This can suppress the threshold shift of the transistor. The flip-flop can simplify the manufacturing process.

[0214] The timing chart shown in FIG. 32 is applied to the flip-flop of this embodiment. As a result, the flip-flop of this embodiment significantly shortens the fall time of the output signal. This is because the timing at which the signal 3122 (reset signal) becomes H level can be By shifting the first and second wirings, an L signal can be input to the third wiring 123 via the first transistor 101. Because.

[0215] Next, the configuration and driving of the shift register having the flip-flop of the present embodiment will be described. This section explains how it works.

[0216] The configuration of the shift register of this embodiment will be described with reference to FIG. The flip-flop register consists of n flip-flops (flip-flop 3301_1 to flip-flop 3302_2). It has a 3301_n).

[0217] The connection relationship of the shift register in Fig. 33 will be explained. The shift register in Fig. 33 has i-stage Flip-flop 3301_i (Flip-flop 3301_1~3301_n) Among them, the flip-flop 330 in the 4N-3th stage (N is a natural number of 1 or more) 1_4N-3 and the 4N-1-th flip-flop 3301_4N-1 are connected to the second wiring 3312, the fourth wiring 3314, the sixth wiring 3316, the seventh wiring 3317, and the eighth wiring 3318, 11th wiring 3321_i-1, 11th wiring 3321_i, 11th wiring 3 321_i+2. Furthermore, the flip-flop 3301_4N in the 4N-2 stage is connected to The flip-flops 3301_4N at the -2 and 4N stages are connected to the third wiring 3313, the fifth wiring 3314, Wiring 3315, sixth wiring 3316, seventh wiring 3317, eighth wiring 3318, eleventh wiring the first wiring 3321_i-1, the eleventh wiring 3321_i, and the eleventh wiring 3321_i+2. However, the first stage flip-flop 3301_1 is connected to the first wiring 3111, A second wiring 3312, a fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317, The eighth wiring 3318, the eleventh wiring 3321_1, and the eleventh wiring 3321_3 are connected to Furthermore, the flip-flop 3101_n-1 in the (n-1)th stage is connected to the second wiring 3312, A fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317, an eighth wiring 3318, Tenth wiring 3320, eleventh wiring 3321_n-2, eleventh wiring 3321_n-1 Furthermore, the n-th flip-flop 3301_n is connected to the third wiring 3313 , fifth wiring 3315, sixth wiring 3316, seventh wiring 3317, eighth wiring 3318 , the ninth wiring 3319, the eleventh wiring 3321_n-1, and the eleventh wiring 3321_n. To be continued.

[0218] The first wiring 3311 is connected to the first wiring 121 of the flip-flop 3301_1 shown in FIG. The second wiring 3312 is connected to the flip-flop 3301_4N-3 shown in FIG. 1. In the flip-flop 3301_4N-1, the third wiring 125 shown in FIG. The third wiring 3313 is connected to the wiring 126 of the flip-flop 3301_4N In the flip-flop 3301_4N, it is connected to the fifth wiring 125 shown in FIG. The fourth wiring 3314 is connected to the sixth wiring 126 shown in FIG. 301_4N-3 is connected to the sixth wiring 126 shown in FIG. 1, and the flip-flop 330 1_4N-1 is connected to the fifth wiring 125 shown in FIG. The flip-flop 3301_4N-2 is connected to the sixth wiring 126 shown in FIG. In the flip-flop 3301_4N, it is connected to the fifth wiring 125 shown in FIG. 306 is connected to the seventh wiring 127 shown in FIG. 1 at all stages of the flip-flops. The wiring 3317 is connected to the eighth wiring 128 shown in FIG. 1 in all the flip-flops. The eighth wiring 3318, the fourth wiring 124 shown in FIG. 1 in all stages of flip-flops, the ninth wiring The ninth wiring 331 is connected to the line 129, the tenth wiring 130, and the eleventh wiring 131. 9 is connected to the second wiring 122 of the flip-flop 3301_n shown in FIG. The wiring 3120 of the flip-flop 3301_n-1 is connected to the second wiring 122 shown in FIG. The eleventh wiring 3321_i is connected to the flip-flop 3301_i-2 shown in FIG. 1 of the flip-flop 3301_i. , and the first wiring 121 of the flip-flop 3301_i+1 shown in FIG. However, the eleventh wiring 3321_1 is the third wiring of the flip-flop 3301_1 shown in FIG. 1 of the flip-flop 3301_2. Furthermore, the eleventh wiring 3321_2 is connected to the flip-flop 3301_2 in FIG. 1 of the flip-flop 3301_3. 1. Furthermore, the eleventh wiring 3321_n is connected to the flip-flop 3301_n 1. The third wiring 123 shown in FIG.

[0219] The sixth wiring 3316 and the seventh wiring 3317 are supplied with a potential of V1. The eighth wiring 3318 is supplied with a potential of V2.

[0220] The first wiring 3311, the second wiring 3312, the third wiring 3314, and the fifth wiring 33 Signals are input to the 15th, 9th and 10th wirings 3319 and 3320. The signal input to the first wiring 3311 is a start signal, and the signal input to the second wiring 3312 is a The signal input to the third wiring 3313 is the first clock signal, and the signal input to the third wiring 3314 is the second clock signal. The signal input to the fourth wiring 3314 is the third clock signal, The signal input to the fifth wiring 3315 is the fourth clock signal, and the signal input to the ninth wiring 3319 is the fourth clock signal. The signal input to the 10th wiring 3320 is the first reset signal. is a second reset signal. Furthermore, the first wiring 3311, the second wiring 3312, and the third wiring 3313 are connected to each other. the first wiring 3314, the fifth wiring 3315, the ninth wiring 3319 and the tenth wiring 3320 The input signals are digital signals with the H signal potential at V1 and the L signal potential at V2. be.

[0221] The first wiring 3311 to the tenth wiring 3320 are connected to various signals, currents, or A voltage may be input.

[0222] Signals are output from the eleventh wirings 3321_1 to 3321_n. For example, the signal output from the eleventh wiring 3321_i is Furthermore, the signal output from the eleventh wiring 3321_i is flip-flop. The input signal of the flip-flop 3301_i+1 and the reset of the flip-flop 3301_i-2 are It is also a signal.

[0223] Next, the operation of the shift register shown in FIG. 33 will be explained with reference to the timing chart and The following description will be made with reference to the timing chart of Fig. 36. Here, the timing chart of Fig. 35 The scanning period is divided into a scanning period and a blanking period. When the output of the selection signal from the eleventh wiring 3311_n is completed, The blanking period is the period from when the output of the selection signal from the eleventh wiring 3311_n ends to when the output of the selection signal from the eleventh wiring 3311_n ends. This is the period from the completion of the selection signal output to the start of output of the selection signal from the eleventh wiring 3311_1.

[0224] In FIG. 35, a signal 3511 is input to the first wiring 3311, and a signal 3512 is input to the second wiring 33 12, a signal 3513 input to the third wiring 3313, a signal 3514 input to the fourth wiring 3314, A signal 3514 input to the wiring 3314, a signal 3515 input to the fifth wiring 3315 , a signal 3519 input to the ninth wiring 3319, a signal 3520 input to the tenth wiring 3320, 3520, a signal 3521_1 output to the eleventh wiring 3321_1 and the eleventh wiring 36 shows the signal 3521_n output to the first input 3321_n. A signal 3611 input to the first wiring 3311, a signal 3612 output to the eleventh wiring 3321_1, signal 3621_i-1 output to the eleventh wiring 3321_i-1, The signal 3621_i output to the 11th wiring 3321_i+1 signal 3621_i+1 output to the 11th wiring 3321_n and signal 36 It shows 21_n.

[0225] As shown in FIG. 36, for example, when the flip-flop 3301_i-1 is in the selection period a, An H signal is output from the eleventh wiring 3321_i-1. 301_i is in the set period a. After that, the flip-flop 3301_i-1 is in the select period At the interval b, the H signal continues to be output from the eleventh wiring 3321_i-1. Then, the flip-flop 3301_i is in the selection period a. 01_i-1 is in the reset period and an H signal is output from the eleventh wiring 3321_i-1. At this time, the flip-flop 3301_i is in the selection period b. The shift register of this type outputs an H signal in order from the flip-flop 3301_i-1. However, the selection period b of the flip-flop 3301_i-1 and the selection period i has a period that overlaps with the selection period a.

[0226] When the timing chart of FIG. 32 is applied to the flip-flop of this specification, The shift register may be configured as shown in Figure 34. For example, the wiring 122 shown in FIG. 1 of the flip-flop 3301_i in the i-th stage is connected to the eleventh wiring 33 21_i+3. Furthermore, the flip-flop 3301_n-2 is connected to the first The second wiring 122 is connected to a twelfth wiring 3322 to which a third reset signal is input. Note that the same reference numerals are used for the parts common to FIG. 33, and the description thereof will be omitted.

[0227] The shift register of this embodiment is a flip-flop of this embodiment. Therefore, it is possible to suppress the threshold shift of transistors, extend their lifespan, improve their driving capability, and suppress malfunctions. This allows for the simplification of processes and controls.

[0228] The shift register of this embodiment may be freely changed to the shift register of the first embodiment. For example, the shift register of this embodiment can be implemented in combination with the shift registers shown in FIGS. This can be implemented by freely combining with the shift registers of FIGS. 15 and 17. The shift register of this type is connected to the eleventh wiring 3321_1 to the eleventh wiring 3321_n. You can connect a buffer, generate the reset signal internally, or use a dummy flip-flop. As already mentioned, the same as in the first embodiment Common reference numerals are used and their explanations are omitted.

[0229] Next, the configuration and driving method of a display device having the shift register of the present embodiment will be described. However, the display device of this embodiment is at least All you need is a p-flop.

[0230] The structure of the display device of this embodiment will be described with reference to FIG. 16. The scanning lines G1 to Gn are scanned by a scanning line driving circuit 1602. In the display device of No. 6, video signals are input to the pixels 1803 on odd-numbered rows from the signal lines on odd-numbered rows. The video signal is input to the pixel 1803 on the even-numbered row from the signal line on the even-numbered row. The same reference numerals are used for the components common to those in the configuration of 8, and the description thereof will be omitted.

[0231] 16, the shift register of this embodiment mode is provided in the scanning line driver circuit 1602. By applying this, the same operation as that of the display device in FIG. 8 can be performed by one scanning line driving circuit. Therefore, the display device of FIG. 16 can write video signals to the pixels at high speed. Furthermore, the display device of FIG. 16 can be made larger or have higher definition. Furthermore, the display device of FIG. 16 is designed to reduce power consumption. Furthermore, the display device of FIG. 16 can suppress heat generation in the IC. The display device can reduce the power consumption of the IC.

[0232] As shown in FIG. 22, the scanning lines G1 to Gn are connected to the first scanning line driving circuit 2202a. The first scanning line driver circuit 2202b may be used to scan the first and second scanning line drivers 2202a and 2202b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b are the same as the scanning line driving circuit 16 shown in FIG. It has the same configuration as No. 02, and scans the scanning lines G1 to Gn at the same timing. , the first scanning line driver circuit 2202a and the second scanning line driver circuit 2202b are respectively They may also be called the first drive circuit and the second drive circuit.

[0233] The display device of FIG. 22 includes a first scanning line driving circuit 2202a and a second scanning line driving circuit 220 Even if a defect occurs in one of the scanning line driving circuits 2202a and 2b, the scanning line driving circuit 2202a and the second scanning line driving circuit 2202b can be Since the other of 2202b can scan the scanning lines G1 to Gn, redundancy is provided. Furthermore, the display device of FIG. 22 includes a first scanning line driving circuit 2202a and a second scanning line driving circuit 2202b. Since the scanning line driving circuit 2202b scans the scanning lines G1 to Gn, the first scanning line driving circuit The load 2202a (the wiring resistance of the scanning line and the parasitic capacitance of the scanning line) and the second scanning line driving circuit The load on the display 2202b can be reduced to half compared to that in FIG. The device is a load of the first scanning line driving circuit 2202a and a load of the second scanning line driving circuit 2202b. Since the load is reduced, the signals input to the scanning lines G1 to Gn (the first scanning line driving circuit 2202a and the output signal of the second scanning line driving circuit 2202b) Furthermore, in the display device of FIG. 22, the load of the first scanning line driving circuit 2202a Since the load on the second scanning line driving circuit 2202b is reduced, the scanning lines G1 to Gn Furthermore, by scanning the scanning lines G1 to Gn at high speed, This allows for larger panels or higher resolution panels. The advantage of the display device is that the first scanning line driver circuit 2202a and the second scanning line driver circuit When amorphous silicon is used for the semiconductor layer of the transistor included in the circuit 2202b, It is more effective. The same symbols are used for the parts common to the configuration in FIG. 16, and the explanations are as follows. The details are omitted.

[0234] In this embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to the content or part of the content described in another figure. Furthermore, in the diagrams mentioned above, for each part, By combining different parts, more figures can be constructed.

[0235] Similarly, the contents or part of the contents described in each drawing of this embodiment may be applied to the drawings of another embodiment. The present invention can also be applied to the contents or parts of the contents described in the above, or can be combined. Furthermore, in the drawings of this embodiment, each part may be combined with a part of another embodiment. By combining them, even more figures can be constructed.

[0236] It should be noted that this embodiment is an example of a case where the contents described in the other embodiments are embodied, and is slightly modified. Examples of cases where the product has been shaped, examples of cases where a part has been changed, examples of cases where the product has been improved, and examples of cases where the product has been described in detail It shows examples of the concept, examples of its application, and examples of related parts. Therefore, the contents described in the other embodiments can also be applied to this embodiment. It can be combined.

[0237] (Embodiment 3) In this embodiment, a flip-flop different from those in Embodiments 1 and 2, Driving circuit having a flip-flop, and configuration and driving method of a display device having the driving circuit - Patents.com The flip-flop of this embodiment has an output signal and the transfer signal of the flip-flop are output from separate wirings by separate transistors. The features of the present invention are as follows. Note that the same features as those of the first and second embodiments are common to both. The same reference numerals are used to denote the same parts or parts having similar functions, and detailed descriptions thereof will be omitted.

[0238] The basic structure of the flip-flop of this embodiment will be described with reference to FIG. The flip-flop shown in FIG. 7 includes a first transistor 101, a second transistor 102, The third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, the seventh transistor 107, the eighth transistor 108, and In this embodiment, the eighth transistor 108 and The ninth transistor 109 is an N-channel transistor, and the gate and source voltage When the voltage (Vgs) exceeds the threshold voltage (Vth), the transistor becomes conductive.

[0239] The flip-flop of FIG. 27 is the flip-flop of FIG. 1 with an eighth transistor 10 The eighth and ninth transistors 109 are added. a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor a fifth transistor 104, a fifth transistor 105, a sixth transistor 106 and a seventh transistor The register 107 can be the same as that shown in FIG.

[0240] The connection relationship of the flip-flop in FIG. 27 will be described. The first electrode (either the source electrode or the drain electrode) is connected to the fifth wiring 125, and the first The second electrode (the other of the source electrode and the drain electrode) of the transistor 101 is connected to the third wiring 1. The first electrode of the second transistor 102 is connected to the fourth wiring 124. The second electrode of the second transistor 102 is connected to a third wiring 123. The first electrode of the third transistor 103 is connected to the sixth wiring 126. The second electrode of the third transistor is connected to the gate electrode of the second transistor 102. The gate electrode of the fourth transistor 103 is connected to the seventh wiring 127. The first electrode of the fourth transistor 104 is connected to the ninth wiring 129, and the second electrode of the fourth transistor 104 is connected to the second wiring 129. The gate electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102. The first transistor 105 is connected to the gate electrode of the first transistor 101. The first electrode of the fifth transistor 105 is connected to the eighth wiring 128, and the second electrode of the fifth transistor 105 is connected to the first wiring 128. The gate electrode of the fifth transistor 105 is connected to the gate electrode of the fifth transistor 101. The first electrode of the sixth transistor 106 is connected to the first wiring 121. 130, and the second electrode of the sixth transistor 106 is connected to the first transistor 101 The gate electrode of the sixth transistor 106 is connected to the gate electrode of the second transistor The first electrode of the seventh transistor 107 is connected to the gate electrode of the eleventh transistor 102. The second electrode of the seventh transistor 107 is connected to the line 131, and the second electrode of the seventh transistor 107 is connected to the line 132. The gate electrode of the seventh transistor 107 is connected to the second wiring 122. A first electrode of the eighth transistor 108 is connected to the thirteenth wiring 133. The second electrode of the eighth transistor 108 is connected to the twelfth wiring. The gate electrode of the ninth transistor 108 is connected to the gate electrode of the first transistor 101. The first electrode of the transistor 109 is connected to the fourteenth wiring 134, and the second electrode of the transistor 109 is connected to the fourteenth wiring 134. The second electrode of the ninth transistor 109 is connected to the twelfth wiring 132, and the gate of the ninth transistor 109 is connected to the The electrode is connected to the gate electrode of the second transistor 102 .

[0241] The twelfth wiring 132 and the third wiring 133 are respectively referred to as the sixth signal line and the seventh signal line. Furthermore, the fourteenth wiring may be called the seventh power supply wiring.

[0242] The fourteenth wiring 134 is supplied with V2.

[0243] A signal is input to the thirteenth wiring 133. The signal input to the third wiring is The signal input to the wiring 125 can be the same as the signal input to the wiring 125.

[0244] A signal is output from the twelfth wiring 132. Furthermore, as explained in the first embodiment, In this way, a signal is also output from the third wiring 123.

[0245] The first wiring 121, the second wiring 122, the fourth wiring 124, the fifth wiring 125, The sixth wiring 126, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring The signal input or the potential supplied to each of the line 130 and the eleventh wiring 131 is the same as that shown in FIG. is the same as:

[0246] The flip-flop of FIG. 27 is the flip-flop of FIG. 1 with an eighth transistor 10 The case where the eighth and ninth transistors 109 are added is shown, but FIG. B), Fig. 4(C), Fig. 4(D), Fig. 5(A), Fig. 5(B), Fig. 5(C), Fig. 5(D), Fig. 7(A), 7(B), 7(C), 21(A), 21(B) and 21(C). An eighth transistor 108 and a ninth transistor 109 are added to the flip-flop. You may do so.

[0247] Next, regarding the operation of the flip-flop shown in Figure 1, please refer to the timing chart in Figure 28. Furthermore, the same symbols are used for the parts common to the timing chart in FIG. Therefore, the explanation will be omitted.

[0248] The signal 232 indicates a signal output from the twelfth wiring 132. Signal 221, signal 225, signal 226, potential 241, potential 242, signal 222 and signal 22 3 is the same as in FIG. 2 except for the signal 221, the signal 225, the signal 226, the potential 241, The potential 242, the signal 222, and the signal 223 are the same as those shown in FIG. 6, FIG. 31, or FIG. 32. It can also be used.

[0249] In this embodiment, as already described, the output signal of the flip-flop and the The transfer signal of the data transfer buffer is output from separate wiring by separate transistors. That is, the flip-flop of FIG. 27 has a first transistor 101 and a second transistor The signal is output from the third wiring 123 by the eighth transistor 102, and the eighth transistor 108 The ninth and eighth transistors output a signal from the twelfth wiring 132. The transistor 108 and the ninth transistor are the first transistor 101 and the second transistor Since it is connected in the same manner as the transistor 102, the twelfth wiring 132 as shown in FIG. The signal (signal 232) output from the third wiring 123 is the signal (signal 223) output from the third wiring 123. ) is roughly the same waveform as the signal 232. Here, the signal 232 is the output signal of the flip-flop. , the signal 223 is a transfer signal of the flip-flop. The output signal of the flip-flop, signal 232, may be the transfer signal of the flip-flop.

[0250] The eighth transistor 108 and the ninth transistor 109 are the same as the first transistor. The eighth transistor 101 has the same function as the second transistor 102. The ninth transistor 108 and the ninth transistor 109 may be called a buffer unit.

[0251] From the above, in the flip-flop of FIG. 27, a large load is connected to the third wiring 132. Therefore, even if the signal 232 is delayed or distorted, malfunctions can be prevented. Therefore, the flip-flop in Figure 27 has the output signal of the flip-flop and the The output signal is then transferred to a separate transistor via a separate line. This is because signal delays and distortions do not affect the operation of the flip-flop.

[0252] Furthermore, the flip-flop of FIG. 27 is the same as the flip-flop shown in the first and second embodiments. As with flops, the layout area is reduced, the threshold shift of transistors is suppressed, and the process Simplification of the manufacturing process, fabrication of semiconductor devices such as large display devices, and semiconductor devices such as long-life display panels. This can provide benefits such as the creation of

[0253] Note that the operation timing described in Embodiment 2 is applied to the flip-flop of this embodiment mode. You can also do this.

[0254] The configuration and driving method of the shift register having the flip-flop of this embodiment mode described above We will explain about this.

[0255] The configuration of the shift register of this embodiment will be described with reference to FIG. The register consists of n flip-flops (flip-flop 2901_1 to flip-flop 2902_2). It has a function (2901_n).

[0256] The connection relationship of the flip-flop in Figure 29 will be explained. The flip-flop in Figure 29 has the following: The i-th flip-flop 2901_i (flip-flops 2901_1 to 2901_n Any one of the second wiring 2912, the third wiring 2913, and the fourth wiring 2914 , the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_i-1, the eighth wiring 2918_i, an eighth wiring 2918_i+1, and a ninth wiring 2919_i. However, the first stage flip-flop 2901_1 is connected to the first wiring 2911 and the second wiring 2912. 912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2 916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1 Furthermore, the n-th stage flip-flop 2901_n is connected to the second wiring 2912, A third wiring 2913, a fourth wiring 2914, a fifth wiring 2915, a sixth wiring 2916, The seventh wiring 2917, the eighth wiring 2918_n-1, the eighth wiring 2918_n, and the ninth wiring It is connected to the wiring 2919_n.

[0257] The first wiring 2911 is the first wiring 121 shown in FIG. 27 of the flip-flop 2901_1. The second wiring 2912 is connected to the first wiring 2913 shown in FIG. 2. The third wiring 2913 is connected to the sixth wiring 126 shown in FIG. In the flip-flops at even stages, it is connected to the sixth wiring 126 shown in FIG. The fifth wiring 125 shown in FIG. 27 is connected to the third wiring 133. The fourth wiring 2914 is The flip-flops in all stages are connected to the seventh wiring 127 shown in FIG. 27. 15 is connected to the eighth wiring 128 shown in FIG. 27 at all stages of the flip-flops. The wiring 2916 is connected to the fourth wiring 124 and the ninth wiring 125 shown in FIG. 27 in all stages of the flip-flops. 129, the 29th wiring 130, and the 11th wiring 131. _i is the second wiring 122 of the flip-flop 2901_i-1 shown in FIG. 27, The third wiring 123 of the flip-flop 2901_i shown in FIG. 27 and the flip-flop 2901i +1 is connected to the first wiring 121 shown in FIG. 27. However, the eighth wiring 2918_1 is , the third wiring 123 and the flip-flop 2901_1 shown in FIG. 2901_2 is connected to the first wiring 121 shown in FIG. 27. Furthermore, the eighth wiring 291 8_n is the second wiring 122 and the flip-flop 2901_n-1 shown in FIG. The ninth wiring 2 is connected to the third wiring 123 shown in FIG. The 9th wiring 2919_1 to 9th wiring 2919_n are connected to the flip-flops 2901_1 to 2901_n, respectively. The twelfth wiring 132 shown in FIG. 27 of the flip-flop 2901_n is connected to the twelfth wiring 132.

[0258] The flip-flops 2901_1 to 2901_n and the first wiring 29 11, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 29 15, the fifth wiring 2916, and the seventh wiring 2907 are the flip-flops shown in FIG. Flip-flop 1001_1 to flip-flop 1001_n, first wiring 1011, second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, the fifth wiring The wiring 1016 corresponds to the seventh wiring 1007, and a similar signal or potential is supplied to the wiring 1016.

[0259] Next, the operation of the shift register shown in Figure 29 will be explained with reference to the timing chart in Figure 30. This will be explained in light of the above.

[0260] In FIG. 30, a signal 3011 is input to the first wiring 2911, and a signal 3012 is input to the eighth wiring 2918. a signal 3018_1 output to the eighth wiring 2918_i; i, a signal 3018_i+1 output to the eighth wiring 2918_i+1, a signal 3018_n output to the ninth wiring 2919_1; 9_1, a signal 3019_i output to the ninth wiring 2918_i, i+1 and a signal 3019_i+1 output to the ninth wiring 2919_n. It shows 3018_n.

[0261] As shown in FIG. 30, for example, when the flip-flop 2901_i is in the selected period, the eighth An H signal is output from the first wiring 2918_i and the ninth wiring 2919_i. The flip-flop 2901_i+1 is in the set period. 1_i is in the reset period, and the eighth wiring 2918_i and the ninth wiring 2919_i At this time, the flip-flop 2901_i+1 is in the selected period. After that, the flip-flop 2901_i enters the first non-selection period, and the eighth wiring 29 The ninth wiring 2918_i and the ninth wiring 2919_i are in a floating state, and the potential is maintained at the L level. At this time, the flip-flop 2901_i+1 is in the reset period. The drop 2901_i is in the second non-selection period, and the eighth wiring 2918_i and the ninth wiring An L signal is output from the line 2919_i. At this time, the flip-flop 2901_i+1 This is the first non-selection period. Thus, the flip-flop 2901_i is set in the next set period. The first non-selection period and the second non-selection period are repeated until the period

[0262] From the above, the shift register of FIG. 29 sequentially transmits the transfer signal from the eighth wiring 2918_1. 29 can be output to the eighth wiring 2918_n. The selection signal is output from the ninth wiring 2919_1 to the ninth wiring 2919_n in order. That is, the shift register of FIG. 29 can be implemented by the ninth wiring 2919_1 to the ninth wiring 2919_2. 2919_n. Therefore, the shift register of FIG. The function as a register can be fully obtained.

[0263] Furthermore, the shift register of FIG. 29 includes ninth wirings 2919_1 to ninth wirings 2919_n. Even if a large load (resistance, capacitance, etc.) is connected to the Furthermore, the shift register of FIG. 29 has ninth wiring 2919_1 to ninth wiring 2919_2. Even if any of the 19_n is shorted to the power line or signal line, normal operation can continue. Therefore, the shift register of FIG. 29 can improve the driving capability. Then, the shift register in Figure 29 has the transfer signal of each flip-flop and This is because the output signal from the amplifier is divided into two parts.

[0264] Furthermore, the shift register of FIG. 29 applies the flip-flop shown in this embodiment. This reduces the layout area, suppresses the threshold shift of transistors, simplifies the process, Manufacturing of semiconductor devices such as large display devices, manufacturing of semiconductor devices such as long-life display panels, etc. The benefits of this system can be obtained.

[0265] It should be noted that the configuration is not limited to that of FIG. 29 as long as it performs the same operation as that of FIG. 29. For example, By freely combining with the shift registers in Figures 13, 14, 15, and 17, , the same advantages as those shown in FIGS. 13, 14, 15, and 17 can be obtained.

[0266] The structure and driving method of the display device having the shift register of the above-described embodiment will be described. However, the display device of this embodiment mode is at least the flip-flop of this embodiment mode. It is sufficient to have a

[0267] As the display device of this embodiment, the display devices shown in FIGS. 8, 18, 16, 20, and 22 are used. Therefore, the display device of this embodiment can be realized by using the present embodiment as a scanning line driving circuit. By applying the shift register of the embodiment, it is possible to reduce the layout area. Furthermore, in the display device of this embodiment, threshold voltage shift of the transistor can be suppressed. In the display device of this embodiment, the manufacturing process can be simplified. The display device of this embodiment can be made larger or have higher definition. In particular, the display devices shown in Figs. 8, 16 and 22 are provided with a scanning line driver. If the shift register of this embodiment is applied as a driving circuit, it is possible to achieve a larger size or higher definition. Furthermore, the shift register of this embodiment is applied to the circuits shown in FIG. 8, FIG. 16, or FIG. The display device of 22 can achieve power saving. The display devices shown in FIG. 8, FIG. 16, or FIG. 22, which use the capacitor, can suppress heat generation in the IC. 8, 16, or 22 to which the shift register of this embodiment is applied. C can be made more energy efficient.

[0268] In this embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to the content or part of the content described in another figure. Furthermore, in the diagrams mentioned above, each part Regarding the part, by combining different parts, more figures can be constructed. come.

[0269] Similarly, the contents or part of the contents described in each drawing of this embodiment may be applied to the drawings of another embodiment. The present invention can also be applied to the contents or parts of the contents described in the above, or can be combined. Furthermore, in the drawings of this embodiment, each part may be combined with a part of another embodiment. By combining them, even more figures can be constructed.

[0270] It should be noted that this embodiment is an example of a case where the contents described in the other embodiments are embodied, and is slightly modified. Examples of cases where the product has been shaped, examples of cases where a part has been changed, examples of cases where the product has been improved, and examples of cases where the product has been described in detail It shows examples of the concept, examples of its application, and examples of related parts. Therefore, the contents described in the other embodiments can be applied to this embodiment or can be combined. It can be matched.

[0271] (Fourth embodiment) In this embodiment, a P-channel transistor is used as a transistor constituting the flip-flop of this specification. A case where a transistor is applied will be described. The configuration and driving method of a driver circuit and a display device having the driver circuit will be described.

[0272] The flip-flop of this embodiment has the same structure as the flip-flop of FIG. The case where the transistor characteristic is a P-channel type will be explained. (C), Figure 4(D), Figure 5(A), Figure 5(B), Figure 5(C), Figure 5(D), Figure 7(A), 7(B), 7(C), 21(A), 21(B), 21(C) or 27 The polarity of the transistors included in the flip-flops can also be P-channel. Furthermore, the flip-flop of this embodiment mode can be freely configured in the same manner as in Embodiment Modes 1 to 3. It can also be implemented in combination with

[0273] The basic structure of the flip-flop of this embodiment will be described with reference to FIG. The flip-flop shown in FIG. 3 includes a first transistor 2301, a second transistor 2302, and a 2, the third transistor 2303, the fourth transistor 2304, and the fifth transistor 2 305, a sixth transistor 2306, and a seventh transistor 2307. In this embodiment, the first transistor 2301, the second transistor 2302, the third transistor a fourth transistor 2303, a fourth transistor 2304, a fifth transistor 2305, a sixth transistor 2306, a sixth transistor 2307, a sixth transistor 2308, a sixth transistor 2309, a sixth transistor 2310, a sixth transistor 2311, a sixth transistor 2312, a sixth transistor 2313, a sixth transistor 2314, a sixth transistor 2315, a sixth transistor 2316, a The first transistor 2306 and the seventh transistor 2307 are P-channel transistors. The absolute value of the gate-source voltage (|Vgs|) is the absolute value of the threshold voltage (|Vt h|) (when Vgs falls below Vth), the conduction state is assumed.

[0274] The connection relationship of the flip-flop in FIG. 23 will be described. The first electrode (one of the source electrode and the drain electrode) is connected to the fifth wiring 2325. The second electrode (the other of the source electrode and the drain electrode) of the first transistor 2301 is connected to the third The first electrode of the second transistor 2302 is connected to the fourth wiring 2323. 24, and the second electrode of the second transistor 2302 is connected to the third wiring 2323. A first electrode of the third transistor 2303 is connected to a sixth wiring 2326. The second electrode of the third transistor 2303 is connected to the gate electrode of the second transistor 2302. The gate electrode of the third transistor 2303 is connected to a seventh wiring 2327 . A first electrode of the fourth transistor 2304 is connected to a ninth wiring 2329. a second electrode of the second transistor 2304 connected to the gate electrode of the second transistor 2302; The gate electrode of the fourth transistor 2304 is connected to the gate electrode of the first transistor 2301. A first electrode of the fifth transistor 2305 is connected to an eighth wiring 2328. , the second electrode of the fifth transistor 2305 is connected to the gate electrode of the first transistor 2301. The gate electrode of the fifth transistor 2305 is connected to the first wiring 2321. A first electrode of the sixth transistor 2306 is connected to a tenth wiring 2330. The second electrode of the transistor 2306 is connected to the gate electrode of the first transistor 2301. The gate electrode of the sixth transistor 2306 is connected to the gate electrode of the second transistor 2302. A first electrode of the seventh transistor 2307 is connected to an eleventh wiring 2331. The second electrode of the seventh transistor 2307 is connected to the gate of the first transistor 2301. The gate electrode of the seventh transistor 2307 is connected to the second wiring 2322. Connected.

[0275] The gate electrode of the first transistor 2301 and the gate electrode of the fourth transistor 2304 a second electrode of the fifth transistor 2305; a second electrode of the sixth transistor 2306; The connection point between the electrode and the second electrode of the seventh transistor 2307 is a node 2341 . Furthermore, the gate electrode of the second transistor 2302, the second the first electrode of the fourth transistor 2304 and the gate of the sixth transistor 2306 The connection point of the root electrode is designated as node 2342.

[0276] The fourth wiring 2324, the ninth wiring 2329, the tenth wiring 2330 and the eleventh wiring 23 31 may be connected to each other or may be the same wiring. The 27th and eighth wirings 2328 may be connected to each other or may be the same wiring.

[0277] The first to seventh transistors 2301 to 2307 are the same as those in FIG. The first to seventh transistors 101 to 107 correspond to each other and have the same functions.

[0278] The first wiring 2321 to the eleventh wiring 2331 are the same as the first wiring 121 in FIG. 11th wiring 131. However, the first wiring 2321 to the 11th wiring 23 The signal input to the first wiring 121 in FIG. 1, the potential supplied to the second wiring 121 in FIG. 1, or the signal output from the first wiring 121 in FIG. -Compared to the signal input to the eleventh wiring 131, the potential supplied, or the signal output The H and L levels are inverted.

[0279] Note that a potential of V2 is supplied to the seventh wiring 2327 and the eighth wiring 2328. The fourth wiring 2324, the ninth wiring 2329, the tenth wiring 2330 and the eleventh wiring 23 31 are each supplied with a potential of V1.

[0280] The first wiring 2321, the second wiring 2322, the fifth wiring 2325 and the sixth wiring 2326 are A signal is input to each of the first wirings 2326. A signal is input to the first wiring 2321. The signal input to the second wiring 2322 is a reset signal, and the signal input to the fifth wiring 2323 is a reset signal. The signal input to 2325 is the first clock signal, and the signal input to the sixth wiring 2326 is the The signal transmitted through the first wiring 2321 and the second wiring 2322 is the second clock signal. The signals input to the fifth wiring 2325 and the sixth wiring 2326 are the voltages of the H signals. The potential of the L signal is V2 (hereinafter also referred to as the L level). It is a digital signal.

[0281] The first wiring 2321, the second wiring 2322, and the second wiring 2322 to the eleventh wiring 2323 are connected to each other. Various signals, currents or voltages may be input to 331 respectively.

[0282] A signal is output from the third wiring 2323. The signal is the output signal of the flip-flop of each stage, and is the output signal of the flip-flop of the next stage. This is also the start signal of the loop (hereinafter also referred to as the transfer signal). The signal output from the H signal has a potential of V1 (hereinafter also referred to as the H level), and the L signal has a potential of V2 (hereinafter also referred to as the H level). is the digital signal V2 (hereinafter also referred to as L level).

[0283] Next, regarding the operation of the flip-flop shown in FIG. 23, the timing chart of FIG. 24 is Further, the timing chart of FIG. 24 is divided into a selection period and a non-selection period. The non-selection period is divided into a first non-selection period, a second non-selection period, a set period, and a The explanation will be divided into the period and the reset period. As shown, each period is made up of a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period. The selection period, the first non-selection period, and the second non-selection period are arranged in this order. The operation period excluding the selection period and the reset period includes a first non-selection period and a second non-selection period. Furthermore, the period before the set period is a second non-selection period.

[0284] The timing chart in Figure 24 shows the H level and L level of the timing chart in Figure 2. is the same as the inverse of

[0285] The flip-flop of this embodiment has a structure in which the H level and L level of FIG. In addition, the H level and L level of the timing charts in Figures 6, 28, 31 and 32 An inverted version of the rule may also be used.

[0286] In FIG. 24, the signals 2421, 2425, 2426, the potential 2441, and the potential The output 2442, the signal 2422, and the signal 2423 are input to the first wiring 2321. a signal input to the fifth wiring 2325; a signal input to the sixth wiring 2326; The potential of the node 2341, the potential of the node 2342, the signal input to the second wiring 2322, A signal output from the third wiring 2323 is shown.

[0287] In addition, the signal 2421, the signal 2425, the signal 2426, the potential 2441, the potential 2442, the signal 2. The signals 2422 and 223 correspond to the signals 221, 225, and 226 in FIG. 241, potential 242, signal 222 and signal 223. As shown, the H level and L level are inverted.

[0288] First, in the set period shown in FIG. 24(A), the signal 2421 is at the L level, so the fifth gate The transistor 2305 is turned on, and the signal 2422 is at H level, so the seventh transistor 230 At this time, the potential of the node 2341 is The electrode of the fifth transistor 2305 serves as a source electrode, and the potential of the eighth wiring 2328 and the potential of the fifth transistor 2305 Since it is the sum of the absolute value of the threshold voltage of V2+|Vth(2305)|(Vth(23 05): the threshold voltage of the fifth transistor 2305. The first and fourth transistors 2301 and 2304 are turned on, and the fifth transistor 2305 is turned on. At this time, the potential of the node 2342 (potential 2442) is The resistance ratio (L / W and applied voltage) between the third transistor 2303 and the fourth transistor 2304 is determined. V1-θ (θ: any positive number). Furthermore, θ<|Vth(2302)|(Vt h(2302): threshold voltage of the second transistor 2302) and θ<|Vth(23 06)|(threshold voltage of the sixth transistor 2306). That is, the ninth wiring 2 The potential difference (V1-V2) between the potential (V1) of the sixth wiring 2329 and the potential (V2) of the sixth wiring 2326 is The voltage is divided by the third transistor 2303 and the fourth transistor 2304. As a result, the second transistor 2302 and the sixth transistor 2306 are turned off. During the set period, the third wiring 2323 is connected to the fifth wiring 2325 to which an H signal is input. Therefore, the potential of the third wiring 2323 becomes V1. The potential is output from the wiring 2323. Furthermore, the potential of the node 2341 is V2+|Vth(23 05)| and becomes floating while maintaining

[0289] During the selection period shown in FIG. 24B, the signal 2421 is at H level, and the fifth transistor 2 305 is turned off, and the signal 2422 remains at H level, so the seventh transistor 2307 is turned on. At this time, the potential of the node 2341 is maintained at V2+|Vth(2305)|. Therefore, the first transistor 2301 and the fourth transistor 2304 are turned on. At this time, the potential of the node 2342 is set to the H level when the sixth wiring 2326 is set to the H level. Therefore, the second transistor 2302 and the sixth transistor 23 06 remains off. Here, an L signal is input to the fifth wiring 2325, so the third The potential of the wiring 2323 starts to decrease. Then, the potential of the node 2341 decreases. The voltage drops from V2+|Vth(2305)| to V2-|Vth(230 1) |-γ(Vth(2301): threshold voltage of the first transistor 2301, γ: arbitrary Therefore, the potential of the third wiring 2323 is equal to that of the fifth wiring 2325. The potential becomes equal to V2. This bootstrap operation is This is achieved by capacitive coupling of the parasitic capacitance between the gate electrode and the second electrode of the transistor 2301. In this way, during the selection period, the third wiring 2323 is connected to the fifth wiring 2323 to which the L signal is input. 325, the potential of the third wiring 2323 becomes V2. It is output from the third wiring 2323.

[0290] During the reset period shown in FIG. 24(C), the signal 2421 remains at H level, so the fifth transistor The transistor 2305 remains off, and the signal 2422 goes low to activate the seventh transistor. At this time, the potential of the node 2341 is equal to the potential of the 11th wiring (V 1) is supplied via the seventh transistor 2307, so it becomes V1. The transistor 2301 and the fourth transistor 2304 are turned off. At this time, the node 2 The potential of the sixth transistor 342 is supplied to the sixth transistor 2303 through the second electrode of the third transistor 2303 as the source electrode. The potential (V2) of the wiring 2326 is subtracted from the threshold voltage of the third transistor 2303. V2+|Vth(2303)|(Vth(2303): third transistor Therefore, the second transistor 2302 and the sixth transistor 2303 In this way, during the reset period, the third wiring 2323 is connected to V 1 is supplied to the fourth wiring 2324, the potential of the third wiring 2323 becomes V Therefore, the H signal is output from the third wiring 2323.

[0291] During the first non-selection period shown in FIG. 24(D), the signal 2421 remains at H level. The transistor 2305 remains off, and the signal 2422 goes high to turn on the seventh transistor. The transistor 2307 is turned off. At this time, the potential of the node 2342 is Since an H signal is input to the second transistor 2302 and the sixth transistor 2303, the voltage V1 is V2. The transistor 2306 is turned off. At this time, the node 2341 is in a floating state, so the current Therefore, the first transistor 2301 and the fourth transistor 23 04 remains off. In this way, during the first non-selection period, the third wiring 2323 is floating. Since the third wiring 2323 is in a free state, the potential of the third wiring 2323 is maintained at V1.

[0292] In the second non-selection period shown in FIG. 24(E), the signal 2421 remains at H level. The transistor 2305 remains off and the signal 2422 remains at the H level. The transistor 2307 remains off. At this time, the potential of the node 2342 is An L signal is input to the wiring 2326, and the transistor 2304 is off, so V2+|V th(2303)|. Therefore, the second transistor 2302 and the sixth transistor At this time, the potential of the node 2341 is equal to the potential of the tenth wiring 2330. The potential (V1) is supplied via the sixth transistor 2306, so it remains at V1. Therefore, the first transistor 2301 and the fourth transistor 2304 remain off. In this way, during the second non-selection period, the third wiring 2323 is connected to the fourth wiring 2323 to which V1 is supplied. Since the third wiring 2323 is electrically connected to the second wiring 2324, the potential of the third wiring 2323 remains at V1. As a result, an H signal is output from the third wiring 2323 .

[0293] From the above, the flip-flop in Figure 23 performs bootstrap operation during the selection period. By using this operation, the potential of the node 2341 is made lower than V2-|Vth(2301)|. As a result, the potential of the third wiring 2323 can be set to V2. The flip-flop is configured such that this bootstrap operation generates a second voltage of the first transistor 2301. The layout is done by using the capacitive coupling of the parasitic capacitance between the electrode and the gate electrode. This provides advantages such as a reduced area and a reduced number of elements.

[0294] Furthermore, the flip-flop of FIG. 23 includes a second transistor 2302 and a sixth transistor Since the second transistor 2306 is turned on only during the second non-selection period, the second transistor 230 The shift in the threshold voltage of the second and sixth transistors 2306 can be suppressed.

[0295] In addition, in the flip-flop of FIG. 23, V2 is applied to the gate electrode of the third transistor 2303. and inputting a second clock signal to the first electrode of the third transistor 230. The shift in threshold voltage of 3 can also be suppressed.

[0296] Furthermore, the flip-flop of FIG. 23 includes a first transistor 2301, a fourth transistor The first non-selected transistor 2304, the fifth transistor 2305 and the seventh transistor 2307 are connected to the first non-selected transistor 2304. Since the first transistor 2301 and the second transistor 2302 are not turned on during the selection period and the second non-selection period, The fourth transistor 2304, the fifth transistor 2305 and the seventh transistor 230 7, the shift in the threshold voltage can be suppressed.

[0297] 23. Furthermore, the flip-flop in FIG. 23 is configured such that the potential of the node 2341 and the potential of the third wiring 2323 Even if the potential fluctuates during the first non-selection period, the potential of the node 23 By supplying V1 to the node 2341 and the third wiring 2323, the potential of the node 2341 and the third wiring 2323 are The potential of the wiring 2323 can be reset to V1. The flop is caused by the node 2341 and the wiring 2323 being in a floating state. A malfunction caused by a change in the potential of the third wiring 2323 can be suppressed.

[0298] Furthermore, the flip-flop in Figure 23 can suppress the threshold shift of the transistor. Therefore, malfunctions caused by a shift in the threshold voltage of the transistor can be suppressed.

[0299] Furthermore, the flip-flop of FIG. 23 includes the first transistor 2301 to the seventh transistor 2302. The transistors 2307 are all P-channel transistors. Therefore, the flip-flop of FIG. 23 can simplify the manufacturing process and reduce the manufacturing cost. This can reduce costs and improve yields.

[0300] If the operation is the same as that shown in FIG. 24, the arrangement and number of transistors may be the same as that shown in FIG. 4. Therefore, the flip-flop of FIG. 24 may be equipped with transistors, other New elements (resistance elements, capacitance elements, etc.), diodes, switches, various logic circuits, etc. It may be placed.

[0301] The shift register of this embodiment is the flip-flop of this embodiment. The present invention can be implemented by freely combining with the shift registers described in any of Embodiments 1 to 3. For example, the shift register of this embodiment may be the flip-flop of this embodiment shown in FIG. 13, 14, 15, 17, 29, 33, and 34. However, the shift register of this embodiment can be implemented in any combination. In comparison with the shift registers described in the first to third embodiments, The rule is inverted.

[0302] The display device of this embodiment may be configured by using the shift register of this embodiment in the first to third embodiments. The present embodiment can be freely combined with the display device described in the third embodiment. The display device of the embodiment can be freely combined with the display devices of FIGS. 8, 18, 16, 20 and 22. However, the display device of this embodiment can be implemented in combination with the display device of the first embodiment. Compared to the display device described in the first to third embodiments, the H level and L level are inverted.

[0303] In this embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to the content or part of the content described in another figure. Furthermore, in the diagrams mentioned above, for each part, By combining different parts, more figures can be constructed.

[0304] Similarly, the contents or part of the contents described in each drawing of this embodiment may be applied to the drawings of another embodiment. The present invention can also be applied to the contents or parts of the contents described in the above, or can be combined. Furthermore, in the drawings of this embodiment, each part may be combined with a part of another embodiment. By combining them, even more figures can be constructed.

[0305] It should be noted that this embodiment is an example of a case where the contents described in the other embodiments are embodied, and is slightly modified. Examples of cases where the product has been shaped, examples of cases where a part has been changed, examples of cases where the product has been improved, and examples of cases where the product has been described in detail It shows examples of the concept, examples of its application, and examples of related parts. Therefore, the contents described in the other embodiments can also be applied to this embodiment. It can be combined.

[0306] (Embodiment 5) In this embodiment mode, the signal line driver circuit of the display device described in any of Embodiments 1 to 4 will be described. The circuit will be described.

[0307] The signal line driver circuit shown in Fig. 37 will be described. The signal line driver circuit shown in Fig. 37 includes a driver I C5601, switch group 5602_1 to 5602_M, first wiring 5611, second wiring The switch has a first wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the groups 5602_1 to 5602_M includes a first switch 5603a, a second switch 5603b and a third switch 5603c.

[0308] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M are connected to the first wiring 5611, the second wiring 5612, and the third wiring 561 3 and wiring 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively. 621_M. These are a first switch 5603a, a second switch 5603b and a third switch 5603c. For example, the Jth row wiring 5621_J (wiring Any one of the wirings 5621_1 to 5621_M is a wiring of the switch group 5602_J. A first switch 5603a, a second switch 5603b, and a third switch 5603c are connected to the signal lines Sj-1, Sj, and Sj+1 via the

[0309] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0310] The driver IC5601 is mounted on a glass substrate using a single crystal substrate or polycrystalline semiconductor. Furthermore, the switch group 5602 is preferably formed in the same manner as in the first to third embodiments. It is desirable that the pixel section shown in the fourth embodiment is formed on the same substrate. The driver IC 5601 and the switch group 5602 may be connected via an FPC or the like.

[0311] Next, the operation of the signal line driver circuit shown in FIG. 37 will be described with reference to the timing chart of FIG. The timing chart in FIG. 38 is explained with reference to the timing chart in FIG. 38 when the i-th scanning line Gi is selected. Furthermore, the timing chart shows the selection period of the i-th scanning line Gi. is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driving circuit of FIG. In this case, the same operation as in FIG. 38 is performed.

[0312] In the timing chart of FIG. 38, the wiring 5621_J in the Jth column is connected to the first switch 56 03a, the second switch 5603b, and the third switch 5603c, and the signal line Sj 1, and is connected to signal line Sj and signal line Sj+1.

[0313] The timing chart of FIG. 38 shows the timing when the i-th scanning line Gi is selected, The on / off timing 5703a of the first switch 5603a, the second switch 5603 b on / off timing 5703b, the third switch 5603c on / off timing 5703c and a signal 5721_J input to the J-th row wiring 5621_J. There are.

[0314] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the signal is output to the wiring 5621 during the third sub-selection period T3. The video signal input to the signal line Sj+1 is input to the signal line Sj+2. In the second sub-selection period T2 and the third sub-selection period T3, The video signals to be input are Dataj-1, Dataj, and Dataj+1, respectively.

[0315] As shown in FIG. 38, the first switch 5603a is turned on during the first sub-selection period T1. Then, the second switch 5603b and the third switch 5603c are turned off. Dataj-1 input to the line 5621_J is output as a signal via the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on. At this time, the first switch 5603a and the third switch 5603c are turned off. Dataj input to the wiring 5621_J is connected to the signal line 5603b via the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on, The first switch 5603a and the second switch 5603b are turned off. Dataj+1 input to 621_J is transmitted to the signal line S via the third switch 5603c. It is input to j+1.

[0316] From the above, the signal line driver circuit in FIG. 37 can be realized by dividing one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the display is mounted and the substrate on which the pixel area is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one-third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0317] The signal line driving circuit of this embodiment may be applied to the display devices shown in the first to fourth embodiments. By doing so, it is possible to further reduce the number of connections between the substrate on which the pixel section is formed and the external substrate. Therefore, the display device of this embodiment mode can improve reliability. Furthermore, the display device of this embodiment mode can increase the yield.

[0318] Next, the first switch 5603a, the second switch 5603b, and the third switch 560 A case where an N-channel transistor is applied to 3c will be described with reference to FIG. In addition, the same parts as those in FIG. 37 are indicated by the same reference numerals, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0319] The first transistor 5903a corresponds to the first switch 5603a, and the second transistor The third transistor 5903b corresponds to the second switch 5603b, and the third transistor 5903c corresponds to the This corresponds to switch 5603c in 3.

[0320] For example, in the case of the switch group 5602_J, the first transistor 5903a has a first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj-1, and the gate electrode is The first electrode of the second transistor 5903b is connected to the first wiring 5611. 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the second wiring A first electrode of the third transistor 5903c is connected to the wiring 5621_ J, the second electrode is connected to the signal line Sj+1, and the gate electrode is connected to the third wiring 561 3 is connected.

[0321] Note that the first transistor 5903a, the second transistor 5903b, and the third transistor The first transistor 5903c functions as a switching transistor. A transistor 5903a, a second transistor 5903b, and a third transistor 5903 c turns on when the signal input to the gate electrode is at H level, and It is turned off when the signal input to is at L level.

[0322] The first switch 5603a, the second switch 5603b, and the third switch 560 By using an N-channel transistor as 3c, the semiconductor layer of the transistor Since amorphous silicon can be used as the material, the manufacturing process can be simplified. This is because it is possible to reduce manufacturing costs and improve yields. This is because it is possible to manufacture a semiconductor device such as a display panel of a different type. Even if polysilicon or polycrystalline silicon is used as the semiconductor layer of the transistor, the manufacturing process can be simplified. It is possible to achieve this.

[0323] In the signal line driver circuit of FIG. 39, the first transistor 5903a and the second transistor 59 03b, when an N-channel transistor is used as the third transistor 5903c However, the first transistor 5903a, the second transistor 5903b, A P-channel transistor may be used as the third transistor 5903c. When the signal input to the gate electrode is at L level, the transistor is turned on. When the signal input to the output electrode is at H level, the output is turned off.

[0324] As shown in Figure 37, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, there are no limitations on the arrangement, number, driving method, etc. of the switches.

[0325] For example, three or more signal lines are connected to one wiring in each of three or more sub-selection periods. If you want to input a video signal to each, you need to add a switch and wiring to control the switch. However, if one gate selection period is divided into four or more sub-selection periods, Therefore, one gate selection period is divided into two or three sub-selection periods. It is desirable to divide it between

[0326] As another example, as shown in the timing chart of FIG. 40, one selection period is precharged. The first sub-selection period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 are Furthermore, in the timing chart of FIG. 40, the scanning line Gi of the i-th row is selected. the timing of turning on / off the first switch 5603a, the timing of turning on / off the second switch 5603b, The on / off timing 5803b of the first switch 5603b, the on / off timing 5803b of the third switch 5603c The on / off timing 5803c and the signal 58 input to the J-th row wiring 5621_J As shown in FIG. 40, in the precharge period Tp, the first switch The first switch 5603a, the second switch 5603b and the third switch 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is applied to the first switch 560 3a, a second switch 5603b, and a third switch 5603c. Sj-1, signal line Sj, and signal line Sj+1. The first switch 5603a is turned on, and the second switch 5603b and the third switch 56 At this time, Dataj-1 input to the wiring 5621_J is The signal is input to the signal line Sj-1 via the switch 5603a. The second switch 5603b is turned on, and the first switch 5603a and the third switch 5603b are turned on. At this time, Dataj input to the wiring 5621_J is In the third sub-selection period T3, the third The first switch 5603a and the second switch 5603c are turned on. At this time, Dataj+1 input to the wiring 5621_J is The signal is input to the signal line Sj+1 via the switch 5603c.

[0327] From the above, the signal line driver circuit of FIG. 37 to which the timing chart of FIG. 40 is applied By providing a precharge selection period before the block selection period, the signal lines can be precharged. This allows for high-speed writing of video signals to the pixels. The same parts or parts with similar functions are shown using the same symbols. A detailed explanation will be omitted.

[0328] In FIG. 41, as in FIG. 37, one gate selection period is divided into multiple sub-selection periods, During each of the multiple sub-selection periods, a video signal is sent from one wiring to each of the multiple signal lines. 41 shows the signal line driver circuit of the switch in the Jth column. Only the group 6022_J is shown. The switch group 6022_J includes the first transistor 60 01, a second transistor 6002, a third transistor 6003, and a fourth transistor The transistor 6004, the fifth transistor 6005, and the sixth transistor 6006. First transistor 6001, second transistor 6002, third transistor 6003 , a fourth transistor 6004, a fifth transistor 6005, a sixth transistor 60 The switch group 6022_J is connected to the first wiring 60 11, the second wiring 6012, the third wiring 6013, the fourth wiring 6014, the fifth wiring 60 15, the sixth wiring 6016, the wiring 5621_J, the signal line Sj-1, the signal line Sj, the signal line S j+1 is connected to the

[0329] A first electrode of the first transistor 6001 is connected to the wiring 5621_J, and a second electrode of the first transistor 6001 is connected to the wiring 5621_J. The second transistor is connected to the signal line Sj-1, and the gate electrode is connected to the first wiring 6011. The first electrode of the transistor 6002 is connected to the wiring 5621_J, and the second electrode is connected to the signal line Sj The third transistor 6 is connected to the first wiring 6011 and the gate electrode is connected to the second wiring 6012. The first electrode of the pixel 003 is connected to the wiring 5621_J, and the second electrode is connected to the signal line Sj. The gate electrode of the fourth transistor 6004 is connected to a third wiring 6013. The electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is The first electrode of the fifth transistor 6005 is connected to the fourth wiring 6014. 21_J, the second electrode is connected to the signal line Sj+1, and the gate electrode is connected to the fifth wiring A first electrode of the sixth transistor 6006 is connected to a wiring 5621_J. The second electrode is connected to the signal line Sj+1, and the gate electrode is connected to the sixth wiring 6016. Connected.

[0330] Note that the first transistor 6001, the second transistor 6002, and the third transistor 6003, a fourth transistor 6004, a fifth transistor 6005, a sixth transistor The first transistor 6006 functions as a switching transistor. a first transistor 6001, a second transistor 6002, a third transistor 6003, a fourth transistor 6004, a The first transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 are , and are turned on when the signal input to the gate electrode is at H level. When the input signal is at L level, it is turned off.

[0331] The first wiring 6011 and the second wiring 6012 correspond to the first wiring 5911 in FIG. The third wiring 6013 and the fourth wiring 6014 correspond to the second wiring 5912 in FIG. The fifth wiring 6015 and the sixth wiring 6016 correspond to the third wiring 5913 in FIG. The first transistor 6001 and the second transistor 6002 correspond to the transistors shown in FIG. The third transistor 6003 corresponds to the first transistor 5903a of the third transistor 6003. The fifth transistor 6004 corresponds to the second transistor 5903b in FIG. The transistor 6005 and the sixth transistor 6006 are the same as the third transistor in FIG. Equivalent to 5903c.

[0332] In FIG. 41, the first transistor 600 is turned on during the first sub-selection period T1 shown in FIG. Either the first or second transistor 6002 is turned on. When the third transistor 6003 or the fourth transistor 6004 is turned on, In the third sub-selection period T3, the fifth transistor 6005 or the sixth transistor 6006 is turned on. Furthermore, during the precharge period Tp shown in FIG. The first transistor 6001, the third transistor 6003, and the fifth transistor 60 605, the second transistor 6002, the fourth transistor 6004 and the sixth transistor Either of the starters 6006 turns on.

[0333] Therefore, in FIG. 41, the on time of each transistor can be shortened, and therefore, This can suppress the deterioration of the transistor characteristics. For example, in the first In the sub-selection period T1, the first transistor 6001 or the second transistor 60 If either 02 is on, can a video signal be input to signal line Sj-1? For example, in the first sub-selection period T1 shown in FIG. By simultaneously turning on the first transistor 6001 and the second transistor 6002, A video signal can also be input to the signal line Sj-1.

[0334] In FIG. 41, two transistors are connected in parallel between the wiring 5621 and the signal line. However, the present invention is not limited to this case, and three or more transistors may be connected to the wiring 56. 21 and the signal line. The deterioration of characteristics can be suppressed.

[0335] In this embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to the content or part of the content described in another figure. Furthermore, in the diagrams mentioned above, for each part, By combining different parts, more figures can be constructed.

[0336] Similarly, the contents or part of the contents described in each drawing of this embodiment may be applied to the drawings of another embodiment. The present invention can also be applied to the contents or parts of the contents described in the above, or can be combined. Furthermore, in the drawings of this embodiment, each part may be combined with a part of another embodiment. By combining them, even more figures can be constructed.

[0337] It should be noted that this embodiment is an example of a case where the contents described in the other embodiments are embodied, and is slightly modified. Examples of cases where the product has been shaped, examples of cases where a part has been changed, examples of cases where the product has been improved, and examples of cases where the product has been described in detail It shows examples of the concept, examples of its application, and examples of related parts. Therefore, the contents described in the other embodiments can also be applied to this embodiment. It can be combined.

[0338] (Sixth embodiment) In this embodiment mode, defects due to electrostatic breakdown of the display devices shown in Embodiment Modes 1 to 4 are A configuration for preventing this will be described.

[0339] Electrostatic breakdown occurs when positive or negative charges accumulated on the human body or an object come into contact with a semiconductor device. When the device is turned on, a large current flows into the device due to instantaneous discharge through the device's input / output terminals. This refers to the destruction that occurs when water flows.

[0340] FIG. 42(A) shows a structure for preventing electrostatic breakdown occurring in the scanning lines by using a protection diode. FIG. 42(A) shows a configuration in which a protection diode is placed between the wiring 6111 and the scanning line. Although not shown, a plurality of pixels are connected to the i-th row scanning line Gi. The transistor 6101 is used as a protection diode. 01 is an N-channel transistor. However, if a P-channel transistor is used, The polarity of the transistor 6101 may be changed depending on the polarity of the transistors included in the scan line driver circuit and the pixel. The same polarity may be used.

[0341] Although only one protection diode is installed, multiple protection diodes are installed in series. The electrodes may be arranged in series, in parallel, or in series-parallel.

[0342] The first electrode of the transistor 6101 is connected to the i-th scanning line Gi, and the second electrode is connected to the wiring 6111, and the gate electrode is connected to the i-th row scanning line Gi.

[0343] The operation of FIG. 42(A) will be described. A certain potential is input to the wiring 6111. The potential of this signal is lower than the L level of the signal input to the i-th scanning line Gi. If negative charges are not discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi is Since the voltage is at H level or L level, the transistor 6101 is turned off. When the electric charge is discharged to the ith scanning line Gi, the potential of the ith scanning line Gi drops instantaneously. At this time, the potential of the i-th row scanning line Gi is changed from the potential of the wiring 6111 to the potential of the transistor 61 When the voltage drops below the threshold voltage of transistor 6101, transistor 6101 turns on and the current The current flows through the transistor 6101 to the wiring 6111. The configuration shown prevents large currents from flowing into the pixel, reducing the electrostatic Destruction can be prevented.

[0344] FIG. 42(B) shows a circuit for preventing electrostatic breakdown when a positive charge is discharged to the i-th scanning line Gi. The transistor 6102 functioning as a protection diode is connected to the scan line and the wiring 6112. Only one protection diode is provided. However, multiple protection diodes may be arranged in series or in parallel. The transistor 6102 may be an N-channel type. However, a P-channel transistor may also be used. The polarity of the transistor 6102 is the same as that of the transistors in the scanning line driver circuit and the pixel. The first electrode of the transistor 6102 is connected to the i-th scan line Gi, and the second electrode of the transistor 6102 is connected to the i-th scan line Gi. The electrode is connected to a wiring 6112, and the gate electrode is connected to the wiring 6112. A potential higher than the H level of the signal input to the i-th row scanning line Gi is input to 6112. Therefore, the transistor 6102 discharges the electric charge to the scanning line Gi of the i-th row. On the other hand, when a positive charge is discharged to the i-th scan line Gi, When the voltage of the scanning line Gi of the i-th row is increased, the voltage of the scanning line Gi of the i-th row rises instantaneously. The potential of the wiring 6112 becomes higher than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102. When this happens, the transistor 6102 turns on, and the current flows through the transistor 6102 to the wiring 61 Therefore, the configuration shown in FIG. 42(B) prevents a large current from flowing into the pixel. Since this prevents the pixels from being caught in the electrostatic discharge, it is possible to prevent electrostatic damage to the pixels.

[0345] As shown in FIG. 42(C), a configuration in which FIG. 42(A) and FIG. 42(B) are combined is also possible. By doing so, even if a positive charge is discharged to the i-th scanning line Gi, a negative charge is Even if a discharge occurs to the scanning line Gi, electrostatic damage to the pixel can be prevented. 2(A) and (B) are shown with the same symbols, and the same or similar parts are shown. A detailed description of the functional parts will be omitted.

[0346] FIG. 43A shows a transistor 6201 functioning as a protective diode connected to a scan line and a storage capacitor. The figure shows the configuration when connected between the measurement line and the protection diode. However, multiple protection diodes may be arranged in series or in parallel. The transistor 6201 may be an N-channel type. However, a P-channel transistor may also be used. The polarity of the transistor 6201 is the same as that of the transistors in the scanning line driver circuit and the pixel. The wiring 6211 functions as a storage capacitor line. The first electrode of the pixel is connected to the i-th scanning line Gi, and the second electrode of the pixel is connected to the wiring 6211. The gate electrode is connected to the scanning line Gi of the i-th row. A potential lower than the L level of the signal input to the line Gi is input. When the charge is not discharged to the i-th scanning line Gi, the transistor 6201 is turned off. On the other hand, when negative charges are discharged to the i-th scanning line Gi, At this time, the potential of the scanning line Gi of the i-th row drops from the potential of the wiring 6211. When the voltage drops below the threshold voltage of the transistor 6201 minus the threshold voltage of the transistor 6202, the transistor 62 6201 is turned on, and a current flows through the transistor 6201 to the wiring 6211. Therefore, the configuration shown in FIG. 43(A) can prevent a large current from flowing into the pixel. Therefore, electrostatic damage to the pixels can be prevented. Since the storage capacitance line is used as a wiring to release the charge, there is no need to add a new wiring. There is no.

[0347] FIG. 43(B) shows a circuit for preventing electrostatic breakdown when a positive charge is discharged to the i-th scanning line Gi. Here, the wiring 6211 is a configuration for stopping the signal from being input to the i-th row scanning line Gi. Therefore, a potential higher than the H level of the signal input to the transistor 6201 is is turned off when no charge is discharged to the i-th scanning line Gi. When the electric charge is discharged to the ith scanning line Gi, the potential of the ith scanning line Gi rises instantaneously. At this time, the potential of the i-th scan line Gi is equal to the potential of the wiring 6211 and the transistor 62 When the voltage exceeds the sum of the threshold voltages of transistors 6201 and 6202, transistor 6201 turns on and the current The current flows through the transistor 6201 to the wiring 6211. This structure prevents large currents from flowing into the pixels, reducing the risk of electrostatic damage to the pixels. Furthermore, in the configuration shown in FIG. 43(B), the storage capacitor line is Since it is used as a relief wiring, there is no need to add new wiring. B) The same parts or parts having the same functions are designated by common symbols. A detailed description of the parts will be omitted.

[0348] Next, the configuration for preventing electrostatic breakdown occurring in signal lines using protection diodes is shown in Figure 44. FIG. 44(A) shows a case where a protection diode is placed between a wiring 6411 and a signal line. Although not shown, a plurality of pixels are connected to the j-th column signal line Sj. Note that a transistor 6401 is used as a protective diode. The transistor 6401 is an N-channel transistor. The polarity of the transistor 6401 may be determined by the polarity of the signal line driver circuit or the pixel. The polarity of the transistor may be the same as that of the transistor.

[0349] Although only one protection diode is installed, multiple protection diodes are installed in series. The electrodes may be arranged in series, in parallel, or in series-parallel.

[0350] The first electrode of the transistor 6401 is connected to the j-th signal line Sj, and the second electrode is connected to the wiring 6411, and the gate electrode is connected to the j-th signal line Sj.

[0351] The operation of FIG. 44A will be described. A certain potential is input to the wiring 6411. The potential is also low when the minimum value of the video signal input to the j-th signal line Sj is low. If negative charges are not discharged to the jth signal line Sj, the potential of the jth signal line Sj is Since the potential is the same as the video signal, the transistor 6401 is turned off. is discharged to the j-th signal line Sj, the potential of the j-th signal line Sj drops instantaneously. At this time, the potential of the j-th signal line Sj is changed from the potential of the wiring 6411 to the potential of the transistor 6401. When the voltage drops below the threshold voltage, the transistor 6401 turns on and the current flows. It flows through the transistor 6401 to the wiring 6411. This structure prevents large currents from flowing into the pixels, thus preventing electrostatic damage to the pixels. It can be prevented.

[0352] FIG. 44(B) shows the structure for preventing electrostatic breakdown when a positive charge is discharged to the j-th signal line Sj. The transistor 6402 functioning as a protective diode is connected to the scan line and the wiring 6412. Only one protection diode is provided. However, multiple protection diodes may be arranged in series or in parallel. The transistor 6402 may be an N-channel type. However, a P-channel transistor may also be used. The polarity of the transistor 6402 is the same as that of the transistors in the scanning line driver circuit and the pixel. The first electrode of the transistor 6402 is connected to the signal line Sj in the j-th row, and the second electrode of the transistor 6402 is connected to the signal line Sj in the j-th row. The electrode is connected to a wiring 6412, and the gate electrode is connected to a wiring 6412. 6412 receives a voltage higher than the maximum value of the video signal input to the j-th signal line Sj. Therefore, the transistor 6402 discharges the charge to the j-th signal line Sj. When the signal is not turned on, it is turned off. On the other hand, a positive charge is discharged to the jth signal line Sj. When the signal line Sj is turned on, the potential of the signal line Sj in the jth row rises instantaneously. The potential of Sj is higher than the sum of the potential of the wiring 6412 and the threshold voltage of the transistor 6402. When the voltage drops, the transistor 6402 turns on and the current flows through the Therefore, the configuration shown in FIG. 44(B) prevents a large current from flowing to the pixel. Since the electrostatic discharge can be prevented from entering the pixel, electrostatic damage to the pixel can be prevented.

[0353] As shown in FIG. 44(C), a configuration in which FIG. 44(A) and FIG. 44(B) are combined is also possible. By doing so, even if a positive charge is discharged to the jth signal line Sj, a negative charge is Even if a discharge occurs to the signal line Sj, electrostatic damage to the pixel can be prevented. 4(A) and (B) are shown with the same symbols, and the same or similar parts are shown. A detailed description of the functional parts will be omitted.

[0354] In this embodiment, a structure for preventing electrostatic breakdown of pixels connected to scanning lines and signal lines is used. However, the configuration of this embodiment is such that the capacitance of the pixel connected to the scanning line and the signal line is It is not only applied to the prevention of destruction. For example, The wiring to which a signal or potential is inputted is connected to the scanning line driver circuit and the signal line driver circuit. When the embodiment is applied, electrostatic damage to the scanning line driving circuit and the signal line driving circuit is prevented. It is possible.

[0355] In this embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to the content or part of the content described in another figure. Furthermore, in the diagrams mentioned above, for each part, By combining different parts, more figures can be constructed.

[0356] Similarly, the contents or part of the contents described in each drawing of this embodiment may be applied to the drawings of another embodiment. The present invention can also be applied to the contents or parts of the contents described in the above, or can be combined. Furthermore, in the drawings of this embodiment, each part may be combined with a part of another embodiment. By combining them, even more figures can be constructed.

[0357] It should be noted that this embodiment is an example of a case where the contents described in the other embodiments are embodied, and is slightly modified. Examples of cases where the product has been shaped, examples of cases where a part has been changed, examples of cases where the product has been improved, and examples of cases where the product has been described in detail It shows examples of the concept, examples of its application, and examples of related parts. Therefore, the contents described in the other embodiments can also be applied to this embodiment. It can be combined.

[0358] (Embodiment 7) In this embodiment mode, a display device that can be applied to the display devices described in Embodiments 1 to 4 will be described. This section explains the new configuration of the device.

[0359] Figure 45(A) shows a diode-connected transistor between two scan lines. In FIG. 45(A), the scanning line Gi-1 in the i-1th row and the scanning line Gi-2 in the i-th row are A diode-connected transistor 6301a is arranged between the scan line Gi and the scan line A diode-connected transistor 63 is connected between the scanning line Gi and the (i+1)th scanning line Gi+1. The figure shows the configuration when the transistor 6301a and the transistor 6301b are arranged. The transistor 6301b is an N-channel transistor. The polarities of the transistors 6301a and 6301b may be changed. The polarity of the transistors may be the same as that of the transistors in the line driver circuit and pixels.

[0360] In FIG. 45(A), the scanning line Gi-1 in the (i-1)th row, the scanning line Gi in the i-th row, and The other scan lines are also diode-connected in the same way. The transistors are arranged in a

[0361] A first electrode of the transistor 6301a is connected to the i-th scan line G i , and a second electrode of the transistor 6301a is connected to the i-th scan line G i . The gate electrode is connected to the scanning line Gi-1 in the Gi-1 row. A first electrode of the transistor 6301b is connected to the (i+1)th scan line Gi+1. The second electrode is connected to the i-th scanning line Gi, and the gate electrode is connected to the i-th scanning line Gi. To be continued.

[0362] The operation of Fig. 45(A) will be described. In the driving circuit, during the non-selection period, the scanning line Gi-1 of the (i-1)th row, the scanning line Gi of the i-th row, and The (i+1)th row scanning line Gi+1 is maintained at the L level. 301a and transistor 6301b are off. However, for example, noise When the potential of the i-th row scanning line Gi rises due to Therefore, as shown in Figure 45(A), an incorrect video signal is written to the pixel. By placing a diode-connected transistor between the scan lines, the pixel receives an incorrect video signal. This prevents a signal from being written because the potential of the i-th scanning line Gi The sum of the potential of the scan line Gi-1 in the (i-1)th row and the threshold voltage of the transistor 6301a or more When the potential of the scanning line G i of the i-th row is increased, the transistor 6301a is turned on, and the potential of the scanning line G i of the i-th row is decreased. Therefore, no pixel is selected by the i-th scanning line Gi.

[0363] In addition, the configuration of FIG. 45(A) is such that the scanning line driving circuit and the pixel section are integrally formed on the same substrate. This is advantageous when using an N-channel transistor or a P-channel transistor. In a scanning line driver circuit that consists only of transistors, the scanning lines may be in a floating state. This is because noise is likely to occur in the scanning lines.

[0364] In addition, in FIG. 45(B), the direction of the diode-connected transistors arranged between the scanning lines is This is the reverse configuration. is an N-channel transistor. However, even if a P-channel transistor is used, The polarities of the transistors 6302a and 6302b are often determined by a scanning line driver circuit or a display driver circuit. The polarity of the transistor in the element may be the same as that of the transistor in the element. The first electrode of the resistor 6302a is connected to the scanning line Gi in the i-th row, and the second electrode is connected to the scanning line Gi in the i-1th row. The gate electrode is connected to the ith scanning line Gi-1, and the gate electrode is connected to the ith scanning line Gi. The first electrode of the resistor 6302b is connected to the scanning line Gi+1 of the (i+1)th row, and the second electrode is It is connected to the scanning line Gi in the i-th row, and the gate electrode is connected to the scanning line Gi+1 in the i+1-th row. FIG. 45(B) shows that the potential of the i-th scanning line Gi is equal to the potential of the i-1-th scanning line Gi, as in FIG. 44(A). When the potential of the scan line Gi+1 rises above the sum of the potential of the scan line Gi+1 and the threshold voltage of the transistor 6302b, The transistor 6302b is turned on, and the potential of the i-th row scanning line Gi drops. The pixel is not selected by the ith scanning line Gi, and an incorrect video signal is not written to the pixel. This can prevent the data from being written in.

[0365] As shown in FIG. 45(C), a configuration in which FIG. 45(A) and FIG. 45(B) are combined is also possible. By this, even if the potential of the i-th scan line Gi rises, the transistor 6301a and the transistor Since the transistor 6302b is turned on, the potential of the scanning line Gi in the i-th row drops. In (C), the current flows through two transistors, so it can eliminate larger noises. It is possible to use the same symbols as in Figures 45(A) and (B). In the following description, detailed descriptions of identical parts or parts having similar functions will be omitted.

[0366] As shown in FIGS. 43(A) and 43(B), a diode is connected between the scanning line and the storage capacitor line. Even if a connected transistor is placed, the same effect as in Figures 45(A), (B), and (C) can be obtained. can be done.

[0367] In this embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to the content or part of the content described in another figure. Furthermore, in the diagrams mentioned above, for each part, By combining different parts, more figures can be constructed.

[0368] Similarly, the contents or part of the contents described in each drawing of this embodiment may be applied to the drawings of another embodiment. The present invention can also be applied to the contents or parts of the contents described in the above, or can be combined. Furthermore, in the drawings of this embodiment, each part may be combined with a part of another embodiment. By combining them, even more figures can be constructed.

[0369] It should be noted that this embodiment is an example of a case where the contents described in the other embodiments are embodied, and is slightly modified. Examples of cases where the product has been shaped, examples of cases where a part has been changed, examples of cases where the product has been improved, and examples of cases where the product has been described in detail It shows examples of the concept, examples of its application, and examples of related parts. Therefore, the contents described in the other embodiments can also be applied to this embodiment. It can be combined.

[0370] (Embodiment 8) In this embodiment, the pixel structure of a display device will be described. The elementary structure will be explained.

[0371] Figure 46 shows the pixel structure of a liquid crystal display device, known as the TN type, in which thin film transistors are used. 46A and 46B are a cross-sectional view and a top view of a pixel in which a TFT is combined. 46(A) is a cross-sectional view of the pixel, and FIG. 46(B) is a top view of the pixel. The cross-sectional view of the pixel corresponds to the line a-a' in the top view of the pixel shown in FIG. By applying this embodiment to a liquid crystal display device having the pixel structure shown in FIG. This allows the liquid crystal display device to be manufactured at low cost.

[0372] The pixel structure of a TN liquid crystal display device will be described with reference to Fig. 46(A). A display device has a key component called a liquid crystal panel that displays images. The two processed substrates are bonded together with a gap of several micrometers. In Figure 46(A), the liquid crystal material is injected between the two substrates. are a first substrate 10101 and a second substrate 10116. The first substrate has a TFT and pixel electrodes are fabricated on the second substrate, and a light-shielding film 10114 and a color filter 1011 are fabricated on the second substrate. 5, a fourth conductive layer 10113, a spacer 10117, and a second alignment film 10112 are formed. It may also be manufactured.

[0373] It is possible to carry out the process without fabricating a TFT on the first substrate 10101. When this embodiment is implemented without using the above, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, the simple structure allows for improved yield. When the present embodiment is carried out by fabricating a TFT, a larger display device can be obtained. do.

[0374] The TFT shown in FIG. 46 is a bottom gate type TFT using an amorphous semiconductor. Liquid crystal panels that use TFTs that use crystalline semiconductors can be produced inexpensively using large-area substrates. However, the present embodiment is not limited to this. The TFT structures that can be achieved are channel etch type and channel protection type for bottom gate type TFTs. In addition, a top gate type is also possible. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors are also available. Crystalline semiconductors can also be used.

[0375] This embodiment can be carried out without forming the light-shielding film 10114 on the second substrate 10116. It is possible. When this embodiment is carried out without forming the light-shielding film 10114, the number of steps is reduced. Since the number of components is small, the manufacturing cost can be reduced. On the other hand, when the light-shielding film 10114 is fabricated and the present embodiment is carried out, In this case, a display device with little light leakage during black display can be obtained.

[0376] In this embodiment, the color filter 10115 is not formed on the second substrate 10116. In the case where this embodiment is carried out without fabricating the color filter 10115, In this case, the number of steps is reduced, which reduces the manufacturing cost. However, since the color filter 10115 is made Even if this embodiment is implemented without manufacturing a color LCD panel, the color LCD panel can be driven by field sequential driving. On the other hand, a display device capable of displaying a color image can be obtained by fabricating a color filter 10115. When this embodiment is implemented in this manner, a display device capable of color display can be obtained.

[0377] In this embodiment, the spacer 10117 is not formed on the second substrate 10116, and a spherical This can also be achieved by scattering spacers. When the embodiment is implemented, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, the structure is simple, which can improve the yield. When the present embodiment is carried out by manufacturing 17, the position of the spacer does not vary, so 2 The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained. do.

[0378] Next, a description will be given of processing to be performed on the first substrate 10101. The first substrate 10101 is a light-transmitting substrate. A substrate having such properties is suitable, for example, a quartz substrate, a glass substrate, or a plastic substrate. The first substrate 10101 may be a light-shielding substrate, such as a semiconductor substrate or SOI (S A silicon on insulator (SIL) substrate may also be used.

[0379] First, a first insulating film 10102 may be formed on a first substrate 10101. 10102 is a silicon oxide film, a silicon nitride film or a silicon oxynitride film (SiOxN Alternatively, the first insulating film 10102 may be a silicon oxide film. , a silicon nitride film, a silicon oxynitride film (SiOxNy), or the like. A first insulating film 10102 is formed as a layered insulating film. When implementing the embodiment, impurities from the substrate affect the semiconductor layer and the properties of the TFT. This also prevents the TFT properties from changing. A highly reliable display device can be obtained. When this embodiment is implemented, the number of steps is reduced, and therefore the manufacturing cost can be reduced. In addition, the simple structure allows for improved yield.

[0380] Next, a first conductive layer 1010 is formed on the first substrate 10101 or the first insulating film 10102. The first conductive layer 10103 may be formed by processing the shape. The process for processing the first conductive layer 101 is preferably as follows: At this time, the first conductive layer 10103 is formed by a sputtering device or a C The film may be formed using a film forming apparatus such as a VD apparatus. Then, a photosensitive resist material is formed on the entire surface. The resist material is exposed to light according to the desired shape by direct writing or the like. Either the resist material that has been exposed to light or the resist material that has not been exposed to light is used as the etching material. By removing the mask by etching, the mask for shaping the first conductive layer 10103 is formed. Then, the first conductive layer 10103 is formed according to the formed mask pattern. The first conductive layer 10103 is shaped into a desired pattern by etching away the remaining part. The first conductive layer 10103 can be etched by chemical etching. There are two methods: wet etching and dry etching. Considering the material of the conductive layer 10103 and the properties of the material below the first conductive layer 10103, The material used for the first conductive layer 10103 is Mo, Ti, Al, , Nd, Cr, etc. are preferable. Alternatively, Mo, Ti, Al, Nd, Cr, etc. It may also have a laminated structure in which two or more layers are combined.

[0381] Next, a second insulating film 10104 is formed. At this time, the second insulating film 10104 is formed by a sputtering method. The second insulating film may be formed using a film forming apparatus such as a CVD apparatus. The material used for the film 10104 is a thermal oxide film, a silicon oxide film, a silicon nitride film or an oxide film. Silicon nitride film is preferable. Alternatively, a thermal oxide film, a silicon oxide film, or a silicon nitride film is preferable. It may also be a laminated structure combining two or more of a silicon oxide nitride film or a silicon oxynitride film. The second insulating film 10104 in contact with the first semiconductor layer 10105 is made of silicon oxide. It is particularly preferable that the semiconductor layer 10 is a silicon oxide film. This is because the trap level at the interface with the first conductive layer 105 is reduced. When the first conductive layer 101 is made of Mo, the second insulating film 101 in contact with the first conductive layer 101 is The silicon nitride film is preferable because the silicon nitride film does not oxidize Mo. Because it is.

[0382] Next, a first semiconductor layer 10105 is formed. Then, a second semiconductor layer 10106 is formed. It is preferable to form the first semiconductor layer 10105 and the second semiconductor layer 10106. The shape of the 0106 may be processed. It is preferable to use a method such as a lithography method. The material is preferably silicon or silicon germanium (SiGe). The material used for the second semiconductor layer 10106 is preferably silicon containing phosphorus or the like. .

[0383] Next, the second conductive layer 10107 is formed. At this time, the method of forming the second conductive layer 10107 is as follows. As a method, a sputtering method or a printing method is preferably used. The material used for 107 may be transparent or reflective. In the case of a compound, for example, indium tin oxide (ITO) is a compound in which indium oxide is mixed with tin oxide. O) film, indium tin oxide (ITO) mixed with silicon oxide (ITSO) film, indium zinc oxide (IZO) film, which is a mixture of indium oxide and zinc oxide In addition, IZO is a film obtained by adding 2 to 10% of ITO to the film. Sputtering was performed using a target containing 20 wt% zinc oxide (ZnO). On the other hand, when it has reflectivity, Ti, Mo, Ta, Cr , W, Al, etc. can be used. Also, Ti, Mo, Ta, Cr, W and Al can be stacked. a two-layer structure with Al sandwiched between metals such as Ti, Mo, Ta, Cr, and W; and a three-layer structure with Al sandwiched between metals such as Ti, Mo, Ta, Cr, and W. The second conductive layer 10107 may be formed by processing the shape. The method for processing the film is preferably the above-mentioned photolithography method. The etching method is preferably dry etching. ECR (Electron Cyclotron Resonance) and ICP (In Driving with high density plasma sources such as Inductive Coupled Plasma This may be done by an etching apparatus.

[0384] Next, the channel region of the TFT is formed. At this time, the second semiconductor layer 10106 is etched. The second conductive layer 10107 may be used as a mask for etching, or the second conductive layer A mask (resist) may be used to etch the layer 10107. This reduces the number of masks required, thereby reducing manufacturing costs. By etching the second semiconductor layer 10106, the removed portion becomes a TFT. The first semiconductor layer 10105 and the second semiconductor layer 10106 are formed as a channel region. It is not formed continuously, but after the formation of the first semiconductor layer 10105, a layer that will become the channel region of the TFT is formed. A film that will serve as a stopper is formed and patterned in the area where the second semiconductor layer 10 is to be formed. The first semiconductor layer 10105 and the second semiconductor layer 10106 may be formed. The second conductive layer 10107 is processed into a shape by the above-mentioned photolithography method or the like. The second conductive layer 1010 is then etched using the same mask. Since the channel region of the TFT can be formed without using the layer 7 as a mask, The advantage is that the degree of freedom in the out pattern is increased. During etching, the first semiconductor layer 10105 is not etched. This has the advantage that the channel region of the TFT can be formed reliably without causing defects.

[0385] Next, a third insulating film 10108 is formed. The third insulating film is required to be transparent. It is preferable that the material used for the third insulating film 10108 is an inorganic material (silicon oxide, Silicon nitride, silicon oxynitride, etc.) or low dielectric constant organic compound material (photosensitive or Non-photosensitive organic resin materials are suitable. Materials containing siloxane may also be used. Siloxane is a material whose skeletal structure is made up of bonds between silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) Alternatively, a fluoro group may be used as a substituent. As the group, an organic group containing at least hydrogen and a fluoro group may be used. Contact holes are selectively formed in the insulating film 10108 by etching. The contact hole is formed at least on the second conductive layer 10107. When the third insulating film 10108 is etched, the second insulating film 10104 is also etched. By doing so, not only the second conductive layer 10107 but also the contact with the first conductive layer 10103 can be formed. The surface of the third insulating film 10108 is preferably The reason is that the surface that the liquid crystal contacts is uneven, which can cause the liquid crystal molecules to move. This is because the orientation is affected.

[0386] Next, a third conductive layer 10109 is formed. At this time, the method of forming the third conductive layer 10109 is as follows. As a method, a sputtering method or a printing method is preferably used. The material used for the second conductive layer 109 may be transparent or reflective, similar to the second conductive layer 10107. The material that can be used for the third conductive layer 10109 is the same as that of the second conductive layer 10109. The third conductive layer 10109 may be the same as the first conductive layer 10107. The method for processing the shape may be the same as that for the second conductive layer 10107.

[0387] Next, a first alignment film 10110 is formed. The alignment film 10110 is made of a high-molecular-weight material such as polyimide. After the first alignment film 10110 is formed, the alignment of the liquid crystal molecules is Rubbing may be performed to control the alignment film. Therefore, this is the process of making lines on the alignment film. It can be made directional.

[0388] The first substrate 10101 prepared as above, the light-shielding film 10114, and the color filter 10 115, the fourth conductive layer 10113, the spacer 10117 and the second alignment film 10112. The second substrate 10116 is attached with a sealant with a gap of several μm. Then, by injecting liquid crystal material between the two substrates, a liquid crystal panel can be created. In the TN liquid crystal panel shown in FIG. 13 may be fabricated on the entire surface of the second substrate 10116.

[0389] Next, we will explain the characteristics of the pixel structure of a TN liquid crystal panel shown in Figure 46. The liquid crystal molecule 10118 shown in (A) is a long and thin molecule with a long axis and a short axis. In order to indicate the direction of the child 10118, in FIG. 46(A), it is expressed by its length. That is, the long axis of the liquid crystal molecule 10118 is parallel to the paper surface. The shorter the liquid crystal molecule, the closer its long axis is to the normal direction of the paper. In other words, the liquid crystal molecules 10118 shown in FIG. The direction of the long axis of the substrate near the first substrate 10101 is 9°. The liquid crystal molecules 10118 positioned between these two have a long axis direction that is different from these two. That is, the liquid crystal molecule 101 shown in FIG. 18 is twisted 90 degrees between the first substrate 10101 and the second substrate 10116. The alignment state is as follows.

[0390] Next, referring to FIG. 46(B), when this embodiment is applied to a TN-type liquid crystal display device, An example of the pixel layout in this case will be described. The pixels of the liquid crystal display device are connected to a scanning line 10121, a video signal line 10122, and a capacitance line 10123. , a TFT 10124, a pixel electrode 10125, and a pixel capacitor 10126. Good too.

[0391] The scanning line 10121 is electrically connected to the gate electrode of the TFT 10124. It is preferably made up of a conductive layer 10103 .

[0392] The video signal line 10122 is electrically connected to the source electrode or the drain electrode of the TFT 10124. In order to connect the scanning line, it is preferable that the scanning line is made of the second conductive layer 10107. The lines 10121 and the video signal lines 10122 are arranged in a matrix, so at least It is preferably formed of different conductive layers.

[0393] The capacitance line 10123 is arranged in parallel with the pixel electrode 10125, so that the pixel capacitance 1012 6, and is preferably made of the first conductive layer 10103. As shown in FIG. 46(B), the capacitance line 10123 is connected to the video signal line 10122. The image signal line 10122 may be extended along the same line so as to surround the image signal line 10122. As the potential of the image signal line 10122 changes, the potential of the electrode that should maintain the potential also changes. This can reduce the phenomenon known as crosstalk. In order to reduce the cross capacitance of the first semiconductor layer 10105, as shown in FIG. 46(B), may be provided in the crossing area of ​​the capacitance line 10123 and the video signal line 10122.

[0394] The TFT 10124 is a switch that connects the video signal line 10122 and the pixel electrode 10125. As shown in FIG. 46(B), the source region of the TFT10124 The source region or the drain region is surrounded by a gate insulating film. This allows a large channel width to be obtained in a small area, As shown in FIG. 46(B), the switching ability can be increased. The gate electrode 10124 may be arranged to surround the first semiconductor layer 10105 .

[0395] The pixel electrode 10125 is electrically connected to either the source electrode or the drain electrode of the TFT 10124. The pixel electrode 10125 is electrically connected to the image signal line 10122. This is an electrode for applying voltage to the liquid crystal element. Also, by placing the capacitance line 10123, A pixel capacitor 10126 may be formed. In this way, the pixel electrode 10125 receives the video signal. The signal voltage transmitted by the signal line 10122 can be easily maintained. 25 may be rectangular as shown in FIG. 46(B). Since the aperture ratio can be increased, the efficiency of the liquid crystal display device is improved. When the OLED is made of a transparent material, a transmission type liquid crystal display device can be obtained. Transmissive LCD devices have high color reproducibility and can display high-quality images. In addition, when the pixel electrode 10125 is made of a reflective material, a reflective type A reflective liquid crystal display device can be obtained in a bright environment such as outdoors. High visibility in the dark and no backlight is required, so power consumption is extremely low. The pixel electrode 10125 can be made of a transparent material and a reflective material. When both of the above are used, a semi-transmissive liquid crystal display device having the advantages of both can be obtained. If the pixel electrode 10125 is made of a reflective material, The surface of the electrode 10125 may be uneven. By making the surface uneven, the pixel electrode 10125 can also be made uneven. This has the advantage that the reflected light is diffused, reducing the angle dependency of the intensity distribution of the reflected light. In other words, it is possible to obtain a reflective liquid crystal display device that has a constant brightness regardless of the viewing angle. can.

[0396] Next, referring to Figure 47, the liquid crystal display in VA (Vertical Alignment) mode A case where this embodiment is applied to a display device will be described. Figure 47 shows a liquid crystal display in VA mode. The pixel structure of the device uses protrusions for alignment control, allowing the liquid crystal molecules to have various orientations. This is what is called MVA (Multi-domain Verification) which controls the image in a way that widens the viewing angle. 4 shows a cross section of a pixel when this embodiment is applied to a holographic alignment method. 47A is a cross-sectional view of the pixel, and FIG. 47B is a top view of the pixel. The cross-sectional view of the pixel shown in (A) of FIG. This corresponds to the line a-a' in the top view of the liquid crystal display device having the pixel structure shown in FIG. By applying this embodiment, a wide viewing angle, a fast response speed, and high contrast can be achieved. Therefore, a liquid crystal display device with a large display area can be obtained.

[0397] The pixel structure of an MVA liquid crystal display device will be described with reference to Fig. 47(A). A liquid crystal display device has a key component called a liquid crystal panel that displays images. Two processed substrates are bonded together with a gap of several micrometers. In Figure 47(A), the liquid crystal material is injected between two substrates. The plates are a first substrate 10201 and a second substrate 10216. The first substrate has a TF The second substrate is provided with a light-shielding film 10214 and a color filter 102. 15, a fourth conductive layer 10213, a spacer 10217, a second alignment film 10212, and An alignment control protrusion 10219 may be fabricated.

[0398] It should be noted that this embodiment can be implemented without fabricating TFTs on the first substrate 10201. When this embodiment is carried out without fabricating a TFT, the number of steps is reduced, and the manufacturing cost is reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when the present embodiment is implemented by fabricating a TFT, a larger display device can be manufactured. can be obtained.

[0399] The TFT shown in FIG. 47 is a bottom gate type TFT using an amorphous semiconductor. Liquid crystal panels that use TFTs that use crystalline semiconductors can be produced inexpensively using large-area substrates. However, the present embodiment is not limited to this. The TFT structures that can be achieved are channel etch type and channel protection type for bottom gate type TFTs. In addition, a top gate type is also possible. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors are also available. Crystalline semiconductors can also be used.

[0400] This embodiment can be carried out without forming the light-shielding film 10214 on the second substrate 10216. If this embodiment is carried out without forming the light-shielding film 10214, the number of steps can be reduced. Since the number of components is small, the manufacturing cost can be reduced. On the other hand, when the light-shielding film 10214 is fabricated and the present embodiment is carried out, In this case, a display device with little light leakage during black display can be obtained.

[0401] In this embodiment, the color filter 10215 is not formed on the second substrate 10216. In the case where this embodiment is implemented without fabricating the color filter 10215, In this case, the number of steps is reduced, which reduces the manufacturing cost. However, since the color filter 10215 is made Even if this embodiment is implemented without manufacturing a color LCD panel, the color LCD panel can be driven by field sequential driving. On the other hand, a display device capable of displaying a color image can be obtained by fabricating a color filter 10215. When this embodiment is implemented in this manner, a display device capable of color display can be obtained.

[0402] In this embodiment, the spacers 10217 are not formed on the second substrate 10216, and the spherical This can also be achieved by scattering spacers. When the embodiment is implemented, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, the structure is simple, which can improve the yield. When the present embodiment is carried out by manufacturing 17, the position of the spacer does not vary, so 2 The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained. do.

[0403] Next, the first substrate 10201 may be processed using the method described in FIG. Here, the first substrate 10201, the first insulating film 10202, the first conductive film 10203, and the first insulating film 10204 are an insulating layer 10203, a second insulating film 10204, a first semiconductor layer 10205, and a second semiconductor layer 10206, a second conductive layer 10207, a third insulating film 10208, and a third conductive layer 1020 9 and the first alignment film 10210 correspond to the first substrate 10101 and the first The insulating film 10102, the first conductive layer 10103, the second insulating film 10104, the first semiconductor layer 10105, a second semiconductor layer 10106, a second conductive layer 10107, a third insulating film 10 108, a third conductive layer 10109, and a first alignment film 10110. Although it is not necessary to provide the alignment control protrusions on the first substrate side, this will provide a more reliable alignment control. The alignment of the liquid crystal molecules can be controlled. The alignment film 10212 may be a vertical alignment film. It can be oriented directly.

[0404] The first substrate 10201, the light-shielding film 10214, and the color filter 10202 are then combined. 215, a fourth conductive layer 10213, a spacer 10217, and a second alignment film 10212 The second substrate 10216 on which the above-mentioned was made was placed on the substrate 10216 with a gap of several micrometers by a sealing material. A liquid crystal panel can be made by holding the two substrates together and injecting liquid crystal material between them. In the MVA liquid crystal panel shown in FIG. The fourth conductive layer 10 may be formed on the entire surface of the second substrate 10216. The alignment control protrusion 10219 may be formed in contact with the alignment control protrusion 10213. There is no limitation on the shape of the 0219, but a shape with a smooth curved surface is preferable. By doing so, the alignment of the adjacent liquid crystal molecules 10218 becomes extremely close, and therefore alignment defects are reduced. In addition, the second alignment film 10212 is prevented from being broken by the alignment control protrusions 10219. This also reduces defects in the alignment film caused by the above-mentioned phenomenon.

[0405] Next, we will explain the characteristics of the pixel structure of the MVA liquid crystal panel shown in Figure 47. The liquid crystal molecule 10218 shown in (A) of 7 is a long and thin molecule with a long axis and a short axis. To indicate the orientation of the molecule 10218, in FIG. 47(A), it is expressed by its length. That is, the long axis of the liquid crystal molecule 10218 is parallel to the paper surface. The shorter the liquid crystal molecule 10218, the closer its long axis is to the normal direction of the paper. In other words, the liquid crystal molecule 10218 shown in FIG. Therefore, the orientation of the alignment control protrusion 1021 is aligned in the normal direction of the alignment film. The liquid crystal molecules 10218 in the part with 9 are arranged radially around the protrusion 10219 for alignment control. By achieving this state, a liquid crystal display device with a wide viewing angle can be obtained. do.

[0406] Next, referring to FIG. 47(B), the present embodiment is applied to an MVA type liquid crystal display device. An example of a pixel layout in this case will be described. The pixel of the liquid crystal display device is connected to a scanning line 10221, a video signal line 10222, and a capacitance line 102 23, a TFT 10224, a pixel electrode 10225, a pixel capacitor 10226, and an alignment control and a projection 10219 for supporting the insertion hole.

[0407] The scanning line 10221 is electrically connected to the gate electrode of the TFT 10224. It is preferably made up of a conductive layer 10203 .

[0408] The video signal line 10222 is electrically connected to the source electrode or the drain electrode of the TFT 10224. In order to connect the scanning line, it is preferable that the scanning line is made of the second conductive layer 10207. The lines 10221 and the video signal lines 10222 are arranged in a matrix, so at least It is preferably formed of different conductive layers.

[0409] The capacitance line 10223 is arranged in parallel with the pixel electrode 10225, so that the pixel capacitance 1022 6, and is preferably made of the first conductive layer 10203. As shown in FIG. 47(B), the capacitance line 10223 is connected to the video signal line 10222. The wiring may be extended along the video signal line 10222 so as to surround the video signal line 10222. As the potential of the image signal line 10222 changes, the potential of the electrode that should maintain the potential also changes. This can reduce the phenomenon known as crosstalk. In order to reduce the cross capacitance of the first semiconductor layer 10205, as shown in FIG. 47(B), may be provided in the crossing area of ​​the capacitance line 10223 and the video signal line 10222.

[0410] The TFT 10224 is a switch that connects the video signal line 10222 and the pixel electrode 10225. As shown in FIG. 47(B), the source region of the TFT10224 The source region or the drain region is surrounded by a gate insulating film. This allows a large channel width to be obtained in a small area, As shown in FIG. 47(B), the switching ability can be increased. The gate electrode 10224 may be disposed so as to surround the first semiconductor layer 10205 .

[0411] The pixel electrode 10225 is electrically connected to either the source electrode or the drain electrode of the TFT 10224. The pixel electrode 10225 is electrically connected to the image signal line 10222. This is an electrode for applying voltage to the liquid crystal element. Also, by placing the capacitance line 10223, A pixel capacitor 10226 may be formed. In this way, the pixel electrode 10225 receives the video signal. The signal voltage transmitted by the signal line 10222 can be easily maintained. 25 may be rectangular as shown in FIG. 47(B). Since the aperture ratio can be increased, the efficiency of the liquid crystal display device is improved. When the 0225 is made of a transparent material, a transmission type liquid crystal display device can be obtained. Transmissive LCD devices have high color reproducibility and can display high-quality images. In addition, when the pixel electrode 10225 is made of a reflective material, a reflective type A reflective liquid crystal display device can be obtained in a bright environment such as outdoors. High visibility in the dark and no backlight is required, so power consumption is extremely low. The pixel electrode 10225 can be made of a transparent material and a reflective material. When both of the above are used, a semi-transmissive liquid crystal display device having the advantages of both can be obtained. If the pixel electrode 10225 is made of a reflective material, The surface of the electrode 10225 may be uneven. By making the surface uneven, the pixel electrode 10225 can also be made uneven. This has the advantage that the reflected light is diffused, reducing the angle dependency of the intensity distribution of the reflected light. In other words, it is possible to obtain a reflective liquid crystal display device that has a constant brightness regardless of the viewing angle. can.

[0412] Next, referring to Figure 48, the liquid crystal display in VA (Vertical Alignment) mode Another example of a display device to which this embodiment is applied will be described. In the pixel structure of the liquid crystal display device, the fourth conductive layer 10313 is patterned. , the liquid crystal molecules are controlled to have various orientations, widening the viewing angle, so-called PVA (P This embodiment is applied to the Alternated Vertical Alignment (ALA) method. 48A and 48B are a cross-sectional view and a top view of a pixel when the pixel is in the state shown in FIG. 48(B) is a top view of the pixel. Also, the cross-sectional view of the pixel shown in FIG. This corresponds to the line a-a' in the top view of the pixel shown in FIG. By applying this embodiment to a liquid crystal display device having a basic structure, a wide viewing angle and a high response speed can be achieved. A liquid crystal display device with high contrast and fast response can be obtained.

[0413] The pixel structure of a PVA liquid crystal display device will be described with reference to Fig. 48(A). A liquid crystal display device has a key component called a liquid crystal panel that displays images. Two processed substrates are bonded together with a gap of several micrometers. It is made by injecting a liquid crystal material between two substrates. The plates are a first substrate 10301 and a second substrate 10316. The first substrate has a T FT and pixel electrodes are fabricated, and a light-shielding film 10314, a color filter, and a reflective film are fabricated on the second substrate. The second alignment film 10315, the fourth conductive layer 10313, the spacer 10317, and the second alignment film 10318 are arranged in a row. 312 may be made.

[0414] It should be noted that this embodiment can be implemented without fabricating a TFT on the first substrate 10301. When this embodiment is carried out without fabricating a TFT, the number of steps is reduced, and the manufacturing cost is reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when the present embodiment is implemented by fabricating a TFT, a larger display device can be manufactured. can be obtained.

[0415] The TFT shown in FIG. 48 is a bottom gate type TFT using an amorphous semiconductor. Liquid crystal panels that use TFTs that use crystalline semiconductors can be produced inexpensively using large-area substrates. However, the present embodiment is not limited to this. The TFT structures that can be achieved are channel etch type and channel protection type for bottom gate type TFTs. In addition, a top gate type is also possible. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors are also available. Crystalline semiconductors can also be used.

[0416] This embodiment can be carried out without forming the light-shielding film 10314 on the second substrate 10316. It is possible. When this embodiment is carried out without forming the light-shielding film 10314, the number of steps is reduced. Since the number of components is small, the manufacturing cost can be reduced. On the other hand, when the light-shielding film 10314 is fabricated and the present embodiment is carried out, In this case, a display device with little light leakage during black display can be obtained.

[0417] In this embodiment, the color filter 10315 is not formed on the second substrate 10316. In the case where this embodiment is carried out without fabricating the color filter 10315, In this case, the number of steps is reduced, which reduces the manufacturing cost. However, since the color filter 10315 is made Even if this embodiment is implemented without manufacturing a color LCD panel, the color LCD panel can be driven by field sequential driving. On the other hand, a display device capable of displaying a color image can be obtained by fabricating a color filter 10315. When this embodiment is implemented in this manner, a display device capable of color display can be obtained.

[0418] In this embodiment, the spacer 10317 is not formed on the second substrate 10316, and a spherical This can also be achieved by scattering spacers. When the embodiment is implemented, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, the structure is simple, which can improve the yield. When the present embodiment is carried out by manufacturing 17, the position of the spacer does not vary, so 2 The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained. do.

[0419] Next, the first substrate 10301 may be processed using the method described in FIG. Here, the first substrate 10301, the first insulating film 10302, the first conductive film 10303, and the first insulating film 10304 are an insulating layer 10303, a second insulating film 10304, a first semiconductor layer 10305, and a second semiconductor layer 10306, a second conductive layer 10307, ​​a third insulating film 10308, and a third conductive layer 1030 9 and the first alignment film 10310 correspond to the first substrate 10101 and the first The insulating film 10102, the first conductive layer 10103, the second insulating film 10104, the first semiconductor layer 10105, a second semiconductor layer 10106, a second conductive layer 10107, a third insulating film 10 108, the third conductive layer 10109, and the first alignment film 10110. An electrode cutout may be provided in the third conductive layer 10309 on the substrate 10301 side. By doing so, the alignment of the liquid crystal molecules can be controlled more reliably. The second alignment film 10312 and the second alignment film 310 may be vertical alignment films. The child 10318 can be oriented vertically.

[0420] The first substrate 10301, the light-shielding film 10314, and the color filter 10302 are then combined. 315, a fourth conductive layer 10313, a spacer 10317, and a second alignment film 10312 The second substrate 10316 on which the above-mentioned was made was attached with a sealant with a gap of several μm. A liquid crystal panel can be fabricated by combining the two substrates and injecting liquid crystal material between them. In the PVA type liquid crystal panel shown in FIG. 48, the fourth conductive layer 10313 is The electrode cutout 10319 may be formed by applying a cutting process. There is no limit to the shape of 10319, but it is a shape that combines multiple rectangles with different orientations. This allows multiple regions of different orientation to be formed, improving visibility. A liquid crystal display device with large corners can be obtained. The shape of the fourth conductive layer 10313 at the boundary of the conductive layer 10313 is a smooth curve. By doing so, the alignment of the adjacent liquid crystal molecules 10318 is very close. Therefore, the alignment defect is reduced. 319 can also reduce defects in the alignment film caused by step disconnection. do.

[0421] Next, we will explain the characteristics of the pixel structure of the PVA liquid crystal panel shown in Figure 48. The liquid crystal molecule 10318 shown in (A) of 8 is a long and thin molecule with a long axis and a short axis. To show the orientation of the molecule 10318, in Figure 48(A) it is expressed by its length. That is, the long axis of the liquid crystal molecule 10318 is parallel to the paper surface. The shorter the liquid crystal molecule 10318, the closer its long axis is to the normal direction of the paper. In other words, the liquid crystal molecule 10318 shown in FIG. The direction of the electrode cutout portion 1031 is aligned in the normal direction of the alignment film. The liquid crystal molecules 10318 in the part where the electrode cutout 10319 is located are in contact with the fourth conductive layer 103. The liquid crystal molecules are oriented radially around the boundary of 13. This state increases the viewing angle. Therefore, a liquid crystal display device can be obtained.

[0422] Next, referring to FIG. 48(B), the present embodiment is applied to a PVA type liquid crystal display device. An example of a pixel layout in this case will be described. The pixel of the liquid crystal display device is connected to a scanning line 10321, a video signal line 10322, and a capacitance line 103 23, a TFT 10324, a pixel electrode 10325, a pixel capacitor 10326, and an electrode cutout A notch 10319 may be provided.

[0423] The scanning line 10321 is electrically connected to the gate electrode of the TFT 10324. It is preferably made up of a conductive layer 10303 .

[0424] The video signal line 10322 is electrically connected to the source electrode or the drain electrode of the TFT 10324. In order to connect the scanning line, it is preferable that the scanning line is made of the second conductive layer 10307. The lines 10321 and the video signal lines 10322 are arranged in a matrix, so at least It is preferably formed of different conductive layers.

[0425] The capacitance line 10323 is arranged in parallel with the pixel electrode 10325, so that the pixel capacitance 1032 6, and is preferably made of the first conductive layer 10303. As shown in FIG. 48(B), the capacitance line 10323 is connected to the video signal line 10322. The image signal line 10322 may be extended along the same line so as to surround the image signal line 10322. As the potential of the image signal line 10322 changes, the potential of the electrode that should maintain the potential also changes. This can reduce the phenomenon known as crosstalk. In order to reduce the cross capacitance of the first semiconductor layer 10305, as shown in FIG. 48(B), may be provided in the intersecting region of the capacitance line 10323 and the video signal line 10322.

[0426] The TFT 10324 is a switch that connects the video signal line 10322 and the pixel electrode 10325. As shown in FIG. 48(B), the source region of the TFT10324 The source region or the drain region is surrounded by a gate insulating film. This allows a large channel width to be obtained in a small area, As shown in FIG. 48(B), the switching ability can be increased. The gate electrode 10324 may be disposed to surround the first semiconductor layer 10305 .

[0427] The pixel electrode 10325 is electrically connected to either the source electrode or the drain electrode of the TFT 10324. The pixel electrode 10325 is electrically connected to the image signal line 10322. This is an electrode for applying voltage to the liquid crystal element. Also, by placing the capacitance line 10323, A pixel capacitor 10326 may be formed. In this way, the pixel electrode 10325 receives the video signal. The signal voltage transmitted by the signal line 10322 can be easily maintained. 25 is an electrode notch provided in the fourth conductive layer 10313 as shown in FIG. 48(B). The pixel electrode 103 is formed in the area where there is no electrode cutout 10319, in accordance with the shape of the electrode cutout 10319. It is preferable to form a cutout portion 25. By doing so, the liquid crystal molecules 10318 Since it is possible to form a plurality of regions with different orientations, a liquid crystal display device with a wide viewing angle can be manufactured. Furthermore, when the pixel electrode 10325 is made of a transparent material, A transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility. In addition, the pixel electrode 10325 can be made reflective. When the liquid crystal display device is made of a material having the above property, a reflective liquid crystal display device can be obtained. The display device has high visibility in bright environments such as outdoors and does not require a backlight. Therefore, the power consumption can be reduced significantly. When made using both a material with a transparent property and a material with a reflective property, the advantages of both can be combined. A semi-transmissive liquid crystal display device having the pixel electrode 10325 can be obtained. If the pixel electrode 10325 is made of a material having a certain property, the surface of the pixel electrode 10325 may have an uneven surface. Alternatively, the pixel electrode 10325 may be formed by providing an uneven surface to the third insulating film 10308. It can also be made uneven. This causes the reflected light to be scattered, resulting in an intensity distribution of the reflected light. This has the advantage that the angle dependency of the light is small. In other words, the light has a constant brightness regardless of the angle from which it is viewed. A reflective liquid crystal display device can be obtained.

[0428] Next, referring to FIG. 49, a case where this embodiment is applied to a liquid crystal display device of the IPS panel type will be described. Figure 49 shows a switching method in which the alignment of liquid crystal molecules is always horizontal to the substrate. In order to do this, the pixel electrode is used in the pixel structure of a liquid crystal display device that applies an electric field in the horizontal direction. By applying a comb-like pattern to the common electrode 10425 and the common electrode 10423, the electric field is distributed horizontally. This implementation is based on the so-called IPS (In-Plane-Switching) method. 49A and 49B are a cross-sectional view and a top view of a pixel when the above-mentioned configuration is applied. 49(A) and 49(B) are top views of the pixel. The cross-sectional view corresponds to the line a-a' in the top view of the pixel shown in FIG. By applying this embodiment to a liquid crystal display device having the pixel structure shown in FIG. A liquid crystal display device having a large field angle and small grayscale dependency of response speed can be obtained.

[0429] The pixel structure of an IPS liquid crystal display device will be described with reference to Fig. 49(A). A liquid crystal display device has a key component called a liquid crystal panel that displays images. Two processed substrates are bonded together with a gap of several μm between them. In Figure 49(A), the two substrates are the first The first substrate has a TFT and a pixel. The element electrodes are fabricated, and the second substrate is provided with a light-shielding film 10414 and a color filter 10415. , spacers 10417, and a second alignment film 10412 may be fabricated.

[0430] It should be noted that this embodiment can be implemented without fabricating a TFT on the first substrate 10401. When this embodiment is carried out without fabricating a TFT, the number of steps is reduced, and the manufacturing cost is reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when the present embodiment is implemented by fabricating a TFT, a larger display device can be manufactured. can be obtained.

[0431] The TFT shown in FIG. 49 is a bottom gate type TFT using an amorphous semiconductor. Liquid crystal panels that use TFTs that use crystalline semiconductors can be produced inexpensively using large-area substrates. However, the present embodiment is not limited to this. The TFT structures that can be achieved are channel etch type and channel protection type for bottom gate type TFTs. In addition, a top gate type is also possible. Furthermore, not only amorphous semiconductors but also polycrystalline semiconductors are also available. Crystalline semiconductors can also be used.

[0432] This embodiment can be carried out without forming the light-shielding film 10414 on the second substrate 10416. It is possible. When this embodiment is carried out without forming the light-shielding film 10414, the number of steps is reduced. Since the number of components is small, the manufacturing cost can be reduced. On the other hand, when the light-shielding film 10414 is fabricated and the present embodiment is carried out, In this case, a display device with little light leakage during black display can be obtained.

[0433] In this embodiment, the color filter 10415 is not formed on the second substrate 10416. In the case where this embodiment is implemented without fabricating the color filter 10415, In this case, the number of steps is reduced, which reduces the manufacturing cost. Even when this embodiment is implemented without fabricating the filter 10415, the field sequence A display device capable of color display can be obtained by driving the LEDs. Therefore, the yield can be improved. When this embodiment is implemented in this manner, a display device capable of color display can be obtained.

[0434] In this embodiment, the spacer 10417 is not formed on the second substrate 10416, and a spherical This can also be achieved by scattering spacers. When the embodiment is implemented, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, the structure is simple, which can improve the yield. When the present embodiment is carried out by manufacturing 17, the position of the spacer does not vary, so 2 The distance between the substrates can be made uniform, and a display device with less display unevenness can be obtained. do.

[0435] Next, the first substrate 10401 may be processed using the method described in FIG. Here, the first substrate 10401, the first insulating film 10402, the first conductive film 10403, and the first insulating film 10404 are an insulating layer 10403, a second insulating film 10404, a first semiconductor layer 10405, and a second semiconductor layer 10406, a second conductive layer 10407, a third insulating film 10408, and a third conductive layer 1040 9 and the first alignment film 10410 correspond to the first substrate 10101 and the first The insulating film 10102, the first conductive layer 10103, the second insulating film 10104, the first semiconductor layer 10105, a second semiconductor layer 10106, a second conductive layer 10107, a third insulating film 10 108, the third conductive layer 10109, and the first alignment film 10110. The third conductive layer 10409 on the substrate 10401 side is patterned to form two interlocking Alternatively, one of the comb-shaped electrodes may be formed in a comb-like shape. The comb-shaped electrode is electrically connected to either the source electrode or the drain electrode, and the other comb-shaped electrode is a common electrode. The liquid crystal molecules 10418 may be electrically connected to the electrode 10423. This allows a lateral electric field to be applied effectively to the

[0436] The first substrate 10401, the light-shielding film 10414, and the color filter 10402 are then combined. 415, a spacer 10417, and a second alignment film 10412 are formed on the second substrate 10. 416 are bonded together with a sealant, leaving a gap of several micrometers. A liquid crystal panel can be fabricated by injecting a liquid crystal material between the substrates. A conductive layer may be formed on the second substrate 10416 side. By forming the above, it is possible to make the device less susceptible to the influence of external electromagnetic noise.

[0437] Next, we will explain the characteristics of the pixel structure of an IPS-type liquid crystal panel shown in Figure 49. The liquid crystal molecule 10418 shown in (A) of 9 is a long and thin molecule with a long axis and a short axis. To indicate the orientation of the molecule 10418, in FIG. 49(A), it is expressed by its length. That is, the long axis of the liquid crystal molecule 10418 is parallel to the paper surface. The shorter the liquid crystal molecule 10418, the closer its long axis is to the normal direction of the paper. In other words, the liquid crystal molecule 10418 shown in FIG. In FIG. 49(A), This shows the orientation in the absence of an electric field, but when an electric field is applied to the liquid crystal molecules 10418, The long axis of the crystal rotates in a horizontal plane while always maintaining a direction parallel to the substrate. By adopting this state, a liquid crystal display device with a wide viewing angle can be obtained.

[0438] Next, referring to FIG. 49(B), the present embodiment is applied to an IPS liquid crystal display dev...

Claims

1. A semiconductor device comprising first to seventh transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to an output signal line; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is electrically connected to the output signal line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a power supply line; one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate of the second transistor; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the power supply line; a gate electrode of the third transistor is electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a first gate signal line; a gate electrode of the fourth transistor is electrically connected to the first gate signal line; one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the power supply line; a gate electrode of the fifth transistor is electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the power supply line; a gate electrode of the sixth transistor is electrically connected to a second gate signal line; one of a source electrode and a drain electrode of the seventh transistor is electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the power supply line; a gate electrode of the seventh transistor is electrically connected to the first gate signal line; the first conductive layer having a region functioning as the other of the source electrode or the drain electrode of the second transistor includes a region functioning as the other of the source electrode or the drain electrode of the third transistor, a region functioning as the other of the source electrode or the drain electrode of the fifth transistor, a region functioning as the other of the source electrode or the drain electrode of the sixth transistor, and a region functioning as the other of the source electrode or the drain electrode of the seventh transistor; The second conductive layer having a region functioning as a gate electrode of the second transistor has a region functioning as a gate electrode of the fifth transistor.

2. A semiconductor device comprising first to seventh transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to an output signal line; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is electrically connected to the output signal line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a power supply line; one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate of the second transistor; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the power supply line; a gate electrode of the third transistor is electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a first gate signal line; a gate electrode of the fourth transistor is electrically connected to the first gate signal line; one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the power supply line; a gate electrode of the fifth transistor is electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the power supply line; a gate electrode of the sixth transistor is electrically connected to a second gate signal line; one of a source electrode and a drain electrode of the seventh transistor is electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the power supply line; a gate electrode of the seventh transistor is electrically connected to the first gate signal line; the first conductive layer having a region functioning as the other of the source electrode or the drain electrode of the second transistor includes a region functioning as the other of the source electrode or the drain electrode of the third transistor, a region functioning as the other of the source electrode or the drain electrode of the fifth transistor, a region functioning as the other of the source electrode or the drain electrode of the sixth transistor, and a region functioning as the other of the source electrode or the drain electrode of the seventh transistor; a second conductive layer having a region functioning as a gate electrode of the second transistor has a region functioning as a gate electrode of the fifth transistor; a third conductive layer having a region functioning as one of a source electrode or a drain electrode of the first transistor is electrically connected to a fourth conductive layer in the same layer as the second conductive layer; The fourth conductive layer has a region that functions as the output signal line.

Images