Power Converter
By strategically arranging support posts within the power converter to overlap with flat plate terminals but not with the semiconductor chip, the design mitigates thermal deformation and associated damage to the heat pipe, ensuring efficient cooling for the semiconductor chip.
Patent Information
- Application Number
- JP2021090454
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2021-05-28
- Publication Date
- 2025-05-07
- Estimated Expiration
- 2041-05-28
AI Technical Summary
In power converters using flat heat pipes for cooling semiconductor chips and flat plate terminals, thermal deformation of the cooling plate at the edge can lead to damage of the heat pipe due to heat generated by the flat plate terminals.
The power converter design includes a flat heat pipe with support posts arranged to overlap with the flat plate terminals and adjacent areas, but not with the semiconductor chip, to suppress thermal deformation of the cooling plate and reduce damage to the heat pipe.
This arrangement effectively reduces the damage caused by thermal deformation of the cooling plate near the flat plate terminals, while maintaining the cooling efficiency for the semiconductor chip.
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Abstract
Description
[Technical field]
[0001] The technology disclosed in this specification relates to a power converter including a semiconductor chip for power conversion and a heat pipe for cooling the semiconductor chip. [Background technology]
[0002] Semiconductor chips for power conversion generate a large amount of heat. A power converter using a heat pipe to cool the semiconductor chip for power conversion is known (for example, Patent Document 1). The power converter of Patent Document 1 uses a flat heat pipe. The flat heat pipe is sometimes called a vapor chamber.
[0003] The flat heat pipe has a cooling plate on which a semiconductor chip is attached and a case joined to the back surface of the cooling plate, and a working fluid and a wick are sealed in the case. In the flat heat pipe, the length of the cooling plate in the normal direction is shorter than the length in the direction intersecting the normal direction. That is, the cooling plate corresponds to the wide surface of the flat shape. When the temperature of the semiconductor chip rises, the wide cooling plate may be thermally deformed. In order to suppress the thermal deformation of the cooling plate, a support that connects the bottom plate of the case and the cooling plate is provided inside the case. In the power converter of Patent Document 1, the support is arranged so that it does not overlap with the semiconductor chip when the cooling plate is viewed in a plane. If the support is arranged so that it overlaps with the semiconductor chip when the cooling plate is viewed in a plane, the support may reduce the cooling efficiency for the semiconductor chip. In the power converter of Patent Document 1, the support is arranged so that it does not overlap with the semiconductor chip, so that the cooling efficiency for the semiconductor chip is not reduced. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] Patent No. 5757194 Summary of the Invention [Problem to be solved by the invention]
[0005] In the case of a power converter, a metal plate is used as a conductive member connecting a semiconductor chip to an external electrical device so that it can withstand a large current. Hereinafter, the metal plate electrically connecting the semiconductor chip to an external electrical device is referred to as a flat terminal. The flat terminal through which a large current flows also generates a large amount of heat. Therefore, the flat terminal is also a cooling target, and is also attached to a cooling plate. The flat terminal is arranged to reach the edge of the cooling plate so that it can be easily connected to a conductive member extending from an external electrical device. If the flat terminal generates heat and the cooling plate is deformed at the edge of the cooling plate, the boundary between the cooling plate and the case may crack. This specification relates to a power converter equipped with a semiconductor chip, a flat terminal, and a heat pipe for cooling them, and provides a technology for reducing damage to the heat pipe caused by thermal deformation of the flat terminal. [Means for solving the problem]
[0006] The power converter disclosed in this specification includes a semiconductor chip for power conversion, a flat terminal for electrically connecting the semiconductor chip to an external electric device, and a flat heat pipe. The heat pipe includes a cooling plate, a case, and a support. The semiconductor chip and the flat terminal are attached to the cooling plate. The case is joined to the rear surface of the cooling plate. A working fluid and a wick are sealed in the case sealed by the cooling plate. The support connects the bottom plate of the case to the cooling plate inside the case. The flat terminal reaches the edge of the cooling plate. When the cooling plate is viewed in a plane, the support is arranged in at least one of a range overlapping with the flat terminal and a range adjacent to the flat terminal, and is arranged so as not to overlap with the semiconductor chip. By arranging the support in the above-mentioned range, deformation of the cooling plate at the location where the flat terminal is attached is suppressed, and damage to the heat pipe is reduced. In addition, since the support is arranged so as not to overlap with the semiconductor chip, the cooling performance for the semiconductor chip is not hindered.
[0007] When insulating the flat terminal from the cooling plate, a heat-conducting insulating layer is sandwiched between the flat terminal and the cooling plate. If the cooling plate is conductive, the flat terminal and the semiconductor chip can be brought into direct contact with the cooling plate, and the flat terminal and the semiconductor chip can be electrically connected via the cooling plate. This improves the heat transfer from the flat terminal and the semiconductor chip to the cooling plate.
[0008] Typically, a semiconductor chip and an external electrical device are connected with two terminals, one for the positive electrode and one for the negative electrode. In this case, one of the flat terminals may be in direct contact with the cooling plate, but a heat-conducting insulating layer must be sandwiched between the other flat terminal (another flat terminal) and the cooling plate. Even when such a structure is adopted, at least one of the two flat terminals can be in direct contact with the cooling plate, and the flat terminal can be cooled efficiently.
[0009] Details and further improvements of the technology disclosed in this specification are described in the following "Forms for Carrying Out the Invention". [Brief description of the drawings]
[0010] [Figure 1] FIG. 2 is a plan view of the power converter according to the embodiment. [Diagram 2] 2 is a cross-sectional view of the power converter taken along line II-II in FIG. [Diagram 3] 3 is a cross-sectional view of the power converter taken along line III-III in FIG. [Figure 4] FIG. 13 is a plan view showing another example of a support column arrangement. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011] A power converter 2 according to an embodiment will be described with reference to the drawings. Fig. 1 shows a plan view of the power converter 2. Fig. 2 is a cross-sectional view of the power converter 2 taken along line II-II in Fig. 1, and Fig. 3 is a cross-sectional view of the power converter 2 taken along line III-III in Fig. 1. For ease of explanation, the +Z direction of the coordinate system in the drawings is defined as "upward" and the -Z direction is defined as "downward."
[0012] The power converter 2 includes a semiconductor chip 10, a substrate 40, a first flat plate terminal 21, a second flat plate terminal 31, and a flat heat pipe 3.
[0013] A substrate 40 is placed on the semiconductor chip 10, the first flat plate terminal 21, and the second flat plate terminal 31, but in order to make it easier to see the semiconductor chip 10 etc., the substrate 40 (and the wiring pattern 41 and insulating layer 22 described below) are drawn with imaginary lines (two-dot chain lines) in Fig. 1. In addition, the supports 7a, 7b, and 8 arranged inside the heat pipe 3 are drawn with dotted lines.
[0014] The semiconductor chip 10 is for power conversion, and is, for example, a power transistor. A first electrode 11 is exposed on the bottom surface of the semiconductor chip 10, and a second electrode 12 is exposed on the top surface. A plurality of control electrodes 13 are also exposed on the top surface of the semiconductor chip 10. A circuit connected to the control electrodes 13 is mounted on the substrate 40, but illustration and description of the circuit are omitted.
[0015] The first plate terminal 21 and the second plate terminal 31 are electrically connected to the semiconductor chip 10 and are conductive members that electrically connect the semiconductor chip 10 to an external electrical device. A large current handled by the semiconductor chip 10 flows through the first plate terminal 21 and the second plate terminal 31. Metal plates (the first plate terminal 21 and the second plate terminal 31) are used for the terminals of the semiconductor chip 10 so that they can withstand the large current.
[0016] Conductive members extending from an external electric device are connected to the first plate terminal 21 and the second plate terminal 31. When a large current flows through the semiconductor chip 10 via the first plate terminal 21 and the second plate terminal 31, the first plate terminal 21 and the second plate terminal 31 generate heat as well as the semiconductor chip 10. The heat pipe 3 cools the semiconductor chip 10, the first plate terminal 21, and the second plate terminal 31.
[0017] The heat pipe 3 will be described. The heat pipe 3 includes a cooling plate 4, a case 5, and multiple support pillars 7a, 7b, 8. The case 5 is joined to the rear surface of the cooling plate 4, and the internal space SP is sealed. The case 5 is joined along an edge 9 of the cooling plate 4. A working fluid and a wick (not shown) are sealed in the internal space SP of the case 5. The length (thickness) of the heat pipe 3 in the normal direction to the cooling plate 4 is shorter than the length in the direction intersecting the normal direction. The heat pipe 3 has a flat shape with a short length in the normal direction to the cooling plate 4.
[0018] The semiconductor chip 10, the first plate terminal 21, and the second plate terminal 31 are attached to the front surface of the cooling plate 4. When the semiconductor chip 10 operates, the semiconductor chip 10, the first plate terminal 21, and the second plate terminal 31 generate heat, and the heat spreads to the cooling plate 4.
[0019] The working fluid sealed in the case 5 is a liquid with a low boiling point. A substance whose boiling point is lower than the upper limit temperature of the semiconductor chip 10 during operation is selected as the working fluid. The working fluid in the vicinity of the cooling plate 4 is vaporized by the heat of the cooling plate 4. When the working fluid vaporizes, it takes heat from the cooling plate 4. That is, the cooling plate 4 is cooled. The vaporized working fluid spreads in the internal space SP and liquefies when it touches the bottom plate 6, which has a low temperature. When the working fluid vaporizes in the upper part of the internal space SP, the working fluid (liquid) in the vicinity of the bottom plate 6 moves to the vicinity of the back surface of the cooling plate 4 through the wick due to the capillary phenomenon of the wick (not shown). The working fluid that has moved to the vicinity of the back surface of the cooling plate 4 is vaporized by the heat of the cooling plate 4 and moves to the entire internal space SP. In this way, the cooling plate 4 (i.e., the semiconductor chip 10, the first flat terminal 21, etc.) is cooled by the vaporization / liquefaction cycle of the working fluid.
[0020] The cooling plate 4 is conductive. As shown in FIG. 2, the first plate terminal 21 is directly (or via a conductive bonding material such as solder) bonded to the cooling plate 4. The lower surface of the semiconductor chip 10 (the surface on which the first electrode 11 is exposed) is also directly (or via a conductive bonding material such as solder) bonded to the cooling plate 4. Therefore, the first electrode 11 and the first plate terminal 21 are electrically connected to each other via the conductive cooling plate 4. Since the first plate terminal 21 and the semiconductor chip 10 are attached to the cooling plate 4 directly (or via a bonding material such as solder), the efficiency of heat transfer from the first plate terminal 21 and the semiconductor chip 10 to the cooling plate 4 is high. That is, the first plate terminal 21 and the semiconductor chip 10 are efficiently cooled by the heat pipe 3. Note that the bonding material such as solder has high conductivity and high heat transfer efficiency, and is therefore suitable for bonding the semiconductor chip 10 and the first plate terminal 21 to the cooling plate 4, which is both conductive and heat absorbing. The first plate terminal 21 is joined to the substrate 40 via an insulating layer 22, and the first plate terminal 21 is insulated from the substrate 40.
[0021] 3, the second plate terminal 31 is attached to the cooling plate 4 via a heat conductive insulating layer 32. In other words, the heat conductive insulating layer 32 is sandwiched between the second plate terminal 31 and the cooling plate 4. Since the heat conductive insulating layer 32 is sandwiched, the second plate terminal 31 is insulated from the cooling plate 4, while the heat of the second plate terminal 31 is well conducted to the cooling plate 4.
[0022] A substrate 40 is attached onto the semiconductor chip 10, the first plate terminal 21, and the second plate terminal 31. The second plate terminal 31 is bonded to the substrate 40, and the top surface of the semiconductor chip 10 (the surface on which the second electrode 12 is exposed) is also bonded to the substrate 40. A circuit (not shown) that drives the semiconductor chip 10 is mounted on the substrate 40. A drive signal generated by the circuit is sent to the semiconductor chip 10 via the control electrode 13.
[0023] A wiring pattern 41 is provided on the lower surface of the substrate 40. The wiring pattern 41 connects the second plate terminal 31 and the second electrode 12. In other words, the second plate terminal 31 and the second electrode 12 are electrically connected by the wiring pattern 41 provided on the substrate 40.
[0024] The semiconductor chip 10, the first plate terminal 21, the second plate terminal 31, and the cooling plate 4 have different linear expansion coefficients. The cooling plate 4 corresponds to the wide surface of the flat heat pipe 3. Therefore, when the semiconductor chip 10, the first plate terminal 21, and the second plate terminal 31 generate heat, the cooling plate 4 may deform. In particular, due to the difference in linear expansion coefficient, the cooling plate 4 deforms so as to bulge outward in the area where the first plate terminal 21 and the second plate terminal 31 are joined.
[0025] The first plate terminal 21 and the second plate terminal 31 are arranged so as to reach the edge 9 of the cooling plate 4 when the power converter 2 is viewed in plan. This is to facilitate joining the first plate terminal 21 and the second plate terminal 31 to a conductive member of an external electrical device. When the first plate terminal 21 and the second plate terminal 31 generate heat, the cooling plate 4 is deformed in the vicinity of the edge 9. Since the cooling plate 4 and the case 5 are joined on the back side of the edge 9 of the cooling plate 4, the deformation of the cooling plate 4 may induce a break in the joint boundary between the cooling plate 4 and the case 5. On the other hand, the semiconductor chip 10 is arranged at a position separated from the edge 9 of the cooling plate 4 when the cooling plate 4 is viewed in plan. Therefore, the damage to the heat pipe 3 caused by the thermal deformation of the cooling plate 4 in the vicinity of the semiconductor chip 10 is not as great as the damage to the heat pipe 3 caused by the thermal deformation of the cooling plate 4 in the vicinity of the first plate terminal 21 and the second plate terminal 31.
[0026] Therefore, in order to suppress thermal deformation of the cooling plate 4 near the edge 9 (near the first flat plate terminal 21 and the second flat plate terminal 31), the pillars 7a and 7b are provided inside the case 5. The pillars 7a and 7b connect the cooling plate 4 to the bottom plate 6. The pillars 7a and 7b are provided so as to overlap the first flat plate terminal 21 or the second flat plate terminal 31 when the cooling plate 4 is viewed in a plan view. The pillars 7a and 7b suppress thermal deformation of the cooling plate 4 due to heat generation from the first flat plate terminal 21 and the second flat plate terminal 31 (particularly, deformation of the cooling plate 4 such that the cooling plate 4 bulges outward from the heat pipe 3). The pillars 7a and 7b particularly suppress deformation of the cooling plate 4 such that the cooling plate 4 bulges outward from the heat pipe 3. As a result, damage to the heat pipe 3 caused by thermal deformation of the cooling plate 4 is reduced.
[0027] The heat pipe 3 has a support pillar 8 in addition to the support pillars 7a and 7b. The support pillar 8 is provided at a position where it does not overlap with any of the first flat plate terminal 21, the second flat plate terminal 31, and the semiconductor chip 10 when the cooling plate 4 is viewed in a plan view. The support pillar 8 suppresses thermal deformation of the cooling plate 4 at locations away from the first flat plate terminal 21, the second flat plate terminal 31, and the semiconductor chip 10. Since the support pillar 8 is provided at a position where it does not overlap with the semiconductor chip 10, the first flat plate terminal 21, and the second flat plate terminal 31, it does not affect the cooling efficiency for these.
[0028] Another example of the support arrangement is shown in Fig. 4. Fig. 4 is a plan view of the power converter 2a. In other words, Fig. 4 is a diagram of the heat pipe 3a when the cooling plate 4 is viewed in plan. In Fig. 4, the components depicted by the two-dot chain lines in Fig. 1 (i.e., the substrate 40, the wiring pattern 41, and the insulating layer 22) are omitted.
[0029] The heat pipe 3a has pillars 7c, 7d, and 7e inside. As with the heat pipe 3 of the embodiment, the pillars 7c, 7d, and 7e connect the bottom plate of the case of the heat pipe 3a to the cooling plate 4. The gray area A in FIG. 4 indicates the area adjacent to the first flat plate terminal 21 and the area adjacent to the second flat plate terminal 31. The pillars 7c, 7d, and 7e are provided in the area adjacent to the first flat plate terminal 21 or the area adjacent to the second flat plate terminal 31 when the cooling plate 4 is viewed in a plan view. By providing the pillars 7c, 7d, and 7e in the area adjacent to the flat plate terminals (the first flat plate terminal 21 and the second flat plate terminal 31) when the cooling plate 4 is viewed in a plan view so as not to overlap with the semiconductor chip 10, it is possible to suppress thermal deformation of the cooling plate 4 in the vicinity of the edge 9. As a result, damage to the heat pipe 3a caused by thermal deformation of the flat plate terminals is suppressed.
[0030] The support pillar 7c is disposed between two flat terminals (first flat terminal 21 and second flat terminal 31) when the cooling plate 4 is viewed in plan. When the two flat terminals are arranged side by side along the edge 9 of the cooling plate 4, it is preferable to dispose the support pillar at a position adjacent to each of the two flat terminals when the cooling plate 4 is viewed in plan. In other words, it is preferable to dispose the support pillar between the two flat terminals. The area between the two flat terminals is particularly subject to large thermal deformation. The support pillar disposed between the two flat terminals connects the portion of the cooling plate that is subject to large thermal deformation to the bottom plate, thereby effectively suppressing damage caused by thermal deformation of the cooling plate.
[0031] Points to note regarding the techniques described in the examples are as follows. The support pillars may be fixed to the bottom plate and the cooling plate by various techniques. For example, the support pillars may be fixed by being pressed into holes provided in the cooling plate or the bottom plate. Alternatively, the support pillars may be fixed to the bottom plate and the cooling plate by an anchor metal driving technique. Furthermore, the support pillars may be fixed to the bottom plate and the cooling plate by a metal diffusion bonding technique, an ultrasonic bonding technique, a friction diffusion bonding technique, a room temperature diffusion bonding technique, or the like, or by a combination of these techniques.
[0032] The support may also serve as a member for sealing an inlet for introducing working fluid into the case.
[0033] There is no limit to the number of support posts, as long as the support posts are arranged in at least one of an area overlapping the flat terminals and an area adjacent to the flat terminals when the cooling plate is viewed from above, and are arranged so as not to overlap the semiconductor chip.
[0034] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful. [Explanation of symbols]
[0035] 2, 2a: power converter 3, 3a: heat pipe 4: cooling plate 5: case 6: bottom plate 7a-7e, 8: support 9: edge 10: semiconductor chip 11: first electrode 12: second electrode 13: control electrode 21: first flat plate terminal 22: insulating layer 31: second flat plate terminal 32: heat transfer insulating layer 40: substrate 41: wiring pattern SP: internal space
Claims
1. A semiconductor chip (10) for power conversion; Flat terminals (21, 31) for electrically connecting the semiconductor chip to an external electrical device; 、 A flat heat pipe (3); Equipped with The heat pipe is a cooling plate (4) attached to the semiconductor chip and the flat terminal; A case (5) joined to the rear surface of the cooling plate and sealing a working fluid; Inside the case, a support (7) is provided connecting the bottom plate (6) of the case to the cooling plate. a to 7e), Equipped with The flat terminal extends to the edge (9) of the cooling plate, The support pillars are provided in a range that overlaps with the flat terminals and a range that overlaps with the flat terminals when the cooling plate is viewed from above. The terminal is disposed at least on one side of the adjacent range of the terminal and does not overlap the semiconductor chip. They are arranged so that The cooling plate is electrically conductive, and the flat terminal (21) and the semiconductor chip are A power converter, which is in conduction through a cooling plate.
2. Further, the semiconductor chip is electrically connected to another flat terminal (31). A thermally conductive insulating layer (32) is sandwiched between the other flat terminal and the cooling plate.
2. The power converter of claim 1.
Citation Information
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