Semiconductor Device

Abstract

To reduce the number of transistors connected to a capacitor.SOLUTION: A semiconductor device includes a capacitor and a transistor. One electrode of the capacitor is connected to a wire and the other electrode of the capacitor is connected to a gate of the transistor. A clock signal is input to the wire and the clock signal is input to the gate of the transistor through the capacitor. The conductive state of the transistor is controlled by a signal synchronizing with the clock signal and the transistor is set to the on state and the off state repeatedly. Thus, the deterioration in transistor can be suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device and a display device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a liquid crystal display device, a driving method for the device, or an electronic device having the device. Regarding. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single crystal semiconductors are used to form a pixel region. The technology of configuring driving circuits such as gate drivers on a substrate is expected to contribute greatly to reducing costs and improving reliability. Development is underway actively to contribute significantly to the

[0003] However, transistors made of non-single crystal semiconductors have a higher threshold voltage and When the degradation of this transistor progresses, the driving circuit stops working. This causes a problem that the image cannot be displayed due to the difficulty in adjusting the brightness. The present invention discloses a shift register configuration that can suppress the degradation of transistors. In Patent Document 1, one electrode of the capacitance element is connected to a wiring to which a clock signal is input, The other electrode of the capacitance element is connected to the gates of the two transistors. The potential of the capacitor is increased or decreased in synchronization with the clock signal. Using this combination, a signal synchronized with the clock signal is generated at the gates of the two transistors. Then, a signal synchronized with this clock signal is used to control the on and off of the transistor. Then, the period when the transistor is on and the period when the transistor is off are repeated. Since the power supply is returned to the outside, deterioration of the transistor can be suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2006-24350 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in Patent Document 1, the other electrode of the capacitance element is connected to the gates of the two transistors. Therefore, there is a problem that the parasitic capacitance of the node connected to the capacitive element becomes large. This causes a problem that the potential of the H level of the signal synchronized with the clock signal becomes lower. In this case, when the threshold voltage of the transistor increases, the transistor becomes on. In other words, the life of the shift register is shortened. Or, the parasitic capacitance connected to the capacitive element is large, so the capacitance The capacitance of the element must be increased. Since it is necessary to increase the area where one electrode overlaps the other electrode, the layer of the capacitance element However, there are issues such as the surface area becoming larger.

[0006] In addition, in Patent Document 1, since it is necessary to increase the area of ​​the capacitance element, one electrode and the other There is also the issue that the electrodes on both sides are easily shorted out by dust and other debris. There are issues such as lower yields and increased costs.

[0007] In addition, in Patent Document 1, since it is necessary to increase the capacitance value of the capacitive element, The delay or distortion of the signal (e.g., clock signal or inverted clock signal) being fed is large. Another problem is that the power consumption is high.

[0008] Alternatively, a circuit having a large current driving capability as a circuit for outputting a signal to be supplied to a capacitive element Since it is necessary to use an external circuit, the larger the external circuit becomes, the Another problem is that the display device becomes large.

[0009] In Patent Document 1, the period during which the gate of the pull-up transistor Tu is in a floating state is Therefore, the potential of the gate of the pull-up transistor Tu is unstable, and noise This causes problems such as the shift register malfunctioning.

[0010] In view of the above, an object of the present invention is to reduce the number of transistors connected to a capacitor. Alternatively, the object is to reduce the parasitic capacitance of a transistor connected to the capacitive element. Another object of the present invention is to increase the H level potential of a signal synchronized with a clock signal. Alternatively, the layout area can be reduced. Alternatively, the life can be extended. The objective is to reduce the delay or distortion of signals. Or, the objective is to reduce power consumption. Another object of the present invention is to reduce the influence of noise. The object of the present invention is to suppress or reduce deterioration of a transistor. Another object of the present invention is to prevent a short circuit between one electrode and the other electrode of a capacitor. Another object of the present invention is to reduce the current drive capacity of an external circuit. The object of the present invention is to reduce the size of an external circuit. The objectives of the present invention are to provide a method for solving the above problems. Note that the description of these objectives does not preclude the existence of other objectives. [Means for solving the problem]

[0011] The capacitor includes a capacitor and a transistor. One electrode of the capacitor is connected to a wiring. The other electrode of the capacitance element is connected to the gate of the transistor. The clock signal is input, so that the clock signal is input to the gate of the transistor via the capacitance element. The transistor conduction state is controlled by a signal synchronized with the clock signal. The transistor is controlled to alternate between being on and off. This makes it possible to suppress deterioration of the transistor.

[0012] An exemplary embodiment of the present invention includes a driving circuit and a pixel, the pixel including a liquid crystal element, The driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first terminal of the first transistor and a first capacitance element; a second terminal of the first transistor electrically connected to a second wiring; a first terminal of the second transistor electrically connected to the second wiring; a second terminal of the second transistor electrically connected to a gate of the first transistor; a gate of the second transistor is electrically connected to the first wiring; A first terminal of the third transistor is electrically connected to a third wiring. A second terminal of the transistor is electrically connected to the gate of the first transistor, A first terminal of the fourth transistor is electrically connected to the third wiring. A second terminal of the transistor is electrically connected to the gate of the third transistor, a gate of a fourth transistor is electrically connected to the gate of the first transistor; One electrode of the capacitance element is electrically connected to the first wiring, and the other electrode of the capacitance element is The electrode of the liquid crystal display device is electrically connected to the gate of the third transistor.

[0013] The switch may be of various types. For example, an electrical switch may be used. In other words, anything that can control the flow of electric current is acceptable. For example, a transistor (e.g., a bipolar transistor) may be used as a switch. transistors, MOS transistors, etc.), diodes (e.g. PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal diode, MIS (Metal Insulator Semiconductor) conductor diodes, diode-connected transistors, etc. Alternatively, a logic circuit that combines these can be used as a switch.

[0014] An example of a mechanical switch is the digital micromirror device (DMD). As shown in the figure, switches using MEMS (microelectromechanical systems) technology There is Chi.

[0015] In addition, both N-channel and P-channel transistors are used to realize a CMO An S-type switch may be used as the switch.

[0016] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits, etc.). Therefore, a given connection relationship is For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may be modified in any manner without departing from the spirit or scope of the present invention. This also includes things other than relationships.

[0017] For example, if A and B are electrically connected, the following can be considered: The elements that function as One or more diodes (e.g., anode, diode, etc.) may be connected between A and B. Alternatively, When A and B are functionally connected, a circuit (e.g. For example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits , step-down circuits, level shifter circuits that change the potential level of signals, voltage sources, current sources , switching circuits, amplification circuits (circuits that can increase the signal amplitude or current, etc., operational amplifiers , differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, One or more control circuits may be connected between A and B. For example, If the signal output from A is transmitted to B, even if there is another circuit between them, then A and B are considered to be are considered to be functionally connected.

[0018] In addition, when it is explicitly stated that A and B are electrically connected, it means that A and B are electrically When A and B are electrically connected (i.e., when another element or circuit is placed between A and B), A and B are functionally connected (i.e., there is no connection between A and B) and B is functionally connected (i.e., there is no connection between A and B). When A and B are connected directly ( In other words, A and B are connected without any other element or circuit between them. In other words, when it is explicitly stated that something is electrically connected, it should simply be " is the same as if it were expressly stated only that the

[0019] In addition, a display element, a display device which is a device having a display element, a light-emitting element, The light-emitting device can have a variety of configurations and elements. For example, the display element, display device, light-emitting element, or light-emitting device may be an EL (electroluminescent EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent transistors that emit light when exposed to light, electron emitters, liquid crystal elements, electronic ink, electrophoretic elements, graphene Rating light bulbs (GLV), plasma displays (PDP), digital microphones Chroma mirror device (DMD), piezoelectric ceramic display, carbon nanotube, Displays whose contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic effects. The display device using the EL element may be an EL display. As a display device using electron emission elements, a field emission display (FED) ) and SED type flat panel displays (SED: Surface-conduction Display devices using liquid crystal elements such as LCDs and LCD displays (transmissive LCDs, semi-transmissive LCDs, reflective LCDs) LCDs, direct-view LCDs, projection LCDs), electronic inks, An example of a display device using an electrophoretic element is electronic paper.

[0020] The liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. It is an element that consists of a pair of electrodes and liquid crystal. The optical modulation action of liquid crystal is as follows: Controlled by the electric field applied to the liquid crystal (including the horizontal electric field, vertical electric field, or diagonal electric field) The liquid crystal element is a nematic liquid crystal, a cholesteric liquid crystal, a smectic liquid crystal, Liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal , polymer liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal , Side-chain polymer liquid crystal, Plasma-addressed liquid crystal (PALC), Banana-shaped liquid crystal, TN (Twi sted Nematic) mode, STN (Super Twisted Nematic) ic) mode, IPS (In-Plane-Switching) mode, FFS (Fr inge Field Switching) mode, MVA (Multi-domai n Vertical Alignment) mode, PVA(Patterned V ertical Alignment), ASV (Advanced Super Vi ew) mode, ASM(Axially Symmetric aligned Mic ro-cell) mode, OCB(Optical Compensated Bire) fringence) mode, ECB (Electrically Controlled) mode d Birefringence mode, FLC (Ferroelectric Li quid Crystal) mode, AFLC(AntiFerroelectric) mode Liquid Crystal mode, PDLC (Polymer Disperse d Liquid Crystal mode, guest host mode, Blue phase However, the present invention is not limited to this, and liquid crystal elements may be used. A variety of materials can be used as the

[0021] In addition, display devices that require a light source, such as liquid crystal displays (transmissive liquid crystal displays) Semi-transmissive LCD, reflective LCD, direct-view LCD, projection type liquid crystal display (LCD), display device using grating light valve (GLV), As a light source for a display device using a digital micromirror device (DMD), Uses thermoluminescence, cold cathode tubes, hot cathode tubes, LEDs, laser light sources, mercury lamps, etc. However, the present invention is not limited to this, and various light sources can be used as the light source. Cut.

[0022] Note that various types of transistors can be used. There is no limitation on the type of transistor to be used. For example, amorphous silicon, polycrystalline silicon, Microcrystalline (also called microcrystalline, nanocrystalline, or semi-amorphous) silicon The use of thin film transistors (TFTs) having non-single crystal semiconductor films, such as is possible.

[0023] In addition, when producing microcrystalline silicon, by using a catalyst (such as nickel), It is possible to further improve the crystallinity and manufacture transistors with good electrical characteristics. In this case, the crystallinity can be improved by simply applying heat treatment without laser irradiation. As a result, part of the source driver circuit (analog switches, etc.) and the gate The gate driver circuit (scanning line driver circuit) can be formed integrally on the substrate. If laser irradiation is not performed for crystallization, unevenness in the crystallinity of silicon can be suppressed. Therefore, it is possible to display images with improved quality.

[0024] However, polycrystalline silicon and microcrystalline silicon can be produced without using a catalyst (such as nickel). It is possible.

[0025] Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. These features result in less variation in characteristics, size, and shape, higher current supply capacity, and These transistors allow the manufacture of transistors with low noise. This makes it possible to reduce the power consumption of the circuit or to increase the degree of integration of the circuit.

[0026] Or ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, SnO and transistors having compound semiconductors or oxide semiconductors such as these. A thin film transistor in which a compound semiconductor or an oxide semiconductor is thinned can be used. These features allow the manufacturing temperature to be lowered, making it possible to manufacture transistors at room temperature, for example. As a result, it is difficult to directly transfer the heat to a substrate with low heat resistance, such as a plastic substrate or a film substrate. In addition, these compound semiconductors or oxide semiconductors can be used to form transistors. It can be used not only for the channel part of a transistor but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistor elements, pixel electrodes, and light-transmitting Furthermore, they can be formed simultaneously with a transistor or as an electrode. Since it is possible to form the semiconductor device, the cost can be reduced.

[0027] Alternatively, transistors formed by inkjet or printing methods can be used. These allow fabrication at room temperature, in a low vacuum, or on large substrates. Since it is possible to manufacture the transistors without using a mask (reticle), The layout can be easily changed. Furthermore, since there is no need to use a resist, This reduces the cost of materials and the number of processes. Furthermore, since the film is applied only to the necessary parts, This method is less wasteful and less costly than the method of etching after forming a film on the entire surface. can be done.

[0028] Alternatively, transistors having organic semiconductors or carbon nanotubes can be used. This makes it possible to form transistors on a flexible substrate. A semiconductor device using such a substrate can be made resistant to shocks.

[0029] Furthermore, transistors of various structures can be used. For example, MOS transistors Transistors such as junction transistors and bipolar transistors can be used as transistors. By using MOS transistors, the size of the transistors can be reduced. Therefore, a large number of transistors can be mounted. By using transistors, it is possible to pass a large current. Therefore, it is possible to perform high-speed circuit testing. It can be made to work.

[0030] In addition, MOS transistors, bipolar transistors, etc. can be mixed on one substrate. This can realize low power consumption, small size, high speed operation, etc. do.

[0031] In addition, various other transistors can be used.

[0032] Note that the transistor can be formed using various substrates. The substrate is not limited to a specific one. The substrate may be, for example, a single crystal substrate or an SOI substrate. , glass substrate, quartz substrate, plastic substrate, stainless steel substrate, stainless steel A substrate such as a chill foil can be used.

[0033] The structure of the transistor can take various forms and is not limited to a specific structure. For example, a multi-gate structure having two or more gate electrodes can be applied. When the gate structure is used, the channel regions are connected in series, so multiple transistors are connected in series. The configuration is connected to the above.

[0034] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied. In addition, by arranging gate electrodes above and below the channel, multiple transistors can be formed. The configuration is like that of transistors connected in parallel.

[0035] A structure in which a gate electrode is disposed above a channel region, and a structure in which a gate electrode is disposed below a channel region The structure in which the channel region is divided into multiple regions is called the normal staggered structure. a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series In addition, a source electrode and a drain electrode are provided in the channel region (or a part of it). Alternatively, a structure in which an LDD region is provided can be used.

[0036] Note that various types of transistors can be used and can be formed using various substrates. Therefore, all the circuits required to realize a given function can be implemented simultaneously. For example, the circuit required to realize a specific function may be formed on a single substrate. All of the circuits are mounted on various substrates such as glass, plastic, single crystal, or SOI. Alternatively, the substrate may be formed using a material necessary for realizing a desired function. A part of the circuitry required to realize a certain function is formed on a substrate. It is also possible that a part of the semiconductor device is formed on a separate substrate. All of the circuits required for the above-mentioned purpose do not necessarily have to be formed using the same substrate. Some of the circuits required to realize the above functions are formed by transistors on a glass substrate. Another part of the circuitry required to realize a predetermined function is formed on the single crystal substrate; An IC chip consisting of transistors formed on a single crystal substrate is called COG (Chip On Glass). On Glass) to connect to a glass substrate and place the IC chip on the glass substrate. Alternatively, the IC chip can be inserted into a TAB (Tape Automate) It is also possible to connect it to the glass substrate using a printed circuit board or a bonding method. Alternatively, circuits with high drive voltages and high drive frequencies consume large amounts of power. Therefore, the circuits for such parts are not formed on the same substrate. Instead, for example, The circuit for that part is formed on a single crystal substrate, and an IC chip composed of that circuit is used. This can prevent an increase in power consumption.

[0037] A transistor is defined as a transistor having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain region and the source region. A current can be passed through the drain region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is unclear which is the source and which is the drain. Therefore, it is difficult to determine whether the source or drain is the same. In some cases, the region that functions as a source or drain is not called a source or drain. In some cases, they are referred to as the first terminal and the second terminal. They may be referred to as the first electrode and the second electrode. Or, they may be referred to as the first region and the second region. There is a match.

[0038] A transistor has at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector are connected to the first terminal and the second terminal. It may be written as 2 terminals, etc.

[0039] Semiconductor devices include semiconductor elements (transistors, diodes, thyristors, etc.). It also refers to devices that have circuits that can function by utilizing the characteristics of semiconductors. The term "semiconductor device" may generally refer to any device that has semiconductor material. He says.

[0040] Note that the display device refers to a device having a display element. The display device may include a plurality of pixels including a plurality of pixels each including a peripheral circuit. The peripheral driving circuit for driving the plurality of pixels may include a plurality of The display device may be formed on the same substrate as the pixel. Peripheral driving circuits arranged on the substrate by, for example, chip-on-glass (COG) It may include IC chips connected by a wire or IC chips connected by a TAB or the like. The display device may include IC chips, resistor elements, capacitor elements, inductors, transistors, etc. The circuit board may include a flexible printed circuit (FPC) to which a The display device is connected via a flexible printed circuit (FPC) or other device, and the IC chip A printed circuit board on which chips, resistors, capacitors, inductors, transistors, etc. are mounted. The display device may include a polarizing plate or a retardation plate. The display device may include an illumination device, a housing, an audio input / output device, an optical sheet, etc. It may also include an optical sensor.

[0041] The lighting device includes a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflector, and a It has a reflecting sheet, light source (LED, cold cathode fluorescent lamp, etc.), cooling device (water-cooled, air-cooled), etc. That's fine.

[0042] The light-emitting device refers to a device having a light-emitting element or the like. When the light emitting device has a light element, the light emitting device is a specific example of a display device.

[0043] The reflecting device is a device having a light reflecting element, a light diffractive element, a light reflecting electrode, etc. It is said.

[0044] Note that the liquid crystal display device refers to a display device having a liquid crystal element. There are direct-view, projection, transmissive, reflective, and semi-transmissive types.

[0045] In addition, a driving device refers to a device that has semiconductor elements, electric circuits, and electronic circuits. For example, a transistor that controls the input of a signal from a source signal line to a pixel (selection transistor) (sometimes called a transistor for switching, etc.) and supplies a voltage or current to the pixel electrode. The transistors that supply a voltage or current to the light-emitting element are Furthermore, a circuit for supplying a signal to the gate signal line (a gate driver, A circuit that supplies signals to the source signal lines (sometimes called a source line driver circuit, etc.) A pixel driver (sometimes called a pixel driver or a source line driver circuit) is an example of a driver device.

[0046] In addition, the present invention is applicable to display devices, semiconductor devices, lighting devices, cooling devices, light-emitting devices, reflecting devices, driving devices, etc. For example, a display device may include a semiconductor device and a light emitting device. Alternatively, the semiconductor device may include a display device and a driving device. This may be the case.

[0047] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed directly on A. This also includes cases where A and B are not in a state where the object is located between them, that is, where there is another object between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers , etc.).

[0048] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). In the cases listed, layer B is formed directly on layer A, and layer A is formed on layer B. Another layer (such as layer C or layer D) is formed directly on top of it, and layer B is formed directly on top of it. In addition, other layers (such as layers C and D) may be formed as follows: It may be a single layer or a multi-layer.

[0049] Furthermore, the same applies to cases where it is explicitly stated that B is formed above A. It is not limited to B being directly on A, and there is no other object between A and B. This also includes cases where a layer is interposed between layers. For example, if a layer B is formed above a layer A, In this case, layer B is formed directly on layer A, and layer B is formed directly on layer A. Another layer (such as layer C or layer D) is formed on top of it, and layer B is formed directly on top of it. In addition, other layers (such as layers C and D) may be used as single layers. It may be a multi-layer structure.

[0050] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that B is formed, this also includes the case where B is formed diagonally above. .

[0051] The same applies to the case where B is below A, or B is below A.

[0052] In addition, where something is explicitly stated as singular, it is preferable that it be singular. However, it is not limited to this and plurals are also possible. It is preferable that the items described in the above are plural. However, this is not limited to this. It is also possible for the term to be singular.

[0053] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0054] Note that the diagram is a schematic representation of an ideal example, and is not limited to the shapes or values ​​shown in the diagram. For example, there are variations in shape due to manufacturing techniques, variations in shape due to errors, and noise. Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Or, it is possible to include current variation.

[0055] In addition, technical terms may be used for the purpose of describing a specific embodiment or example. Many, but not limited to:

[0056] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It is possible to use the term as meaning equivalent to the general meaning understood by a person skilled in the art. Any words defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0057] In addition, the terms first, second, third, etc., refer to various elements, members, regions, layers, or sections from one another. Therefore, the words first, second, third, etc. are used to distinguish between elements, parts, etc. The number of materials, regions, layers, areas, etc. is not limited. It is possible to replace "second" or "third" etc. Effect of the Invention

[0058] The number of transistors connected to the capacitor can be reduced. The parasitic capacitance of the connected transistor can be reduced. The potential of the H level of the synchronized signal can be increased. Or, the layout area can be reduced. It is possible to reduce the delay or distortion of signals. Or, the power consumption can be reduced. Or, the noise level can be reduced. The influence of the above can be reduced. Alternatively, the deterioration of the transistor can be suppressed or alleviated. Alternatively, a malfunction can be suppressed. This can prevent short circuits with the electrodes. Alternatively, the current drive capacity of the external circuit can be reduced. Alternatively, the size of the external circuit can be reduced. It can be made smaller. [Brief description of the drawings]

[0059] [Figure 1] 1A to 1C are a circuit diagram of a semiconductor device and a timing chart illustrating a driving method thereof. [Diagram 2] 1A to 1C are schematic diagrams illustrating a method for driving a semiconductor device. [Diagram 3] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 4] FIG. 1 is a circuit diagram of a semiconductor device. [Diagram 5] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 6] 1A to 1C are a circuit diagram of a semiconductor device and a timing chart illustrating a driving method thereof. [Figure 7]1A to 1C are schematic diagrams illustrating a method for driving a semiconductor device. [Figure 8] 1A to 1C are schematic diagrams illustrating a method for driving a semiconductor device. [Figure 9] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 10] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 11] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 13] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 14] 1A and 1B are a circuit diagram of a shift register and a timing chart illustrating a driving method thereof. [Figure 15] FIG. 1 is a circuit diagram of a shift register. [Figure 16] FIG. 1 is a circuit diagram of a shift register. [Figure 17] FIG. 1 is a circuit diagram of a shift register. [Figure 18] FIG. 1 is a layout diagram of a shift register. [Figure 19] 1A to 1C are a circuit diagram of a semiconductor device and a timing chart illustrating a driving method thereof. [Figure 20] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 21] FIG. 1 is a circuit diagram of a shift register. [Figure 22] FIG. 1 is a system block diagram of a display device. [Figure 23] FIG. 1 illustrates a structure of a display device. [Figure 24] FIG. 1 is a circuit diagram of a shift register. [Diagram 25] 4 is a timing chart illustrating a method of driving a shift register. [Figure 26] 1A and 1B are a circuit diagram of a signal line driver circuit and a timing chart illustrating a driving method thereof. [Figure 27] 1A and 1B are a circuit diagram of a pixel and a timing chart illustrating a driving method thereof. [Figure 28] 1A and 1B are a circuit diagram and a layout diagram of a pixel, and a timing chart explaining a driving method thereof. [Figure 29]1A and 1B are a circuit diagram of a pixel and a timing chart illustrating a driving method thereof. [Diagram 30] FIG. 1 is a layout diagram of a shift register. [Diagram 31] FIG. 1 is a layout diagram of a shift register. [Diagram 32] FIG. 1 is a cross-sectional view of a transistor. [Diagram 33] 1A to 1C are diagrams illustrating electronic devices. [Diagram 34] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiment may be different from the embodiment. The present invention can be implemented in any manner without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention may be modified in various ways. In addition, in the configuration described below, Reference numerals indicating similar objects are used in different drawings, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0061] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the embodiment, and / or one or more other embodiments The application, combination, or replacement of the contents (or part of the contents) described in the form It is possible to do the following:

[0062] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. The content is what is stated, or what is stated using the text in the specification.

[0063] In addition, a figure (or a part of a figure) described in one embodiment may be different from another part of the figure, The figures (or a part thereof) described in the embodiment and / or one or more other By combining with the figures (or even a part of them) described in the embodiment mode, Many more diagrams can be constructed.

[0064] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. A logic circuit, a logic gate, or a flip-flop.

[0065] First, an example of a semiconductor device in this embodiment will be described with reference to FIG. The semiconductor device of (A) includes a circuit 100, a transistor 101, a transistor 102, and a transistor The semiconductor memory device includes a transistor 103, a transistor 104, a capacitor 105, and a capacitor 106. The transistors 101 to 104 are each an N-channel type, and the gate and source When the potential difference (Vgs) between them exceeds the threshold voltage (Vth), the transistor turns on. However, the present invention is not limited to this, and each of the transistors 101 to 104 is preferably a P-channel type. A P-channel transistor has a potential difference between the gate and source (Vgs ) falls below the threshold voltage (Vth).

[0066] The connection relationship of the semiconductor device in FIG. The second terminal of the transistor 101 is connected to the wiring 121. The first terminal of the transistor 102 is connected to the gate of the transistor 101. A second terminal of the transistor 102 is connected to the wiring 121. The first terminal of the transistor 103 is connected to a wiring 122A. The second terminal of the transistor 103 is connected to the gate of the transistor 101. The first terminal of the transistor 104 is connected to the wiring 122B. The second terminal is connected to the gate of the transistor 103. The other electrode of the capacitor 105 is connected to the gate of the transistor 101. One electrode of the capacitor 106 is connected to the wiring 123. The other electrode of 6 is connected to the gate of transistor 103 .

[0067] The gate of the transistor 101, the first terminal of the transistor 102, The connection point of the second terminal of the transistor 103 or the gate of the transistor 104 is indicated as a node A. The gate of the transistor 103, the second terminal of the transistor 104, or the capacitor The connection point of the other electrode of 106 is indicated as node B. It can be shown as a line.

[0068] In addition, the wiring 121, the wiring 123A, the wiring 123B, the wiring 123C, the wiring 122A, the wiring 1 22B may be designated as a terminal.

[0069] Input to each wiring (wiring 121, wiring 122A to 122B, wiring 123A to 123C) An example of what can be input (e.g., a signal, a voltage, or a current) will be described. The following is an example and is not intended to be limiting. It is possible to input various other things, and each wiring can be set to a floating state (hereinafter, floating It is possible to set the state to "on-hold state."

[0070] As an example, a signal S1 is output from the wiring 121. In particular, when the wiring 121 is connected to a pixel, When the wiring 121 is arranged to extend to the pixel portion, the wiring 121 may be a gate line, a scanning line, Alternatively, it can function as a capacitance line. The signal S1 is an output signal of the semiconductor device. In many cases, the signal is a digital signal having a high level and a low level, and is used as an output signal, a selection signal, It can function as a gate signal or a scanning signal.

[0071] As an example, a voltage V1 is supplied to the wirings 122A to 122B. The wirings 122A to 122B can function as power supply lines. It is often approximately equal to the L level of S1, and is the ground voltage, power supply voltage, or negative It is possible for the wiring 122A to function as a power supply voltage. A signal such as a clock signal can be input to the wiring 122B. 2A to 122B can function as signal lines or clock signal lines. In other words, different voltages or different signals can be input to the wirings 122A and 122B. It is.

[0072] In addition, "generally" refers to errors due to noise, errors due to process variations, and errors due to the manufacturing process of the element. This includes various errors such as errors due to variations in manufacturing process and / or measurement errors.

[0073] As an example, a signal S2 is input to the wirings 123A to 123C. The wirings 123A to 123C can function as signal lines. In most cases, it is a digital signal that repeats H and L levels at a cycle of a clock signal. (CK). However, the present invention is not limited to this. A power supply voltage can be supplied to the wirings 123A to 123C. 3C can function as a power supply line. , separate voltages, or separate signals can be input.

[0074] In this embodiment, as an example, the potential of the L level of the signal is V1, The potential is V2, and V2>V1, but is not limited to this.

[0075] Voltage refers to the difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible.

[0076] The circuit 100, the transistors 101 to 104, the capacitor 105, and the capacitor 106 have functions However, the following is only an example and is not intended to be limiting. The circuit 100 and each element may have various functions in addition to those described below. It is possible that the following functions are not included, and it is also possible that the following functions are not included.

[0077] The circuit 100 has a function of controlling the potential or state of the node A and a function of controlling the potential or state of the wiring 121. For example, the circuit 100 has a function of controlling the potential of the node A or the potential of the wiring 12. a function of increasing the potential of the node A or the potential of the wiring 121; and / or a function of putting the node A or the wiring 121 in a floating state. The resistor 101 is connected to the wiring 123B in response to a signal (for example, the signal S2) input to the wiring 123B. The transistor 102 has a function of increasing the potential of the wiring 123C. The timing at which the wiring 121 and the node A are brought into conduction is controlled in response to a signal (for example, the signal S2). The transistor 103 has a function of switching the potential of the node B. In this way, the timing at which the wiring 122A and the node A are electrically connected is controlled, and the wiring 122A functions as a switch. The transistor 104 turns on or off the wiring 122B and the node B in response to the potential of the node A. The capacitor 105 has a function of controlling the timing of the switching of the power supply 101 and functions as a switch. A function and / or a transistor that increases the potential of node A in response to the potential of line 126. The capacitor 106 has a function of holding a potential difference between the gate and the second terminal of the transistor 101. The potential of the node B is controlled in response to a signal (for example, the signal S2) input to the wiring 123A. It has the function of

[0078] Next, the operation of the semiconductor device of FIG. 1(A) will be described with reference to FIG. 1(B) and FIGS. 2(A) to 2(E). FIG. 1B is a timing chart illustrating the operation of the semiconductor device. This is an example, and includes a period T1, a period T2, a period T3, a period T4, and a period T5. FIG. 1B shows a signal S1, a signal S2, a potential Va of a node A, and a potential Vb of a node B. FIG. 2A is a schematic diagram showing the operation of the semiconductor device in FIG. 1A in the period T1. 2(B) is a schematic diagram showing the operation of the semiconductor device of FIG. 1(A) during the period T2. 2A is a schematic diagram showing the operation of the semiconductor device in FIG. 1A during a period T3. FIG. 2E is a schematic diagram showing the operation of the semiconductor device in FIG. 1A during the period T 5 is a schematic diagram showing the operation of the semiconductor device of FIG.

[0079] When the potential of the node A increases, the semiconductor device performs the operation in the period T1 and the operation in the period T2. The operation in the period T1 and the operation in the period T2 are performed in this order. After that, the potential of the node A rises again. The semiconductor device repeats the operation in the period T4 and the operation in the period T5 in sequence until vinegar.

[0080] First, in a period T1, the signal S2 is at an L level. Then, the transistor 102 is turned on. Therefore, there is no electrical continuity between the node A and the wiring 121. At the same time, the potential of the node B is The potential of the node B is decreased by the capacitive coupling of the capacitor 106. The sum of the potential (V1) of 2A and the threshold voltage (Vth106) of the transistor 103 (V1+V th106), the transistor 103 is turned off. 122A and node A are in a non-conductive state. On the other hand, the circuit 100 raises the potential of node A. Then, the potential of the node A starts to rise to the potential (V1) of the wiring 122B and the potential (V2) of the transistor 1 When the threshold voltage of Vth104 is added to the threshold voltage of Vth104 (V1+Vth104), The transistor 104 is turned on. Then, the wiring 122B and the node B are in a conductive state. Therefore, the voltage V1 is supplied to the node B from the wiring 122B, so that the potential of the node B is V1. As a result, the transistor 103 remains off, and the wiring 122A and the node A Similarly, when the potential of the node A is equal to the potential of the wiring 123B (V1), The sum of this with the threshold voltage of transistor 101 (Vth101) is (V1+Vth101). Meanwhile, the transistor 101 is turned on. Then, the wiring 123B and the wiring 121 are conductive. Therefore, the signal S2 at the L level is supplied from the wiring 123B to the wiring 121. Therefore, the potential of the wiring 121 is equal to the potential of the wiring 123B (the L level of the signal S2 or V1). The circuit 100 then sets the potential at node A to a certain value (e.g., V1+Vt When the voltage rises to h101 or more and V2 or less, the signal supply to node A is stopped. Therefore, the circuit 100 and the node A are in a non-conductive state. Therefore, the node A is in a floating state. The potential of the node A is maintained at a high value. The potential difference between node A and wiring 121 is maintained.

[0081] Note that in the period T1, the circuit 100 applies a voltage V1 or an L-level signal to the wiring 121. Alternatively, the circuit 100 can supply a signal or the like to the wiring 121. By not providing the wiring 121, the circuit 100 and the wiring 121 can be brought out of electrical continuity. In the circuit 100, the wiring 121 can be in a floating state.

[0082] Next, in the period T2, the potential of the node A is maintained at a high value, so that the transistor 104 remains on. Therefore, the wiring 122B and the node B remain in a conductive state. Therefore, the potential of the node B remains at V1. As a result, the transistor 103 remains off. Therefore, the wiring 122A and the node A remain in a non-conductive state. Since the potential is maintained at a high value, the transistor 101 remains on. The wiring 123B and the wiring 121 remain in a conductive state. At this time, when the signal S2 is at the L level, Then, since the wiring 123B and the wiring 121 remain in a conductive state, The potential of the wiring 121 starts to rise. At the same time, the transistor 102 is turned on. The node A and the wiring 121 are in a conductive state. However, the potential of the wiring 121 is different from the potential of the wiring 123C. (V2) minus the threshold voltage (Vth102) of the transistor 102 (V2-Vth When the potential of the wiring 121 rises to 102, the transistor 102 is turned off. The capacitor 105 is connected to the wiring 1 in the period T1. The potential difference between the node 21 and the node A is maintained. Therefore, the potential of the wiring 121 rises. Then, the potential of the node A becomes V2+Vth101+ due to the capacitive coupling of the capacitor 105. α (α is a positive number). This is the so-called bootstrap operation. Therefore, The potential of the wiring 121 becomes equal to the potential of the wiring 123B (the H level of the signal S2 or V1). It rises until

[0083] Note that in the period T2, the circuit 100 often does not supply a signal to the node A. Therefore, the circuit 100 and the node A are often in a non-conductive state. In many cases, node A is left floating.

[0084] Note that the circuit 100 may not supply a signal to the wiring 121 during the period T2. Therefore, there are many cases where the circuit 100 and the wiring 121 are not in electrical contact with each other.

[0085] Next, in a period T3, after the signal S2 falls from the H level to the L level, the circuit 100 decreases the potential of node A to V1. Therefore, the potential of node A is The sum of the potential (V1) of 123B and the threshold voltage (Vth101) of the transistor 101 (V1 +Vth101), the transistor 101 is on. The bell signal S2 is supplied from the wiring 123B to the wiring 121, so that the potential of the wiring 121 is Similarly, when the potential of the node A is decreased to the potential of the wiring 123B (V1), The sum of the potential (V1) of 22B and the threshold voltage (Vth104) of the transistor 104 (V1+ Vth104), the transistor 104 is on. Therefore, Since 1 is supplied to node B from the wiring 122B, the potential of node B remains at V1. As a result, the transistor 103 remains off, and the wiring 122A and the node A are not connected to each other. At this time, the capacitance element 106 is maintained at the potential of the wiring 123A (the L The potential difference between the potential (V1) of the wiring 122B and the potential (V1) of the wiring 122B is maintained.

[0086] Note that in the period T3, the circuit 100 applies the voltage V1 or an L-level signal to the wiring 121. Alternatively, the circuit 100 can supply a signal or the like to the wiring 121. By not providing the wiring 121, the circuit 100 and the wiring 121 can be brought out of electrical continuity. In the circuit 100, the wiring 121 can be in a floating state.

[0087] Next, in a period T4, the signal S2 rises from the L level to the H level. Since the potential of the node A remains at V1, the transistor 101 and the transistor 104 are off. Therefore, since node B remains floating, the potential of node B is The potential of the node B rises due to the capacitive coupling of the terminal 106. The sum of the threshold voltage (Vth103) of the transistor 103 (V1+Vth103) is higher than When the potential Vcc of the wiring 122A increases, the transistor 103 is turned on. Therefore, the voltage V1 is supplied to the node A from the wiring 122A. The potential of node A is maintained at V1. At the same time, transistor 102 is turned on, so that At this time, the voltage V1 is applied to the node A through the wiring 122. A is supplied to the wiring 121. Therefore, the voltage V1 is supplied to the wiring 121 from the wiring 122A. Therefore, the potential of the wiring 121 is maintained at V1.

[0088] During the period T4, the circuit 100 applies a voltage V1 or an L-level signal to the node A. Alternatively, the circuit 100 may not provide a signal to the node A. This makes it possible to put the circuit 100 and the node A in a non-conductive state. Circuit 100 allows node A to float.

[0089] Note that in the period T5, the circuit 100 applies the voltage V1 or an L-level signal to the wiring 121. Alternatively, the circuit 100 can supply a signal or the like to the wiring 121. By not providing the wiring 121, the circuit 100 and the wiring 121 can be brought out of electrical continuity. In the circuit 100, the wiring 121 can be in a floating state.

[0090] Next, in a period T5, the signal S2 decreases from the H level to the L level. Since the potential of the node A remains at V1, the transistor 101 and the transistor 104 are off. Therefore, the potential of the node B is decreased by the capacitive coupling of the capacitive element 106. The potential of the node B is the threshold voltage (V th103), the sum of V1 and Vth103 (V1+Vth103) of transistor 10 3 is turned off. Therefore, the wiring 122A and the node A are not electrically connected to each other. Since the transistor 102 is turned off, the wiring 121 and the node A are not in a conducting state. At this time, the circuit 100 supplies an L-level signal or a voltage V1 to the node A and the wiring 121. In this case, the potential of the node A and the potential of the wiring 121 are maintained at V1. When the L level signal or the voltage V1 is not supplied to the node A and the wiring 121, Since the node A and the wiring 121 are in a floating state, the potential of the node A and the wiring 121 The potential of is maintained at V1.

[0091] In the semiconductor device of FIG. 1A, the other electrode of the capacitor 106 is connected to a Therefore, the number of transistors connected to the other side of the capacitor 106 can be reduced. The parasitic capacitance connected to the electrode, that is, the parasitic capacitance of node B, can be reduced. Parasitic capacitance refers to the gate capacitance of a transistor, the parasitic capacitance between the gate and source of a transistor, Parasitic capacitance, such as the parasitic capacitance between the gate and drain of a transistor and / or wiring capacitance However, the present invention is not limited to this. , it is possible to connect multiple transistors.

[0092] Alternatively, in the semiconductor device of FIG. 1A, the parasitic capacitance of the node B can be reduced. The capacitance value of the capacitance element 106 can be made smaller than that of the conventional technology. Since the area where one electrode of 106 overlaps with the other electrode can be reduced, As a result, the layout area of ​​the capacitor element 106 can be reduced. This can prevent short circuits between the electrode and the other electrode caused by dust or the like. Therefore, the yield can be improved and the cost can be reduced. Since the load of 3A can be reduced, the signal input to the wiring 123A (for example, the signal S2) can be reduced. The current drive capacity of the external circuit can be reduced, making it possible to reduce the size of the external circuit. It can be reduced.

[0093] Alternatively, in the semiconductor device of FIG. 1A, the parasitic capacitance of the node B can be reduced. It is possible to increase the amplitude voltage of the node B when the potential of the wiring 123A changes. Therefore, in the period T4, the potential of the node B can be made higher than in the conventional technology. Therefore, the Vgs of the transistor 103 can be increased. Since the on-resistance of 3 can be reduced, the potential of node B is set to V1 during period T4. Alternatively, the channel width (W) of the transistor 103 can be reduced. Therefore, the layout area can be reduced.

[0094] In the semiconductor device in FIG. 1A, the transistor 102 is turned off during the period T2. Until this happens, the node A and the wiring 121 are often in a conductive state. Since the potential of A decreases, the gate voltages of the transistors 101 and 104 As a result, the characteristics of the transistor 101 and the transistor 104 can be reduced. Deterioration can be suppressed. The gate insulating film of the transistor can be prevented from being destroyed. A transistor with improved mobility can be used by making it thinner. When using a MOSFET, the channel width (W) of the transistor can be reduced. The layout area can be reduced.

[0095] Alternatively, in the semiconductor device of FIG. 1A, all the transistors are N-channel type, or All transistors can be P-channel type. Therefore, compared to CMOS circuits, This can reduce the number of steps, improve yield, and reduce costs. If all the transistors are N-channel type, the semiconductor layer of the transistors is a non-single-crystal A crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor can be used. Therefore, it is possible to reduce the number of steps, improve the yield, and reduce costs. However, the present invention is not limited to this, and the semiconductor device of FIG. 1A may be a P-channel transistor and an N It can be constructed using a CMOS circuit that combines a MOSFET with a channel type transistor. do.

[0096] Alternatively, in the semiconductor device of FIG. 1A, during at least one of the periods T4 and T5, Therefore, the transistors 101 to 104 are turned off. Since the transistor is not always on during the period, there are problems such as an increase in threshold voltage or a decrease in mobility. It is possible to suppress the deterioration of the characteristics.

[0097] In particular, the semiconductor layer of a transistor may be made of a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or In the case where an oxide semiconductor is used, the deterioration of the characteristics of the transistor becomes significant. In the semiconductor device of 1(A), the deterioration of the transistor characteristics can be suppressed, The semiconductor layer of the transistor may be a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor. A conductor can be used. However, the semiconductor layer is not limited to this. A polycrystalline semiconductor can be used as the semiconductor layer. Alternatively, a single crystal semiconductor can be used.

[0098] Note that period T2 is indicated as a selection period, and the other periods (period T1, period T3, period T4, and Periods T1, T2, and T5) can be referred to as non-selection periods. The periods T3, T4, and T5 are respectively a set period, an output period, a reset period, and a first It is possible to refer to this as the non-selection period and the second non-selection period.

[0099] The channel width (W) of the transistor 101 is 03 and / or the channel width of transistor 104. Among the transistors included in the semiconductor device, the channel width of the transistor 101 is the shortest. In this case, the on-resistance of the transistor 101 is small, so that The rise time and fall time of a signal (for example, signal S1) output from the wiring 121 Therefore, in the period T2, the timing at which the transistor 102 turns off is shortened. As a result, the potential of the node A may decrease too much, causing the semiconductor device to malfunction. However, the present invention is not limited to this, and the channel width of the transistor 101 can be suppressed. The channel width of any one of the transistors 102 to 104 or the semiconductor device is The channel width of any one of the transistors may be smaller than that of the other transistors.

[0100] In addition, when referring to the channel width of a transistor, this is the W / L (L: channel This can be rephrased as the ratio of the length of the tube to the length of the tube.

[0101] In addition, the L level of the signal input to the wiring 123A, the wiring 123B, and / or the wiring 123C The potential of the bell can be lower than V1. In this case, the transistor is reverse biased. Since it is possible to apply a voltage of 0.1 V to the transistor, the deterioration of the transistor characteristics can be reduced. In addition, since the transistor 102 is turned on for a long time, the signal input to the wiring 123C The potential of the L level is preferably lower than V1. However, this is not limited thereto. The potential of the L level of the signal input to the wiring 23A, the wiring 123B, and / or the wiring 123C is , it is possible that it is higher than V1.

[0102] In addition, the H level of the signal input to the wiring 123A, the wiring 123B, and / or the wiring 123C The potential of the bell can be lower than V2. In this case, the Vgs of the transistor is small. Since the resistance of the transistor is reduced, the deterioration of the transistor characteristics can be suppressed. Since the time when 02 is on is long, the H-level potential of the signal input to the wiring 123C is It is preferable that the voltage V is lower than V2. However, this is not limited to this. The potential of the H level of the signal input to the wiring 123B and / or the wiring 123C is higher than V2. It is possible.

[0103] The amplitude of the signal input to the wiring 123A, the wiring 123B, and / or the wiring 123C is The voltage can be less than V2-V1. In particular, when transistor 103 is on, Since the time when the voltage V2 is increased is long, the amplitude of the signal input to the wiring 123A is set to be smaller than V2-V1. In this way, it is possible to reduce the Vgs of the transistor 103. In this way, the deterioration of the characteristics of the transistor 103 can be suppressed. However, the present invention is not limited to this. , the amplitude voltage of the signal input to the wiring 123A, the wiring 123B, and / or the wiring 123C can be greater than V2-V1.

[0104] Note that a signal can be input to the wiring 122A and / or the wiring 122B. In this way, the voltage V1 can be omitted, and the number of power sources can be reduced. A reverse bias can be applied to the transistor, reducing the degradation of the transistor characteristics. In particular, the wiring 122A is connected to the transistor 103 during a period when the transistor 103 is turned on (e.g., For example, it is possible to input a signal that is at the L level during periods T1, T3, and T5. As an example, an inverted signal of the signal S2 (hereinafter, also referred to as an inverted clock signal) The wiring 122B is connected to a transistor 104 during a period in which the transistor 104 is turned on (for example, during a period T3, It is possible to input a signal that is at the L level during periods T4 and T5.

[0105] In addition, a voltage (for example, a voltage V2 ) can be supplied. By doing so, the semiconductor device can be used as an inverter circuit. Alternatively, it can function as a buffer circuit.

[0106] As shown in FIG. 3A, the same voltage (for example, In many cases, the pressure V1) is supplied to the wiring 122A and the wiring 122B. For this purpose, the first terminal of the transistor 103 and the second terminal of the transistor 104 are connected to each other. The first terminal is connected to the wiring 122. The wiring 122 is a wiring 122A or a wiring 122 B, and the same can be input to wiring 122. .

[0107] In addition, sharing a plurality of wirings means that elements or circuits connected to the plurality of wirings are connected to the same wiring. Alternatively, it refers to connecting a plurality of wirings to each other.

[0108] As shown in FIG. 3B, the same signal (for example, signal S 2) is often input, so that the wiring 123A to 123C can be shared. For this purpose, the first terminal of the transistor 101, the gate of the transistor 102, and the capacitor One electrode of the capacitance element 106 is connected to the wiring 123. The wiring 123 includes wirings 123A to 123C, and wiring 123 can be input with the same wiring. However, the present invention is not limited to this, and any two or more of the wirings 123A to 123C may be used. Only the wiring of the two circuits can be shared.

[0109] As in FIG. 3B, the wirings 123A to 123C are also shared in FIG. It is possible.

[0110] As shown in FIG. 3C, by combining FIG. 3A and FIG. 3B, a wiring 122 A and the wiring 122B can be shared, and further, the wirings 123A to 123C can be shared. For example, the first terminal of the transistor 103 and the first terminal of the transistor 104 are , the first terminal of the transistor 101, the second terminal of the transistor 102, and the wiring 122. The gate of the capacitor 106 and one electrode of the capacitor 106 can be connected to a wiring 123. do.

[0111] As shown in FIG. 3D, the gate of the transistor 104 is connected to the wiring 121. By connecting the gate of the transistor 104 to the wiring 121, When the transistor 104 is turned on, the gate voltage is V1. When the transistor 104 turns on, the gate voltage (V1+Vth101+α) is lower than this. Therefore, the dielectric breakdown of the transistor 104 or the deterioration of the characteristics of the transistor 104 can be prevented. It can be suppressed.

[0112] As in FIG. 3D, in FIGS. 3A to 3C, the gate of the transistor 104 is The port can be connected to wiring 121.

[0113] As shown in FIG. 3E, the second terminal of the transistor 103 is connected to the wiring 121. The second terminal of the transistor 103 can be connected to the wiring 121. Thus, during the period T4, the voltage V1 is supplied from the wiring 122A to the wiring 121. , the potential of the wiring 121 can be easily maintained at V1.

[0114] As in FIG. 3E, in FIGS. 3A to 3D, the second The terminal can be connected to a wiring 121.

[0115] As shown in FIG. 4A, the capacitor 105 can be omitted. The parasitic capacitance between the gate and the second terminal of the transistor 101 is used as the capacitance element 105. It is possible to do so.

[0116] In FIG. 4A, the capacitor 105 is a gate of the transistor 101 and a second When a parasitic capacitance between the gate and the second terminal of the transistor 101 is used, It is preferable that the parasitic capacitance between the gate and the first terminal is larger than the parasitic capacitance between the gate and the first terminal. Therefore, in the transistor 101, a conductive layer serving as a gate electrode and a The area of ​​the conductive layer functioning as a source electrode or a drain electrode is larger than that of the first terminal side. It is preferable that the second terminal side is larger, but this is not a limitation.

[0117] As in FIG. 4A, the capacitance element 105 is omitted in FIGS. 3A to 3E. It is possible to do so.

[0118] As shown in FIG. 4B, a MOS capacitor can be used as the capacitor 105. In the example shown in FIG. 4B, a transistor 105a is used as the capacitor 105. The transistor 105a is an N-channel type. The second terminal of the transistor 105a is connected to a wiring 121. The gate of the transistor 105a is connected to a node A. By doing so, the period during which it needs to function as a capacitive element (period In the periods T1 and T2, the potential of the node A is high, so that the gate capacitance of the transistor 105a is On the other hand, during the period when it is not necessary to function as a capacitive element (for example During periods T3, T4, and T5, the potential of the node A is low, so that the transistor 105 However, this is not limited to this, and the gate capacitance of the transistor 1 can be reduced. Alternatively, the first of the transistors 105a may be a P-channel type. One of the first terminal and the second terminal may be in a floating state. The gate of the transistor 105a is connected to the wiring 121, and the first and second terminals of the transistor 105a are connected to the wiring 121. The terminal of the transistor 105a can be connected to the node A. The channel region may be doped.

[0119] As in FIG. 4B, in FIGS. 3A to 3E and 4A, the capacitance element A transistor 105a is used as 105, and a first terminal and a second terminal of the transistor 105a are connected to each other. The terminal of the transistor 105a is connected to the wiring 121, and the gate of the transistor 105a is connected to the node A. It is possible.

[0120] As shown in FIG. 4C, a MOS capacitor can be used as the capacitor element 106. In the example of FIG. 4C, a transistor 106a is used as the capacitor 106. The transistor 106a is an N-channel type. The second terminal of the transistor 106a is connected to a node B, and the gate of the transistor 106a is connected to a wiring 123A. However, the present invention is not limited to this, and the transistor 106a is a P-channel type. Alternatively, one of the first terminal and the second terminal of the transistor 106a may be , or may be floating. Alternatively, the gate of transistor 106a may be connected to node B and a first terminal and a second terminal of the transistor 106a are connected to the wiring 123A. Alternatively, the channel region of the transistor 106a may be doped with impurities. It is possible.

[0121] As in FIG. 4(C), in FIGS. 3(A) to (E) and 4(A) to (B), A transistor 106a is used as the capacitor 106. A first terminal of the transistor 106a The second terminal of the transistor 106a is connected to a node B. The gate of the transistor 106a is connected to a wiring 123A. It is possible to be connected.

[0122] As shown in FIG. 4D, the transistor 103 is replaced with a diode 103a. The diode 103a corresponds to the transistor 103. When the potential of node B is lower than the potential of node A, the diode 103a When the potential of node B is higher than the potential of node A, the potential of node A is decreased. The diode 103a has a function of putting one terminal of the diode 103a (hereinafter referred to as , also referred to as an input terminal or anode) is connected to node A, and the other terminal of the diode 103a (hereinafter also referred to as the output terminal or the cathode) is connected to a node B.

[0123] In addition, in the case where the transistor 103 is replaced with the diode 103a in FIG. A voltage V2 can be supplied to the wiring 122B. It is possible to input an inverted signal of the signal S2 (for example, an inverted clock signal).

[0124] As in FIG. 4(D), in FIGS. 3(A) to (E) and 4(A) to (C), The transistor 103 is replaced with a diode 103a. One terminal of the diode 103a The other terminal of the diode 103a is connected to node A, and the other terminal of the diode 103b is connected to node B. It is possible.

[0125] As shown in FIG. 4E, the transistor 104 is replaced with a diode 104a. In the example of FIG. 4E, not only the transistor 104 but also the transistor The transistor 103 is replaced with a diode. The diode 104a corresponds to the potential node A of the potential node B. When the potential of node A is higher than the potential of node B, the potential of node B is increased. When the potential of the die is lower than that of the die, the die has a function of putting the nodes A and B into a non-conductive state. One terminal of the diode 104a is connected to the node A, and the other terminal of the diode 104a is Connected to Node B.

[0126] As in FIG. 4(E), in FIGS. 3(A) to (E) and 4(A) to (D), The transistor 104 is replaced with a diode 104a. One terminal of the diode 104a The other terminal of the diode 104a is connected to node A, and the other terminal of the diode 104b is connected to node B. It is possible.

[0127] As shown in FIG. 4(F), a diode-connected transistor is used as a diode. It is possible to use a diode-connected transistor 103 and a diode The connected transistors 104 correspond to the diodes 103a and 104a, respectively. A first terminal of the transistor 103 is connected to the node B. The second terminal and the gate of the transistor 104 are connected to the node A. The output of the transistor 102 is connected to node A, and the second terminal of the transistor 104 is connected to node B. However, this is not limited to this. The gate of the transistor 103 is connected to the node B. The gate of the transistor 104 may be connected to a node B.

[0128] As in FIG. 4(F), in FIGS. 3(A) to (E) and 4(A) to (E), A first terminal of the transistor 103 is connected to the node B, and a second terminal of the transistor 103 is connected to the node B. The gate of transistor 102 may be connected to node A, and the gate of transistor 103 may be connected to node A. Alternatively, the first terminal of the transistor 104 is connected to the node A, and the The second terminal of the transistor 104 is connected to a node B, and the gate of the transistor 104 is connected to a node A. However, the present invention is not limited to this, and the gate of the transistor 103 may be connected to the may be connected to node B, and the gate of transistor 104 may be connected to node B. It is.

[0129] As shown in FIG. 5A, a diode 107 can be newly added. When an L-level signal is input to the wiring 123A, the diode 107 When a signal of H level is input to the wiring 123A, the signal of H level is input to the wiring 123B. The diode 107 has a function of making the node 3A and the node B non-conductive. The other terminal of the diode 107 is connected to the wiring 123A. However, the other terminal of the diode 107 is not limited to this, and may be connected to a wiring other than the wiring 123A. It is possible to continue.

[0130] As in FIG. 5(A), in FIGS. 3(A) to (E) and 4(A) to (F), A diode 107 is newly added, and one terminal of the diode 107 is connected to node B. The other terminal of the diode 107 can be connected to the wiring 123A.

[0131] As shown in FIG. 5B, a diode-connected transistor 107a is newly added. The diode-connected transistor 107a can be added to the The first terminal of the transistor 107a corresponds to the line 123 and is an N-channel type. A, and the second terminal and the gate of the transistor 107a are connected to node B. However, the present invention is not limited to this, and the transistor 107a may be a P-channel type. Alternatively, the gate of the transistor 107a may be connected to the wiring 123A. It is Noh.

[0132] As with FIG. 5(B), FIGS. 3(A) to (E), 4(A) to (F), and 5(A) In the above, a transistor 107a is newly added, and the first terminal of the transistor 107a the second terminal and the gate of the transistor 107a are connected to the node B. However, the present invention is not limited to this, and the gate of the transistor 107a may be connected to the It is possible for multiple ports to be connected to the Node B.

[0133] As shown in FIG. 5C, the transistor 102 can be omitted.

[0134] As with FIG. 5(C), FIGS. 3(A) to (E), 4(A) to (F), and 5(A) In the cases 1 to 3, the transistor 102 can also be omitted.

[0135] As shown in FIG. 5D, the circuit 100 can be omitted.

[0136] As with FIG. 5(D), FIGS. 3(A) to 3(E), 4(A) to 4(F), and FIG. 5(A) In the cases of 1) to (C), the circuit 100 can also be omitted.

[0137] As shown in FIG. 5E, the transistor 101, the transistor 102, The transistor 103 and the transistor 104 are the transistors 101p, 102p, The transistors 103p and 104p can be replaced with each other. The resistors 101p to 104p correspond to the transistors 101 to 104, respectively, and are P-channel It is assumed to be of type.

[0138] In FIG. 5E, the relationship of potentials is reversed from that of the semiconductor device in FIG. For example, a voltage V2 is supplied to the wirings 122A to 122B, and An inverted signal of the signal S2 can be input to the wiring 121B. In many cases, an inverted signal of signal S1 is output from the

[0139] In FIG. 5E, the circuit 100 reduces the potential of the node A in the period T1. Alternatively, in the period T3, the circuit 100 may have a function of reducing the potential of the node A. In many cases, it has the function of increasing V to V2.

[0140] As with FIG. 5(E), FIGS. 3(A) to (E), 4(A) to (F), and FIG. 5(A) In the diagrams (D) and (D), the transistors 101 to 104 are P-channel transistors. It is possible to use:

[0141] (Embodiment 2) In this embodiment, an example of a semiconductor device will be described. This is a specific example of the semiconductor device described in the first embodiment. A specific example of the circuit 100 will be described. Note that the contents described in the first embodiment are the same as those in the present embodiment. The present invention can be applied to the semiconductor device of the embodiment.

[0142] A specific example of the circuit 100 will be described with reference to FIG. 6(A). The circuit 100 may have various configurations other than that shown in FIG. The circuit shown in FIG. 1(A) is the same as that shown in FIG. The explanation will be omitted.

[0143] The circuit 100 includes a transistor 131, a transistor 132, a transistor 133, a transistor The transistors 131 to 135 are However, the transistors 131 to 135 are P-channel. It is possible for the shape to be a type.

[0144] The connections of the transistors in the circuit 100 will be described. A first terminal of the transistor 131 is connected to the wiring 125, and a second terminal of the transistor 131 is connected to the node A. The gate of the transistor 131 is connected to the wiring 125. The first terminal of the transistor 132 is connected to the wiring 125, and the second terminal of the transistor 132 is connected to the node A. The gate of the transistor 132 is connected to the wiring 124A. The first terminal of the transistor 133 is connected to the wiring 121. The gate of the transistor 133 is connected to the wiring 124B. A first terminal of the transistor 134 is connected to the wiring 122C, and a second terminal of the transistor 134 is connected to the node A. The gate of the transistor 135 is connected to the wiring 126. A first terminal of the transistor 135 is connected to the wiring 122D, and a second terminal of the transistor 135 is connected to the wiring 121. The gate of the transistor 135 is connected to the wiring 126 .

[0145] Input to wiring 122C to 122E, wiring 124A to 124B, wiring 125, and wiring 126 An example of what can be detected (e.g., a signal, a voltage, or a current) will be described. However, the following is an example and is not intended to be limiting. It is possible to input various things other than the above, and each wiring can be left floating (hereafter referred to as floating). It is possible to set the state to "on-loading state."

[0146] The voltage V1 is supplied to the wirings 122C to 122E in the same manner as the wirings 122A and 122B. Therefore, the wirings 122C to 122E function as power supply lines. However, the present invention is not limited to this. For example, a clock signal or the like may be transmitted to the wirings 122C to 122E. In this case, the wirings 122C to 122E are used as signal lines. Alternatively, the wirings 122C to 122E can be supplied with different voltages. It is possible to provide

[0147] As an example, it is assumed that a signal S3 is input to the wirings 124A and 124B. Thus, the wirings 124A to 124B can function as signal lines. In most cases, this is an inverted signal of signal S2, or a signal whose phase is shifted by approximately 180° from signal S2. It can also function as an inverted clock signal (CKB). In this case, a voltage can be supplied to the wirings 124A and 124B. The lines 124A to 124B can function as power supply lines. It is possible to input different signals to 124A to 124B.

[0148] As an example, a signal S4 is input to the wiring 125. The signal S4 has an L level and an H level. It is often a digital signal that transmits a start signal (SP), a transfer signal from another row (stage), Alternatively, the signal may function as a signal for selecting another row. In this case, the wiring 125 functions as a power supply line. It is possible.

[0149] As an example, a signal S5 is input to the wiring 126. The signal S5 has an L level and an H level. This is often a digital signal that selects a row, resets the row (RE), or selects another row. However, the present invention is not limited to this, and the wiring 126 can be supplied with a voltage. In this case, the wiring 126 can function as a power supply line.

[0150] An example of the functions of the transistors 131 to 135 will be described. The above is merely an example, and the present invention is not limited to this. In addition to the functions described above, it is possible for the device to have various other functions, and it may not have the functions described below. It is also possible.

[0151] The transistor 131 is turned on or off in response to a signal (for example, a signal S4) input to the wiring 125. The transistor 132 has a function of increasing the potential of the node A and functions as a diode. In response to a signal (for example, signal S3) input to the wiring 124A, the wiring 125 and the node A The transistor 1 has the function of controlling the timing at which the transistor 1 is turned on, and functions as a switch. 33 is connected to the wiring 122E in response to a signal (for example, the signal S3) input to the wiring 124B. It has a function of controlling the timing of electrical continuity between the line 121 and the transistor 122, and functions as a switch. The transistor 134 changes the value of the line 126 in response to a signal (for example, the signal S5) input to the line 126. It has the function of controlling the timing of conduction between 2C and node A, and functions as a switch. The transistor 135 is connected in response to a signal (for example, a signal S5) input to the wiring 126. It has a function of controlling the timing at which the line 122D and the wiring 121 are electrically connected, and acts as a switch. It works.

[0152] Next, the operation of the semiconductor device of FIG. 6(A) will be described with reference to FIG. 6(B), FIGS. 7(A) to 7(C), and The description will be made with reference to FIGS. 8(A) and (B). FIG. 6(B) is a diagram for explaining the operation of the semiconductor device. 1 is an example of a timing chart for performing the above-mentioned operation. 7A is a diagram illustrating the operation of the semiconductor device of FIG. FIG. 7B is a schematic diagram showing the operation of the semiconductor device in FIG. 7C is a schematic diagram showing the operation of the semiconductor device in FIG. 6A in the period T3. FIG. 8A is a schematic diagram showing the operation of the semiconductor device of FIG. 6A during the period T4. 6B) is a schematic diagram showing the operation of the semiconductor device of FIG. 6A during the period T5. The description of the operation common to that of the semiconductor device of A) will be omitted.

[0153] First, in a period T1, the signal S5 is at an L level, so that the transistors 134 and The transistor 135 is turned off. Therefore, the wiring 122C and the node A are not electrically connected to each other. At the same time, the signal S3 and the signal S4 are Since the output of the transistor 131, the transistor 132, and the transistor 13 3 is turned on. Then, the wiring 125 and the node A are brought into electrical continuity, and the wiring 122E and Therefore, the signal input to the wiring 125 (the signal S 4) is supplied to node A from the wiring 125, so that the potential of node A starts to rise. Then, the wiring 122E and the wiring 121 are in a conductive state, so that the voltage V1 is distributed from the wiring 122E. Then, the potential of the node A is changed from the H level potential (V1) of the signal S4 to the H level potential (V2) of the signal S5. The value obtained by subtracting the threshold voltage (Vth131) of the transistor 133 from the When the potential of node A rises to the level of signal The threshold voltage (Vth132) of the transistor 132 is subtracted from the H level potential (V1) of the S3. When the voltage rises to the set value (V1-Vth132), the transistor 132 turns off. When the transistors 131 and 132 are turned off, a charge is supplied to the node A. Therefore, the potential of node A is high (at least V1+Vth101 or more). ), and node A is in a floating state. For convenience, the potential of node A is When V1-Vth131, the transistor 131 and the transistor 132 are turned off. Therefore, the wiring 125 and the node A are not electrically connected to each other. The potential at node A remains at V1-Vth131, and node A is in a floating state.

[0154] Next, during a period T2, the signal S4 goes to the L level, so that the transistor 131 is turned off. Then, the signal S3 goes to the L level, so the transistor 132 remains off. Therefore, the transistor 133 is turned off. Therefore, the wiring 125 and the node A are not electrically connected to each other. The signal S5 remains in the non-conductive state, and the wiring 122E and the wiring 121 are not electrically connected to each other. remains at the L level, so the transistors 134 and 135 remain off. Therefore, the wiring 122C and the node A remain in a non-conducting state, and the wiring 122D and The line 121 remains in a non-conductive state.

[0155] Next, during a period T3, the signal S4 remains at the L level, so the transistor 131 is turned off. Then, the signal S5 goes to the H level, so that the transistors 134 and Then, the wiring 122C and the node A are brought into a conductive state, and the wiring The line 122D and the wiring 121 are in a conductive state. As the voltage V1 is applied to node A, the voltage at node A decreases to V1. is supplied from the wiring 122D to the wiring 121, so that the potential of the wiring 121 becomes V1. At the same time, the signal S3 goes to H level, so that the transistors 132 and Then, the wiring 125 and the node A are brought into a conductive state, and the wiring 12 2E and the wiring 121 are brought into a conductive state. Therefore, the signal S4 at the L level is supplied to the node A. As a result, the potential of node A decreases to V1. , the potential of the wiring 121 decreases to V1.

[0156] Next, during a period T4, the signal S4 remains at the L level, so the transistor 131 is turned off. Then, the signal S5 goes to the L level, so that the transistors 134 and The transistor 135 is turned off. Therefore, the wiring 122C and the node A are not electrically connected to each other. The wiring 122D and the wiring 121 are not electrically connected to each other. At this time, the signal S4 becomes L level. Therefore, the transistor 132 and the transistor 133 are turned off. and the node A are brought out of electrical continuity, and the wiring 122E and the wiring 121 are brought out of electrical continuity.

[0157] Next, during a period T5, the signal S4 remains at the L level, so the transistor 131 is turned off. Since the signal S5 remains at the L level, the transistors 134 and The transistor 135 remains off. Therefore, the wiring 122C and the node A are not electrically connected to each other. The wiring 122D and the wiring 121 remain in a non-conductive state. Since S4 is at H level, the transistor 132 and the transistor 133 are turned on. Then, the wiring 125 and the node A are brought into electrical continuity, and the wiring 122E and the wiring 121 are brought into electrical continuity. Therefore, the signal S4 at the L level is supplied to the node A from the wiring 125. Similarly, the voltage V1 is applied from the wiring 122E to the wiring 121 , the potential of the wiring 121 is maintained at V1.

[0158] In the semiconductor device of FIG. 6A, a signal of an L level is applied to the node A during the periods T4 and T5. Alternatively, the voltage V1 is supplied, so that the noise at the node A can be reduced. The operation can be prevented.

[0159] Alternatively, in the semiconductor device in FIG. 6A, the transistor 131 and the transistor Since both the transistor 132 and the transistor 133 are turned on, the potential at the node A can be increased quickly. Alternatively, the channel width of the transistor 131 or the channel width of the transistor 132 is reduced. It can be made easier.

[0160] Note that the channel width of the transistor 131 is The channel width of the transistor 103 can be larger than that of the transistor 13. The channel width of transistor 134 or the channel width of transistor 103 is In the period T2, the potential of the node A can be larger than the width of the loop. It is preferable that the potential at the node A increases faster, and it is preferable that the potential at the node A decreases slower in the period T3. In other words, if the potential of the node A rises quickly in the period T2, the driving frequency It is possible to improve the wave number, suppress the through current, and reduce the power consumption. In 3, if the potential of the node A decreases slowly, the on-time of the transistor 101 becomes longer. Therefore, by shortening the fall time of the signal (for example, the signal S1) output from the wiring 121, Therefore, the transistor having the function of increasing the potential of the node A in the period T2 can be used. The channel width of the transistor is such that the potential of node A decreases during period T3. However, it is not limited to this, and the channel width of the transistor 1 is preferably larger than that of the transistor 2. The channel width of transistor 31 is the same as the channel width of transistor 134 or the channel width of transistor 103. Similarly, the channel width of transistor 132 can be smaller than the channel width of transistor 132. The channel width of the transistor 134 is smaller than the channel width of the transistor 103. is possible.

[0161] The sum of the channel width of the transistor 131 and the channel width of the transistor 134 is The channel width of the transistor 134 is larger than the channel width of the transistor 103. This is possible because, during the period T2, the signal S4 at the H level is The line 12 is connected to the transistor 132 through two transistors connected in parallel. 5 to the node A. However, this is not limited to this, and the transistor 131 The sum of the channel width of the transistor 134 and the channel width of the transistor 134 is It is possible that the width of the gate electrode 104 is smaller than the width of the gate electrode 104 or the channel width of the transistor 103.

[0162] The channel width of the transistor 134 is smaller than the channel width of the transistor 133. Similarly, the channel width of transistor 132 can be Similarly, the channel width of transistor 103 can be smaller than that of can be smaller than the channel width of the transistor 102 because the wiring 1 The load of 21 (e.g., wiring resistance, parasitic capacitance, connected transistors, etc.) is Therefore, when a signal or voltage is supplied to node A, The channel width of the transistor that has the function of supplying a signal or a voltage to the wiring 121 is It is preferable that the width of the transistor is smaller than the channel width of the transistor. However, this is not limited to this. The channel width of transistor 134 may be greater than the channel width of transistor 133. Similarly, the channel width of transistor 132 is Similarly, the channel width of transistor 103 can be greater than the It is possible that the width of the channel of the resistor 102 is larger than that of the resistor 102 .

[0163] The channel width of the transistor 103 is larger than the channel width of the transistor 132. This is because the transistor 103 reduces the voltage of the node A during the period T4. The transistor 132 has the function of maintaining the potential at V1 during the period T5. This is because the potential of the node A is maintained at V1. The signal input to the line 123B (for example, the signal S2) becomes H level. At this time, the node A When the potential of the wiring 121 increases and the transistor 101 is turned on, the potential of the wiring 121 increases. Therefore, the transistor 103 maintains the potential of the node A at V1, and the transistor Since it is desired to keep resistor 101 off, the channel of transistor 103 On the other hand, in the period T5, the signal (e.g., For example, the signal S2) is at the L level, so that even if the transistor 101 is turned on, the line 121 In other words, even if the potential of the node A rises or falls from V1, the potential of the wiring 12 Therefore, the on-resistance of the transistor 132 needs to be reduced. Since the channel width of transistor 132 is small, it is preferable that the channel width of transistor 132 is small. The channel width of the transistor 103 is not limited to the above, and may be larger than the channel width of the transistor 132. Because the transistor 132 is The channel of the transistor 132 is connected to the ground potential Vout. By increasing the width, the potential of node A can be increased more quickly.

[0164] The channel width of the transistor 102 is smaller than the channel width of the transistor 133. This is because if the channel width of the transistor 102 is made too large, In the period T2, the potential of the node A decreases too much, which may cause the semiconductor device to malfunction. Specifically, both the transistor 102 and the transistor 133 are connected to the wiring 1. However, in the period T2, the potential of the wiring 121 is changed to V1. The potential of the wiring 123C is changed from the potential (V1) to the threshold voltage (Vth102) of the transistor 102. The transistor 102 remains on until the voltage Vth rises to the subtracted value (V1-Vth102). Therefore, in order to prevent the potential of node A from decreasing too much during period T2, The channel width of the transistor 102 is preferably small. The channel width of the wiring 121 is preferably large in order to maintain the potential of the wiring 121 at V1. However, the channel width of the transistor 102 is not limited to this. This is because in the period T4, the signal S2 is at the H level. This is because there is a high possibility that the potential of the wiring 121 will increase when the transistor By increasing the channel width of the transistor 102, the increase in the potential of the wiring 121 is suppressed. Because it's easier to do.

[0165] As in the first embodiment, the wiring 124A, the wiring 124B, the wiring 125, and / or The L level potential of the signal input to the wiring 126 can be lower than V1. Since the transistors 132 and 133 are turned on for a long time, the wiring 12 The potential of the L level of the signal input to the wiring 124A and the wiring 124B is preferably lower than V1. I wish.

[0166] As in the first embodiment, the wiring 124A, the wiring 124B, the wiring 125, or the wiring 12 The potential of the H level of the signal input to the transistor 6 can be lower than V2. The transistor 132 and the transistor 133 are easily deteriorated. It is preferable that the H level potential of the signal input to 124B is lower than V2.

[0167] As in the first embodiment, a signal is applied to the wiring 122C, the wiring 122D, or the wiring 122E. For example, the wiring 122C is connected to a transistor 134 that is turned on. It is possible to input a signal that is at L level during a period (for example, period T3) in which the Examples of the signal include the signal S2 and the signal S4. It is possible to input a signal that is at L level during the period when 5 is on (for example, during period T3). Examples of such a signal include a signal S2 or a signal S4. During the period when the transistor 133 is turned on (for example, the period T1, the period T3, and the period T5), As an example, the signal S2, the signal S3, etc. be.

[0168] Note that in FIG. 13C, as an example, the first terminal of the transistor 103 is connected to the wiring 124B. a first terminal of the transistor 104 is connected to the wiring 126, and a second terminal of the transistor 1 A first terminal of a transistor 133 is connected to the wiring 123A, and a first terminal of a transistor 134 is connected to the wiring 1 23A, and the first terminal of transistor 135 is connected to wiring 123A. However, the present invention is not limited to this configuration. 4A or the wiring 125. Alternatively, the first 1, the first terminal of transistor 134, or the first terminal of transistor 135. It can be connected to the wiring 121, the wiring 123B, the wiring 123C, or the wiring 126. do.

[0169] As in the first embodiment, the wiring 124A, the wiring 124B, and / or the wiring 126 It is possible to supply a voltage (for example, voltage V1 or voltage V2). Therefore, the semiconductor device can function as an inverter circuit or a buffer circuit. become.

[0170] As shown in FIG. 9A, the same signal (for example, For example, a signal S3 is input, so that the wiring 124A and the wiring 124B can be shared. For this reason, the gate of the transistor 132 and the gate of the transistor 133 are The wiring 124 is connected to the wiring 124. The wiring 124 corresponds to the wiring 124A or the wiring 124B. It is possible to input wiring similar to these.

[0171] FIG. 9(C) shows a configuration in which FIG. 3(C) and FIG. 9(A) are combined. For example, the first terminal of the transistor 101, the gate of the transistor 102, and the capacitor 1 One electrode of the transistor 132 is connected to the wiring 123. The gate of the transistor 133 is connected to the wiring 124. , the first terminal of transistor 104, the first terminal of transistor 133, A first terminal of the transistor 34 and a first terminal of the transistor 135 are connected to the wiring 122 .

[0172] As shown in FIG. 9C, the gate of the transistor 131 is connected to the wiring 127. It is possible to supply a voltage V2 to the wiring 127, for example. However, the wiring 127 can function as a current line. For example, the input to the wiring 127 is The signal to be output is at H level during period T1 and at L level during period T2. Therefore, it is possible to input the signal S3 to the wiring 127. In this case, the wiring 1 27 can be connected to the wiring 124A or the wiring 124B and serves as a signal line. It is possible to function.

[0173] In FIG. 9C, the gate of the transistor 131 is connected to the wiring 127. For example, the first terminal of the transistor 131 may be connected to the wiring 127. The gate of the transistor 131 can be connected to the wiring 125.

[0174] As in FIG. 9C, in FIGS. 9A to 9B, the gate of the transistor 131 is The port can be connected to wiring 127.

[0175] As shown in FIG. 10A, the transistor 131 can be omitted. Even if the transistor 131 is omitted, the transistor 132 is turned on during the period T1. Therefore, the potential at node A rises.

[0176] As in FIG. 10(A), the transistor 131 is omitted in FIGS. 9(A) to 9(C). It is possible to omit it.

[0177] As shown in FIG. 10B, the transistor 132 can be omitted. Even if the transistor 132 is omitted, the node A is in a floating state during the period T5. The potential of node A is maintained at V1.

[0178] As in FIG. 10(B), the trajectory is also shown in FIGS. 9(A) to 9(C) and FIG. 10(A). It is possible to omit the resistor 132.

[0179] As shown in FIG. 10C, the transistors 134 and 135 are omitted. Alternatively, one of the transistors 134 and 135 may be omitted. Even if the transistor 134 is omitted, the transistor As transistor 132 turns on, the potential at node A decreases to V1. Even if the transistor 135 is omitted, the transistor 133 is turned on during the period T3. Therefore, the potential of the wiring 121 decreases to V1.

[0180] As in FIG. 10(C), in FIGS. 9(A) to (C) and 10(A) to (B), Also, the transistors 134 and 135 may be omitted.

[0181] As shown in FIG. 11A, the transistor 133 can be omitted. Even if the transistor 133 is omitted, the wiring 121 is in a floating state during the period T5. The potential of the wiring 121 is maintained at V1.

[0182] As in FIG. 11(A), in FIGS. 9(A) to (C) and 10(A) to (C), Also, the transistor 133 may be omitted.

[0183] As shown in FIG. 11B, the transistor 102 can be omitted. Even if the transistor 102 is omitted, the wiring 121 is in a floating state during the period T4. The potential of the wiring 121 is maintained at V1.

[0184] As in FIG. 11B, FIGS. 9A to 9C, 10A to 10C, and 11 In (A) as well, the transistor 102 can be omitted.

[0185] As shown in FIG. 11C, the transistor 103, the transistor 104, and the capacitor It is possible to omit element 106. Transistors 103, 104, and Even if the capacitor 106 is omitted, the wiring 121 is in a floating state during the period T4. The potential of the wiring 121 is maintained at V1.

[0186] As with FIG. 11(C), FIGS. 9(A) to (C), 10(A) to (C), and FIG. In (A) and (B), the transistor 103, the transistor 104, and the capacitor element 1 The 06 can be omitted.

[0187] As shown in FIG. 12A, the transistor 133 may be replaced with a diode 133a. The diode 133a corresponds to the transistor 133. When an L-level signal is input to the wiring 124B, the terminal 133a changes the potential of the wiring 121. When a signal of H level is input to the wiring 124B, and the wiring 121 in a non-conductive state. The other terminal of the diode 133a is connected to the wiring 121. The terminal (hereinafter also referred to as an output terminal or a cathode) is connected to the wiring 124B.

[0188] In addition, in FIG. 12A, when the transistor 133 is replaced with a diode 133a, In this case, the signal S2 can be input to the wiring 124B. The wiring 124B is connected to the lines 123A to 123C, and the wiring 124B shares the lines 123A to 123C. It is possible.

[0189] As in FIG. 12(A), FIGS. 9(A) to 9(C), 10(A) to 10(C), and 11 In (A) to (C), the transistor 133 is replaced with a diode 133a. One terminal of the diode 133a is connected to the wiring 121, and the other terminal of the diode 133a is connected to the wiring 121. can be connected to wiring 124B.

[0190] As shown in FIG. 12B, the transistor 133 can be diode-connected. The diode-connected transistor 133 corresponds to the diode 133a. A first terminal of the transistor 133 is connected to the wiring 124B. The terminal of the transistor 133 is connected to the wiring 121. However, the present invention is not limited to this. The gate of the transistor 133 is connected to the wiring 124B. It is possible to do so.

[0191] As in FIG. 12(B), FIGS. 9(A) to (C), 10(A) to (C), and 11(A 12A, the first terminal of the transistor 133 is connected to the wiring 12. 4B, a second terminal of the transistor 133 is connected to the wiring 121, and the transistor The gate of the transistor 133 can be connected to the wiring 121. However, this is not limited to the above. First, the gate of the transistor 133 can be connected to the wiring 124B.

[0192] As shown in FIG. 12C, the transistor 134 may be replaced with a diode 134a. , the transistor 135 can be replaced by a diode 135a. Diode 134a corresponds to transistor 134, and diode 135a corresponds to transistor 135. When an L-level signal is input to the wiring 126, the diode 134a A function of decreasing the potential of the node A and a function of decreasing the potential of the node A when an H-level signal is input to the wiring 126. The diode 135a has a function of turning off electrical continuity between the wiring 126 and the node A. A function of decreasing the potential of the wiring 121 when an L-level signal is input to the line 126; and When a signal of H level is input to the wiring 126, the wiring 126 and the wiring 121 are not electrically connected to each other. One terminal of the diode 134a (hereinafter referred to as an input terminal or an anode) The other terminal of the diode 134a (hereinafter, referred to as an output terminal or The cathode of the diode 135a is connected to the wiring 126. The output terminal or anode) of the diode 135a is connected to the wiring 121, and the other terminal ( Hereinafter, the output terminal (also referred to as the cathode) is connected to a wiring 126 .

[0193] In FIG. 12C, the transistors 134 and 135 are diodes. In this case, for example, an inverted signal of the signal S5 is input to the wiring 126. It is possible.

[0194] In FIG. 12C, only one of the transistors 134 and 135 is It is possible to replace it with a diode.

[0195] As in FIG. 12(C), FIGS. 9(A) to (C), 10(A) to (C), and 11(A 12(A)-(B), the transistor 134 is replaced with a diode 1 34a, one terminal of the diode 134a is connected to the node A, and the diode The other terminal of the transistor 134a can be connected to the wiring 126. The capacitor 135 is replaced with a diode 135a, and one terminal of the diode 135a is connected to the wiring 12. 1, and the other terminal of the diode 135a can be connected to the wiring 126. be.

[0196] As shown in FIG. 13A, the transistor 134 and the transistor 135 are connected to a die. A diode-connected transistor 134 and a diode The diodes 134a and 135a are connected to the diodes 134a and 135a. A first terminal of the transistor 134 is connected to the wiring 126. The second terminal of transistor 34 is connected to node A, and the gate of transistor 134 is connected to node A. The first terminal of the transistor 135 is connected to the wiring 126. A second terminal of the transistor 135 is connected to the wiring 121, and a gate of the transistor 135 is , and is connected to the wiring 121. However, this is not limited thereto. , and the gate of the transistor 135 can be connected to the wiring 126. It is possible to connect to 6.

[0197] As in FIG. 13(A), FIGS. 9(A) to (C), 10(A) to (C), and 11(A) 12(A) to (C), the first terminal of the transistor 134 is A second terminal of the transistor 134 is connected to the wiring 126, and a second terminal of the transistor 134 is connected to the node A. The gate of the transistor 134 can be connected to node A. A first terminal of the transistor 135 is connected to the wiring 126, and a second terminal of the transistor 135 is connected to the wiring 1 21, and the gate of the transistor 135 can be connected to the wiring 121. However, the present invention is not limited to this. The gate of the transistor 134 is connected to the wiring 126. The gate of the transistor 135 may be connected to the wiring 126. It is Noh.

[0198] As shown in FIG. 13B, a transistor 137 and a transistor 138 are newly added. The transistors 137 and 138 are N-channel transistors. However, the transistor 137 and the transistor The first end of the transistor 137 may be a P-channel type. The first terminal of the transistor 137 is connected to the wiring 121. The gate of the transistor 137 is connected to the wiring 128. A first terminal of the transistor 138 is connected to the wiring 122G, and a second terminal of the transistor 138 is connected to the node A. The gate of the transistor 138 is connected to the wiring 128. As an example, a signal S6 is input. Therefore, the wiring 128 functions as a signal line. The signal S6 is a digital signal having an H level and an L level. In many cases, it can function as, for example, a reset signal for all stages. As an example, a voltage V1 is supplied to the wiring 122G. The wiring 122F and the wiring 122G can function as a power supply line. In this case, the first transistor 137 may be shared. The terminal and the first terminal of the transistor 138 are connected to the wiring 122 as shown in FIG. However, the wiring 128, the wiring 122F, and the wiring 122G are It is possible to input various things such as current, voltage, and signals.

[0199] In FIG. 13B, the signal S6 is in a period before the semiconductor device starts to operate. Alternatively, the semiconductor device shown in FIG. When used in a register, the signal S6 is turned on for a period before the shift register begins scanning. Or, it can be at H level during the period after the shift register finishes scanning. Therefore, the signal S6 may be a start pulse for the shift register or However, in this embodiment, the output signal of the final stage of the transistor can be used. is not limited to this.

[0200] In FIG. 13B, only one of the transistors 137 and 138 is It is possible to add new ones.

[0201] As in FIG. 13(B), FIGS. 9(A) to (C), 10(A) to (C), and 11(A 12(A) to (C), and FIG. 13(A). A first terminal of the transistor 137 is connected to the wiring 122F. A second terminal of the transistor 137 is connected to the wiring 121, and a gate of the transistor 137 is connected to the wiring 1 28. Alternatively, a transistor 138 may be newly added and A first terminal of the transistor 138 is connected to the wiring 122G, and a second terminal of the transistor 138 is connected to the wiring 122G. The gate of the transistor 138 may be connected to the wiring 128. It is Noh.

[0202] (Embodiment 3) In this embodiment, an example of a shift register will be described. The semiconductor device may include the semiconductor device according to the first embodiment and the second embodiment. In this embodiment, the shift register can be referred to as a semiconductor device or a gate driver. The contents described in the first and second embodiments are based on the shift register of the present embodiment. It is possible to apply

[0203] First, an example of a shift register will be described with reference to FIG. The data bus 220 includes wirings 201_1 to 201_N (N is a natural number), a wiring 202, a wiring 203, It is connected to wiring 204 , wiring 205 , and wiring 206 .

[0204] The wiring 202 is the same as the wiring 123 (wiring 12) described in the first and second embodiments. 3A to 123C), or wiring 124 (wirings 124A to 124B), The wiring 202 can function as a clock signal line. The signal GS2 is input from the It corresponds to the signal S2 or the signal S3 described in the second embodiment and functions as a clock signal. is possible.

[0205] The wiring 203 is the same as the wiring 123 (wiring 12) described in the first and second embodiments. 3A to 123C), or wiring 124 (wirings 124A to 124B), The wiring 203 can function as a clock signal line. The signal GS3 is input from the This corresponds to the signal S2 or signal S3 described in the second embodiment and functions as an inverted clock signal. It is possible.

[0206] The wiring 204 is the same as the wiring 122 (wiring 12) described in the first and second embodiments. 2A to 122G) and can function as a power supply line. 4 is supplied with a voltage V1 from a circuit 221.

[0207] The wiring 205 corresponds to the wiring 125 described in the first and second embodiments. The wiring 205 can function as a signal line. The signal GS4 is input as in the first and second embodiments. The signal S4 corresponds to the start signal (hereinafter, start pulse) or vertical sync signal S5. It can function as a signal.

[0208] The wiring 206 corresponds to the wiring 126 described in the first and second embodiments. The wiring 206 can function as a signal line. The signal GS5 is input as in the first and second embodiments. This corresponds to signal S5 described below and can function as a reset signal.

[0209] However, the present invention is not limited to this, and various types of wiring such as signals, voltages, or currents may be used for the wirings 202 to 206. It is possible to input anything and leave each wire in a floating state.

[0210] As shown in FIG. 6C, the signal S2 or the signal S3 is an unbalanced clock signal. In this case, as an example, the signal S3 is expressed as follows with respect to the signal S2: It is possible to make the phase shift by 180 degrees. When the semiconductor device is used in a shift register, a selection signal for a certain stage is This can prevent the selection signal from overlapping with the selection signal.

[0211] The wirings 201_1 to 201_N are the wirings described in the first and second embodiments. 121 and can function as a gate line or a scanning line. Signals GS1_1 to GS1_N are output from 201_1 to 201_N, respectively. GS1_1 to GS1_N are signals S1 and can function as an output signal, a selection signal, a scan signal, or a gate signal. be.

[0212] As shown in FIG. 14B, the signals GS1_1 to GS1_N are For example, when the signal GS1_i-1 (where i is one of 1 to N) is at the H level, Then, when the signals GS2 and GS3 are inverted, the signal GS1_i -1 goes to L level, and signal GS1_i goes to H level. Then, signals GS2 and When the signal GS3 is inverted, the signal GS1_i becomes L level and the signal GS1_i+1 becomes H level. In this way, the signals GS1_1 to GS1_N become H level in order. Then, the wirings 201_1 to 201_N are selected in order.

[0213] The circuit 221 supplies a signal or a voltage to the shift register 220. 0 and can function as a control circuit or controller. In this embodiment, the circuit 211 includes a wiring 202, a wiring 203, a wiring 204, and a wiring 205. 05, and the wiring 206 are respectively connected to a signal GS2, a signal GS3, a voltage V1, a signal GS4, and a signal GS5. However, the shift register 220 is not limited to this. It is possible to supply signals, currents, or voltages to various circuits and control these circuits. For example, the circuit 221 may be a signal line driver circuit, a scanning line driver circuit, and / or a pixel It is possible to supply a signal or voltage to the circuits, etc., to control these circuits.

[0214] The circuit 221 includes, for example, a circuit 222 and a circuit 223. It has the function of generating power supply voltages such as positive power supply voltage, negative power supply voltage, ground voltage, and reference voltage. The circuit 223 can function as a clock, a power supply circuit, or a regulator. clock signal, inverted clock signal, start signal, reset signal, and / or video signal, etc. It has the function of generating various signals and can function as a timing generator. However, the present invention is not limited to this. In addition to the circuit 222 and the circuit 223, the circuit 221 may include For example, the circuit 221 may include an on Silencing, level shift circuit, inverter circuit, buffer circuit, DA conversion circuit, AD conversion Circuits, operational amplifiers, shift registers, lookup tables, coils, transistors, capacitors The input may include a capacitance element, a resistance element, and / or a frequency divider.

[0215] Next, an example of the shift register 220 will be described with reference to FIG. The flip-flop register consists of multiple flip-flops 200_1 to 200_N (N is a natural number). The flip-flops 200_1 to 200_N each include This corresponds to the semiconductor device described in the first and second embodiments. 9B is used as a flip-flop.

[0216] The connection relationship of the shift register will be described. First, as an example, flip-flop 20 The connection relationship of the wiring 121 in the flip-flop 200_i will be described. , the wiring 122, the wiring 123, the wiring 124, the wiring 126, and the wiring 127 are each 01_i, wiring 204, wiring 202, wiring 203, wiring 201_i-1, wiring 201_i +1. However, the odd-numbered flip-flops and the even-numbered flip-flops In many cases, the connection destinations of the wiring 123 and the wiring 124 are reversed. For example, In the flip-flop, the wiring 123 is connected to the wiring 202, and the wiring 124 is connected to the wiring 20. In this case, in the even-numbered flip-flops, the wiring 123 is connected to the wiring 2 03, and the wiring 124 is connected to the wiring 202. On the other hand, the odd-numbered flip-flops In the chip, the wiring 123 is connected to the wiring 203, and the wiring 124 is connected to the wiring 202. In this case, in the even-numbered flip-flops, the wiring 123 is connected to the wiring 202. Thus, the wiring 124 is connected to the wiring 203 .

[0217] Note that in the flip-flop 200_1, the wiring 125 is connected to the wiring 205.

[0218] Note that in the flip-flop 200_N, the wiring 126 is connected to the wiring 206.

[0219] Next, an example of the operation of the shift register in FIG. 15 will be described with reference to the timing chart in FIG. The operation of the semiconductor device according to the first and second embodiments will be described with reference to the following. Where necessary, the explanation will be omitted.

[0220] The operation of the flip-flop 200_i will be described. First, when the signal GS1_i-1 is at the H level, Then, the flip-flop 200_i starts operating in the period T1, and the signal G S1_i becomes L level. After that, the signals GS2 and GS3 are inverted. Then, The flip-flop 200_i starts its operation in the period T2, and the signal GS1_i goes high. The signal GS1_i is input to the flip-flop 200_i-1 as a reset signal. is inputted and inputted to the flip-flop 200_i+1 as a start signal. The flip-flop 200_i-1 starts its operation in the period T3. The process 200_i+1 starts operation in the period T1. Then, the signal GS2 and the signal GS3 is inverted again. Then, the flip-flop 200_i+1 operates in the period T2. The signal GS1_i+1 goes to the H level. The reset signal is input to the flip-flop 200_i. Since the signal GS1_i starts its operation in the period T3, the signal GS1_i becomes L level. Until the signal GS1_i-1 again becomes H level, the flip-flop 200_i holds the signal Each time the signals GS2 and GS3 are inverted, the operation in period T4 and the operation in period T5 are This process is repeated.

[0221] In addition, in the flip-flop 200_1, instead of the output signal of the previous stage flip-flop, Then, a signal GS4 is input from an external circuit via a wiring 205. Therefore, when the signal GS4 is H When this level is reached, the flip-flop 200_1 starts its operation in the period T1.

[0222] In addition, in the flip-flop 200_N, instead of the output signal of the next stage flip-flop, Then, the signal GS5 is input from an external circuit via the wiring 206. Therefore, when the signal GS5 is H When this level is reached, the flip-flop 200_N starts operation in the period T3.

[0223] The semiconductor device according to the first and second embodiments is used for the shift register according to the present embodiment. By doing so, it is possible to obtain the same advantages as those of the semiconductor device.

[0224] It is possible to omit the wiring 206. In this case, as an example, As the group 200_N, a transistor 134 and a transistor It is possible to use a configuration in which 135 is omitted.

[0225] In addition, in the flip-flops 200_1 to 200_N, a signal is used instead of the voltage V1. In this case, the wiring 204 can be omitted.

[0226] It is to be noted that the signal GS4 can be input to the wiring 206 in the same manner as the wiring 205. In this case, by connecting the wiring 206 to the wiring 205, the wiring 205 and the wiring 206 Alternatively, the signal GS2 may be shared with the wiring 206 in the same manner as the wiring 202. In this case, by connecting the wiring 206 to the wiring 202, Thus, the wiring 206 and the wiring 202 can be shared. In this case, the signal GS3 can be input to the wiring 206 in the same manner as the wiring 203. By connecting the wiring 206 to the wiring 203, it is possible to share the wiring 203 with the wiring 206. Alternatively, the voltage V1 can be input to the wiring 206, similarly to the wiring 204. In this case, by connecting the wiring 206 to the wiring 204, the wiring 206 and the wiring 2 It is possible to share with 04.

[0227] As for the flip-flops 200_1 to 200_N, as shown in FIG. 13(B), the signal S6 If a configuration requiring this is used, then wiring 207 may be added as shown in FIG. A signal GS6 is input to the wiring 207. This corresponds to the signal S6 described below and can function as an all-stage reset signal. The wiring 207 corresponds to the wiring 128 in FIG. 13B and can function as a signal line. It is possible.

[0228] However, the present invention is not limited to this, and the number of wirings may be reduced by sharing the wiring 207 with another wiring. Alternatively, the number of signals or power supply voltages can be reduced. It is possible to input the signal GS4 in the same manner as the line 205. Therefore, the line 207 is connected to the line 2 05, it is possible to share wiring 207 and wiring 205. Alternatively, the signal GS5 can be input to the wiring 207, similarly to the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, the wiring 207 and the wiring 206 Alternatively, the wiring 207 may be connected to the output of the flip-flop 200_N. Therefore, the wiring 207 can be connected to the wiring 20 By connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N. be.

[0229] In addition, the voltage V2 of the flip-flops 200_1 to 200_N is set as shown in FIG. 9(C). If a required configuration is used, it is possible to add new wiring. A voltage V2 is supplied to the wiring. The wiring corresponds to the wiring 127 in FIG. 9(C). It can function as a line.

[0230] As described in the first and second embodiments, the deterioration of the transistor characteristics In order to suppress the degradation of the L level, the potential of the signal is lower than V1, and the potential of the H level is higher than V2. A signal with a voltage amplitude smaller than V2-V1 is input to the flip-flop. In this case, a new wiring can be added. A signal is input to the wiring, and the The wiring can function as a signal line.

[0231] As shown in FIG. 17A, the shift register includes a circuit 212, a circuit 213, and a circuit 214. 14, circuit 215, and / or circuit 216. 16 has the function of increasing (or decreasing) the amplitude voltage or input voltage of the input signal and outputting it. The circuits 212 to 216 can function as a level shift circuit. has the function of inverting the input signal and outputting it, and can be used as an inverter circuit or a buffer circuit. The wiring 202 is connected to the flip-flop through the circuit 212. The wiring 203 is connected to the flip-flop through the circuit 213. The wiring 205 is connected to the flip-flop through the circuit 215. The wiring 206 is connected to the flip-flop via the circuit 216. This allows a small amplitude signal to be input to the shift register. Therefore, the driving voltage of the external circuit can be reduced, thereby reducing the cost of the external circuit. This makes it possible to reduce power consumption, etc.

[0232] In FIG. 17A, the shift register is any one of the circuits 212 to 216. , or two or more.

[0233] As shown in FIG. 17B, the shift register has circuits 211_1 to 211_N. The circuits 211_1 to 211_N have a function of increasing the current capability of the input signal. The function of increasing the amplitude voltage of the input signal or the function of inverting the input signal is provided. It can function as a fader circuit, a level shift circuit, or an inverter circuit. The circuits 211_1 to 211_N are respectively connected to the flip-flops 200_1 to 200_N and the wiring For example, the circuit 211_i is a flip-flop. The flip-flop 200 is connected between the flip-flop 200_i and the wiring 201_i. The signal GS1_i, which is the output signal of the ._i, is output from the wiring 201_i via the circuit 211_i. In this way, the drive voltage of each flip-flop can be reduced, resulting in reduced power consumption. It is possible to reduce the number of flip-flops and suppress the deterioration of the transistor characteristics. By reducing the channel width of the transistor (particularly the transistor 101) included in the chip, This allows the layout area to be reduced.

[0234] In the example of FIG. 17B, the flip-flop 200_i-1 receives a reset signal and Then, the signal GS1_i is input via the circuit 211_i. In the step 200_i-1, the period during which the transistor 101 is on is long in the period T3. Therefore, the falling edge of the signal GS_i-1, which is the output signal of the flip-flop 200_i-1, On the other hand, the flip-flop 200_i+1 receives the start signal As a signal, the signal GS1_i is input without passing through the circuit 211_i. In the flip-flop 200_i+1, the potential of the node A is increased quickly in the period T1. Therefore, the driving frequency can be improved. However, the present invention is not limited to this. The flip-flop 200_i-1 receives the signal GS1_i as a reset signal from the circuit 211. Alternatively, the input signal can be input to the flip-flop 200_i+1 without passing through the flip-flop 200_i+1. In the first embodiment, a signal GS1_i is input as a start signal through a circuit 211_i. It is possible.

[0235] In the shift register of FIG. 14(A), the signals S1_1 to S1_N are 1 / 1 the signal S2. The delay was 2 periods or 1 / 2 period of the signal S3. However, the delay was not limited to this. The signals S1_1 to S1_N are each 1 / 2×M (M is a natural number) period of the signal S2, or the signal S3 In other words, the signals S1_1 to S1_N can be shifted by 1 / 2×M periods. In this case, the period during which the signal in one row is at H level and the period during which the signal in another row is at H level are To achieve this, the shift register is provided with 2 × M phase clocks. It is possible to input a clock signal.

[0236] A specific example will be described with reference to the shift register of FIG. Only flip-flops 200_i+1 to 200_i+2M+1 are shown. The wirings 123 of +1 to 200_i+M are connected to the wirings 203_1 to 203_M, respectively. The wiring 124 of the flip-flops 200_i+1 to 200_i+M is 1 to 204_M. Flip-flops 200_i+M+1 to 200_i+2M The wiring 123 is connected to the wirings 204_1 to 204_M, respectively, and the flip-flop 20 The wiring 124 of 0_i+M+1 to 200_i+2M is respectively the wiring 203_1 to 203_M The wiring 125 of the flip-flop 200_i+1 is connected to the flip-flop The wiring 121 of the flip-flop 200_i+1 is connected to the wiring 122 of the flip-flop 200_i+2. 6 is connected to the wiring 121 of the flip-flop 200_i+M+1. The wirings 203_1 to 203_M correspond to the wiring 203. The wirings 204_1 to 204_M correspond to the wiring 2 As shown in FIG. 25(A), the wirings 203_1 to 203_M each have Signals GS2_1 to GS2_M are input to the wirings 204_1 to 204_M. Signals GS3_1 to GS3_M are input. Signals GS2_1 to GS2_M are 1 / 2 in phase. These are M clock signals shifted by M periods, and correspond to the signal GS2. GS3_M is an inverted signal of the signals GS2_1 to GS2_M, and corresponds to the signal GS3. In this way, the signal S2 is turned on for 1 / 2×M (M is a natural number) period, or the signal S3 is turned on for 1 / 2×M period. ×M periods can be offset.

[0237] In FIG. 24, the wiring 125 of the flip-flop 200_i+1 is The wiring 121 of each of the chips 200_i-M+1 to 200_i-1 is connected to the corresponding one of the wirings 121 of the chips 200_i-M+1 to 200_i-1. This allows the flip-flop 200_i+1 to Since the timing at which the resistor 131 turns on can be advanced, the potential of the node A rises. Therefore, the drive frequency can be increased. Alternatively, the channel width of the transistor 131 or the transistor 132 can be reduced. This allows the layout area to be reduced.

[0238] In FIG. 24, the wiring 126 of the flip-flop 200_i+1 is The wire 121 of any one of the pins 200_i+M+2 to 200_i+2M is connected to the pin By doing so, the transistor in the flip-flop 200_i+1 can be Since the timing at which the transistor 101 turns off can be delayed, the signal S1_i+1 The fall time of the signal can be shortened.

[0239] In FIG. 24, the wiring 126 of the flip-flop 200_i+1 is It is possible to connect to any one of the wirings 121 of the loops 200_i+2 to 200_i+M. By doing so, the pulse width of the signals S1_1 to S1_N is set to half the clock signal. Therefore, the driving frequency can be reduced while reducing power consumption. It can be made higher.

[0240] In FIG. 24, it is preferable that M≦4. More preferably, M≦2. This is because, when the shift register of FIG. 23 is used in a scanning line driving circuit of a display device, In this case, if M is too large, multiple types of video signals are written to the pixel. When this happens, the pixel receives an invalid video signal for a long period of time, causing a deterioration in display quality. FIG. 25B shows an example of a timing chart for M=2. An example of a route is shown below.

[0241] (Embodiment 4) In this embodiment, an example of a semiconductor device and a shift register including the semiconductor device will be described. The contents described in the first to third embodiments are the same as those in the present embodiment. The present invention can be applied to semiconductor devices and shift registers in various types.

[0242] First, the semiconductor device of this embodiment mode will be described with reference to FIG. The parts common to 1(A) are indicated by the same reference numerals and their explanation will be omitted.

[0243] The semiconductor device in FIG. 19A includes a circuit 100, a transistor 101, a transistor 102, A transistor 103, a transistor 104, a capacitor 105, a capacitor 106, and a transistor The transistor 301 corresponds to the transistor 101. The transistor 301 has a function similar to that of the transistor 101. The transistor 301 is an N-channel type. However, the transistor 301 can be a P-channel type.

[0244] A first terminal of the transistor 301 is connected to the wiring 123D. The terminal 2 of the transistor 301 is connected to the wiring 311, and the gate of the transistor 301 is connected to the node A. do.

[0245] The wiring 123D corresponds to the wirings 123A to 123C, and receives the signal S2. Therefore, similarly to FIG. 3D, the wiring 123D and the wirings 123A to 123C are shared. In this case, the first terminal of the transistor 301 is connected to the wiring 123. A signal S7 is output from the wiring 311. The signal S7 corresponds to the signal S1. do.

[0246] Next, the operation of the semiconductor device in FIG. 19A will be described with reference to a timing chart in FIG. The description will be given with reference to Fig. 1(A) and will be omitted for the operations common to those in Fig. 1(A).

[0247] First, in a period T1, the potential of the node A starts to rise. Similarly, the potential of the node A is equal to the potential of the wiring 123D (V1) and the threshold voltage of the transistor 301. When the sum of Vth301 and Vth301 is (V1+Vth301), the transistor 301 Then, the wiring 123D and the wiring 311 are in a conductive state. Since the signal S2 of the line 123D is supplied to the line 311, the potential of the line 311 becomes V1 It decreases so that

[0248] Next, in the period T2, the potential of node A becomes V1+Vth101+α. The resistor 301 remains on. Then, the wiring 123D and the wiring 311 remain in a conductive state. Therefore, the signal S2 of the H level is supplied from the wiring 123D to the wiring 311. The potential of the wiring 311 rises to V2.

[0249] Next, during period T3, the potential of node A starts decreasing to V1. Similarly to the transistor 101, the potential of the node A is the same as the potential of the wiring 123D (V1) and the potential of the transistor 301. The transistor Therefore, the signal S1 at the L level is shared from the wiring 123D to the wiring 311. Since the potential of the wiring 311 is V1, the potential of the node A decreases to V2. When the potential Vth decreases to V1+Vth301, the transistor 301 turns off.

[0250] During periods T4 and T5, the potential of node A is maintained at V1, so that transistor 3 01 remains off. Therefore, the wiring 123D and the wiring 311 remain in a non-conductive state. do.

[0251] In the semiconductor device of FIG. 19A, the wiring 121 and the wiring 311 output signals at the same timing. Therefore, the signal S1 output from the wiring 121 and the signal S2 output from the wiring 311 can be input. One of the signals S1 and S2 is used to drive a load such as a gate line or a pixel. The other signal can be used as a signal to drive another circuit, such as a signal for transfer. This prevents signal distortion caused by driving a load, etc. Alternatively, it can drive another circuit without being affected by delay or the like.

[0252] Note that a capacitor may be connected between the gate and the second terminal of the transistor 301. The capacitance element corresponds to the capacitance element 105.

[0253] As shown in FIG. 20A, a transistor 301 is added to the semiconductor device of FIG. It is possible to add

[0254] As shown in FIG. 20B, the transistor 302, the transistor 303, and / or A transistor 304 can be added to the transistor 302. The transistors 303 and 304 are transistors 134 and 102, respectively. , which corresponds to the transistor 133 and has a similar function. The second terminal of the transistor 302 is connected to the wiring 331. The gate of the transistor 302 is connected to the wiring 126. A first terminal of the transistor 303 is connected to a wiring 331, and a second terminal of the transistor 303 is connected to a node A. The gate of the transistor 303 is connected to the wiring 123E. A first terminal of the transistor 4 is connected to the wiring 122I, and a second terminal of the transistor 304 is connected to the wiring 331, and the gate of the transistor 304 is connected to the wiring 124C. , including but not limited to, transistor 302, transistor 303, and transistor 30 It is possible to add only one or two of the four.

[0255] In FIG. 20B, the wiring 123D and the wiring 123E are connected to the wirings 123A to 123E. Since the same signal (signal S2) as that of 23C is input, the wiring 123D and the wiring 123E In this case, the wirings 123A to 123C can be shared by the transistors 3. The first terminal of the transistor 301 and the gate of the transistor 303 are connected to the wiring 123. It is possible.

[0256] In addition, in FIG. 20B, the wiring 122H and the wiring 122I are connected to the wirings 122A to 122C. Since the same voltage (voltage V1) as that of the wiring 122E is supplied to the wiring 122H and the wiring 122I, In this case, the wirings 122A to 122E can be shared by the transistors 3. A first terminal of the transistor 302 and a first terminal of the transistor 304 are connected to the wiring 122. It is possible.

[0257] In FIG. 20B, the transistor 302 is a diode, like the transistor 135. It is possible to replace the diode with a diode-connected transistor. The transistor 304, like the transistor 133, is a diode or It is possible to replace the transistor with a connected transistor.

[0258] Next, an example of a shift register having the above-mentioned semiconductor device will be described with reference to FIG. The contents described in the third embodiment will not be described. The same reference numerals are used for the parts common to 4, and the explanation thereof will be omitted.

[0259] The shift register is made up of a number of flip-flops 320_1 to 320_N. The flip-flops 320_1 to 320_N are the same as the flip-flops in FIG. 200_1 to 200_N. Or, flip-flops 320_1 to 320_N corresponds to the semiconductor device of FIG. 19(A), FIG. 20(A), or FIG. 20(B). 20A is used as an example.

[0260] In the flip-flop 320_i, the wiring 311 is connected to the wiring 321_i. Then, the wiring 126 is connected to the wiring 321_i-1.

[0261] Signals GS7_1 to GS7_N are output from the wirings 321_1 to 321_N, respectively. The signals GS7_1 to GS7_N correspond to the signal S7 and are signals for transfer and output. , a selection signal, a scanning signal, or a gate signal.

[0262] Next, the operation of the shift register in FIG. 21 will be described with reference to the timing chart in FIG. 14(B). This will be explained in light of the above.

[0263] The operation of the flip-flop 320_i will be described. First, when the signal GS7_i-1 is at the H level, Then, the flip-flop 320_i starts its operation in the period T2, and the signal Then, the signal GS1_i and the signal GS7_i become L level. S3 is inverted. Then, the flip-flop 320_i starts the operation in the period T2. The signal GS1_i and the signal GS7_i become H level. The signal GS7_i is input to the flip-flop 320_i-1 as a reset signal. The start signal is input to the flip-flop 320_i+1. 20_i−1 starts operation in period T3, and the flip-flop 320_i+1 The operation starts in the period T1. Then, the signals GS2 and GS3 are inverted again. Then, the flip-flop 320_i+1 starts operating in the period T2, and the signal GS The signal GS1_i+1 is fed to the flip-flop 320_i. Therefore, the flip-flop 320_i is set in the period T3. Then, the signal GS1_i and the signal GS7_i become L level. Until the signal GS7_i-1 again becomes H level, the flip-flop 320_i holds the signal Each time the signals GS2 and GS3 are inverted, the operation in period T4 and the operation in period T5 are This process is repeated.

[0264] In the shift register of this embodiment, signals GS7_1 to GS7_N are used as start signals. Since the delay time of the signals S1_1 to S1_N can be shortened by using the Since the signals GS7_1 to GS7_N are not input to the gate lines or pixels, the signals S1_ This is because the delay or distortion is smaller compared to 1 to S1_N.

[0265] Alternatively, in the shift register of this embodiment, the signals GS1_1 to GS1_N are reset signals. Since the flip-flops operate in the period T3, the transistors Therefore, the time during which the signal S1_1 to S1_2 are turned on can be increased. 1, and the fall times of the signals GS7_1 to GS7_N can be shortened.

[0266] The signals GS1_1 to GS1_N are used as start signals to activate the flip-flops in the next stage. For example, the signal GS1_i can be input to the flip It can be input to flop 320_i+1.

[0267] The signals GS7_1 to GS7_N are used as reset signals to reset the flip-flops in the previous stage. For example, the signal GS7_i can be input to the flip-flop as a reset signal. The signal can be input to a flop 320_i-1.

[0268] (Embodiment 5) In this embodiment, an example of a display device will be described.

[0269] First, an example of a system block of a liquid crystal display device will be described with reference to FIG. The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_2, 2, a pixel portion 5364, a circuit 5365, and a lighting device 5366. In the example shown in FIG. 5, a plurality of wirings 5371 are arranged extending from a circuit 5362, and a plurality of wirings 5372 are arranged in a circuit. The circuit 5363_1 and the circuit 5363_2 are arranged to extend from each other. Each of the intersections of the wiring 5371 and the wiring 5372 has a display element such as a liquid crystal element. The pixels 5367 are arranged in a matrix.

[0270] In response to a video signal 5360, a circuit 5361 is connected to a circuit 5362, a circuit 5363_1, a circuit 5364, a circuit 5365, a 363_2 and the circuit 5365 have a function of outputting a signal or a voltage, etc., It can function as a controller, a control circuit, a timing generator, or a regulator. It is Noh.

[0271] The circuit 5361 is, for example, a start signal for the signal line driver circuit (SSP), Clock signal for the line (SCK), inverted clock signal for the signal line driver circuit (SCKB), video Signals such as signal data (DATA) and latch signal (LAT) are output to the circuit 5362. In response to these signals, the circuit 5362 outputs video signals to a plurality of wirings 5372. The signal line driver circuit has a function of driving a signal line.

[0272] When video signals are input to the multiple wirings 5371, the multiple wirings 5371 It can function as a line, a video signal line, a source line, or the like.

[0273] The circuit 5361 is, for example, a start signal for the scanning line driving circuit (GSP), Clock signal for the line (GCK), and clock signal for the inversion scanning line driving circuit (GCKB), etc. The signal is output to the circuit 5363_1 and the circuit 5363_2. In response to these signals, the circuit 5363_2 outputs scanning signals to a plurality of wirings 5371. The scanning line driver circuit has a function of detecting a scanning voltage.

[0274] When scanning signals are input to the multiple wirings 5372, the multiple wirings 5372 are signal lines. , a scanning line, a gate line, or the like.

[0275] The same signal is input from the circuit 5361 to the circuit 5363_1 and the circuit 5363_2. Therefore, the scanning signals output from the circuit 5363_1 to the wirings 5367 and the The timing of the scanning signals output from 3_2 to the multiple wirings 5367 is roughly the same. Therefore, the loads driven by the circuit 5363_1 and the circuit 5363_2 are reduced. Therefore, the display device can be made larger. Alternatively, the circuit 5363_1 and the circuit 5363_2 can have high resolution. Since the channel width of the transistor can be reduced, a display device with a narrow frame can be obtained. This can be done.

[0276] As an example, the circuit 5361 outputs a backlight control signal (BLC) to the circuit 5365. The circuit 5365 outputs a backlight signal to the lighting device 5366 in response to a backlight control signal (BLC). By controlling the amount of power supplied or the time, the brightness (or It has the function of controlling the average brightness and functions as a power supply circuit.

[0277] Note that one of the circuit 5363_1 and the circuit 5363_2 can be omitted.

[0278] In addition, in the pixel portion 5364, wiring such as a capacitance line, a power supply line, and a scanning line can be newly arranged. It is possible. The circuit 5361 can output a signal or a voltage to these wirings. Alternatively, a circuit similar to the circuit 5363_1 or the circuit 5363_2 may be newly added. This newly added circuit outputs signals such as scanning signals to the newly added wiring. It is possible.

[0279] Note that the pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 22B, the display element emits light, so the circuit 5365 and The lighting device 5366 may be omitted, and a light source may be used to power the display element. In order to achieve this, a plurality of wirings 5373 capable of functioning as power supply lines are arranged in the pixel portion 5364. The circuit 5361 supplies a power supply voltage (ANO) to the wiring 5373. This wiring 5373 can be connected for each color element of the pixel. It is possible for the signal line 14 to be connected in common to all pixels.

[0280] Note that in FIG. 22B, as an example, the circuit 5361 includes a circuit 5363_1 and a circuit 536 3_2 is supplied with separate signals. Start signal (GSP1), clock signal for scanning line driving circuit (GCK1), and inversion scanning The signal such as the clock signal (GCKB1) for the line driving circuit is output to the circuit 5363_1. The circuit 5361 outputs a start signal (GSP2) for the scanning line driver circuit, Clock signal (GCK2), and inversion scan line driver clock signal (GCKB2), etc. The circuit 5363_1 outputs the signal to the circuit 5363_2. 72, and the circuit 5363_2 scans only the odd-numbered wirings of the plurality of wirings 5372. That is, only the wirings in the even rows can be scanned. Since the driving frequency of the circuit 5363_2 can be reduced, the power consumption can be reduced. Alternatively, the area in which one flip-flop can be laid out can be increased. Therefore, the display device can be made high-definition. It is possible.

[0281] 22B, the circuit 5361 in FIG. 22A is the same as the circuit 5363 in FIG. It is possible to supply separate signals to circuit 5363_1 and circuit 5363_2.

[0282] Next, an example of the configuration of the display device will be described with reference to FIGS. This will be explained with reference to E).

[0283] In FIG. 23A, a circuit having a function of outputting a signal to a pixel portion 5364 (for example, a circuit 5 362, a circuit 5363_1, and a circuit 5363_2, etc.) are formed on the same substrate as the pixel portion 5364. The circuit 5361 is formed on a substrate different from the pixel portion 5364. This reduces the number of external components, thereby reducing costs. Since the number of signals or voltages input to the board 5380 is reduced, the board 5380 and the external components can be connected more efficiently. The number of connections can be reduced, which improves reliability and yield. can.

[0284] In addition, when the circuit is formed on a substrate different from the pixel portion 5364, the substrate is a TAB (Ta PE Automated Bonding (FPC) method Alternatively, the substrate may be implemented in a printed circuit board (PCB). 5364 is mounted on the same substrate 538 as the pixel part 5364 by the COG (Chip on Glass) method. It is possible to implement 0.

[0285] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is preferably made of a single crystal semiconductor. Therefore, a transistor formed on the substrate can be formed. The circuit has the advantages of improved drive frequency, improved drive voltage, and reduced output signal variation. You can get the points.

[0286] In addition, a signal, voltage, or current is input from an external circuit via an input terminal 5381. This is often the case.

[0287] In FIG. 23B, circuits with low drive frequencies (for example, circuit 5363_1, circuit 5363_ 2) is formed on the same substrate 5380 as the pixel portion 5364. The circuit 5362 is formed on a substrate different from that of the pixel portion 5364. The transistors make it possible to configure the circuits formed on the substrate 5380. As a semiconductor layer of a transistor, a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide Therefore, it is possible to increase the size of the display device and reduce the number of processes. It is possible to achieve a reduction in the number of parts, a reduction in costs, and an improvement in yield.

[0288] As shown in FIG. 23C, a part of the circuit 5362 (a circuit 5362a) is The remaining circuit 5362 (circuit 5362b) is formed on the same substrate 5380 as the pixel portion 564. The circuit 5362a may be formed on a different substrate from the one 364. Circuits that can be constructed using transistors (e.g., shift registers, selectors, shift registers, etc.) In addition, the circuit 5362b has high mobility and characteristic variations. Circuits that are preferably constructed using transistors with low distortion (e.g., shift registers) In many cases, the IC has a built-in amplifier (e.g., a 32-bit amplifier ... By doing so, as in FIG. 23(B), a non-single layer can be used as the semiconductor layer of the transistor. A crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. This allows for a further reduction in the number of external components.

[0289] In FIG. 23D, a circuit having a function of outputting a signal to the pixel portion 5364 (for example, the circuit 5 362, circuit 5363_1, and circuit 5363_2, etc.), and controlling these circuits A circuit having a function (for example, a circuit 5361) is formed on a substrate different from the pixel portion 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. Therefore, the yield can be improved.

[0290] In FIG. 23E, a part of the circuit 5361 (circuit 5361a) is formed on the same substrate as the pixel portion 5364. 5380, and the remaining circuit 5361 (circuit 5361b) is formed separately from the pixel portion 5364. The circuit 5361a is formed on a substrate. In some cases, the device has a circuit that can be used to The circuit 5361b uses transistors with high mobility and small variation. A circuit (e.g., a shift register, a timing generator, an o The input often has a built-in inverting resistor, regulator, or analog buffer.

[0291] Note that the circuits 5363_1 and 5363_2 may be the same as those in the first to fourth embodiments. A semiconductor device or a shift register can be used. In this case, the circuit 5363_ 1, and when the circuit 5363_2 is formed on the same substrate as the pixel portion, All transistors can be either N-channel or P-channel. Therefore, it is possible to reduce the number of steps, improve the yield, and reduce costs. By making all the transistors N-channel, the semiconductor A non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used for the layer. This makes it possible to increase the size of the display device, reduce costs, and improve yields. It is possible to achieve this.

[0292] Note that a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used as a semiconductor layer. The transistors used as the gate electrodes tend to have deteriorated characteristics such as an increase in threshold voltage or a decrease in mobility. However, the semiconductor device or shift register according to the first to fourth embodiments Since the deterioration of the transistor characteristics can be suppressed, the life of the display device can be extended. can be done.

[0293] As a part of the circuit 5362, the semiconductor device of any one of the first to fourth embodiments or For example, a circuit 5362a shown in FIG. It is possible to have the semiconductor device according to the first to fourth embodiments or a shift register. do.

[0294] (Embodiment 6) In this embodiment mode, a layout diagram (hereinafter also referred to as a top view) of a shift register will be described. In this embodiment, as an example, the layout diagram of the shift register in FIG. In addition, the contents described in this embodiment are the same as those of the shift register shown in FIG. The present invention can also be applied to the semiconductor device, shift register, or display device of the first to fifth embodiments. It should be noted that the layout diagram of this embodiment is merely an example and is not intended to be limiting. Please note that this is not intended to be a

[0295] The layout diagram of this embodiment will be described with reference to FIGS. 30 and 31. FIG. 31 shows an example of a layout diagram of a part of a shift register. 2 shows a layout diagram of the flip-flop 200_i.

[0296] The transistors, capacitors, wirings, and the like shown in FIGS. 30 and 31 are formed by using a conductive layer 401, a semiconductor The conductive layer 402, the conductive layer 403, the conductive layer 404, and the contact hole 405 However, the present invention is not limited to this, and may be implemented by forming another conductive layer, an insulating film, or another contact hole. For example, in order to connect the conductive layer 401 and the conductive layer 403, It is possible to add new contact holes for this purpose.

[0297] The conductive layer 401 can include a portion that functions as a gate electrode or a wiring. The conductor layer 402 may include a portion that functions as a semiconductor layer of a transistor. The conductive layer 403 may include a portion that functions as a wiring, a source, or a drain. The conductive layer 404 may include a portion that functions as a transparent electrode, a pixel electrode, or a wiring. The contact hole 405 is for connecting the conductive layer 401 and the conductive layer 404, or It can be used to connect the conductive layer 403 and the conductive layer 404 .

[0298] In the example of FIG. 30, the wiring 202 has an opening 411 and the wiring 203 has an opening 412. In this way, the wiring 202 and the wiring 203 have openings, so that the parasitic Capacitance can be reduced. Or, damage to transistors caused by electrostatic discharge can be prevented. However, the present invention is not limited to this. Alternatively, the opening 412 may be omitted. As with the wiring 203, an opening can be provided.

[0299] In the example of FIG. 30, an opening is provided at a part of an intersection between the wiring 202 or the wiring 203 and another wiring. By providing the wiring, the cross capacitance of the wiring can be reduced. It is possible to reduce the noise, or reduce signal delay or distortion.

[0300] In the example of FIG. 30, a conductive layer 404 is formed on a part of a conductive layer 403 of the wiring 204. The conductive layer 404 is then connected to the conductive layer 404 via a contact hole 405. 03. This reduces the wiring resistance, resulting in a reduction in voltage drop. However, the present invention is not limited to this, and the present invention can also be used to reduce the delay or distortion of signals. The conductive layer 404 and the contact hole 405 can be omitted. Similarly to the wiring 204, in the wiring 202 or the wiring 203, a part of the conductive layer 403 A conductive layer 404 is formed on the conductive layer 403, and the conductive layer 404 is connected to the conductive layer 403. It is possible.

[0301] In the example of FIG. 30, the width of the wiring 202, the width of the wiring 203, and the width of the wiring 204 are The widths of the wirings of the openings 421, 422, and 423 are respectively shown. The width of 411, the length of the opening 411, the width of the opening 412, and the length of the opening 412 are respectively , width 424, length 425, width 426, length 427.

[0302] In many cases, the signals input to the wiring 202 and the wiring 203 are inverted signals. Therefore, the wiring resistance or parasitic capacitance of the wiring 202 is equal to the wiring resistance or parasitic capacitance of the wiring 203. Therefore, the wiring 202 is preferably set to be approximately equal to the wiring It is preferable that the opening 411 includes a portion that is approximately equal to the line width 422. Alternatively, the opening 411 may be an opening The width 426 of the opening 412 or the length 427 of the opening 412 may be approximately equal to the width 426 of the opening 412. However, the present invention is not limited to this, and the wiring width 421, the wiring width 422, the width of the opening 411, etc. 424, the length 425 of the opening 411, or the length 427 of the opening 412 can be set to various values. For example, the cross capacitance between the wiring 202 and another wiring is 100%. In this case, the wiring resistance of the wiring 202 is made smaller. This reduces the delay or distortion of signals input to the wiring 202 and the wiring 203. For this reason, the wiring 202 has a wiring width of 42 Alternatively, the opening 411 may include more than two portions. Alternatively, the opening 411 may include a portion smaller than the width 426. On the other hand, the wiring 202 and the other wirings may include a portion shorter than the length 427 of 12. If the cross capacitance between the wiring 202 and the other wiring is smaller than the cross capacitance between the wiring 203 and the other wiring, the wiring 202 The opening 411 may include a portion smaller than the line width 422. It is possible for the opening 411 to include a portion that is greater than the width 426 of the mouth 412. may include a portion that is longer than the length 427 of the opening 412.

[0303] When the wiring 204 does not have an opening, the wiring 204 has a wiring width 421 or a wiring width 42 It is preferable that the wiring 204 includes a portion smaller than 2 because the wiring 204 does not have an opening. This is because the wiring resistance of the wiring 204 is small. However, this is not limited to this. 04 may include a portion that is greater than the line width 421 or the line width 422.

[0304] In the example of FIG. 31, one electrode of the capacitor 105 and the capacitor 106 is a conductive layer. The first electrode is formed by the conductive layer 401, and the second electrode is formed by the conductive layer 403. This allows the capacitance per unit area to be increased, resulting in a reduction in layout area. However, the present invention is not limited to this, and the conductive layer 401 and the conductive layer 403 may be A semiconductor layer 402 can be disposed on the conductive layer 401. It is possible to prevent a short circuit between the capacitor and the conductive layer 403. The capacitance element 105 or the capacitance element 106 may be a MOS capacitance.

[0305] In the example of FIG. 31, transistor 101, transistor 103, transistor 104, A transistor 131, a transistor 132, a transistor 133, a transistor 134, and In the transistor 135, the surface where the conductive layer 401 and the conductive layer 403 of the second terminal overlap The area is preferably smaller than the area where the conductive layer 401 and the conductive layer 403 of the first terminal overlap. By doing so, the noise of the gate of the transistor 101 or the wiring 201_i can be reduced. Alternatively, the concentration of the electric field on the second terminal can be suppressed. Therefore, deterioration or destruction of the transistor can be suppressed.

[0306] Note that a semiconductor layer 402 is formed in a portion where the conductive layer 401 and the conductive layer 403 overlap each other. By doing so, the parasitic capacitance between the conductive layer 401 and the conductive layer 403 can be reduced. For the same reason, the conductive layer In the portion where the conductive layer 404 overlaps with the semiconductor layer 401, the semiconductor layer 402 or the conductive layer 403 is formed. It is possible.

[0307] A conductive layer 404 is formed on a part of the conductive layer 401. It is possible to connect the conductive layer 404 through the through hole 405. By this, the wiring resistance can be reduced. The conductive layer 401 is connected to the contact hole 405 through the contact hole 405. The conductive layer 403 is connected to the conductive layer 404 through another contact hole 405. It is possible to connect with the conductive layer 404. By doing so, the wiring resistance can be further reduced. It can be lowered further.

[0308] The conductive layer 404 is formed on a part of the conductive layer 403. It is possible to connect the conductive layer 404 through the through hole 405. This makes it possible to reduce the wiring resistance.

[0309] Note that the conductive layer 401 or the conductive layer 403 is formed under a part of the conductive layer 404. 404 is connected to the conductive layer 401 or the conductive layer 403 through a contact hole 405. By doing so, the wiring resistance can be reduced. .

[0310] In the case where the capacitor 105 is omitted, as described in the first embodiment, The parasitic capacitance between the gate of transistor 101 and the second terminal is smaller than the parasitic capacitance between the gate of transistor 101 and the first terminal. It is possible to increase the parasitic capacitance between the terminals of the transistor 101 and the An example of the layout diagram is shown in FIG. 18. In the example of FIG. The width of the conductive layer 403 that can function as an electrode of the transistor 1 is indicated as width 431. The width of the conductive layer 403, which can function as the second electrode of the electrode 101, is shown as width 432. Thus, width 431 can be greater than width 432. As described in the first embodiment, the parasitic capacitance between the gate and the first terminal of the transistor 101 In this case, the parasitic capacitance between the gate and the second terminal of the transistor 101 can be increased. It is possible, but not limited to this.

[0311] (Embodiment 7) In this embodiment, an example of a signal line driver circuit will be described. It may be referred to as a conductor device or a signal generating circuit.

[0312] An example of a signal line driver circuit will be described with reference to FIG. A plurality of circuits 502_1 to 502_N (N is a natural number), a circuit 500, and a circuit 5 01. Each of the circuits 502_1 to 502_N includes a transistor 503_ The transistor 503 has a number of transistors 1 to 503_k (k is a natural number). _1 to 503_k are assumed to be N-channel type. However, this is not limited to this. The transistors 503_1 to 503_k can be of the P-channel type, and can be implemented by CMOS. The switch may be of the type.

[0313] The connection relationship of the signal line driver circuit will be described using the circuit 502_1 as an example. The first terminals of the transistors 503_1 to 503_k are connected to the wiring 505_1. The second terminals of the transistors 03_1 to 503_k are connected to the wirings S1 to Sk, respectively. The gates of the transistors 503_1 to 503_k are connected to the wirings 504_1 to 504_k, respectively. For example, a first terminal of the transistor 503_1 is connected to a wiring 505_1. A second terminal of the transistor 503_1 is connected to the wiring S1. The port is connected to the wiring 504_1.

[0314] The circuit 500 transmits signals to the circuits 502_1 to 502_k via the wirings 504_1 to 504_k. N, and can function as a shift register, decoder, etc. The signal is often a digital signal and can function as a selection signal. The wirings 504_1 to 504_k can function as signal lines. be.

[0315] The circuit 501 has a function of outputting signals to circuits 502_1 to 502_N, and generates a video signal. For example, the circuit 501 can function as a At the same time, a signal is supplied to the circuit 502_1 via a wiring 505_2. The signal is often an analog signal and functions as a video signal. The wirings 505_1 to 505_N can function as signal lines. It is possible.

[0316] The circuits 502_1 to 502_k select to which wiring the output signal of the circuit 501 is to be output. For example, the circuit 502 has a function of selecting an input from the input terminal of the selector circuit. _1 indicates which of the wirings S1 to Sk the signal output from the circuit 501 to the wiring 505_1 is to be transmitted to It has the function of selecting whether to output to

[0317] The transistors 503_1 to 503_N are connected to the wiring 5 in response to the output signal of the circuit 500. 05_1 and the wiring S1 to Sk, and functions as a switch. do.

[0318] Next, the operation of the signal line driver circuit of FIG. 26(A) will be described with reference to the timing chart of FIG. 26(B). FIG. 26B shows a signal 514_1 input to a wiring 504_1. , a signal 514_2 input to the wiring 504_2, a signal 514 input to the wiring 504_k _k, a signal 515_1 input to the wiring 505_1, and a signal 515_2 input to the wiring 505_2. An example of number 515_2 is shown below.

[0319] Note that one operation period of the signal line driver circuit corresponds to one gate selection period in the display device. A gate selection period is a period during which pixels in a certain row are selected and a video signal is written to the selected pixels. This refers to the period during which it is possible to

[0320] One gate selection period is divided into periods T0, T1, and Tk. is a period for simultaneously applying a precharge voltage to the pixels in the selected row. The periods T1 to Tk can function as a precharge period. This is a period for writing video signals to pixels belonging to a row that has been selected, and functions as a write period. It is possible to do this.

[0321] For convenience, the operation of the signal line driver circuit will be described using the operation of the circuit 502_1 as an example.

[0322] First, in a period T0, the circuit 500 supplies H-level signals to the wirings 504_1 to 504_k. Then, the transistors 503_1 to 503_k are turned on, so that the wiring 50 At this time, the circuit 501 is in a conductive state with the wirings 505_1 and S1 to Sk. Since a precharge voltage Vp is supplied to transistor 1, the precharge voltage Vp is The signals are output to the wirings S1 to Sk via the respective signals 503_1 to 503_k. The charge voltage Vp is written to the pixels belonging to the selected row, so The pixels that correspond to the pixel are precharged.

[0323] Next, in the period T1, the circuit 500 outputs an H-level signal to the wiring 504_1. Then, the transistor 503_1 is turned on, and the wiring 505_1 and the wiring S1 are electrically connected. Then, the wiring 505_1 and the wirings S2 to Sk are in a non-conductive state. If the circuit 501 outputs a signal Data (S1) to the wiring 505_1, Data (S1) is output to the wiring S1 through the transistor 503_1. The signal Data(S1) is a signal corresponding to the pixel in the selected row among the pixels connected to the line S1. is written to the pixel.

[0324] Next, in the period T2, the circuit 500 outputs an H-level signal to the wiring 504_2. Then, the transistor 503_2 is turned on, so that the wiring 505_2 and the wiring S2 are electrically connected. Then, the wiring 505_1 and the wiring S1 are in a non-conductive state, and the wiring 505_1 At this time, the circuit 501 outputs the signal Data If the signal Data (S2) is output to the wiring 505_1, the signal Data (S2) is The signal Data (S2) is output to the wiring S2 via the stator 503_2. Of the pixels connected to the line S2, the pixels belonging to the selected row are written.

[0325] After that, until the period Tk, the circuit 500 outputs a high-level signal to the wirings 504_1 to 504_k. Since the signals are output in sequence, the circuit 5 outputs the signals in sequence from the period T3 to the period Tk in the same manner as the periods T1 and T2. 00 outputs H-level signals to the wirings 504_3 to 504_k in sequence. The transistors 503_3 to 503_k are turned on in sequence, so that the transistors 503_1 to 503 _N are turned on in sequence. Therefore, the signal output from the circuit 501 is In this way, signals can be written in order to the pixels in the selected row. It becomes possible.

[0326] The signal line driver circuit of this embodiment has a circuit that functions as a selector, so the number of signals Or, the number of wirings can be reduced. 0), a voltage for precharging is written to the pixels, so when the video signal is written This makes it possible to shorten the time required for the display device to be large and to have high resolution. However, the present invention is not limited to this, and the period T0 may be omitted and the pixels may not be precharged. It is possible.

[0327] If k is too large, the time it takes to write to the pixel becomes too short, so the time it takes to write to the pixel of the video signal becomes too short. Writing may not finish in time, so k≦6 is preferred. More preferably, k≦3. Further preferably, k=2. It is nice.

[0328] In particular, if the color components of a pixel are divided into n (n is a natural number), it is possible to set k=n. For example, if a pixel's color components are divided into three, red (R), green (G), and blue (B), , k=3. In this case, one gate selection period includes a period T0, a period T1, , period T2, and period T3. In periods T1, T2, and T3, It is possible to write video signals to red (R), green (G), and blue (B) pixels. However, the order of the periods T1, T2, and T3 is not limited to this, and may be set arbitrarily. It is possible to do so.

[0329] In particular, a pixel has n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or sub-pixels). For example, if a pixel is divided into two sub-pixels, k=n. In this case, one gate selection period is a period T In the period T1, one of the two sub-pixels In the period T1, a video signal is written to the other of the two sub-pixels. It is possible.

[0330] In addition, since the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low, The circuit 500 and the circuits 502_1 to 502_N may be formed on the same substrate as the pixel portion. This makes it possible to reduce the number of connections between the substrate on which the pixel unit is formed and the external circuit. This allows for improved yield and reliability. As shown in FIG. 3(C), the scanning line driver circuit is also formed on the same substrate as the pixel section, so that This significantly reduces the number of connections to external circuits.

[0331] The circuit 500 may be a semiconductor device or a shift register according to any one of the first to fourth embodiments. In this case, the polarity of all the transistors in the circuit 500 can be changed to It can be made into either an N-channel type or a P-channel type. Therefore, the number of processes can be reduced. The yield can be improved or the cost can be reduced.

[0332] In addition to the circuit 500, all the transistors included in the circuits 502_1 to 502_N are The polarity of the transistor can be either N-channel or P-channel. 00, and when the circuits 502_1 to 502_N are formed on the same substrate as the pixel portion, the number of steps In particular, it is possible to reduce the number of transistors, improve the yield, and reduce the cost. By making the polarity of the transistor N-channel type, A crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. In other words, the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low. That is why.

[0333] (Embodiment 8) In this embodiment, a pixel configuration and pixel operation that can be applied to a liquid crystal display device will be described. explain.

[0334] FIG. 27A is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device. The pixel circuit 5080 includes a transistor 5081, a liquid crystal element 5082, and a capacitor element 5083. The gate of the transistor 5081 is electrically connected to the wiring 5085. The first terminal of the transistor 5081 is electrically connected to the wiring 5084. The first terminal of the liquid crystal element 5082 is electrically connected to the wiring. The first terminal of the capacitor 5083 is electrically connected to the first terminal of the liquid crystal element 5082. The second terminal of the capacitor 5083 is electrically connected to the wiring 5086. will be done.

[0335] The wiring 5084 can function as a signal line. The signal line is input from the outside of the pixel. The wiring 5085 is a wiring for transmitting the signal voltage to the pixel 5080. The scan line is used to control the on / off of the transistor 5081. The wiring 5086 can function as a capacitance line. This is a wiring for applying a predetermined voltage to the second terminal of the transistor 5083. The capacitor 5083 can function as a storage capacitor. The storage capacitor can store the signal voltage even when the switch is off. The wiring 5087 is a capacitor for continuously adding to the capacitor 082. The counter electrode can be used to apply a predetermined voltage to the second terminal of the liquid crystal element 5082. However, the functions that each wiring can have are not limited to these. For example, by changing the voltage applied to the capacitance line, The voltage applied to the liquid crystal element can also be adjusted. Since the transistor 5081 only needs to function as a P-channel type, the polarity of the transistor 5081 may be a P-channel type. Alternatively, the transistor may be of an N-channel type.

[0336] FIG. 27(B) is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device. 27(A) in which the wiring 5087 is omitted. The second terminal of the liquid crystal element 5082 and the second terminal of the capacitance element 5083 are electrically connected. The pixel configuration is the same as that shown in FIG. 27(A), except that the pixel is connected to the The pixel configuration example shown in FIG. 27(B) is particularly suitable for liquid crystal elements in a horizontal electric field mode (IP This is applicable when the liquid crystal element is horizontally shifted (including S mode and FFS mode). In the field mode, the second terminal of the liquid crystal element 5082 and the second terminal of the capacitor element 5083 are Since they can be formed on the same substrate, the second terminal of the liquid crystal element 5082 and the capacitor element 5 This is because it is easy to electrically connect the second terminal of the junction box 083 to the second terminal of the junction box 083. By using the pixel configuration as shown in FIG. 1, the wiring 5087 can be omitted, and the manufacturing process can be simplified. This allows the manufacturing cost to be reduced.

[0337] The pixel configuration shown in FIG. 27(A) or FIG. 27(B) is arranged in a matrix. In this way, a display section of a liquid crystal display device is formed, and various images can be displayed. FIG. 27C shows a pixel arrangement in which a plurality of pixel configurations shown in FIG. 27A are arranged in a matrix. FIG. 27C is a diagram showing a circuit configuration in the case where the display unit has The figure shows four pixels extracted from a plurality of pixels. A pixel located at a position (i,j) is denoted as pixel 5080_i,j. The wiring 5084_i, the wiring 5085_j, and the wiring 5086_j are electrically connected to each other. Similarly, for the pixel 5080_i+1,j, the wiring 5084_i+1 and the wiring 5084_i+2 are connected. 5085_j and the wiring 5086_j are electrically connected to the pixel 5080_i,j+ For 1, wiring 5084_i, wiring 5085_j+1, wiring 5086_j+1 and electrical Similarly, for pixel 5080_i+1,j+1, a wiring 5084_i +1, a wiring 5085_j+1, and a wiring 5086_j+1. A line can be shared by multiple pixels that belong to the same column or row. In the pixel configuration shown in FIG. 7(C), the wiring 5087 is a counter electrode. Since the wiring 5087 is common to all wiring, the notation using natural numbers i or j is not used. It is also possible to use the pixel configuration shown in FIG. Even if the wiring 5087 is shown in the configuration, the wiring 5087 is not essential and other wirings may be used. It can be omitted by being shared with other

[0338] The pixel configuration shown in FIG. 27(C) can be driven in various ways. The liquid crystal display is driven by a method called flow driving, which prevents deterioration of the liquid crystal element (burn-in). FIG. 27(D) shows a case where dot inversion driving, which is one of the AC driving methods, is used. When the pixel configuration shown in FIG. 27C is used, the timing of the voltage applied to each wiring is FIG. 1 is a diagram showing a pixel timing chart of a pixel in which dot inversion driving is performed and AC driving is performed. This can suppress the flickering that is visible when the D) shows a signal 5185_j input to wiring 5085_j, a signal 5185_j input to wiring 5085_j+1, A signal 5185_j+1 is input to a wiring 5084_i, a signal 5184_i is input to a wiring 5084_i, and a wiring A signal 5184_i+1 input to 5084_i+1, a voltage 5 supplied to the wiring 5086 Shows 186.

[0339] In the pixel configuration shown in FIG. 27C, The switch in is in the selected state (on state) during the j-th gate selection period in one frame period. In the other period, it is in the non-selected state (off state). After the j+1-th gate selection period, the j+1-th gate selection period is provided. In this manner, sequential scanning is performed. As a result, all pixels are selected in sequence within one frame period. In the timing chart, when the voltage is in a high state (high level), The switch is in the selected state, and the voltage is low (low level) to deselect the switch. Note that this is the case when the transistors in each pixel are N-channel type, and not P-channel type. When a N-channel transistor is used, the relationship between the voltage and the selection state is different from that of the N-channel type. The opposite is true.

[0340] In the timing chart shown in FIG. 27(D), the jth pulse in the kth frame (k is a natural number) During the gate selection period, a positive signal voltage is applied to the wiring 5084_i used as a signal line. A negative signal voltage is applied to the wiring 5084_i+1. In the j+1-th gate selection period, a negative signal voltage is applied to the wiring 5084_i, A positive signal voltage is applied to 084_i+1. After that, each signal line is In each selection period, a signal with the polarity inverted is added alternately. As a result, in the kth frame, A positive signal voltage is applied to the pixel 5080_i,j, and a negative signal voltage is applied to the pixel 5080_i+1,j. A negative signal voltage is applied to pixel 5080_i, j+1, and a positive signal voltage is applied to pixel 5080_i+1, j+1. In the k+1-th frame, the signal voltages are added as follows: In each pixel, a signal voltage of the opposite polarity to the signal voltage written in the kth frame is written. As a result, in the k+1th frame, the pixel 5080_i,j A negative signal voltage is applied to pixel 5080_i+1,j, a positive signal voltage is applied to pixel 5080_i,j A positive signal voltage is applied to pixel 5080_i+1,j+1, and a negative signal voltage is applied to pixel 5080_i+1,j+1. In this way, adjacent pixels in the same frame have different polarities. A signal voltage having a specific polarity is applied to each pixel, and a signal voltage The dot inversion driving method inverts the polarity of the liquid crystal. This is visible when the entire or part of the displayed image is uniform while suppressing deterioration of the element. Flicker can be reduced. The voltage applied to all the wirings 5086 including the wiring 5086 can be a constant voltage. The timing chart for the signal voltage of the line 5084 only indicates the polarity. In this case, various signal voltage values ​​can be used for the displayed polarity. Although the polarity is inverted for each pixel, the present invention is not limited to this. For example, the polarity of the signal voltage written every two gate selection periods can be reversed. By reversing the polarity, it is possible to reduce the power consumption required to write the signal voltage. In addition, the polarity can be inverted for each column (source line inversion) or for each row. It is also possible to invert the polarity (gate line inversion)

[0341] In addition, the second terminal of the capacitor 5083 in the pixel 5080 is A constant voltage is sufficient. Here, the voltage applied to the wiring 5085 used as the scanning line is The voltage applied is low for most of the frame period, and a nearly constant voltage is applied. Therefore, the second terminal of the capacitor element 5083 in the pixel 5080 is connected to the wiring 5 FIG. 27(E) is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device. The pixel configuration shown in FIG. 27(E) has a wiring 5086 is omitted, and the second terminal of the capacitance element 5083 in the pixel 5080 and the The wiring 5085 in the row is electrically connected to the In the range shown in FIG. 27(E), the pixel 5080_i,j+1 and the pixel The second terminal of the capacitance element 5083 in 5080_i+1, j+1 is connected to the wiring 5085_j. In this manner, the second terminal of the capacitance element 5083 in the pixel 5080 and By electrically connecting the wiring 5085 in the previous row, the wiring 5086 is omitted. Since the second terminal of the capacitor 5083 can be connected to the The destination may be the wiring 5085 in another row, not just the wiring 5085 in the previous row. The driving method of the pixel configuration shown in FIG. 27(E) is the same as that of the pixel configuration shown in FIG. The same movement method can be used.

[0342] The capacitor 5083 and the wiring electrically connected to the second terminal of the capacitor 5083 are By using this, the voltage applied to the wiring 5084 used as a signal line can be reduced. The pixel configuration and driving method in this case will be described with reference to FIG. 27(F) and FIG. 27(G). The pixel configuration shown in FIG. 27(F) has a wiring 5 compared to the pixel configuration shown in FIG. 086 is provided for each pixel column, and the second The feature of this type is that the electrical connection to the terminals is made alternately between adjacent pixels. The wiring 5086 in question will be referred to as wiring 5086-1 and wiring 5086-2, respectively. Specifically, in the range shown in FIG. , j, the second terminal of the capacitance element 5083 is electrically connected to the wiring 5086-1_j. The second terminal of the capacitance element 5083 in the pixel 5080_i+1,j is connected to the wiring 5086-2 _j, and the second terminal of the capacitance element 5083 in the pixel 5080_i,j+1 The element is electrically connected to the wiring 5086-2_j+1 and is connected to the pixel 5080_i+1, j+1. A second terminal of the capacitor 5083 in the In addition, in FIG. 27G, a signal 5185_j input to the wiring 5085_j and a signal 5185_j input to the wiring 50 A signal 5185_j+1 is input to the wiring 5084_i. 184_i, a signal 5184_i+1 input to a wiring 5084_i+1, a wiring 5086- A signal 5186-1_j is input to the wiring 5086-2_j, and a signal 51 86-2_j, signal 5186-1_j+1 input to wiring 5086-1_j+1, wiring 5 shows a signal 5186-2_j+1 input to 5086-2_j+1.

[0343] For example, as shown in FIG. 27G, in the k-th frame, pixel 5080_i, When a positive signal voltage is written to j, the wiring 5086-1_j is the jth gate selection During the j-th gate selection period, the signal is kept at a low level, and after the j-th gate selection period ends, the signal is changed to a high level. Then, it maintains the high level for one frame period, and in the k+1th frame In the jth gate selection period, a signal voltage of negative polarity is written, and then the signal voltage is changed to a low level. In this way, after a signal voltage of positive polarity is written to the pixel, the second By changing the voltage of the wiring electrically connected to the terminal in the positive direction, This allows the voltage written to the pixel to be changed in the positive direction by a specified amount. This reduces the power consumption required for signal writing. In addition, when a signal voltage of negative polarity is written in the j-th gate selection period, After a signal voltage of negative polarity is written to the pixel, the second terminal of the capacitance element 5083 is electrically connected to the By changing the voltage of the wiring connected to the liquid crystal display in the negative direction, the voltage applied to the liquid crystal element is Since the voltage can be changed by a given amount in the negative direction, the pixel The signal voltage to be written can be made small. The electrically connected wiring is connected to the same row of the same frame when a positive polarity signal voltage is applied. The pixels to which a positive polarity signal voltage is applied have different wiring. FIG. 27(F) shows a case where a signal voltage of positive polarity is written in the k-th frame. A wiring 5086-1 is electrically connected to the pixel, and a signal voltage of negative polarity is applied in the k-th frame. In this example, the wiring 5086-2 is electrically connected to the pixel to which the voltage is written. This is just one example. For example, a pixel to which a signal voltage of a positive polarity is written and a pixel to which a signal voltage of a negative polarity is written In the case of a driving method in which pixels to which light is written appear every two pixels, the wiring 5086-1 and Accordingly, the electrical connection of the wiring 5086-2 is also performed alternately every two pixels. It is preferable that the signal voltage of the same polarity is written to all pixels in one row (gain In this case, one wiring 5086 may be provided per row. That is, even in the pixel configuration shown in FIG. 27(C), the same applies when FIGS. 27(F) and 27(G) are used. A driving method for reducing the signal voltage written to the pixel, as described in the following, can be used. do.

[0344] Next, the liquid crystal element is a vertical alignment (VA) type, typically represented by MVA mode or PVA mode. A pixel configuration and a driving method thereof that are particularly preferable in the VA mode will be described. This LCD has many advantages, such as no rubbing process required during manufacturing, little light leakage during black display, and low driving voltage. However, the image quality deteriorates when the screen is viewed at an angle (the viewing angle is narrow). In order to widen the viewing angle in the VA mode, the following problems are solved: As shown in (B), a pixel configuration having multiple sub-pixels in one pixel is used. In the pixel configuration shown in FIG. 28(A) and FIG. 28(B), the pixel 5080 is 5 shows an example of a case in which the subpixels are two (subpixel 5080-1 and subpixel 5080-2). The number of sub-pixels in one pixel is not limited to two, and various numbers of sub-pixels can be used. The larger the number of sub-pixels, the wider the viewing angle can be. The sub-pixels can have the same circuit configuration. In this case, all the sub-pixels are shown in FIG. The circuit configuration of the first subpixel 5080-1 is the same as that shown in FIG. A transistor 5081-1, a liquid crystal element 5082-1, and a capacitor element 5083-1 The connections of each are based on the circuit configuration shown in FIG. The second subpixel 5080-2 includes a transistor 5081-2, a liquid crystal element 5082-2, and a capacitor The circuit configuration shown in FIG. 27A is that the elements 5083-2 are included, and the connections of the elements 5083-2 are the same as those shown in FIG. shall be governed by the same.

[0345] The pixel configuration shown in FIG. 28(A) is used as a scanning line for two sub-pixels that make up one pixel. The two wirings 5085 (wiring 5085-1 and wiring 5085-2) are used as signal lines. The wiring 5084 is used as a capacitor line, and the wiring 5086 is used as a capacitor line. In this way, the signal line and the capacitance line are shared by two sub-pixels, The throughput can be improved and the signal line driver circuit can be simplified. This reduces manufacturing costs and the number of connections between the liquid crystal panel and the driver IC. The pixel configuration shown in FIG. 28(B) is a pixel configuration in which two sub-pixels make up one pixel. For each pixel, there is one wiring 5085 used as a scanning line, and one wiring 50 The wiring 5084 has two wirings 5084 (wiring 5084-1 and wiring 5084-2) and is used as a capacitance line. In this way, the scanning lines and the capacitance lines are divided into two sub-pixels. By sharing the same pixel, the aperture ratio can be improved and the total number of scanning lines can be reduced. This allows the gate line selection period to be sufficiently long even in high-resolution LCD panels. It is possible to lengthen the length so that an appropriate signal voltage can be written to each pixel.

[0346] 28(C) and 28(D) show the pixel configuration shown in FIG. 28(B) in which the liquid crystal element is This is an example that shows a schematic diagram of the electrical connection state of each element after replacing it with the shape of a pixel electrode. In FIG. 28(C) and FIG. 28(D), electrode 5088-1 represents the first pixel electrode, The electrode 5088-2 represents the second pixel electrode. The electrode 5088-1 corresponds to the first terminal of the liquid crystal element 5082-1 ​​in FIG. The pixel electrode 5088-2 corresponds to the first terminal of the liquid crystal element 5082-2 in FIG. That is, the first pixel electrode 5088-1 corresponds to the source of the transistor 5081-1. The second pixel electrode 5088-2 is electrically connected to one of the drain and the drain of the transistor 5 It is electrically connected to either the source or drain of 081-2. In this embodiment, the connection relationship between the pixel electrode and the transistor is reversed. 88-1 is electrically connected to one of the source and drain of the transistor 5081-2. The second pixel electrode 5088-2 is connected to the source or drain of the transistor 5081-1. It is assumed that one of them is electrically connected.

[0347] The pixel configurations shown in FIG. 28(C) and FIG. 28(D) are alternately arranged in a matrix. By doing so, a special effect can be obtained. Examples are shown in FIG. 28(E) and FIG. 28(F). The pixel configuration shown in FIG. 28(E) is pixel 5. The part corresponding to pixel 080_i,j and pixel 5080_i+1,j+1 is shown in FIG. The part corresponding to the pixel 5080_i+1,j and the pixel 5080_i,j+1 is In this configuration, the timing shown in FIG. 28(F) is When the image is driven as shown in the timing chart, in the jth gate selection period of the kth frame, A positive electrode is applied to the first pixel electrode of the pixel 5080_i,j and the second pixel electrode of the pixel 5080_i+1,j. A signal voltage of the polarity is written to the second pixel electrode of the pixel 5080_i,j and the pixel 508 A signal voltage of negative polarity is written to the first pixel electrode of 0_i+1,j. In the j+1-th gate selection period of the pixel 5080_i,j+1, A positive signal voltage is written to the first pixel electrode of the pixel 5080_i+1,j+1, A first pixel electrode of the pixel 5080_i,j+1 and a second pixel electrode of the pixel 5080_i+1,j+1 In the k+1th frame, a negative signal voltage is written to the electrode. In this way, the polarity of the signal voltage is inverted in a pixel configuration including sub-pixels. While achieving a drive equivalent to dot inversion drive, the polarity of the voltage applied to the signal line is changed by one frame. Since the power consumption required for writing the signal voltage to the pixel can be made the same during the period of the program, It is possible to significantly reduce the number of wirings including the wiring 5086_j and the wiring 5086_j+1. The voltage applied to all the wirings 5086 can be a constant voltage. 7(F) is a signal 5185_j input to a wiring 5085_j, a signal 5085_j+1 a signal 5185_j+1 input to the line 5084- 1_i, a signal 5184-2_i input to the wiring 5084-2_i, a signal 5084-1_ A signal 5184-1_i+1 is input to the wiring 5084-2_i+1. Signal 5184-2_i+1, voltage 5186 supplied to wiring 5186 is shown.

[0348] Furthermore, by using the pixel configuration and the driving method thereof shown in FIG. 28(G) and FIG. 28(H), The magnitude of the signal voltage written to the pixel can be reduced. The capacitance lines electrically connected to the sub-pixels of the pixel are different for each sub-pixel. That is, the pixel configuration and the driving method thereof shown in FIG. 28(E) and FIG. 28(F) are used. Therefore, for sub-pixels to which the same polarity is written in the same frame, the capacitance Sub-pixels that share a common line and have different polarities written in the same frame are Then, when writing to each row is completed, The voltage of the positive polarity signal voltage is written to the subpixel in the positive direction, and the voltage of the negative polarity signal voltage is written to the In the subpixel where a signal voltage is written, the signal voltage written to the pixel is changed in the negative direction. Specifically, the wiring 5086 used as the capacitance line is arranged in each row. The first pixel of pixel 5080_i,j is connected to two lines (line 5086-1 and line 5086-2). The electrode and the wiring 5086-1_j are electrically connected through a capacitor. The second pixel electrode of pixel _i, j is electrically connected to the wiring 5086-2_j via a capacitance element. The first pixel electrode of the pixel 5080_i+1,j and the wiring 5086-2_j form a capacitive element. The second pixel electrode of the pixel 5080_i+1,j is electrically connected to the wiring 508 6-1_j is electrically connected to the first pixel 5080_i,j+1 via a capacitance element. The pixel electrode and the wiring 5086-2_j+1 are electrically connected via a capacitance element. The second pixel electrode 5080_i,j+1 and the wiring 5086-1_j+1 are connected via a capacitance element. The first pixel electrode of the pixel 5080_i+1,j+1 and the wiring 5086 are electrically connected to each other. -1_j+1 is electrically connected to the pixel 5080_i+1,j+1 via a capacitance element. The second pixel electrode and the wiring 5086-2_j+1 are electrically connected through a capacitance element. However, this is just an example. For example, if a pixel to which a signal voltage of positive polarity is written and a pixel to which a signal voltage of negative polarity is written are In the case of a driving method in which a pixel to which a signal voltage of the same polarity is written appears every two pixels, wiring 5 The electrical connections of the wiring 5086-1 and wiring 5086-2 are also made alternately every two pixels. Moreover, it is preferable that signal voltages of the same polarity are written to all pixels in one row. In this case, the wiring 5086 is connected to one row. In other words, even in the pixel configuration shown in FIG. 28(E), A driving method for reducing the signal voltage written to the pixel, as explained using 28(H), is used. In addition, in FIG. 27(H), the signal 518 input to the wiring 5085_j is 5_j, a signal 5185_j+1 input to the wiring 5085_j+1, a wiring 5084-1_ i, and a signal 5184-1_i is input to the wiring 5084-2_i. -2_i, a signal 5184-1_i+1 input to the wiring 5084-1_i+1, a signal 50 Signal 5184-2_i+1 input to 84-2_i+1, input to wiring 5086-1_j a signal 5186-1_j input to a wiring 5086-2_j, and a signal 5186-2_j input to a wiring 5086-2_j. , a signal 5186-1_j+1 input to the wiring 5086-1_j+1, a signal 5186-1_j+1 input to the wiring 5086-2 5186-2_j+1 is input to _j+1.

[0349] The pixel of the present embodiment and the semiconductor device, shift register, or By combining it with a display device, various benefits can be obtained. For example, However, when using pixels with a subpixel structure, the number of signals required to drive the display device increases. As a result, the number of gate lines or source lines may increase. However, the number of connections between the board and the external circuitry may increase significantly. Even if the number of lines increases, as shown in the fifth embodiment, the scanning line driver circuit is formed on the same substrate as the pixel section. Therefore, the number of connections between the substrate on which the pixel unit is formed and the external circuit can be reduced. A sub-pixel structure can be used without significantly increasing the source current. Even if the number of source lines increases, the signal line driver circuit of the seventh embodiment can be used to reduce the Therefore, the number of connections between the substrate on which the pixel unit is formed and the external circuit can be reduced. Therefore, a pixel having a sub-pixel structure can be used without significantly increasing the pixel count.

[0350] Or, when inputting a signal to a capacitance line, the number of connections between the substrate on which the pixel unit is formed and the external circuit Therefore, the semiconductor device according to the first to fourth embodiments is provided on the capacitance line. The signals can be provided using semiconductor devices or shift registers. The semiconductor device or shift register of the first to fourth embodiments is formed on the same substrate as the pixel section. Therefore, the number of connections between the substrate on which the pixel unit is formed and the external circuit can be significantly reduced. Therefore, a signal can be input to the capacitance line without increasing the capacitance.

[0351] Or, when AC driving is used, the time required to write a video signal to a pixel becomes long. As a result, there may not be enough time to write the video signal to the pixels. Similarly, when using pixels with a subpixel structure, the time it takes to write a video signal to the pixel is short. As a result, there may not be enough time to write the video signal to the pixel. Therefore, it is possible to write a video signal to the pixel by using the signal line driver circuit of the seventh embodiment. In this case, a precharge voltage is applied to the pixel before writing a video signal to the pixel. Since the video signal is written to the pixel in a short time, the video signal can be written to the pixel in a short time. As shown in FIG. 25(A) or FIG. 25(B), there is a period in which a certain row is selected and a period in which another row is selected. By overlapping the selected period, the video signal of another row is set to the precharge voltage. It is possible to use it as such.

[0352] The pixel driving method of this embodiment and the driving methods of FIGS. 24, 25(A), and 25(B) By combining this with a driving method, the period during which a video signal is written to a pixel can be shortened. With reference to the timing chart of FIG. 29(A) and the pixel configuration of FIG. 27(C), In the k-th frame, a positive video signal is input to the wiring 5084_i. , a negative video signal is input to the wiring 5084_i+1. In the +1 frame, a negative video signal is input to the wire 5084_i, and the wire 5084_i Assume that a positive video signal is input to +1. This is called source line inversion driving. For example, in the second half of the period in which an H signal is input to the wiring 5085_j and It is assumed that the line 5085_j+1 overlaps with the first half of the period in which the H signal is input. In the (k-1)th frame, a negative video signal is written to pixel 5080_i, j+1. In rare cases, pixel 5080_i, j+1 holds a negative video signal. A positive video signal is written to pixels 5080_i+1, j+1. It is assumed that the line 5085_ holds a positive video signal. j, and a signal 5185_j input to a wiring 5085_j+1. +1, a signal 5184_i input to a wiring 5084_i, a signal 5184_i input to a wiring 5084_i+1 5 shows the signal 5184_i+1 being transmitted.

[0353] First, in the k-th frame, a period during which an H signal is input to the wiring 5085_j and a period during which an H signal is input to the wiring 508 In the period where the H signal is input to pixel 508_j+1, a positive video signal is input to pixel 508_j+2. 0_i, j and a negative video signal is written to pixels 5080_i+1, j. At this time, the positive video signal is also written to pixel 5080_i,j+1, and the negative video signal is also written to pixel 5080_i,j+1. The video signal is also written to the pixels 5080_i+1, j+1. The pixels in the j+1th row are precharged using the video signal written to the pixels in the j+1th row. After that, in the k-th frame, during the period in which the H signal is input to the wiring 5085_j+1, In the second half, a positive video signal is written to pixel 5080_i, j+1, and a negative video signal is Of course, the positive video signal is written to the pixels 5080_i+1, j+1. Since pixel 5080_i, j+2 is written to, pixel 5080_i, j+2 is precharged. Similarly, the negative video signal is written to pixels 5080_i+1, j+2. In this way, the pixels 5080_i+1 and j+2 in the jth row are precharged. By precharging the pixels in the j+1th row with the video signal to the pixels, , the period during which a video signal is written to pixels in the j+1th row can be shortened.

[0354] In addition, by combining the driving method of FIG. 29(A) with the pixel configuration of FIG. 29(B), In the pixel configuration of FIG. 29(B), pixel 5 Pixel 5080_i, j is connected to the wiring 5084_i. On the other hand, pixel 5080_i, j+1 is , and the wiring 5084_i+1. In other words, the pixels in the i-th column are alternately connected row by row. In this way, the wiring 5084_i and the wiring 5084_i+1 are connected. The pixel is written with alternating positive and negative video signals, one row at a time, so the dots Inversion driving can be realized. However, this is not limited to this. The pixels in the i-th column are The wiring 5084_i and the wiring 5084_i+1 are alternately arranged in groups of multiple rows (for example, two or three rows). It is possible to be connected.

[0355] (Embodiment 9) In this embodiment, examples of the structure of a transistor will be described with reference to FIGS. ) will be referred to for explanation.

[0356] FIG. 32A shows an example of the structure of a top-gate transistor. FIG. 32B shows This is an example of the structure of a bottom-gate transistor. 1 is an example of a structure of a transistor manufactured by

[0357] FIG. 32A shows a substrate 5260, an insulating layer 5261 formed on the substrate 5260, A region 5262a, a region 5262b, a region 5262c, and a region 5262d are formed on an insulating layer 5261. A semiconductor layer 5262 having regions 5262d and 5262e and a semiconductor layer 5262 having a The insulating layer 5263 is formed as shown in FIG. A conductive layer 5264 having an insulating layer 5263 and a conductive layer 5264 having an opening is formed over the insulating layer 5263 and the conductive layer 5264. and a conductive layer 5265 formed on the insulating layer 5265 and in the opening of the insulating layer 5265. A layer 5266 and a conductive layer 5267 formed on the insulating layer 5265 and having an opening. An insulating layer 5267 and a conductive layer formed on the insulating layer 5267 and in the opening of the insulating layer 5267. 5268, and an insulating layer having an opening formed on the insulating layer 5267 and the conductive layer 5268. A border layer 5269 and a light-emitting layer 5 formed on the insulating layer 5269 and in the opening of the insulating layer 5269. 270 and a conductive layer 5271 formed on the insulating layer 5269 and on the light-emitting layer 5270. show.

[0358] FIG. 32B shows a substrate 5300, a conductive layer 5301 formed on the substrate 5300, An insulating layer 5302 formed to cover the conductive layer 5301, and a conductive layer 5301 and an insulating layer 5302 A semiconductor layer 5303a formed on the semiconductor layer 5303a and a semiconductor layer 5303b formed on the semiconductor layer 5303a. A conductor layer 5303b and a conductive layer formed on the semiconductor layer 5303b and on the insulating layer 5302. A layer 5304 and an insulating layer having an opening formed on the insulating layer 5302 and the conductive layer 5304. A border layer 5305 and a conductive layer 5306 formed on the insulating layer 5305 and in the openings of the insulating layer 5305. 306, a liquid crystal layer 5307 disposed on the insulating layer 5305 and on the conductive layer 5306, A conductive layer 5308 formed on the liquid crystal layer 5307 is shown.

[0359] FIG. 32C shows a semiconductor substrate 5352 having a region 5353 and a region 5355, An insulating layer 5356 formed on the semiconductor substrate 5352 and a A conductive layer 5357 is formed on the insulating layer 5356. 4. An insulating layer 535 having an opening formed on the insulating layer 5356 and the conductive layer 5357. 8 and a conductive layer 5359 formed on the insulating layer 5358 and in the opening of the insulating layer 5358. Thus, transistors are formed in each of the regions 5350 and 5351.

[0360] The insulating layer 5261 can function as a base film. The insulating layer 5263 serves as an isolation layer (e.g., a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as a gate electrode. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are an interlayer film or a flat The conductive layer 5266, the conductive layer 5304, and the conductive layer 5 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a bank. The conductive layer 5271 and the conductive layer 5308 function as a counter electrode, a common electrode, or the like. It is possible.

[0361] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, and a silicon substrate. , a metal substrate, a stainless steel substrate, a flexible substrate, etc. An example of a glass substrate is Examples of flexible substrates include barium borosilicate glass and aluminoborosilicate glass. Examples are polyethylene terephthalate (PET) and polyethylene naphthalate (PEN). , plastics such as polyethersulfone (PES), or flexible materials such as acrylic. Other examples include laminated films (polypropylene, polyester, etc.). steril, vinyl, polyvinyl fluoride, polyvinyl chloride, etc.), paper containing fibrous materials, base fiber Films (polyester, polyamide, inorganic vapor deposition film, paper, etc.)

[0362] The semiconductor substrate 5352 is, for example, a single crystal Si substrate having n-type or p-type conductivity. However, the present invention is not limited to this, and a plate similar to the substrate 5260 can be used. The region 5353 can be, for example, a semiconductor substrate 5352 with impurities. For example, if the semiconductor substrate 5352 is a p-type conductive region, If the region 5353 has an n-type conductivity, the region 5353 functions as an n-well. On the other hand, when the semiconductor substrate 5352 has an n-type conductivity, the region 5353 has a p-type conductivity. The region 5355 has a p-well function. 352 and function as a source region or a drain region. The conductive substrate 5352 may have LDD regions formed therein.

[0363] An example of the insulating layer 5261 is silicon oxide (SiO x ), silicon nitride (SiN x ), nitric oxide Silicon carbide (SiO x N y )(x>y), silicon oxynitride (SiN x O y )(x>y) and other acids The insulating layer 5261 has a two-layer structure. As an example of the structure, a silicon nitride film is provided as the first insulating layer, and a silicon nitride film is provided as the second insulating layer. A silicon oxide film can be provided as the insulating film. The insulating layer 5261 is provided in a three-layer structure. In one example, a silicon oxide film is provided as the first insulating film and a silicon dioxide film is provided as the second insulating film. It is possible to provide a silicon nitride film as the first insulating film and a silicon oxide film as the third insulating film.

[0364] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is an amorphous Amorphous semiconductors, microcrystalline semiconductors, polycrystalline semiconductors, single crystal Crystalline semiconductors, oxide semiconductors (e.g., zinc oxide (ZnO), IGZO (InGaZnO) etc.) Single-layer structure of a compound semiconductor (e.g., gallium arsenide (GaAs)) or a laminated structure thereof.

[0365] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, a small amount of impurity is added to the region 5262a. The impurity added to the region 5262a can be added to the region 5262b, 5262c, 5262d, or 5262e. It is preferable that the regions 5262b and 5262d are lightly doped with impurities. This region functions as a Lightly Doped Drain (LDD) region. However, the area 5262b and the area 5262d can be omitted. The regions 5262c and 5262e are regions in which impurities are added to the semiconductor layer 5262 at a high concentration. It functions as a source region or a drain region.

[0366] When the semiconductor layer 5262 is used for a transistor, the conductivity type of the region 5262c and the It is preferable that the conductivity type is the same as that of region 5262e.

[0367] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0368] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0369] An example of the insulating layer 5263, the insulating layer 5273, and the insulating layer 5356 is silicon oxide (Si O x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y )(x>y), silicon oxynitride SiN x O y ) (x>y) or a film having oxygen or nitrogen, or a laminate structure thereof There are various constructions.

[0370] A conductive layer 5264, a conductive layer 5266, a conductive layer 5268, a conductive layer 5271, a conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 An example of the conductive film 9 is a conductive film having a single layer structure or a laminated structure thereof. Examples include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum. (Mo), Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni) , platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt ( Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon ( C), Scandium (Sc), Zinc (Zn), Phosphorus (P), Boron (B), Arsenic (As) It is composed of gallium (Ga), indium (In), tin (Sn), and oxygen (O). A film of a single element selected from the group, or a film containing one or more elements selected from the group. Examples of the compound include one or more compounds selected from the above group. Alloys containing the elements (Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium tin oxide with silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO ), Cadmium Tin Oxide (CTO), Aluminum Neodymium (Al-Nd), Magnesium Silver (M g-Ag), Molybdenum Niobium (Mo-Nb), Molybdenum Tungsten (Mo-W), Molybdenum-tantalum (Mo-Ta) alloy materials, one selected from the above group or Compounds of multiple elements with nitrogen (nitride films such as titanium nitride, tantalum nitride, and molybdenum nitride) ), or a compound of one or more elements selected from the above group with silicon (tungsten Tensilicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum Other examples include carbon nanotubes, organic nanotubes, etc. The nanotube materials include nanotubes, inorganic nanotubes, or metallic nanotubes.

[0371] Silicon (Si) contains n-type impurities (such as phosphorus) or p-type impurities (such as boron). It is possible to do so.

[0372] When copper is used as a conductive layer, it is recommended to use a laminated structure to improve adhesion. is preferred.

[0373] The conductive layer in contact with the oxide semiconductor or silicon may be formed using molybdenum or titanium. It is preferable to use

[0374] In addition, by using an alloy material of neodymium and aluminum as the conductive layer, This makes it less likely for nium to cause hillocks.

[0375] When a semiconductor material such as silicon is used as the conductive layer, the semiconductor material such as silicon The material can be formed simultaneously with a semiconductor layer of the transistor.

[0376] In addition, ITO, IZO, ITSO, ZnO, Si, SnO, CTO, or carbon nanotube Since the tubes and the like have light-transmitting properties, these materials can be used as pixel electrodes, counter electrodes, or common electrodes. It can be used in light-transmitting parts such as electrodes.

[0377] In addition, by forming a laminated structure using a low resistance material (such as aluminum), The resistance of the line can be reduced.

[0378] In addition, low heat-resistant materials (such as aluminum) are replaced with high heat-resistant materials (such as molybdenum). By sandwiching the low heat resistant material (such as tantalum, titanium, neodymium, etc.) in a laminated structure, This makes it possible to take advantage of the advantages of the material while improving the heat resistance of wiring, electrodes, etc.

[0379] In addition, materials that react to other materials and change their properties are called materials that do not react easily to those other materials. For example, ITO and aluminum can be used to sandwich or cover the material. When connecting the ITO and aluminum, neodymium alloy, titanium, molybdenum For example, when connecting silicon and aluminum, Neodymium alloy, titanium, or molybdenum can be sandwiched between silicon and aluminum. These materials can be used for wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. It can be used anywhere.

[0380] When the conductive layer is provided in a laminated structure, for example, Al may be replaced with Mo or Ti. It is preferable to sandwich the aluminum between the two layers. This improves the resistance of the aluminum to heat and chemical reactions. It can improve the sex.

[0381] An insulating layer 5265, an insulating layer 5267, an insulating layer 5269, an insulating layer 5305, and an insulating layer 535 An example of the insulating film 8 is a single-layer insulating film or a laminated structure thereof. One example is silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride ( SiO x N y )(x>y), silicon oxynitride (SiN x O y ) (x>y) or Nitrogen-containing films, carbon-containing films such as DLC (Diamond-Like Carbon), or siloxane San resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene Examples of the material include organic materials such as acrylic and the like.

[0382] An example of the light-emitting layer 5270 is an organic EL element or an inorganic EL element. An example of the element includes a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, and a hole transport layer made of a hole transport material. a light-emitting layer made of a light-emitting material; an electron transport layer made of an electron transport material; A single layer structure of an electron injection layer, etc., or a layer in which a plurality of these materials are mixed, or These laminated structures are available.

[0383] Note that an insulating layer functioning as an alignment film was provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0384] Note that a color filter, a black matrix, or a protrusion is provided on the conductive layer 5308. An insulating layer or the like that functions as a conductive layer can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0385] In the cross-sectional structure of FIG. 32A, the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 is omitted, and the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 32(B) are replaced with the insulating layer 526 7 and conductive layer 5268.

[0386] In the cross-sectional structure of FIG. 32(B), the liquid crystal layer 5307 and the conductive layer 5308 are omitted. 32(A), an insulating layer 5269, a light-emitting layer 5270, and a conductive layer 5271 are formed on the insulating layer 530. 5 and on the conductive layer 5306.

[0387] In the cross-sectional structure of FIG. 32C, 32(A), an insulating layer 5269, a light-emitting layer 5270, and a conductive layer 5271 are formed. Alternatively, the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. It is possible to form a conductive layer 5267 and a conductive layer 5268 .

[0388] The transistor of the present embodiment is the same as the semiconductor device of the first to eighth embodiments, the shift register In particular, the transistor in FIG. In the present invention, the semiconductor layer is formed of a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor. In this case, the transistor may be deteriorated. In the semiconductor device, the shift register, or the display device according to the first to eighth embodiments, Deterioration can be suppressed.

[0389] (Embodiment 10) In this embodiment, an example of an electronic device will be described.

[0390] 33(A) to 33(H) and 34(A) to 34(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, and an LED. Lamp 5004, operation key 5005, connection terminal 5006, sensor 5007 (force, displacement, position Position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time , hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays 5008, etc.)

[0391] FIG. 33(A) shows a mobile computer, which includes, in addition to the above, a switch 5009, The portable terminal 5010 may have an infrared port 5010. FIG. A type of image reproducing device (e.g., a DVD reproducing device) that, in addition to the above, also has a second display 33C shows a goog In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. FIG. 33(D) shows a portable game machine. In addition to the above, the device may have a recording medium reading unit 5011, etc. In addition to the above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 33(F) shows a portable gaming machine, which, in addition to the above, has a second display unit. 5002, a recording medium reading unit 5011, etc. In addition to the above, the image sensor may also include a tuner, an image processor, etc. 33(H) is a portable television receiver, capable of transmitting and receiving signals in addition to the above. FIG. 34(A) shows a display, and the above-mentioned In addition to the above, a support stand 5018 and the like can be provided. FIG. 34(B) shows a camera. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 34(C) is a computer, In addition, there is a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 34(D) shows a mobile phone, which includes the above-mentioned In addition, an antenna 5014, a 1-segment partial reception service tuner for mobile phones and mobile terminals It may have a nozzle, etc.

[0392] The electronic devices shown in FIGS. 33(A) to 33(H) and 34(A) to 34(D) are For example, various information (still images, videos, text images, etc.) Function to display on the display unit, touch panel function, calendar, date or time display, etc. Functions, functions to control processing by various software (programs), wireless communication functions, A function to connect to various computer networks using wireless communication functions, A function to transmit or receive various data using a program recorded on a recording medium The data can be read out and displayed on the display unit. In electronic devices with displays, one display unit is used primarily to display image information, and another A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a stereoscopic image. In electronic devices having an image receiving unit, the functions of taking still images, taking videos, and The function to automatically or manually correct the captured image, and to store the captured image on a recording medium (external or in the camera) It can have functions such as storing the captured image on a built-in memory and displaying the captured image on the display unit. Note that the electronic devices shown in FIGS. The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0393] The electronic device described in this embodiment has a display unit for displaying some information. The electronic device of the present embodiment and the semiconductor device of the first to ninth embodiments are By combining it with a semiconductor memory device, a shift register, or a display device, the reliability and yield can be improved. This allows for improved resolution, reduced costs, and a larger, more precise display. .

[0394] Next, application examples of the semiconductor device will be described.

[0395] FIG. 34(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. The semiconductor device is a wall-mounted type that is integrated with the building and requires a large space to install. It can be installed without requiring a large space.

[0396] FIG. 34(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 and is The display panel 5026 becomes viewable.

[0397] In this embodiment, a wall and a unit bath are taken as examples of buildings. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various structures.

[0398] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0399] FIG. 34G is a diagram showing an example in which the semiconductor device is provided in an automobile. 028 is attached to the body 5029 of the automobile, and is connected to the body of the automobile or the vehicle. The information input can be displayed on demand. It may be possible.

[0400] FIG. 34(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 34(H) shows a passenger airplane with a display panel 5031 installed on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 5030. and are attached together via a hinge portion 5032, and the expansion and contraction of the hinge portion 5032 causes The passengers can view the display panel 5031. The display panel 5031 can be operated by the passengers. It has the function of displaying information in the above format.

[0401] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorail, etc.) They can be installed on a variety of things, including buildings, railways, ships, etc. [Explanation of symbols]

[0402] 100 circuits 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Capacitive element 106 Capacitive element 107 Diode 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 126 Wiring 127 Wiring 128 Wiring 131 Transistor 132 Transistor 133 Transistor 134 Transistor 135 Transistor 137 Transistor 138 Transistor 200 Flip-Flops 201 Wiring 202 Wiring 203 Wiring 204 Wiring 205 Wiring 206 Wiring 207 Wiring 211 Circuit 212 Circuit 213 Circuit 214 Circuit 215 Circuit 216 Circuits 220 Shift Register 221 Circuit 222 Circuit 223 Circuit 301 Transistor 302 Transistor 303 Transistor 304 Transistor 311 Wiring 320 Flip-flop 321 Wiring 401 Conductive layer 402 Semiconductor layer 403 Conductive layer 404 Conductive layer 405 Contact Hole 411 Opening 412 Opening 421 Wiring width 422 Wiring width 423 Width 424 Width 426 Width 431 Width 432 Width 500 circuits 501 Circuit 502 Circuit 503 Transistor 504 Wiring 505 Wiring 514 Signal 515 Signal 101p transistor 102p transistor 103a Diode 103p transistor 104a Diode 104p transistor 105a Transistor 106a Transistor 107a Transistor 122A Wiring 122B Wiring 122C Wiring 122D Wiring 122E Wiring 122F Wiring 122G Wiring 122H Wiring 122I Wiring 123A Wiring 123B Wiring 123C Wiring 123D Wiring 123E Wiring 124A Wiring 124B Wiring 124C Wiring 133a Diode 134a Diode 135a Diode 5000 cabinet 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Reader / Writer 5022 Case 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bath 5028 Display Panel 5029 Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection Lens 5080 pixels 5081 Transistor 5082 Liquid crystal element 5083 Capacitive element 5084 Wiring 5085 Wiring 5086 Wiring 5087 Wiring 5088 Electrode 5184 Signal 5185 Signal 5186 Signal 5260 PCB 5261 Insulation layer 5262 Semiconductor layer 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulation layer 5268 Conductive layer 5269 Insulation layer 5270 Light-emitting layer 5271 Conductive layer 5273 Insulation layer 5300 Board 5301 Conductive layer 5302 Insulating layer 5304 Conductive layer 5305 Insulation layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 PCB 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5360 Video signal 5361 Circuit 5362 Circuit 5363 Circuit 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 PCB 5381 Input terminal 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a Circuit 5361b circuit 5362a Circuit 5362b circuit

Claims

1. A semiconductor device comprising first to sixth transistors, a first capacitance element, a second capacitance element, and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; the gate of the second transistor is always electrically connected to the fourth wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the first wiring; the gate of the sixth transistor is always electrically connected to the sixth wiring; a first electrode of the first capacitance element is always electrically connected to a gate of the fourth transistor; a second electrode of the first capacitance element is always electrically connected to the second wiring; a first electrode of the second capacitance element is always electrically connected to the first wiring; a second electrode of the second capacitance element is always electrically connected to a gate of the first transistor; the first wiring has a function as a first gate line, the second wiring has a function as a first clock signal line, The third wiring has a function as a power supply line, the fourth wiring has a function as a second clock signal line, when the fifth wiring and the gate of the first transistor are electrically connected via at least a channel formation region of the third transistor, a potential of the fifth wiring is applied to the gate of the first transistor via at least a channel formation region of the third transistor, The channel width of the second transistor is larger than the channel width of the third transistor. Semiconductor device.

2. A semiconductor device comprising first to sixth transistors, a first capacitance element, a second capacitance element, and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; the gate of the second transistor is always electrically connected to the fourth wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the first wiring; the gate of the sixth transistor is always electrically connected to the sixth wiring; a first electrode of the first capacitance element is always electrically connected to a gate of the fourth transistor; a second electrode of the first capacitance element is always electrically connected to the second wiring; a first electrode of the second capacitance element is always electrically connected to the first wiring; a second electrode of the second capacitance element is always electrically connected to a gate of the first transistor; the first wiring has a function as a first gate line, the second wiring has a function as a first clock signal line, The third wiring has a function as a power supply line, the fourth wiring has a function as a second clock signal line, when the fifth wiring and the gate of the first transistor are electrically connected via at least a channel formation region of the third transistor, a potential of the fifth wiring is applied to the gate of the first transistor via at least a channel formation region of the third transistor, a first conductive layer having a function as one of a source and a drain of the first transistor has a function as the other of the source and the drain of the second transistor, a function as the other of the source and the drain of the sixth transistor, and a function as a first electrode of the second capacitor; The channel width of the second transistor is larger than the channel width of the third transistor. Semiconductor device.

3. In claim 2, In the first conductive layer, a region having a function as the other of the source and the drain of the second transistor includes a region disposed between a region having a function as the other of the source and the drain of the sixth transistor and a region having a function as a first electrode of the second capacitor element. Semiconductor device.

4. A semiconductor device comprising first to sixth transistors, a first capacitance element, a second capacitance element, and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; the gate of the second transistor is always electrically connected to the fourth wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the first wiring; the gate of the sixth transistor is always electrically connected to the sixth wiring; a first electrode of the first capacitance element is always electrically connected to a gate of the fourth transistor; a second electrode of the first capacitance element is always electrically connected to the second wiring; a first electrode of the second capacitance element is always electrically connected to the first wiring; a second electrode of the second capacitance element is always electrically connected to a gate of the first transistor; the first wiring has a function as a first gate line, the second wiring has a function as a first clock signal line, The third wiring has a function as a power supply line, the fourth wiring has a function as a second clock signal line, when the fifth wiring and the gate of the first transistor are electrically connected via at least a channel formation region of the third transistor, a potential of the fifth wiring is applied to the gate of the first transistor via at least a channel formation region of the third transistor, a first conductive layer having a function as one of a source and a drain of the first transistor has a function as the other of the source and the drain of the second transistor, a function as the other of the source and the drain of the sixth transistor, and a function as a first electrode of the second capacitor; the second conductive layer having a function as the other of the source and the drain of the first transistor has a function as a second electrode of the first capacitor; The channel width of the second transistor is larger than the channel width of the third transistor. Semiconductor device.

5. A semiconductor device comprising first to sixth transistors, a first capacitance element, a second capacitance element, and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; the gate of the second transistor is always electrically connected to the fourth wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the first wiring; the gate of the sixth transistor is always electrically connected to the sixth wiring; a first electrode of the first capacitance element is always electrically connected to a gate of the fourth transistor; a second electrode of the first capacitance element is always electrically connected to the second wiring; a first electrode of the second capacitance element is always electrically connected to the first wiring; a second electrode of the second capacitance element is always electrically connected to a gate of the first transistor; the first wiring has a function as a first gate line, the second wiring has a function as a first clock signal line, The third wiring has a function as a power supply line, the fourth wiring has a function as a second clock signal line, when the fifth wiring and the gate of the first transistor are electrically connected via at least a channel formation region of the third transistor, a potential of the fifth wiring is applied to the gate of the first transistor via at least a channel formation region of the third transistor, a first conductive layer having a function as one of a source and a drain of the first transistor has a function as the other of the source and the drain of the second transistor, a function as the other of the source and the drain of the sixth transistor, and a function as a first electrode of the second capacitor; the second conductive layer having a function as the other of the source and the drain of the first transistor has a function as a second electrode of the first capacitor; one third conductive layer having a function as one of a source or a drain of the fourth transistor has a function as one of a source or a drain of the fifth transistor, a function as one of a source or a drain of the second transistor, and a function as one of a source or a drain of the sixth transistor; The channel width of the second transistor is larger than the channel width of the third transistor. Semiconductor device.

6. A semiconductor device comprising first to sixth transistors, a first capacitance element, a second capacitance element, and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; the gate of the second transistor is always electrically connected to the fourth wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the first wiring; the gate of the sixth transistor is always electrically connected to the sixth wiring; a first electrode of the first capacitance element is always electrically connected to a gate of the fourth transistor; a second electrode of the first capacitance element is always electrically connected to the second wiring; a first electrode of the second capacitance element is always electrically connected to the first wiring; a second electrode of the second capacitance element is always electrically connected to a gate of the first transistor; the first wiring has a function as a first gate line, the second wiring has a function as a first clock signal line, The third wiring has a function as a power supply line, the fourth wiring has a function as a second clock signal line, when the fifth wiring and the gate of the first transistor are electrically connected via at least a channel formation region of the third transistor, a potential of the fifth wiring is applied to the gate of the first transistor via at least a channel formation region of the third transistor, a first conductive layer having a function as one of a source and a drain of the first transistor has a function as the other of the source and the drain of the second transistor, a function as the other of the source and the drain of the sixth transistor, and a function as a first electrode of the second capacitor; the second conductive layer having a function as the other of the source and the drain of the first transistor has a function as a second electrode of the first capacitor; one third conductive layer having a function as one of a source or a drain of the fourth transistor has a function as one of a source or a drain of the fifth transistor, a function as one of a source or a drain of the second transistor, and a function as one of a source or a drain of the sixth transistor; a fourth conductive layer having a function as a gate of the fourth transistor has a function as a first electrode of the first capacitor; The channel width of the second transistor is larger than the channel width of the third transistor. Semiconductor device.

7. In any one of claims 1 to 6, a fifth conductive layer having a function as a gate of the first transistor has a function as a gate of the fifth transistor and a function as a second electrode of the second capacitor element; Semiconductor device.

8. In any one of claims 4 to 6, a fifth conductive layer having a function as a gate of the first transistor has a function as a gate of the fifth transistor and a function as a second electrode of the second capacitor; the fifth conductive layer has a first region overlapping the first conductive layer and a second region overlapping the second conductive layer; The first region has an area larger than that of the second region. Semiconductor device.

9. In claim 5 or 6, a fifth conductive layer having a function as a gate of the first transistor has a function as a gate of the fifth transistor and a function as a second electrode of the second capacitor; the fifth conductive layer has a fifth region overlapping with one sixth conductive layer having a function as the other of the source and the drain of the fifth transistor, and a sixth region overlapping with the third conductive layer; The fifth region has an area smaller than that of the sixth region. Semiconductor device.

10. In any one of claims 7 to 9, In the fifth conductive layer, a region having a function as a gate of the first transistor includes a region disposed between a region having a function as a gate of the fifth transistor and a region having a function as a second electrode of the second capacitor element. Semiconductor device.

11. In any one of claims 1 to 10, a seventh conductive layer having a function as a gate of the third transistor includes a third region overlapping with an eighth conductive layer having a function as one of a source and a drain of the third transistor, and a fourth region overlapping with a ninth conductive layer having a function as the other of the source and the drain of the third transistor; The third region has an area smaller than that of the fourth region. Semiconductor device.

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