COMMUNICATION DEVICE, CONTROL METHOD AND PROGRAM FOR COMMUNICATION DEVICE

Abstract

To prevent a reduction in the accuracy of time synchronization regardless of the magnitude of the difference between a reference time and the time of a communication device.SOLUTION: A communication device comprises: a first counter that synchronizes with a reference time; a second counter that synchronizes with the first counter; generation means that generates a synchronization signal every time the value of the second counter is incremented by a predetermined number; correction means that corrects the value of the second counter so that the value approaches the value of the first counter; and control means that calculates the difference between the value of the first counter and the value of the second counter, and when the calculated difference is larger than a predetermined threshold, controls the correction means to gradually correct the value of the second counter.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a communication device that performs time synchronization using a network. [Background technology]

[0002] 2. Description of the Related Art In recent years, technology for synchronizing the time of a plurality of devices and operating them as a large system has come to be used in many fields. One example of such a system is a technology called stadium vision or volumetric studio, which uses images from multiple time-synchronized cameras and creates free-viewpoint video by switching to an image of any viewpoint in real time.

[0003] To obtain high-quality free viewpoint video, the time between multiple cameras must be accurately synchronized. One example of a technology for achieving time synchronization between the communication terminals that control each camera is the Precision Time Protocol (PTP). Synchronization signals such as Pulse Per Second (PPS) and Generator Lock (GenLock) can be used to synchronize the time between the communication terminals and the cameras.

[0004] The internal clock of the communication terminal that controls each camera may contain errors due to jitter, etc., so a time synchronization system generally includes a time server that distributes a reference time. This time server has a highly accurate clock such as a Global Positioning System (GPS) as a reference for aligning the synchronization signal, and distributes its own time as the reference time to each communication terminal.

[0005] Patent Document 1 discloses a synchronization signal output device that acquires time from a time server, synchronizes an internal clock to the acquired time, generates a synchronization signal, and outputs it to an image capture device. Specifically, the synchronization signal output device of Patent Document 1 acquires the error between the time of the time server and the time of the internal clock, and sets an operation mode in which the timing of the synchronization signal based on the error is not adjusted if the magnitude of the acquired error exceeds a threshold. In other words, when the error between the time of the time server and the time of the internal clock exceeds a threshold, a free-running mode in which the synchronization signal is not adjusted is used to prevent a certain degree of deviation or more in the synchronization signal input to the image capture device, which makes it impossible to continue image capture. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2018-191226 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, the communication terminal that controls each camera does not necessarily have a highly accurate internal clock. If the accuracy of the internal clock of a communication terminal is low, there is a risk that the synchronization signal input from the communication terminal to the camera will gradually become out of sync in the technology described in Patent Document 1. In such a case, if the communication terminal outputs a gradually out-of-sync synchronization signal to the camera without executing resynchronization processing with the reference time distributed from the time server, it may become difficult to continue synchronous imaging using multiple cameras.

[0008] An object of the present invention is to make it possible to suppress a decrease in accuracy in time synchronization, regardless of the magnitude of the difference between the reference time and the time of the own device. [Means for solving the problem]

[0009] In order to achieve the above object, a communication device according to the present invention includes a first counter synchronized with a reference time, a second counter synchronized with the first counter, a generating means for generating a synchronization signal based on a value of the second counter being incremented by a predetermined number, a correcting means for controlling the second counter based on a correction value based on a timing pulse for updating the second counter output from the first counter so that the value of the second counter approaches the value of the first counter, and a control means for calculating a difference between the value of the first counter and the value of the second counter, and if the calculated difference is greater than a predetermined threshold, controlling the second counter using a value based on the predetermined threshold as the correction value, and controlling the correcting means. Generate means Generated by The timing of output of the synchronization signal does not overlap. Effect of the Invention

[0010] According to the present invention, it is possible to suppress a decrease in accuracy in time synchronization, regardless of the magnitude of the difference between the reference time and the time of the own device. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing an example of a network configuration of a time synchronization system according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram showing an example of the internal configuration of the synchronous communication device according to the embodiment. [Diagram 3] 3 is a block diagram showing an example of a detailed internal configuration of a synchronization signal generating unit in FIG. 2; [Figure 4] 5 is a timing chart illustrating a process in which a synchronization signal generating unit according to the embodiment generates a synchronization signal. [Diagram 5] 4 is a block diagram showing an example of a detailed internal configuration of the counter 2 in FIG. 3. [Figure 6]5 is a flowchart showing an example of a processing procedure of a correction process for a counter 2 executed by a synchronization signal generating unit of the synchronous communication device according to the first embodiment. [Figure 7] 5 is a waveform diagram illustrating an example of a relationship between synchronous imaging timing of a time synchronization system and timing of receiving a synchronization signal from each imaging device. [Figure 8] 11 is a waveform diagram illustrating an example of output timing of a control signal corrected by a synchronization signal generating unit of a synchronous communication device according to a second embodiment. FIG. [Figure 9] 11 is a flowchart showing an example of a processing procedure of a correction process for a counter 2 executed by a synchronization signal generating unit of a synchronous communication device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment for carrying out the present invention will be described in detail with reference to the attached drawings. Note that the embodiment described below is one example of a means for realizing the present invention, and should be appropriately modified or changed depending on the configuration of the device to which the present invention is applied and various conditions, and the present invention is not limited to the following embodiment. Also, not all of the combinations of features described in the present embodiment are necessarily essential to the solution of the present invention.

[0013] (Embodiment 1) <Network configuration of time synchronization system> Fig. 1 is a diagram showing an example of a network configuration of a system 1 for performing time synchronization according to the present embodiment. Fig. 1 shows a system for performing synchronous imaging using a plurality of imaging devices as an example, but the present embodiment is not limited to this and may be applied to any system that can utilize time synchronization using a network. The time synchronization system 1 in FIG. 1 includes a time server 11, a plurality of synchronous communication devices 12a, 12b, 12c, 12d, 12e, and 12f, a TC switching hub 13, and a plurality of imaging devices 14a, 14b, 14c, 14d, 14e, and 14f.

[0014] 1, the time server 11 is connected to the synchronous communication devices 12a, 12d, and 12f via a switching hub 13 on a network, and transmits time information of the time server 11 to the synchronous communication devices 12a, 12d, and 12f. Alternatively, the time server 11 may be directly connected to the synchronous communication devices 12a, 12d, and 12f without going through the TC switching hub 13. The synchronous communication device 12b and the synchronous communication device 12c are daisy-chained to the synchronous communication device 12a, and the synchronous communication device 12a is daisy-chained to the synchronous communication device 12d.

[0015] Imaging devices 14a to 14f such as cameras are connected to the synchronous communication devices 12a to 12f via a network, respectively. The synchronous communication devices 12a to 12f synchronize their times with each other via the network and transmit and receive data. The network may be, for example, GbE (Gigabit Ethernet), 10 GbE, or 100 GbE conforming to the IEEE standard, which is Ethernet (registered trademark). The network may also be combined with other wired lines, such as interconnect (Infiniband) and industrial Ethernet. The network is not limited to these, and may be other types of networks, such as wireless lines using Wi-Fi (registered trademark), Bluetooth (registered trademark), or a combination of these.

[0016] The time server 11 is a server that has an accurate internal clock and distributes the time of its own clock as a time source using a time synchronization protocol. The time source of the time server 11 may be a GPS, a standard radio wave, an atomic clock, or the like, but this embodiment is not limited to these. Other types of time sources, such as an oven controlled crystal oscillator (OCXO), may be used as the time source of the time server 11 as long as they are more accurate than the synchronous communication devices 12a to 12f.

[0017] The time synchronization protocol may be PTP (Precision Time Protocol) conforming to the IEEE1588 standard, but the present embodiment is not limited to this. The system according to the present embodiment may also be configured with other types of time synchronization protocols, such as AVB (Audio Video Bridging) conforming to the IEEE802.1 standard or PPS (Pulse Per Second) signals. In the time synchronization system of FIG. 1, multiple time servers 11 may be provided to ensure redundancy in time synchronization.

[0018] The synchronous communication devices 12a-12f may all be the same device, but may have different configurations as long as they have the functions described below. The synchronous communication devices 12a-12f have internal clocks, update the time of their own clocks using a time synchronization protocol, and transmit control signals 15a-15f to the imaging devices 14a-14f, respectively. While the synchronous communication devices 12a to 12f cannot receive the time synchronization protocol, they maintain the synchronization signal in the control signals 15a to 15f using their own clocks, and execute time synchronization with the imaging devices 14a to 14f.

[0019] Taking the synchronous communication device 12b as an example, the synchronous communication device 12b is connected to the synchronous communication devices 12a and 12c connected before and after the synchronous communication device 12b, and transmits and receives time information and image data. The synchronous communication device 12b transmits a synchronous signal generated based on the time information from the synchronous communication devices 12a and 12c before and after the synchronous communication device 12b to the imaging device 14b connected to the synchronous communication device 12b. The connection form between the synchronous communication devices 12a to 12f is arbitrary, and the synchronous communication devices 12a, 12b, and 12c, and the synchronous communication devices 12d and 12e may be daisy-chained. Alternatively, the synchronous communication devices 12a, 12d, and 12f may be star-connected using a TC switching hub 13. The connections between the synchronous communication devices 12a to 12f may be duplicated to ensure redundancy in time synchronization.

[0020] The TC switching hub 13 has a TC (Transparent Clock) function that measures the time required for relaying a PTP packet in its own device and notifies the destination of the PTP message. The switching hub 13 is a hub that connects the time server 12 to the downstream destination while maintaining the time synchronization protocol. The switching hub 13 is necessary when using multiple time servers 11 or when star-connecting the synchronous communication devices 12a, 12d, and 12f, but is not necessary when the time server 11 has multiple ports and directly connects the synchronous communication devices 12a, 12d, and 12f.

[0021] The imaging devices 14a to 14f are devices to which the control signals 15a to 15f are output from the synchronous communication devices 12a to 12f. The imaging devices 14a to 14f receive the control signals 15a to 15f from the synchronous communication devices 12a to 12f, respectively, and transmit image data captured in synchronization based on the synchronization signals in the control signals 15a to 15f to the synchronous communication devices 12a to 12f. The imaging devices 14a to 14f have internal clocks and update their own time based on the control signals 15a to 15f. The imaging devices 14a to 14f also have a synchronization signal reception timing at which they can receive a synchronization signal in response to the synchronization signal in the control signals 15a to 15f. The imaging devices 14a to 14f can be time-synchronized with the synchronous communication devices 12a to 12f by receiving a synchronization signal during a period defined by the synchronization signal reception timing.

[0022] The imaging devices 14a to 14f do not have to have the same configuration, and may be different models of devices, for example. The devices may also include distance measuring sensors such as LiDAR (Light Detection and Ranging) and RADAR (Radio Detecting and Ranging). In this embodiment, unless otherwise specified, the image will be described as including a moving image and a still image. That is, in the time synchronization system 1 according to this embodiment, time synchronization processing is possible for both a still image and a moving image.

[0023] The control signals 15a to 15f are sent from the synchronous communication devices 12a to 12f to the imaging devices 14a to 14f, respectively, and include setting information and synchronization signals for the imaging devices 14a to 14f. The synchronization signals include a GenLock signal, which is a pulse that notifies the imaging device of a precise imaging interval, a Timecode signal, and the like. By imaging a subject in synchronization with other imaging devices based on such synchronization signals, imaging can be performed with the imaging times synchronized at a constant cycle among the imaging devices 14a to 14f.

[0024] <Internal configuration of synchronous communication device> Fig. 2 is a block diagram showing an example of the internal configuration of the synchronous communication device shown in Fig. 1. Note that Fig. 2 representatively shows the synchronous communication device 12b, its internal configuration, and connections with other devices, among the synchronous communication devices 12a to 12f shown in Fig. 1, but the other synchronous communication devices 12a, 12c to 12f connected to the synchronous communication device 12b may have the same internal configuration.

[0025] The synchronous communication device 12b includes communication units 21a and 21b, a control unit 22, a storage unit 23, a synchronous signal generation unit 24, a video transmission processing unit 25, an imaging device control unit 26, and an image processing unit 27. The functional blocks 21a, 21b, and 22 to 27 of the synchronous communication device 12b are interconnected via a system bus, and transmit and receive various control information, image data, etc. The synchronous communication device 12b is connected to the synchronous communication device 12a at the front stage and the synchronous communication device 12c at the rear stage via the communication units 21a and 21b, respectively.

[0026] The communication units 21a and 21b are communication interfaces consisting of PHY, which is a physical layer, and MAC, which is a data link layer. The communication unit 21a receives image data from the preceding synchronous communication device 12a and supplies it to the video transmission processing unit 25. The communication unit 21b receives image data from the preceding stage and the imaging device 14b from the video transmission processing unit 25, and transmits it to the following synchronous communication device 12c.

[0027] The communication units 21a and 21b also acquire accurate time information and timing information from the time server 11 via a time synchronization protocol such as PTP, and notify the synchronization signal generating unit 24 of the acquired time information and timing information. Here, the time information is a value associated with the current time that can be used by the synchronization signal generating unit 24, and the timing information is a signal that notifies the timing of updating the value of the time information. When the synchronous communication device 12b is the terminal farthest from the time server 11 in the daisy chain connection or when it is star-connected with the time server 11, it is the terminal that is the end terminal, and therefore the communication unit 21b does not need to be connected to the outside.

[0028] The control unit 22 is a processor such as a CPU that executes the overall control of the synchronous communication device 12b. The control unit 22 executes control of a time synchronization sequence defined by a time synchronization standard such as PTP, control of image packet transfer including image data received from the preceding synchronous communication device 12a, and the like. The control unit 22 also generates a timecode to be stored in the control signal 15b based on time information acquired from the communication units 21a and 21b via the system bus. The timecode is a timing signal for video synchronization. The control unit 22 transmits control information 305 for causing the synchronization signal generating unit 24 to execute a synchronization signal generating process (correction process) according to this embodiment, the details of which will be described later with reference to FIG. 3.

[0029] The storage unit 23 is a main storage device that can be shared and used by each functional block in the synchronous communication device 12b, and may be mainly composed of a semiconductor memory such as a dynamic random access memory (DRAM), etc. The storage unit 23 stores various information used by each functional block 21a, 21b to 27 of the synchronous communication device 12b, control information for controlling the imaging device 14b, etc.

[0030] The synchronization signal generating unit 24 receives time information and timing information from the communication units 21a and 21b, and generates a pulse 301 to be output to the video transmission processing unit 25 and the imaging device control unit 26. The pulse 301 is a signal that is the basis of a synchronization signal, which will be described later, and may be, for example, a PPS having accurate intervals and ratios. Details of the pulse 301 generation process will be described later with reference to Figs. 3 to 5. The synchronization signal generating unit 24 also has a register for setting and storing a threshold value and the like when aligning the phase of the pulse 305 via the system bus.

[0031] The video transmission processing unit 25 generates image packets to be output by the synchronous communication device 12b. Specifically, the video transmission processing unit 25 packetizes the images captured by the imaging device 14b and received from the image processing unit 27, and transmits the packets to the communication unit 21b together with the image packets of the preceding synchronous communication device 12a received from the communication unit 21a. The video transmission processing unit 25 also receives a pulse 301 from the synchronization signal generating unit 24 and supplies a time stamp to the image data received from the image processing unit 27. When the synchronous communication device 12b is the terminal closest to the time server 11 in the daisy chain connection or when the synchronous communication device 12b is star-connected with the time server 11, the image packet of the preceding synchronous communication device does not need to be present.

[0032] The imaging device control unit 26 generates a control signal 15b for controlling the imaging device 14b, and transmits the generated control signal 15b to the imaging device 14b. Specifically, the imaging device control unit 26 receives a pulse 301 supplied from the synchronization signal generating unit 24, and generates a synchronization signal in the control signal 15b. The imaging device control unit 26 also stores a timecode supplied from the control unit 22 in the control signal 15b.

[0033] The image processing unit 27 performs various image processing on the image data transmitted from the imaging device 14b. The image data is captured by the imaging device 14b in synchronization with a synchronization signal in a control signal 151 output from the imaging device control unit 26 to the imaging device 14b. The captured image data is transmitted to the image processing unit 27 together with a timecode. The image processing unit 27 performs various image processing, such as cutting out the background and foreground, on the image data received from the imaging device 14b, and supplies the processed image data to the video transmission processing unit 25.

[0034] In addition, all or part of the synchronous signal generating unit 24, the video transmission processing unit 25, the imaging device control unit 26, and the image processing unit 27 of the synchronous communication device 12b shown in FIG. 2 may be implemented in hardware. The functions realized by the hardware may be realized, for example, by automatically generating a dedicated circuit on the FPGA from a program for realizing the function of each functional module by using a predetermined compiler. FPGA is an abbreviation for Field Programmable Gate Array. Also, a gate array circuit may be formed in the same manner as the FPGA, and the functions may be realized as hardware. Also, the functions may be realized by an ASIC (Application Specific Integrated Circuit). Also, the functions realized by the software may be realized by storing a program for providing the function of each functional module in a memory such as a ROM. Then, the program may be read into a RAM and executed by a CPU. Furthermore, the functional block configuration shown in FIG. 2 is just an example, and multiple functional blocks may execute one function, or any of the functional blocks may be divided into blocks that execute multiple functions.

[0035] FIG. 3 is a block diagram showing an example of a detailed configuration of the synchronization signal generating unit in FIG. 3, the synchronization signal generating unit 24 includes a counter 1 (31), a counter 2 (32), and a bus interface 33. Both the counter 1 (31) and the counter 2 (32) update their own values ​​at the timing of a clock supplied from the outside. The bus interface 33 acquires various setting information and control information via the system bus.

[0036] A clock 302 that drives each component, time information 303 from the communication units 21a and 21b, and update timing 1 (304) that is the update timing of counter 1 (31) are input to the synchronization signal generation unit 24. A pulse 301 is sent from the synchronization signal generation unit 24 to the video transmission processing unit 25 and the imaging device control unit 26.

[0037] Counter 1 (31) is a free-running counter whose value can be rewritten from the outside, and increments its own value by clock 302, which is an internal clock, except at update timings. Counter 1 (31) is notified of time information 303 and update timing 1 (304) from communication units 21a and 21b, and at the timing of update timing 1 (304), counter 1 (31) is rewritten to the value of time information 303. This allows counter 1 (31) to synchronize with the accurate time from time server 11, which is the time source. Counter 1 (31) outputs its own value 306 and update timing 2 (307), which is generated based on its own value, to counter 2 (32).

[0038] Counter 2 (32) is a self-running counter whose value can be rewritten from the outside, and increments its own value according to clock 302, which is an internal clock, except at update timings. Counter 2 (32) is notified of counter 1 value 306 and update timing 2 (307) from counter 1 (31), and counter 2 (32) is updated at the timing of update timing 2 (307). In this embodiment, counter 2 (32) is updated using either counter 1 value 306 or a correction value in control information 305. Counter 2 (32) outputs a pulse 301 by raising a signal when its own value reaches a set value and lowering the signal when it reaches the next set value. Here, the set value is the value at which counter 3 (32) outputs pulse 301. As a result, counter 2 (32) outputs pulse 301, which serves as a synchronization signal, to the video transmission processing unit 25 and the imaging device control unit 26 every time counter 2 (32) is incremented by a predetermined number.

[0039] The bus interface 33 is an interface that communicates with the outside of the synchronization signal generating unit 24 via a system bus. The bus interface 33 outputs, as control information 305, threshold values ​​used when initializing or stopping the counter 1 (31) and the counter 2 (32) and updating the counter 2 (32) to the counter 1 (31) and the counter 2 (32). Clock 302 is a clock signal of an internal clock that drives counter 1 (31) and counter 2 (32). Both counter 1 (31) and counter 2 (32) use this clock 302 to increment their own values ​​except at update timings. Clock 302 is also used to drive bus interface 33.

[0040] The time information 303 and update timing 1 (304) are accurate time information and timing information from the time server 11, which are notified from the communication units 21a and 21b. Pulse 301 is a phase pulse generated based on the value of counter 2 (32). Counter 1 (31), which is the synchronization source of counter 2 (32), is synchronized by time information 303 and update timing 1 (304). Therefore, pulse 301 is sent at the same time between synchronous communication devices 12a to 12f that are time-synchronized.

[0041] The control information 305 is information including a correction value and a threshold value between counter 1 (31) and counter 2 (32) acquired from the control unit 22 via the system bus. In this embodiment, a synchronization signal is generated (corrected) using the correction value and the threshold value between counter 1 (31) and counter 2 (32) included in the control information 305 supplied from the control unit 22 via the bus interface 33.

[0042] Here, the threshold value is the maximum allowable error in time that does not allow the time synchronization between the synchronous communication device 12b and the imaging device 14b to be lost, that is, that ensures synchronous imaging by the multiple imaging devices 14a to 14f, and may be a fixed value. In other words, the threshold value is the maximum phase error required for the synchronization signal to continue synchronous imaging in the time synchronization system. The correction value is a value determined within this threshold value for correcting counter 2 (32) based on counter 1 (31), and may be a fixed value. The correction value may be set to a value smaller than the threshold value or may be set to the same value as the threshold value. The control information 305 may further include default values ​​for resetting the counter 1 (31) and the counter 2 (32), default increment values, and the like.

[0043] Fig. 4 is a timing chart for explaining the process of generating a synchronization signal by the synchronization signal generating unit 24 of this embodiment. Specifically, Fig. 4 shows the process from when the synchronization signal generating unit 24 of Fig. 3 inputs the time information 303 and the update timing 1 (304) from the communication units 21a and 21b to when it generates a pulse 301. In Fig. 4, for simplicity of explanation, time information 303, counter 1 value 306, and counter 2 value 308 are all two digits, but in reality they may be any number of digits. Also, the increment value is 1, but in reality the increment value may be determined by the timing of the clock and pulse. The increment value of counter 2 (32) is determined by a synchronization signal correction process described later with reference to Fig. 6. Fig. 4 explains the operation when the difference between counter 1 (31) and counter 2 (32) is within a threshold value.

[0044] 4, the output of the pulse 301 is a pulse that rises when the counter binary value 308 transitions from 9 to 0, and falls when the counter binary value 308 transitions from 0 to 1. In FIG. 4, it is assumed that time information 303 and update timing 1 (304) are input to the synchronization signal generating unit 24 at times 03, 14, and 25.

[0045] Counter 1 value 306 is the value of the internal counter of counter 1 (31). Counter 1 (31) increments its own value by clock 302 while update timing 1 (304) is not arriving, and is updated to the value of time information 303 at update timing 1 (304). The value of counter 1 (31) is also sent to counter 2 (32) as a reference for updating (correcting) counter 2 value 308. In FIG. 4, counter 1 value 306 is overwritten by the value of time information 303 at the input (rising edge) of update timing 1 (304).

[0046] Update timing 2 (307) is a signal notifying the timing of updating counter 2 value 308 to counter 1 value 306. Counter 1 (31) generates update timing 2 (307) based on its own value and transmits it as a pulse to counter 2 (32). In FIG. 4, update timing 2 (307) is sent to counter 2 (32) at the timing of cycle 11 when counter 1 value 306 is 06, 17, and 28.

[0047] If update timing 2 (307) overlaps with pulse 301 in terms of transmission timing, there is a possibility that a double pulse will be transmitted or that a pulse will not be transmitted. In this case, the synchronization signal generating unit 24 can avoid an effect on the transmission of pulse 301 by setting update timing 2 (307) so that it does not overlap in time with the transmission timing of pulse 301. Also, update timing 1 (304) is a signal inserted from the outside, but if the timing of update timing 1 (304) is predictable, the synchronization signal generating unit 24 can avoid an effect on update timing 2 (307) by avoiding that timing.

[0048] Counter 2 value 308 is the value of an internal counter of counter 2 (32) for generating the output pulse 301. Counter 2 value 308 is updated to counter 1 value 306 at update timing 2 (307) notified from counter 1 (31).

[0049] 4, the synchronization signal generating unit 24 transmits the pulse 301 every time the counter binary value 308 is incremented by 10. Therefore, the synchronization signal generating unit 24 can adjust the timing at which the counter binary value 308 becomes 10, that is, the timing at which the pulse 301 is transmitted, by rewriting the counter binary value 308. Alternatively, the synchronization signal generating unit 24 may adjust the timing of sending the pulse 301 by increasing or decreasing the set value for sending the pulse 301, without rewriting the counter binary value 308 itself. For example, when adjusting the sending of the pulse 301 backward by three clocks, the synchronization signal generating unit 24 may correct the set value of the sending timing from 10 to 13.

[0050] Fig. 5 is a block diagram showing an example of a detailed internal configuration of the counter 2 (32) shown in Fig. 3. Referring to Fig. 5, the counter 2 (32) includes a correction unit 321, an internal counter 322, and a pulse output unit 323. Counter 2 (32) sends out a pulse 301 in the synchronization signal generating unit 24. Specifically, counter 2 (32) receives counter 1 value 306 and update timing 2 (307) from counter 1 (31) and control information 305 from the bus interface 33, and sends out a pulse 301 based on the value of the internal counter 322.

[0051] The correction unit 321 specifies an increment value for the internal counter 322. Specifically, the correction unit 321 calculates the difference between the counter 1 value 306 and the value of the internal counter 322, calculates an increment value for the internal counter 322 based on the calculated difference value, and outputs the calculated increment value to the internal counter 322.

[0052] Here, the difference value is the absolute value of the value obtained by subtracting the counter 1 value 306 from the counter 2 value 308 output by the internal counter 322, but it may be positive or negative. If the counter 1 value 306 lags behind the internal counter 322, the internal counter 322 may be stopped and corrected to wait until the counter 1 value 306 is incremented to the value of the stopped internal counter 322.

[0053] In this embodiment, in addition to the difference between counter 1 (31) and counter 2 (32), a threshold value and a correction value for switching the correction method obtained from the control information 305 are used as the increment value of the internal counter 322, the details of which will be described later with reference to Fig. 6. When performing a correction to stop the internal counter 322, the correction unit 321 may output 0 or the like to the internal counter 322 as the increment value. The internal counter 322 is a counter whose value can be updated, and when a clock is given, the internal counter 322 adds or subtracts a value given by the correction unit 321 to or from its own value.

[0054] The pulse output section 323 generates a pulse 301 based on the binary counter value 308 output by the internal counter 322, and outputs the generated pulse 301 to the video transmission processing section 25 and the imaging device control section . When the correction unit 321 corrects the internal counter 322, the pulse output unit 323 outputs the pulse 301 when the counter binary value 308 after correction reaches a constant value. The correction unit 321 may directly correct the pulse output unit 323 to adjust the timing of outputting the pulse 301. In this case, the pulse output unit 323 may output the pulse 301 when the counter binary value 308 reaches the correction value.

[0055] <Synchronization signal correction process in this embodiment> FIG. 6 is a flowchart showing an example of a procedure for correcting the counter 2 executed by the synchronization signal generating unit 24 of the synchronous communication device 12b according to this embodiment. Each step in Fig. 6 may be realized by the CPU reading and executing a program stored in the ROM of the communication device 12b when the synchronous communication device 12b is powered on and started up. Alternatively, each step in Fig. 6 may be executed when a predetermined operation mode is entered by a user operation or the like or when a predetermined application is started up, instead of when the communication device 12b is powered on. Each step in Fig. 6 may be executed periodically at a predetermined interval while the time synchronous network is formed.

[0056] 6, counter 2 (32) of synchronization signal generating unit 24 receives counter 1 value 306 from counter 1 (31) and control information 305 from bus interface 33, and generates and outputs pulse 301. The flowchart shown in Fig. 6 mainly includes a self-running counter 2, a correction process when the difference between the difference value and a threshold is equal to or smaller than the threshold, and a correction process when the difference value is larger. These correction processes are executed by correction unit 321 of counter 2 (32). In Fig. 6, the difference value and the correction value are absolute values, but as described above, they may be positive or negative values. When the difference value and the correction value are real numbers, it is sufficient to execute the correction process in S8 without executing the processes in S7 and S10 to S13. On the other hand, when the correction value is an absolute value, recalculation is not required when setting it in the weight counter in Fig. 9 described later.

[0057] In S1, counter 2 (32) of synchronization signal generating unit 24 of synchronous communication device 12b determines whether it is time to count the value of counter 2 (32). If it is not time to count the value of counter 2 (32) (S1: N), counter 2 (32) loops the process of S1 and waits until it is time to count the value of counter 2 (32). On the other hand, if it is time to count the value of counter 2 (32) (S1: Y), counter 2 (32) proceeds to S2.

[0058] In S2, counter 2 (32) of synchronization signal generating unit 24 refers to update timing 2 (307) to determine whether it is time to update (correct) counter 2 (32). If it is not time to update counter 2 (32) (S2:N), counter 2 (32) proceeds to S3, counts up using clock 302 without correcting the value of counter 2 (32), and proceeds to S14. On the other hand, if it is time to update counter 2 (32) (S2:Y), counter 2 (32) proceeds to S4.

[0059] In S 4 , the correction unit 321 of the counter 2 ( 32 ) of the synchronization signal generation unit 24 calculates the difference between the counter 2 value 308 and the counter 1 value 306 in order to perform a correction process to bring the counter 2 value 308 closer to the counter 1 value 306 .

[0060] In S5, the correction unit 321 judges whether or not the difference value between counter 1 (31) and counter 2 (32) calculated in S4 exceeds a predetermined threshold. The predetermined threshold referred to in S5 is the maximum allowable error in time that does not allow the time synchronization between the synchronous communication device 12b and the imaging device 14b to be lost, that is, that ensures synchronous imaging by the multiple imaging devices 14a to 14f. This predetermined threshold is included in the control information 305 received from the control unit 22 via the bus interface 33. If the difference value calculated in S4 is equal to or smaller than the predetermined threshold value (S5:N), the correction unit 321 proceeds to S6, whereas if the difference value exceeds the predetermined threshold value (S5:Y), the correction unit 321 proceeds to S10.

[0061] In S6, since the difference between counter 1 value 306 and counter 2 value 308 is equal to or less than the threshold, correction unit 321 sets the difference value calculated in S4 as a correction value for counter 2 (32). By setting the correction value to be set in counter 2 (32) as the difference value with counter 1 (31), counter 2 value 308 is corrected by the difference value in the calculations in S8 and S9 at the subsequent stages. As a result, counter 2 value 308 matches counter 1 value 306 with one correction.

[0062] In S7, correction unit 321 determines whether the difference between counter 2 value 308 and counter 1 value 306 is positive or negative. If counter 1 value 306 is greater than or equal to counter 2 value 308 (S7: Y) after determining whether the difference calculated in S4 is positive or negative, correction unit 321 proceeds to S8, whereas if counter 1 value 306 is less than counter 2 value 308 (S7: N), correction unit 321 proceeds to S9.

[0063] If counter 1 value 306 is equal to or greater than counter 2 value 308, then in S8 correction unit 321 determines that counter 2 value 308 lags behind counter 1 value 306, and adds the difference value, which is a correction value, to counter 2 value 308. In this way, correction unit 321 makes counter 2 value 308 coincide with counter 1 value 306.

[0064] On the other hand, if counter 1 value 306 is less than counter 2 value 308, in S9 correction unit 321 determines that counter 1 value 308 is ahead of counter 1 value 306, and subtracts (decrements) the difference value, which is a correction value, from counter 2 value 308. In this way, correction unit 321 makes counter 2 value 308 coincident with counter 1 value 306. Note that, when making counter 2 value 308 coincident with counter 1 value 306 in S9, the update of counter 2 value 308 may be stopped by the amount of the difference value.

[0065] Returning to S5, if the difference value calculated in S4 exceeds a predetermined threshold value, in S10, the correction unit 321 sets the correction value specified in the control information 305 received from the control unit 22 via the bus interface 33 as the correction value for counter 2 (32). The specified threshold value referenced in S5 is the maximum allowable error within the range in which the imaging device 14b can maintain time synchronization, and since the correction value is equal to or smaller than this specified threshold value, the correction unit 321 can correct the synchronization signal while maintaining time synchronization with the imaging device 14b.

[0066] On the other hand, in S10, because the correction value is smaller than the difference value calculated in S4, even if the calculations in the subsequent stages S12 and S13 are performed, counter 2 value 308 does not match counter 1 value 306 in one go. In this embodiment, counter 2 value 308 is repeatedly corrected using the correction value until the difference value becomes equal to or less than the threshold, thereby gradually bringing counter 2 value 308 closer to counter 1 value 306 (S10 to S13). Then, when the difference value becomes equal to or less than the threshold, counter 2 value 308 is corrected using the difference value, thereby making counter 2 value 308 match counter 1 value 306. In S11, the correction unit 321 judges whether the difference between the counter 2 value 308 and the counter 1 value 306 is positive or negative. If the difference calculated in S4 is judged to be positive or negative and the counter 1 value 306 is equal to or greater than the counter 2 value 308 (S11: Y), the correction unit 321 proceeds to S12, whereas if the counter 1 value 306 is less than the counter 2 value 308 (S11: N), the correction unit 321 proceeds to S13.

[0067] If counter 1 value 306 is equal to or greater than counter 2 value 308, in S12 correction unit 321 determines that counter 2 value 308 lags behind counter 1 value 306, and counts up counter 2 value 308 by the correction value. Since the correction value added to counter 2 value 308 in S12 is smaller than the difference value calculated in S4, counter 2 value 308 does not match counter 1 value 306 in one go.

[0068] On the other hand, if counter 1 value 306 is less than counter 2 value 308, in S13 correction unit 321 determines that counter 2 value 308 is ahead of counter 1 value 306, and counts down counter 2 value 308 by the correction value. Since the correction value subtracted from counter 2 value 308 in S13 is smaller than the difference value calculated in S4, counter 2 value 308 does not match counter 1 value 306 in one go. As described above, in this embodiment, when the difference value is greater than the threshold value, the correction unit 321 corrects the counter 2 value 308 multiple times. This causes the counter 2 value 308 to gradually approach the counter 1 value 306, and ultimately causes the counter 2 value 308 to match the counter 1 value 306. Note that, when correcting the counter 2 value 308 in S13, the update of the counter 2 value 308 may be stopped for the amount of the correction value.

[0069] When the processes of S3, S8, S9, S12, and S13 are each completed, the process proceeds to S14, where the counter 2 (32) of the synchronization signal generating unit 24 determines whether or not an instruction to stop the series of processes has been input. If an instruction to stop the processes has been input (S14: Y), the synchronization signal correction process of Fig. 6 ends. On the other hand, if an instruction to stop the processes has not been input (S14: N), the process returns to S1 and repeats the processes from S1 to S13.

[0070] As described above, according to this embodiment, when a synchronous communication device generates a synchronization signal for time-synchronizing a counterpart device, the synchronous communication device corrects the time of its own device with a reference time supplied from a time server, and generates a synchronization signal based on the corrected time of its own device. Then, the synchronous communication device calculates the difference between the first counter synchronized with a reference time and the second counter, and if the calculated difference exceeds a predetermined threshold, gradually corrects the value of the second counter multiple times so that the value of the second counter approaches the value of the first counter.

[0071] Even if the error between the reference time provided by the time server and the time of the device itself is greater than a threshold value, time synchronization with the reference time is performed, so that time synchronization in the opposing device can be continued, for example, in synchronized imaging by multiple devices. In addition, when the difference between the reference time and the time of the own device is larger than a threshold, the amount of correction of the second counter is limited to a certain range, and the value of the second counter is corrected stepwise. As a result, even if a sudden change occurs in the first counter that is synchronized with the reference time of the time server, the time synchronization of the opposite device can be continued while tracking the time server, improving the accuracy of the time synchronization.

[0072] (Embodiment 2) Hereinafter, the second embodiment will be described in detail with reference to Figs. 7 and 8, focusing only on the differences from the first embodiment. An opposing device to be time-synchronized, for example an imaging device, has a predetermined period of synchronization signal reception timing at which it can receive a synchronization signal output from a synchronous communication device. In the second embodiment, the value of counter 2 is corrected so that the synchronization signal is received by the opposite device within this synchronization signal reception timing range.

[0073] The internal configuration of the synchronous communication device according to the second embodiment is similar to that of the first embodiment shown in FIGS. FIG. 7 is a waveform diagram illustrating an example of the relationship between the synchronous imaging timing in the synchronous imaging system and the timing of receiving a synchronization signal from each imaging device.

[0074] In normal imaging, imaging is performed within the frame rate interval set in the imaging device, but in synchronous imaging, synchronous imaging as a system is performed by having multiple imaging devices complete imaging during synchronous imaging timing within the frame rate interval. 7, synchronization signal reception timings 730 and 731 in the imaging devices 14a and 14b are generated based on previously received control signals 740 and 741, respectively. If the timing at which the imaging devices 14a and 14b receive the control signals 740 and 741 falls outside the period of the synchronization signal reception timings, a re-synchronization process occurs, making it impossible to continue normal synchronous imaging.

[0075] 7, dashed lines 710, 711, and 712 indicate the start points of the imaging times of the imaging devices 14a and 14b, respectively. If the imaging frame rate is 24 fps (frames per second), it arrives every 1 / 24 seconds, and if it is 50 fps, it arrives every 1 / 50 seconds. Meanwhile, dashed lines 720, 721, and 722 indicate the end points of the synchronous imaging timing in the synchronous imaging system 1. The imaging devices 14a and 14b complete imaging within the rising period of this synchronous imaging timing, thereby performing synchronous imaging in the entire system.

[0076] 7, solid lines 730 and 731 respectively indicate the synchronization signal reception timings at which the image capture devices 14a and 14b can receive a synchronization signal. The image capture devices 14a and 14b update their own time based on the control signals 15a and 15b, wait for the next expected control signal, and receive the control signals 15a and 15b within the synchronization signal reception timings 730 and 731, thereby maintaining time synchronization.

[0077] Solid lines 740 and 741 respectively indicate the synchronization pulses of the control signals 15a and 15b. The imaging devices 14a and 14b receive the synchronization pulses 740 and 741 within the synchronization signal reception timings 730 and 731, and after a certain period of time, turn the synchronization signal reception timings 730 and 731 on again to wait for the synchronization pulses 740 and 741.

[0078] For example, consider a case where the synchronous communication devices 12a, 12b are unable to update their own time with the time of the time server 11 due to time synchronization failure or the like. Even in this case, the synchronous communication devices 12a, 12b maintain time synchronization between the synchronous communication devices 12a, 12b and the imaging devices 14a, 14b by continuously sending the control signals 15a, 15b by running the internal clocks independently. In this case, a difference may occur over time between the control signals 15a, 15b that are out of time synchronization with the time server 11 and the synchronous imaging timing of the system that is synchronized with the time of the time server 11 due to accumulation of clock jitter, etc. of the synchronous communication devices 12a, 12b.

[0079] 7, the pulse of the control signal 15a is within the period of the synchronization signal reception timing 730 of the imaging device 14a, so the synchronous communication device 12a is time synchronized with the imaging device 14a. In addition, the pulse of the control signal 15a is also within the period of the system's synchronous imaging timing 720-722, so the imaging device 14a can perform synchronous imaging within the system. On the other hand, the synchronous communication device 12b is time-synchronized with the imaging device 14b because the pulse of the control signal 15b is within the period of the synchronization signal reception timing 731 of the imaging device 14b. However, the pulse of the control signal 15b is out of sync with the system's synchronous imaging timing 722, so the imaging device 14b cannot perform synchronous imaging within the system.

[0080] FIG. 8 is a waveform diagram for explaining correction of the synchronization signal according to the present embodiment when the synchronization signal deviates from the synchronization signal reception timing of the imaging device 14b in the synchronous imaging timing of FIG. A solid line 810 indicates the waveform of the synchronization signal reception timing of the imaging device 14b when the control signal 15b is corrected to fall within the system's synchronous imaging timing. The imaging device 14b receives the synchronization signal only within this synchronization signal reception timing 810, and sets the synchronization signal reception timing again after a certain period. At the first imaging time 710, the imaging device 14b receives the control signal 15b during the first synchronization signal reception timing 810, but at the next imaging time 711, the pulse of the control signal 15b deviates from the synchronization signal reception timing 810. For this reason, the imaging device 14b enters re-synchronization processing after the imaging time 712.

[0081] 8, a solid line 820 indicates the waveform of the synchronization signal in the control signal 15b received by the imaging device 14b when the control signal 15b is corrected to fall within the synchronous imaging timing of the system. At the first imaging time 710, the synchronization signal of the control signal 15b is not within the synchronous imaging timing 720 of the system, so the imaging device 14b cannot perform synchronous imaging within the system. If the synchronization signal is corrected so that it falls within the system's synchronous imaging timing 721 at the next imaging time 711, the pulse of the control signal 15b will deviate from the synchronization signal reception timing 810. Therefore, at the next imaging time 712, the imaging device 14b needs to perform re-synchronization processing, and synchronous imaging cannot be performed until the re-synchronization processing is completed.

[0082] On the other hand, a solid line 811 indicates the waveform of the synchronization signal reception timing of the image capture device 14b when the control signal 15b is corrected within the range of the synchronization signal reception timing of the image capture device 14b. The image capture device 14b receives the synchronization signal only within this synchronization signal reception timing 811, and sets the synchronization signal reception timing again after a certain period.

[0083] The imaging device 14b receives the control signal 15b during the first synchronization signal reception timing 711 at the first imaging time 710, and similarly receives the control signal 15b at the next imaging time 711. Because the synchronization signal was received slightly early at the imaging time 711, the synchronization signal reception timing 811 also shifts forward at the next imaging time 712, a certain time after the reception of the synchronization signal. As a result, at the imaging time 712, the synchronization signal reception timing 811 overlaps partly with the synchronous imaging timing 722 of the system.

[0084] In FIG. 8, a solid line 821 indicates the waveform of the synchronization signal in the control signal 15b received by the imaging device 14b when the correction threshold of the control signal 15b is adjusted within the range of the synchronization signal reception timing of the imaging device 14b. At the first imaging time 710, the synchronization signal of the control signal 15b is not included in the system's synchronous imaging timing 720. Therefore, at the next imaging time 711, the synchronization signal is made closer to the system's synchronous imaging timing 721 within the range of the synchronization signal reception timing 811. Then, the synchronization signal reception timing 811 at the next imaging time 712 is calculated based on the synchronization signal received at the synchronization signal reception timing 811 of the immediately preceding imaging time 711, and therefore is closer to the system's synchronous imaging timing 822 compared to the synchronization signal reception timing 810. The synchronization signal at the imaging time 712 is further closer to the system's synchronous imaging timing within the range of the synchronization signal reception timing 811. As a result, the imaging device 14b can receive the synchronization signal at the synchronization signal reception timing 811 within the system's synchronous imaging timing 722, and resynchronization is not required.

[0085] As described above, according to this embodiment, the synchronization signal generating unit 24 of the synchronous communication devices 12a to 12f adjusts the threshold value for correcting the synchronization signal so that the synchronization signal falls within the range of the synchronization signal reception timing of the imaging devices 14a to 14f, which are the counterpart devices to be time-synchronized. This allows the control signals 15a to 15f to fall within the synchronous imaging timing of the system while maintaining the time synchronization between the synchronous communication devices 12a to 12f and the imaging devices 14a to 14f, making it possible to continue synchronous imaging.

[0086] (Embodiment 3) Hereinafter, the third embodiment will be described in detail with reference to FIG. 9, focusing only on the differences from the above-described embodiments. In this embodiment, the internal counter 322 further includes a wait counter (not shown) that holds the stop period of the counter 2 (32), and when the counter 2 (32) is ahead of the counter 1 (31), the counter 2 (32) is stopped (put on standby) to make a correction.

[0087] FIG. 9 is a flowchart illustrating an example of a procedure of a correction process for the counter 2 executed by the synchronization signal generating unit of the synchronous communication device according to the third embodiment. Compared with the first embodiment shown in FIG. 6, the correction process of the third embodiment shown in FIG. 9 includes additional steps S91 to S99 for setting a weight counter and using the weight counter for correcting the counter 2. In this embodiment, the counter 2 (32) of the synchronous communication devices 12a to 12f includes a wait counter in the internal counter 322, and while the wait counter has a non-zero value, the free-running increment of the counter 2 (32) is temporarily stopped. During this temporary stop, the value of the counter 1 (31) catches up with the value of the counter 2 (32), correcting the value of the counter 2 (32) to match the value of the counter 1 (31). When the correction unit 321 writes to the weight counter, the internal counter 322 may decrement the weight counter until the weight counter becomes 0, and during that time, wait for the counter 2 value 308 to be updated.

[0088] 9, when the count timing of counter 2 (32) arrives in S1 (S1: Y), in S91, counter 2 (32) of synchronization signal generating unit 24 determines whether the value of the wait counter of internal counter 322 is 0 or not. If the value of the wait counter is not 0 (S91: N), the process proceeds to S92, whereas if the value of the wait counter is 0 (S91: Y), the process proceeds to S2.

[0089] In S92, counter 2 (32) stops its free-running count for one clock. This allows counter 1 (31) to catch up with counter 2 (32) by one clock. Note that to stop counter 2 (32), 0 may be given as an increment value and 0 may be added, or the count process itself may not be executed. In S93, counter 2 (32) counts down the wait counter of the internal counter 322, and updates the number of clocks until counter 1 (31) catches up with counter 2 (32). By repeating the free-running count stop process of counter 2 (32) in S92 and S93 until the wait counter becomes 0, the value of counter 1 (31) approaches the value of counter 2 (32) by the value of the wait counter.

[0090] Returning to S2, the timing for updating Counter 2(2) arrives, and in the correction process for Counter 2(32), in S8, the correction unit 321 adds the correction value (difference value) set in S6 to Counter 2(32), and then in S94, sets the wait counter to 0. As a result, in the next loop, Counter 2(32) counts up in S3 until the timing for updating Counter 2(32) arrives. On the other hand, if it is determined in S7 that the value of counter 2 (32) is greater than the value of counter 1 (31), the process proceeds to S95 instead of the subtraction process (S9) of counter 2 (32) in FIG.

[0091] In S95, the correction unit 321 adds 0 to the counter 2 (32), stops the counter 2 (32), and waits for the counter 1 (31) to catch up. Note that, to execute this counter stop processing, the counter 2 (32) may be added with 0, or the count processing itself may be stopped. In S96, the correction unit 321 sets the difference value as a correction value in the weight counter of the internal counter 322. As a result, the counter 2 (32) is corrected in the negative direction. Also, as the counter 2 (32) is corrected by the difference value, the process branches to S92 in the next loop and starts the process of stopping the counter 2 (32).

[0092] Returning to S2, the timing for updating Counter 2(2) arrives, and in the correction process for Counter 2(32), in S12, the correction unit 321 counts up Counter 2(32) by the correction value set in S10, and then in S97, sets the wait counter to 0. As a result, in the next loop, Counter 2(32) counts up in S3 until the timing for updating Counter 2(32) arrives. On the other hand, if it is determined in S11 that the value of counter 2 (32) is greater than the value of counter 1 (31), the process proceeds to S98 instead of the countdown process (S13) of counter 2 (32) in FIG.

[0093] In S98, the correction unit 321 adds 0 to the counter 2 (32), stops the counter 2 (32), and waits for the counter 1 (31) to catch up. Note that, to execute this counter stop process, the counter 2 (32) may be added with 0, or the count process itself may be stopped. In S99, the correction unit 321 sets the correction value in the weight counter of the internal counter 322. As a result, the counter 2 (32) is corrected in the negative direction. Also, as the counter 2 (32) is corrected by the correction value, the process branches to S92 in the next loop and starts the process of stopping the counter 2 (32). The above process is repeated until a stop command is input in S14.

[0094] As described above, according to this embodiment, when correcting in the negative direction by stopping Counter 2 (32), the wait counter holds the period during which Counter 2 (32) is stopped. Therefore, the synchronization signal can be corrected in stages without directly rewriting the value of Counter 2 (32).

[0095] (Modification) The present invention can be embodied, for example, as a system, an apparatus, a method, a program, or a recording medium (storage medium), etc. Specifically, the present invention may be applied to a system composed of multiple devices (for example, a host computer, an interface device, an imaging device, a Web application, etc.), or may be applied to an apparatus composed of a single device. The present invention can also be realized by a program that realizes part or one or more functions of the above-mentioned embodiments. That is, the program can be supplied to a system or device via a network or a storage medium, and one or more processors in a computer (or a CPU, MPU, etc.) of the system or device read and execute the program. The program may also be provided by recording it on a computer-readable recording medium. In addition, the functions of the embodiments are not limited to those that are realized by a computer executing a program read out by the computer. For example, an operating system (OS) running on a computer may perform a part or all of the actual processing based on instructions from the program, and the functions of the above-mentioned embodiments may be realized by the processing. [Explanation of symbols]

[0096] 1...time synchronization system, 11...time server, 12a to 12f...synchronous communication device, 13...TC switching hub, 14a to 14f...imaging device, 15a to 15f...control signal, 21a, 21b...communication unit, 22...control unit, 23...storage unit, 24...synchronization signal generation unit, 25...video transmission processing unit, 26...imaging device control unit, 27...image processing unit, 31...counter 1, 32...counter 2, 33...bus interface

Claims

1. a first counter synchronized with a reference time; a second counter synchronized with the first counter; a generating means for generating a synchronization signal based on the value of the second counter being incremented by a predetermined number; a correction means for controlling the second counter based on a correction value, based on a pulse output from the first counter at a timing for updating the second counter, so that the value of the second counter approaches the value of the first counter; a control means for controlling the correction means to calculate a difference between a value of the first counter and a value of the second counter, and when the calculated difference is greater than a predetermined threshold, to control the second counter using a value based on the predetermined threshold as the correction value, and when the calculated difference is smaller than the predetermined threshold, to control the second counter using the value based on the difference as the correction value; The timing of output of a pulse for updating the second counter output from the first counter does not overlap with the timing of output of the sync signal generated by the generating means. A communication device comprising:

2. When the difference is greater than the predetermined threshold, the control means sets a value equal to or less than the predetermined threshold as a correction value to correct the value of the second counter.

2. The communication device according to claim 1 .

3. When the difference is greater than the predetermined threshold, the control means sets a value smaller than the predetermined threshold as a correction value to correct the value of the second counter.

3. The communication device according to claim 1 or 2.

4. When the difference is equal to or smaller than the predetermined threshold, the control means sets the difference as a correction value to correct the value of the second counter.

4. The communication device according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

5. The control means sets the predetermined threshold value to a maximum phase error that can ensure time synchronization in an opposite device to which the synchronization signal is output.

5. The communication device according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

6. The timing of inputting a pulse for updating the first counter input from outside does not overlap at least one of the timing of outputting a pulse for updating the second counter and the timing of outputting a pulse of the synchronization signal.

6. The communication device according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

7. The control means sets the predetermined threshold value so that a pulse of the synchronization signal is input within a timing range in which the opposite device, which is an output destination of the synchronization signal, can receive the synchronization signal.

7. The communication device according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

8. The correction means corrects the second counter in a negative direction by stopping the second counter when the second counter is ahead of the first counter.

8. A communication device according to claim 1, wherein the communication device is a communication device having a plurality of communication ports.

9. a wait counter that holds a period during which the second counter is stopped; The correction means stops the second counter by decrementing the wait counter.

9. The communication device according to claim 8.

10. The correction means corrects the second counter in a negative direction by decrementing the second counter when the second counter is ahead of the first counter.

8. A communication device according to claim 1, wherein the communication device is a communication device having a plurality of communication ports.

11. The communication device performs time synchronization using PTP (Precision Time Protocol) that complies with the IEEE 1588 standard.

11. The communication device according to claim 1 ,

12. A method for controlling a communication device, comprising: generating a synchronization signal every time a value of a second counter synchronized with a first counter synchronized with a reference time is incremented by a predetermined number; calculating a difference between a value of the first counter and a value of the second counter; and controlling the second counter based on a correction value so that the value of the second counter approaches the value of the first counter based on a pulse output from the first counter at a timing for updating the second counter, In the step of controlling the second counter, when the calculated difference is greater than a predetermined threshold, a value based on the predetermined threshold is used as the correction value to control the second counter, and when the calculated difference is smaller than the predetermined threshold, the value based on the difference is used as the correction value to control the second counter; The timing of output of a pulse for updating the second counter output from the first counter does not overlap with the timing of output of the synchronization signal generated in the step of generating the synchronization signal. A method for controlling a communication device comprising:

13. A program for causing a computer to function as each of the means of the communication device according to any one of claims 1 to 11.

Images