Fault Detection Circuit

Abstract

To facilitate the construction of a structure so as to detect various faults related to sensor connections.SOLUTION: The present invention comprises: a sensor signal line connected to a sensor and a plurality of input terminals; a first comparator in which the sensor signal line is connected to an inverted input terminal and a lower-limit threshold voltage is inputted to a non-inverted input terminal; selection means for causing one of the plurality of input terminals to be connected to the sensor signal line; and an output terminal of the first comparator for outputting a first fault determination result signal when a short-circuiting fault occurs to the sensor. Also included is mask means that, when, with the plurality of input terminals having two input terminals for every one sensor provided, one of the two input terminals is connected to the output signal line of a single-ended sensor and the other of the two input terminals is internally connected to ground potential by the selection means, masks a first fault determination result signal indicating that there is a fault, in order to indicate that there is no fault.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a fault detection circuit. [Background technology]

[0002] The following Patent Document 1 discloses a disconnection detection circuit that detects a disconnection in an output terminal of a bridge circuit in which an intermediate voltage changes depending on a physical quantity that is an object of detection. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-008014 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the technology of Patent Document 1 is configured so that when the output terminal is disconnected, the potential of the output terminal becomes ground potential (i.e., below the reference potential) through a resistor, making it difficult to distinguish the failure from when the output terminal is shorted to ground. In other words, it is difficult to configure the technology of Patent Document 1 to detect various types of failures related to the connection of the sensor. [Means for solving the problem]

[0005] A fault detection circuit according to one embodiment includes a sensor signal line connected to a sensor, a first comparator having an inverting input terminal to which the sensor signal line is connected and a non-inverting input terminal to which a predetermined lower threshold voltage is input, a plurality of input terminals connected to the sensor, a selection means for connecting any one of the plurality of input terminals to the sensor signal line, and an output terminal of the first comparator for outputting a first fault determination result signal indicating that there is a fault related to the connection of the sensor when a short-circuit fault of the sensor occurs, the plurality of input terminals having two input terminals for each sensor, one of the two input terminals being connected to an output signal line of a single-ended sensor, and further including a masking means for masking the first fault determination result signal indicating that there is a fault, to the first fault determination result signal to indicate that there is no fault, when the other of the two input terminals is internally connected to a ground potential by the selection means. Effect of the Invention

[0006] According to an embodiment of the fault detection circuit, it is easy to configure the circuit to detect a variety of faults related to the connection of sensors. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a configuration of a detection system according to an embodiment; [Diagram 2] FIG. 2 is a diagram showing the circuit configuration of a signal processing circuit and a fault detection circuit according to an embodiment; [Diagram 3] FIG. 1 is a diagram showing a location of a disconnection fault that can be detected by a fault detection circuit according to an embodiment; [Figure 4] FIG. 1 is a diagram showing a short-circuit fault location that can be detected by a fault detection circuit according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment will be described with reference to the drawings.

[0009] (Configuration of detection system 10) Fig. 1 is a diagram showing a configuration of a detection system 10 according to an embodiment. The detection system 10 shown in Fig. 1 is a system capable of detecting two different types of detection targets using a first sensor 12 and a second sensor 14. As shown in Fig. 1, the detection system 10 includes the first sensor 12, the second sensor 14, and a signal processing circuit 20.

[0010] The first sensor 12 is a differential sensor that outputs a differential signal representing the detection result as a first detection signal. The first sensor 12 is connected to the signal processing circuit 20 by two output signal lines 12A and 12B. The first sensor 12 outputs the first detection signal (differential signal) representing the detection result to the signal processing circuit 20 via the two output signal lines 12A and 12B.

[0011] The second sensor 14 is a single-ended sensor that outputs a single-ended signal representing the detection result as a second detection signal. The second sensor 14 is connected to the signal processing circuit 20 by one output signal line 14A. The second sensor 14 outputs the second detection signal (single-ended signal) representing the detection result to the signal processing circuit 20 via the one output signal line 14A.

[0012] The signal processing circuit 20 is a circuit (so-called AFE (Analog Front End)) that connects the first sensor 12 and the second sensor 14 that output analog signals to an external device 60 that performs digital signal processing. As shown in FIG. 1, the signal processing circuit 20 includes a multiplexer (MUX) 22, an AD converter (ADC) 24, and a fault detection circuit 30.

[0013] The input terminals of the multiplexer 22 are connected to two output signal lines 12A, 12B connected to the first sensor 12 and one output signal line 14A connected to the second sensor 14. The output terminals of the multiplexer 22 are connected to two signal lines 23A, 23B connected to the AD converter 24. The multiplexer 22 selectively switches between the first detection signal (differential signal) output from the first sensor 12 and the second detection signal (single-ended signal) output from the second sensor 14, and outputs the switched signal to the AD converter 24.

[0014] An input terminal of the AD converter 24 is connected to two signal lines 23A and 23B connected to the multiplexer 22. An output terminal of the AD converter 24 is connected to an output signal line 25 connected to an external device 60. The AD converter 24 converts the first detection signal (differential signal) and the second detection signal (single-ended signal) output from the multiplexer 22 from analog signals to digital signals, and outputs the digital signals to the external device 60. Note that, although it is assumed that a microcomputer is used as the external device 60, the present invention is not limited to this, and various processing devices (e.g., ICs, personal computers, smartphones, tablet terminals, servers, etc.) that perform digital signal processing may be used depending on the purpose of use of the detection system 10.

[0015] The fault detection circuit 30 detects a fault related to the connection between the first sensor 12 and the second sensor 14. The fault detection circuit 30 is connected to two signal lines 23A, 23B connected to the AD converter 24 via two switches 26A, 26B (an example of a "switching means").

[0016] When performing failure detection, the failure detection circuit 30 is connected to the two signal lines 23A and 23B by switching both of the two switches 26A and 26B to the on state.

[0017] On the other hand, when failure detection is not performed (that is, when the signal processing circuit 20 is in normal use), the failure detection circuit 30 is disconnected from the two signal lines 23A, 23B by switching both of the two switches 26A, 26B to the off state.

[0018] (Circuit configuration of signal processing circuit 20 and fault detection circuit 30) Fig. 2 is a diagram showing the circuit configurations of a signal processing circuit 20 and a fault detection circuit 30 according to an embodiment. As shown in Fig. 2, the signal processing circuit 20 includes a power supply voltage terminal VDD, four input terminals INP1, INM1, INP2, and INM2, an input terminal EN_MASK, a first multiplexer 31, a fault detection circuit 30, and two output terminals OUT_H and OUT_L.

[0019] The fault detection circuit 30 includes a second multiplexer 32 , a sensor signal line 33 , a pull-up resistor R 1 , a first comparator 34 , a second comparator 35 , and an AND circuit 37 .

[0020] As shown in FIG. 2, the first sensor 12 has four resistors R2, R3, R4, and R5 that form a bridge circuit. In the first sensor 12, the resistors R2 and R4 are connected in series between the power supply voltage terminal VDD and the ground. In the first sensor 12, the output signal line 12A is connected between the resistors R2 and R4. In the first sensor 12, the resistors R3 and R5 are connected in series between the power supply voltage terminal VDD and the ground. In the first sensor 12, the output signal line 12B is connected between the resistors R3 and R5.

[0021] 2, the second sensor 14 has two resistors R6 and R7 connected in series to each other. In the second sensor 14, the output signal line 14A is connected between the resistors R6 and R7. One end of the resistor R6 is connected to the power supply voltage terminal VDD, and the other end is connected to the resistor R7. One end of the resistor R7 is connected to the resistor R6, and the other end is connected to the ground.

[0022] The input terminals of the first multiplexer 31 are connected to two output signal lines 12A and 12B connected to the first sensor 12 via input terminals INP1 and INM1. The input terminals of the first multiplexer 31 are connected to one output signal line 14A connected to the second sensor 14 via an input terminal INP2. The input terminals of the first multiplexer 31 are connected to a spare input terminal INM2. The first multiplexer 31 selectively switches the signal to be output as a fault determination target between a first detection signal (differential signal) supplied from two output signal lines 12A and 12B connected to the first sensor 12 and a second detection signal (single-ended signal) supplied from one output signal line 14A connected to the second sensor 14. In the signal processing circuit 20 shown in FIG. 2, the first multiplexer 31 corresponds to the multiplexer 22 shown in FIG. 1. 1. In the signal processing circuit 20 shown in FIG. 2, two output signal lines 31A and 31B correspond to the two signal lines 23A and 23B shown in FIG.

[0023] The detection system 10 of the present embodiment can also use another differential sensor instead of the second sensor 14. In this case, the detection system 10 of the present embodiment can also connect two output signal lines connected to the other sensor to the input terminals INP2, INM2 so that a detection signal (differential signal) is input from the other sensor to the fault detection circuit 30 via the two output signal lines.

[0024] The input terminals of the second multiplexer 32 are connected to two output signal lines 31A and 31B which are connected to the output terminals of the first multiplexer 31. The output terminal of the second multiplexer 32 is connected to a sensor signal line 33. The second multiplexer 32 selectively switches the signal to be output as a fault determination target between the signal supplied from the output signal line 31A and the signal supplied from the output signal line 31B.

[0025] The fault detection circuit 30 can selectively switch the signal to be subjected to fault determination, which is supplied to the sensor signal line 33, to any one of the four signals input from the four input terminals INP1, INM1, INP2, and INM2, by controlling the first multiplexer 31 and the second multiplexer 32. In other words, the first multiplexer 31 and the second multiplexer 32 are an example of "a selection means for connecting any one of the multiple input terminals connected to the sensor to the sensor signal line."

[0026] For example, when the output of the first multiplexer 31 is switched to the first detection signal (differential signal) and the output of the second multiplexer 32 is switched to the signal supplied from the output signal line 31A, one of the first detection signals (differential signals) is supplied to the sensor signal line 33.

[0027] Also, for example, when the output of the first multiplexer 31 is switched to the first detection signal (differential signal) and the output of the second multiplexer 32 is switched to the signal supplied from the output signal line 31A, the other signal of the first detection signal (differential signal) is supplied to the sensor signal line 33.

[0028] Also, for example, when the output of the first multiplexer 31 is switched to the second detection signal (single-ended signal) and the output of the second multiplexer 32 is switched to the signal supplied from the output signal line 31A, the second detection signal (single-ended signal) is supplied to the sensor signal line 33.

[0029] Also, for example, when the output of the first multiplexer 31 is switched to the second detection signal (single-ended signal) and the output of the second multiplexer 32 is switched to the signal supplied from the output signal line 31B, the sensor signal line 33 is supplied with an auxiliary signal input from the auxiliary input terminal INM2.

[0030] As described above, any one of the four signals input from the four input terminals INP1, INM1, INP2, and INM2 is supplied as a signal to be subjected to fault determination to the sensor signal line 33. The output side of the sensor signal line 33 is connected to the non-inverting terminal (+) of the first comparator 34 and the inverting terminal (-) of the second comparator 35.

[0031] The pull-up resistor R1 is connected between the power supply voltage terminal VDD and the sensor signal line 33. The pull-up resistor R1 pulls up the potential of the sensor signal line 33 to a high potential (a potential higher than a predetermined upper limit voltage threshold) when a disconnection fault occurs. The pull-up resistor R1 has a resistance value sufficiently higher (for example, 10 times or more) than the resistors R2 to R7 so ​​that the potential of the sensor signal line 33 can be increased above the upper limit threshold voltage VREFH when a fault occurs in the connection between the first multiplexer 31 and the second multiplexer 32, and so that the pull-up resistor R1 has almost no effect on the potential of the sensor signal line 33 when no fault occurs in the connection between the first multiplexer 31 and the second multiplexer 32.

[0032] A non-inverting terminal (+) of the first comparator 34 is connected to the sensor signal line 33. A predetermined upper limit threshold voltage VREFH is input to an inverting terminal (-) of the first comparator 34. An output terminal of the first comparator 34 is connected to an output terminal OUT_H. The upper limit threshold voltage VREFH is a voltage value higher than a predetermined normal voltage range.

[0033] When the voltage value of the signal to be judged as a fault, which is input from the non-inverting terminal (+) of the first comparator 34, is higher than the upper limit threshold voltage VREFH input from the inverting terminal (-), the first comparator 34 outputs a Hi-level first fault judgment result signal indicating that there is a fault in the connection of the first sensor 12 or the second sensor 14.

[0034] On the other hand, when the voltage value of the signal to be judged as a fault, which is input from the non-inverting terminal (+) of the first comparator 34, is lower than the upper limit threshold voltage VREFH input from the inverting terminal (-), the first comparator 34 outputs a first fault judgment result signal of a low level, indicating that there is no fault in the connection of the first sensor 12 or the second sensor 14.

[0035] An inverting terminal (-) of the second comparator 35 is connected to the sensor signal line 33. A predetermined lower limit threshold voltage VREFL is input to a non-inverting terminal (+) of the second comparator 35. An output terminal of the second comparator 35 is connected to an output terminal OUT_L via an AND circuit 37. The lower limit threshold voltage VREFL is a voltage value lower than a predetermined normal voltage range.

[0036] When the voltage value of the signal to be judged as a fault, which is input from the inverting terminal (-), is lower than the lower limit threshold voltage VREFL, which is input from the non-inverting terminal (+), the second comparator 35 outputs a Hi-level second fault judgment result signal, which indicates that there is a fault in the connection of the first sensor 12 or the second sensor 14.

[0037] On the other hand, when the voltage value of the signal to be judged as a fault input from the inverting terminal (-) is higher than the lower limit threshold voltage VREFL input from the non-inverting terminal (+), the second comparator 35 outputs a low-level second fault judgment result signal indicating that there is no fault in the connection of the first sensor 12 or the second sensor 14.

[0038] As a result, when the signal to be judged for fault is outside a predetermined normal voltage range, the fault detection circuit 30 can output a Hi-level signal (first fault judgment result signal or second fault judgment result signal) from the first comparator 34 or the second comparator 35, thereby notifying the outside (e.g., external device 60 shown in FIG. 1) that there is a fault in the connection of the sensor (first sensor 12 or second sensor 14) that is the output source of the signal to be judged for fault.

[0039] The "faults related to the connection of the sensor" that the fault detection circuit 30 can detect are an open circuit fault (that is, an open circuit fault) and a short circuit fault (that is, a short circuit fault).

[0040] (Detection of open circuit faults by fault detection circuit) FIG. 3 is a diagram showing open circuit fault locations that can be detected by the fault detection circuit 30 according to one embodiment.

[0041] In FIG. 3, fault locations F1 to F10 indicated by filled-in symbols "x" are locations where an open circuit fault can be detected by the fault detection circuit 30, and when an open circuit fault occurs, the voltage value of the sensor signal line 33 is pulled up to a high potential higher than the upper limit threshold voltage VREFH by the pull-up resistor R1, causing a Hi-level first fault determination result signal to be output from the output terminal OUT_H.

[0042] Fault location F1: Output signal line 12A of the first sensor 12 Fault location F2: Output signal line 12B of the first sensor 12 Fault location F3: Output signal line 14A of second sensor 14 Fault location F4: Between resistor R4 in the first sensor 12 and ground Fault location F5: Between resistor R5 in the first sensor 12 and ground Fault location F6: Between resistor R7 in the second sensor 14 and ground Fault location F7: Between the switch 36 and the first multiplexer 31 Fault location F8: Output signal line 31A of the first multiplexer 31 Fault location F9: Output signal line 31B of the first multiplexer 31 Faulty part F10: Sensor signal line 33 (the part before the connection point of pull-up resistor R1)

[0043] For example, if an open fault occurs at a fault location F1 on the output signal line 12A, when the output signal line 12A is connected to the sensor signal line 33, the potential of the sensor signal line 33 is pulled up to a high potential higher than the upper limit threshold voltage VREFH by the pull-up resistor R1. As a result, a voltage higher than the upper limit threshold voltage VREFH is input to the non-inverting terminal (+) of the first comparator 34. As a result, the first comparator 34 outputs a first fault determination result signal of Hi level, which indicates that there is an open fault on the output signal line 12A.

[0044] In addition, in Figure 3, fault locations F11 and F12 indicated by the unfilled symbol "X" are locations where an open circuit fault can be detected by the fault detection circuit 30, and when an open circuit fault occurs, the voltage value of the sensor signal line 33 becomes "0 V", which is lower than the lower limit threshold voltage VREFL, and so a Hi-level second fault determination result signal is output from the output terminal OUT_L.

[0045] Fault location F11: Between resistor R2 in the first sensor 12 and power supply voltage VDD Fault location F12: Between resistor R3 in the first sensor 12 and power supply voltage VDD

[0046] For example, if an open circuit fault occurs at fault location F11 between resistor R2 and the power supply voltage VDD, the supply of power supply voltage VDD to the first sensor 12 is interrupted, but the supply of power supply voltage VDD to the fault detection circuit 30 is not interrupted. Therefore, the voltage V_F11 of the sensor signal line 33 at the time of the open circuit at fault location F11 can be expressed by the following equation.

[0047] V_F11=VDD*R5 / (R1+R5) As described above, in this embodiment, the pull-up resistor R1 has a resistance value, for example, 10 times higher than that of the resistor R5. Therefore, when the resistance value of the pull-up resistor R1 is set to a sufficiently high resistance value according to the above formula, the voltage V_F11 of the sensor signal line 33 becomes approximately 0V. As a result, a voltage "0V" lower than the lower limit threshold voltage VREFL is input to the inverting terminal (-) of the second comparator 35. As a result, the second comparator 35 outputs a second fault determination result signal of Hi level, which indicates that there is an open circuit fault between the resistor R2 and the power supply voltage VDD.

[0048] The fault detection circuit 30 can arbitrarily set a voltage range in which faults can be detected by arbitrarily adjusting the upper limit threshold voltage VREFH and the lower limit threshold voltage VREFL by setting a register, etc. This allows the fault detection circuit 30 to subdivide the determination of the fault location.

[0049] (Detection of short circuit faults by fault detection circuit) FIG. 4 is a diagram showing short-circuit fault locations that can be detected by the fault detection circuit 30 according to one embodiment.

[0050] In FIG. 4, fault locations F21 and F22 indicated by filled-in symbols "x" are locations where a short-circuit fault can be detected by the fault detection circuit 30, and are locations where, when a short-circuit fault with the power supply voltage VDD occurs, a Hi-level first fault judgment result signal is output from the output terminal OUT_H, and when a short-circuit fault with ground occurs, a Hi-level second fault judgment result signal is output from the output terminal OUT_L.

[0051] Fault location F21: Output signal line 12A of the first sensor 12 Fault location F22: Output signal line 12B of first sensor 12

[0052] Also, in Figure 4, fault location F23 indicated by the unfilled symbol "X" is a location where a short-circuit fault with the power supply voltage VDD can be detected by the fault detection circuit 30, and is a location where a Hi-level first fault judgment result signal is output from the output terminal OUT_H when a short-circuit fault with the power supply voltage VDD occurs.

[0053] Fault location F23: Output signal line 14A of second sensor 14

[0054] As shown in FIG. 2 to FIG. 4, when a single-ended sensor is connected to INP2 and INM2, the input terminal INM2 is in a non-connected state. In this case, the input of the first multiplexer 31 can be shorted to the ground by switching the switch 36 provided between the input of the first multiplexer 31 and the ground to the on state. However, in this case, the input voltage of the first multiplexer 31 becomes "0V", and when the input terminal INM2 is set as the fault judgment target, the second comparator 35 outputs a Hi-level second fault judgment result signal. That is, a "fault" is erroneously judged. In this case, the fault detection circuit 30 inputs the second fault judgment result signal from the second comparator 35 to one input terminal of the AND circuit 37, and inputs an inverted signal of the Hi-level mask signal input from the input terminal EN_MASK to the other input terminal of the AND circuit 37, thereby masking the output of the Low-level second fault judgment result signal from the AND circuit 37 to the output terminal OUT_L.

[0055] As described above, the fault detection circuit 30 according to one embodiment includes a sensor signal line 33 connected to a sensor, a pull-up resistor R1 connected between the power supply voltage terminal VDD and the sensor signal line 33, and a first comparator 34 having a non-inverting input terminal to which the sensor signal line 33 is connected and an inverting input terminal to which a predetermined upper limit threshold voltage VREFH is input, and outputs a first fault determination result signal from an output terminal of the first comparator 34, which indicates the presence or absence of a fault related to the connection of the sensor.

[0056] As a result, in the event of a fault in the sensor connection, the fault detection circuit 30 of one embodiment can pull up the potential of the sensor signal line 33 by the pull-up resistor R1, and output a first fault determination result signal from the output terminal of the first comparator 34, indicating that there is a fault in the sensor connection.

[0057] In addition, the fault detection circuit 30 according to one embodiment further includes a second comparator 35 having an inverting input terminal to which the sensor signal line 33 is connected and a predetermined lower limit threshold voltage VREFL input to a non-inverting input terminal, and outputs a second fault determination result signal from an output terminal of the second comparator 35, which indicates the presence or absence of a fault related to the connection of the sensor.

[0058] As a result, in one embodiment, the fault detection circuit 30 can output a second fault determination result signal indicating that there is a fault in the sensor connection from the output terminal of the second comparator 35 when a fault in the sensor connection occurs and causes the potential of the sensor signal line 33 to fall below the normal voltage range.

[0059] Moreover, the fault detection circuit 30 according to the embodiment further includes a first multiplexer 31 and a second multiplexer 32 that connect one of the multiple input terminals connected to the sensor to a sensor signal line 33.

[0060] In this way, the fault detection circuit 30 according to the embodiment can determine the presence or absence of a fault related to the connection of the sensor for each of the multiple signal lines connected to the multiple input terminals.

[0061] Moreover, the fault detection circuit 30 according to one embodiment has two input terminals for one sensor, and is capable of connecting two output signal lines of a differential sensor to the two input terminals, and of connecting one output signal line of a single-ended sensor to any one of the two input terminals.

[0062] In this way, the fault detection circuit 30 according to the embodiment can determine the presence or absence of a fault in the connection of the sensor for each of a differential sensor and a single-ended sensor.

[0063] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0064] For example, in one embodiment, the fault detection circuit 30 is configured to detect faults in the connection of the two sensors 12, 14, but this is not limited to the above, and the configuration of the one embodiment can be modified to detect faults in the connection of three or more sensors.

[0065] In addition, for example, in one embodiment, the configuration is capable of performing both fault detection by comparator 34 and fault detection by comparator 35, but this is not limited to the above. For example, the configuration of one embodiment may be modified to a configuration that is capable of performing only fault detection by comparator 34, without providing comparator 35. [Explanation of symbols]

[0066] 10. Detection System 12 First Sensor 12A, 12B Output signal line 14 Second Sensor 14A output signal line 20 Signal Processing Circuit 22 Multiplexer 23A,23B signal line 24 A / D converter 26A, 26B Switch (switching means) 30 Fault detection circuit 31 First multiplexer (selection means) 32 Second multiplexer (selection means) 33 Sensor signal line 34 First Comparator 35 Second comparator 36 Switch 37 AND circuit (mask means) 60 External equipment R1 Pull-up resistor INP1, INM1, INP2, INM2, EN_MASK input terminals OUT_H, OUT_L output terminals VDD Power supply voltage terminal

Claims

1. A sensor signal line connected to the sensor; a first comparator having an inverting input terminal to which the sensor signal line is connected and a non-inverting input terminal to which a predetermined lower limit threshold voltage is input; A plurality of input terminals connected to the sensor; a selection means for connecting any one of the plurality of input terminals to the sensor signal line; an output terminal of the first comparator for outputting a first fault determination result signal indicating the presence of a fault related to the connection of the sensor when a short-circuit fault occurs in the sensor; Equipped with the plurality of input terminals include two input terminals for each of the sensors; a masking means for masking the first fault determination result signal, which indicates that a fault exists, to the first fault determination result signal, when one of the two input terminals is connected to an output signal line of the single-ended sensor and the other of the two input terminals is internally connected to a ground potential by the selection means, so as to indicate that no fault exists; A fault detection circuit comprising:

2. further comprising an input terminal for a mask signal connected to the mask means; The masking means masks the first failure determination result signal when the masking signal is input.

2. The fault detection circuit according to claim 1.

3. the masking means is an AND circuit, The inputs of the AND circuit are the output of the first comparator and an inverted signal of the input terminal of the mask signal, The output of the AND circuit is connected to the output terminal.

3. The fault detection circuit according to claim 2.

4. The sensor further includes an output terminal of a second comparator for outputting a second fault determination result signal indicating the presence of a fault related to the connection of the sensor when a disconnection fault occurs in the sensor.

2. The fault detection circuit according to claim 1.

5. The sensor further includes two input terminals to which an output signal line of the sensor that outputs the detection result as a differential signal is input.

2. The fault detection circuit according to claim 1.

6. When an output signal line of a sensor that outputs a detection result as a differential signal is input to the two input terminals, the other of the two input terminals is not internally connected to a ground potential.

2. The fault detection circuit according to claim 1.

Images